CSD23285F5T [TI]
采用 0.8mm x 1.5mm LGA 封装、具有栅极 ESD 保护的单路、35mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YJK | 3 | -55 to 150;
| 型号： | CSD23285F5T |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 0.8mm x 1.5mm LGA 封装、具有栅极 ESD 保护的单路、35mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YJK | 3 | -55 to 150 栅 开关 脉冲 晶体管 栅极 |
| 文件： | 总14页 (文件大小：1377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD23285F5
ZHCSFD2B –AUGUST 2016 –REVISED FEBRUARY 2022
CSD23285F5 -12V P 沟道FemtoFET™ MOSFET
产品概要
1 特性
TA = 25°C
VDS
典型值
–12
3.2
单位
V
漏源电压
• 低导通电阻
• 低Qg 和Qgd
• 超小尺寸
Qg
nC
nC
栅极电荷总量(-4.5V)
Qgd
0.48
栅极电荷（栅极到漏极）
漏源导通电阻
– 1.53mm x 0.77mm
– 0.50mm 焊盘间距
• 薄型封装
64
49
38
29
VGS = –1.5V
VGS = -1.8V
VGS = -2.5V
VGS = -4.5V
–0.65
RDS(on)
mΩ
– 厚度为0.36mm
• 集成型ESD 保护二极管
VGS(th)
V
阈值电压
– 额定值> 4kV 人体放电模式(HBM)
– 额定值> 2kV 组件充电模式(CDM)
• 无铅且无卤素
器件信息(1)
介质
器件
数量
封装
配送
CSD23285F5
3000
Femto
• 符合RoHS
1.53mm × 0.77mm
7 英寸卷带
卷带式
CSD23285F5T
250
无引线SMD
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 针对工业负载开关应用进行了优化
• 针对通用开关应用进行了优化
绝对最大额定值
3 说明
TA = 25°C
值
单位
VDS
V
–12
–6
漏源电压
该 29mΩ、-12V N 沟道 FemtoFET™ MOSFET 技术
经过设计和优化，能够最大限度地减小在许多手持式和
移动应用中占用的空间。这项技术能够在替代标准小信
号MOSFET 的同时大幅减小封装尺寸。
VGS
ID
IDM
PD
V
栅源电压
持续漏极电流(1)
持续漏极电流(2)
脉冲漏极电流(1) (3)
功率耗散(1)
–3.3
–5.4
–31
0.5
A
A
W
功率耗散(2)
1.4
4000
2000
人体放电模型(HBM)
充电器件模型(CDM)
0.36 mm
V(ESD)
V
TJ、
Tstg
–55 至
150
工作结温、
贮存温度
°C
(1)
(2)
R
R
θJA = 245°C/W（覆铜面积最小时的典型值）。
θJA = 90°C/W（覆铜面积最大时的典型值）。
(3) 脉冲持续时间≤100μs，占空比≤1%。
0.77 mm
1.53 mm
G
图3-1. 典型器件尺寸
S
D
图3-2. 顶视图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS608
CSD23285F5
ZHCSFD2B –AUGUST 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
Table of Contents
6 Device and Documentation Support..............................7
6.1 Receiving Notification of Documentation Updates......7
6.2 Trademarks.................................................................7
7 Mechanical, Packaging, and Orderable Information....8
7.1 Mechanical Dimensions..............................................8
7.2 Recommended Minimum PCB Layout........................9
7.3 Recommended Stencil Pattern................................... 9
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................3
4 Revision History
Changes from Revision A (July 2017) to Revision B (February 2022)
Page
• 将超薄型封装要点中的厚度从0.35mm 更改为0.36mm..................................................................................... 1
• 将超薄型封装图片中的厚度从0.35mm 更新为0.36mm..................................................................................... 1
• Changed ultra-low profile image height from 0.35 mm to 0.36 mm....................................................................8
• Added FemtoFET Surface Mount Guide note.................................................................................................... 9
Changes from Revision * (August 2016) to Revision A (July 2017)
Page
• Added 表7-1 to the 节7.1 section......................................................................................................................8
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: CSD23285F5
CSD23285F5
ZHCSFD2B –AUGUST 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
V
nA
nA
V
VGS = 0 V, IDS = –250 μA
VGS = 0 V, VDS = –9.6 V
VDS = 0 V, VGS = –5 V
–12
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
–100
–25
–0.95
130
IGSS
VGS(th)
VDS = VGS, IDS = –250 μA
VGS = –1.5 V, IDS = –1 A
VGS = –1.8 V, IDS = –1 A
VGS = –2.5 V, IDS = –1 A
VGS = –4.5 V, IDS = –1 A
VDS = –1.2 V, IDS = –1 A
–0.40
–0.65
64
49
80
RDS(on)
Drain-to-source on-resistance
mΩ
38
47
29
35
gfs
Transconductance
8.9
S
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
483
305
37
628
397
48
pF
pF
pF
VGS = 0 V, VDS = –6 V,
ƒ= 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (–4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
17
Ω
Qg
3.2
0.48
0.66
0.40
4.8
15
4.2
nC
nC
nC
nC
nC
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = –6 V, IDS = –1 A
VDS = –6 V, VGS = 0 V
Turnon delay time
Rise time
5
ns
VDS = –6 V, VGS = –4.5 V,
IDS = –1 A, RG = 2 Ω
td(off)
tf
Turnoff delay time
Fall time
30
ns
13
ns
DIODE CHARACTERISTICS
VSD Diode forward voltage
V
ISD = –1 A, VGS = 0 V
–0.73
–1
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-ambient thermal resistance(1)
Junction-to-ambient thermal resistance(2)
MIN
TYP
90
MAX
UNIT
RθJA
°C/W
245
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: CSD23285F5
CSD23285F5
ZHCSFD2B –AUGUST 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
18
16
14
12
10
8
20
18
16
14
12
10
8
TC = 125° C
TC = 25° C
TC = -55° C
6
6
4
4
VGS = -1.5 V
VGS = -1.8 V
VGS = -2.5 V
VGS = -4.5 V
2
0
2
0
0
0.25
0.5
-VDS - Drain-to-Source Voltage (V)
0.75
1
1.25
1.5
1.75
2
0
0.5
1
-VGS - Gate-To-Source Voltage (V)
1.5
2
2.5
3
D002
D003
VDS = –5 V
图5-1. Saturation Characteristics
图5-2. Transfer Characteristics
图5-3. Transient Thermal Impedance
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: CSD23285F5
CSD23285F5
ZHCSFD2B –AUGUST 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
4.5
4
1000
100
10
3.5
3
2.5
2
1.5
1
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0.5
0
0
0
2
4
6
8
-VDS - Drain-to-Source Voltage (V)
10
12
0.5
1
1.5 2
Qg - Gate Charge (nC)
2.5
3
3.5
D005
D004
图5-5. Capacitance
ID = –1 A
VDS = –6 V
图5-4. Gate Charge
0.95
0.85
0.75
0.65
0.55
0.45
0.35
0.25
100
90
80
70
60
50
40
30
20
10
0
TC = 25° C, ID = -1 A
TC = 125° C, ID = -1 A
-75 -50 -25
0
25
50
75 100 125 150 175
0
1
2
3
4
-VGS - Gate-To-Source Voltage (V)
5
6
TC - Case Temperature (èC)
D006
D007
ID = –250 µA
图5-7. On-State Resistance vs Gate-to-Source
Voltage
图5-6. Threshold Voltage vs Temperature
100
1.5
TC = 25èC
TC = 125èC
VGS = -1.8 V
VGS = -2.5 V
VGS = -4.5 V
1.4
1.3
1.2
1.1
1
10
1
0.1
0.01
0.9
0.8
0.7
0.001
0.0001
0
0.2
0.4
0.6
-VSD - Source-To-Drain Voltage (V)
0.8
1
-75 -50 -25
0
25
50
75 100 125 150 175
D009
TC - Case Temperature (èC)
D008
图5-9. Typical Diode Forward Voltage
ID = –1 A
图5-8. Normalized On-State Resistance vs
Temperature
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: CSD23285F5
CSD23285F5
ZHCSFD2B –AUGUST 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
100
10
1
4.5
4
3.5
3
2.5
2
1.5
1
100 ms
10 ms
1 ms
100 µs
0.5
0
0.1
0.1
1
10
-VDS - Drain-To-Source Voltage (V)
100
-50
-25
0
25
50
75
100 125 150 175
TA - Ambient Temperature (èC)
D010
D011
Single pulse, typ RθJA = 245°C/W
Min Cu RθJA = 245°C/W
图5-10. Maximum Safe Operating Area (SOA)
图5-11. Maximum Drain Current vs Temperature
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: CSD23285F5
CSD23285F5
ZHCSFD2B –AUGUST 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Trademarks
FemtoFET™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: CSD23285F5
CSD23285F5
ZHCSFD2B –AUGUST 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
0.77
0.69
B
A
PIN 1 INDEX AREA
1.53
1.45
C
0.36 MAX
SEATING PLANE
3
0.5
(R0.05) TYP
1
1
0.16
0.14
3X
0.015
TOP B
A
0.40
0.38
3X
4222132/A 06/2015
A. All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
B. This drawing is subject to change without notice.
C. This package is a PB-free solder land design.
表7-1. Pin Configuration
POSITION
DESIGNATION
Pin 1
Gate
Pin 2
Source
Pin 3
Drain
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: CSD23285F5
CSD23285F5
ZHCSFD2B –AUGUST 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
7.2 Recommended Minimum PCB Layout
3X (0.39)
(0.05) MIN
ALL AROUND
1
(R0.05) TYP
SYMM
3X (0.15)
2
SOLDER MASK
OPENING
TYP
(0.5)
3
METAL UNDER
SOLDER MASK
TYP
SYMM
A. All dimensions are in millimeters.
A. For more information, see FemtoFET Surface Mount Guide (SLRA003D).
7.3 Recommended Stencil Pattern
3X (0.39)
1
3x (0.15)
3X (0.2)
(R0.05) TYP
SYMM
2
4 x SOLDER MASK EDGE
0.525
3
SYMM
A. All dimensions are in millimeters.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: CSD23285F5
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD23285F5
ACTIVE
ACTIVE
PICOSTAR
PICOSTAR
YJK
YJK
3
3
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
4S
4S
CSD23285F5T
NIAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD23285F5
CSD23285F5T
CSD23285F5T
PICOSTAR YJK
PICOSTAR YJK
PICOSTAR YJK
3
3
3
3000
250
180.0
180.0
178.0
8.4
8.4
8.4
0.92
0.92
0.92
1.68
1.68
1.68
0.42
0.42
0.42
4.0
4.0
4.0
8.0
8.0
8.0
Q1
Q1
Q1
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD23285F5
CSD23285F5T
CSD23285F5T
PICOSTAR
PICOSTAR
PICOSTAR
YJK
YJK
YJK
3
3
3
3000
250
182.0
182.0
220.0
182.0
182.0
220.0
20.0
20.0
35.0
250
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
CSD23381F4T
采用 0.6mm x 1mm LGA 封装、具有栅极 ESD 保护的单路、175mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YJC | 3 | -55 to 150
TI
CSD23382F4T
采用 0.6mm x 1mm LGA 封装、具有栅极 ESD 保护的单路、76mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YJC | 3 | -55 to 150
TI
CSD2410FGH-10
Trigger Output SSR, 1-Channel, 4000V Isolation, ROHS COMPLIANT, PLASTIC PACKAGE-4
CRYDOM
©2020 ICPDF网 联系我们和版权申明