CSD25501F3T [TI]
采用 0.6mm x 0.7mm LGA、具有栅极 ESD 保护的单路、76mΩ、-20V、P 沟道 NexFET™ 功率 MOSFET | YJN | 3 | -55 to 150;
| 型号： | CSD25501F3T |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 0.6mm x 0.7mm LGA、具有栅极 ESD 保护的单路、76mΩ、-20V、P 沟道 NexFET™ 功率 MOSFET | YJN | 3 | -55 to 150 栅 开关 晶体管 栅极 |
| 文件： | 总13页 (文件大小：1936K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD25501F3
ZHCSGW6B –OCTOBER 2017 –REVISED OCTOBER 2021
CSD25501F3 –20V P 沟道FemtoFET™ MOSFET
产品概要
1 特性
TA = 25°C
VDS
典型值
单位
-20
V
漏源电压
• 低导通电阻
• 超低Qg 和Qgd
• 超小尺寸
Qg
1.02
0.09
nC
nC
总栅极电荷(–4.5V)
Qgd
栅极电荷（栅极到漏极）
120
86
– 0.7mm × 0.6mm
• 薄型
VGS = –1.8V
VGS = -2.5V
VGS = –4.5V
-0.75
漏源
导通电阻
RDS(on)
mΩ
64
– 最大高度为0.22mm
• 集成型ESD 保护二极管
• 无铅且无卤素
• 符合RoHS
VGS(th)
V
阈值电压
器件信息
包装介质
器件(1)
数量
封装
配送
CSD25501F3
3000
Femto
0.73mm × 0.64mm
基板栅格阵列(LGA)
2 应用
卷带
包装
7 英寸卷带
CSD25501F3T
250
• 针对负载开关应用进行了优化
• 电池应用
• 手持式和移动类应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
3 说明
绝对最大额定值
此 –20V、64mΩ、P 沟道 FemtoFET™ MOSFET 经
过设计和优化，能够尽可能减小许多手持式和移动应用
中的空间占用。这项技术能够在替代标准小信号
MOSFET 的同时大幅减小封装尺寸。集成的 10kΩ 钳
位电阻器 (RC) 可根据占空比让栅极电压 (VGS) 高于最
大内部栅极氧化值 –6V。通过二极管的栅极泄漏
(IGSS) 随着VGS 增加到高于–6V 而增加。
TA = 25°C（除非另外注明）
值
单位
V
VDS
VGS
ID
-20
-20
漏源电压
V
栅源电压
持续漏极电流(1)
脉冲漏极电流(1) (2)
功率耗散(1)
–3.6
–13.6
500
A
IDM
PD
A
mW
4000
2000
人体放电模式(HBM)
组件充电模式(CDM)
V(ESD)
V
TJ、
Tstg
–55 至
150
运行结温、
贮存温度
°C
(1) 安装在覆铜区域极小的FR4 材料上时的典型RθJA
255°C/W。
=
(2) 脉冲持续时间≤100μs，占空比≤1%。
RC
G
RG
0.2 mm
D
S
0.7 mm
顶视图.........
0.6 mm
典型部件尺寸...............
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS692
CSD25501F3
ZHCSGW6B –OCTOBER 2017 –REVISED OCTOBER 2021
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................4
6 Device and Documentation Support..............................6
6.1 接收文档更新通知....................................................... 6
6.2 支持资源......................................................................6
6.3 Trademarks.................................................................6
6.4 Electrostatic Discharge Caution..................................6
6.5 术语表......................................................................... 6
7 Mechanical, Packaging, and Orderable Information....7
7.1 Mechanical Dimensions..............................................7
7.2 Recommended Minimum PCB Layout........................8
7.3 Recommended Stencil Pattern................................... 8
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2018) to Revision B (October 2021)
Page
• Added footnote with link to support document....................................................................................................8
Changes from Revision * (October 2017) to Revision A (January 2018)
Page
• Added mechanical dimension information and 表7-1 ....................................................................................... 7
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
V
nA
nA
mA
V
VGS = 0 V, IDS = –250 μA
VGS = 0 V, VDS = –16 V
VDS = 0 V, VGS = –6 V
–20
Drain-to-source leakage current
–50
–50
–1
IGSS
Gate-to-source leakage current
Gate-to-source threshold voltage
VDS = 0 V, VGS = –16 V
VDS = VGS, IDS = –250 μA
VGS = –1.8 V, IDS = –0.1 A
VGS = –2.5 V, IDS = –0.4 A
VGS = –4.5 V, IDS = –0.4 A
VDS = –2 V, IDS = –0.4 A
VGS(th)
–0.45
–0.75
120
86
–1.05
260
RDS(on)
Drain-to-source on-resistance
Transconductance
125
mΩ
64
76
gfs
3.4
S
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
295
70
385
91
pF
pF
pF
VGS = 0 V, VDS = –10 V,
ƒ= 100 kHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Series clamp resistance
Gate charge total (–4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
4.1
5.3
33
Ω
RC
10,000
1.02
0.09
0.45
0.36
1.8
Ω
Qg
1.33
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = –10 V, IDS = –0.4 A
VDS = –10 V, VGS = 0 V
Turnon delay time
474
Rise time
428
VDS = –10 V, VGS = –4.5 V,
IDS = –0.4 A, RG = 0 Ω
td(off)
tf
Turnoff delay time
1154
945
Fall time
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
V
ISD = –0.4 A, VGS = 0 V
–0.73
3.0
–0.95
nC
ns
VDS = –10 V, IF = –0.4 A, di/dt = 200 A/
μs
7.4
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-ambient thermal resistance(1)
Junction-to-ambient thermal resistance(2)
TYPICAL VALUES
UNIT
°C/W
°C/W
90
RθJA
255
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
12
10
8
VGS = -1.8 V
VGS = -2.5 V
VGS = -4.5 V
6
4
2
图5-1. Transient Thermal Impedance
0
0
0.2 0.4 0.6 0.8
1
-VDS - Drain-to-Source Voltage (V)
1.2 1.4 1.6 1.8
2
D002
图5-2. Saturation Characteristics
12
TC = 125° C
TC = 25° C
TC = -55° C
10
8
6
4
2
0
0
0.5
1
1.5
2
-VGS - Gate-To-Source Voltage (V)
2.5
3
D003
VDS = –5 V
图5-3. Transfer Characteristics
9
8
7
6
5
4
3
2
1
0
1000
100
10
Measured At External Gate Pin
Charge At Internal Gate Node
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
0
2
4
6
8
10
12
14
-VDS - Drain-to-Source Voltage (V)
16
18
20
0
0.25
0.5
0.75
1
Qg - Gate Charge (nC)
1.25
1.5
D005
D004
图5-5. Capacitance
ID = –0.4 A
VDS = –10 V
图5-4. Gate Charge
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5.3 Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
1.05
0.95
0.85
0.75
0.65
0.55
0.45
0.35
180
150
120
90
TC = 25° C, ID = -0.4 A
TC = 125° C, ID = -0.4 A
60
30
0
-75 -50 -25
0
25
50
75 100 125 150 175
1
1.5
2
2.5
3
3.5
4
4.5
-VGS - Gate-To-Source Voltage (V)
5
5.5
6
TC - Case Temperature (èC)
D006
D007
ID = –250 µA
图5-7. On-State Resistance vs Gate-to-Source Voltage
图5-6. Threshold Voltage vs Temperature
10
1.5
1.4
1.3
1.2
1.1
1
TC = 25èC
TC = 125èC
VGS = -1.8 V
VGS = -2.5 V
VGS = -4.5 V
1
0.1
0.01
0.9
0.8
0.7
0.001
0.0001
0
0.2
0.4
0.6
-VSD - Source-To-Drain Voltage (V)
0.8
1
-75 -50 -25
0
25
50
75 100 125 150 175
D009
TC - Case Temperature (èC)
D008
图5-9. Typical Diode Forward Voltage
ID = –0.4 A
图5-8. Normalized On-State Resistance vs Temperature
100
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
10
1
100 ms
10 ms
1 ms
100 µs
0.1
0.1
1
10
100
-50
-25
0
25
50
75
100 125 150 175
-VDS - Drain-To-Source Voltage (V)
Single pulse, typical RθJA = 255°C/W
图5-10. Maximum Safe Operating Area
TA - Ambient Temperature (èC)
D010
D011
Typical RθJA = 90°C/W
图5-11. Maximum Drain Current vs Temperature
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6 Device and Documentation Support
6.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
6.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
6.3 Trademarks
FemtoFET™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
6.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
6.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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PACKAGE OUTLINE
7 Mechanical, Packaging, and Orderable Information
TheYJfollowing pages include mechanical, packaging, and order ble information. Thiseiinformation is the most
a TM
N0003A PicoStar - 0.22 mm max h ght
TM
current data available for the designated devices. This data is subject to change without notice and revision of
PicoStar
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
0.73
0.65
B
A
PIN 1 INDEX AREA
0.64
0.56
C
0.22 MAX
SEATING PLANE
0.4
0.225
2
1
3
0.175
0.16
0.51
0.49
0.35
2X
0.14
0.16
0.14
0.015
C B A
0.26
0.24
0.015
C A B
2X
4223685/A 05/2017
PicoStar is a trademark of Texas Instruments.
NOTES:
A. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME
Y14.5M.
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
B. This drawing is subject to change without notice.
2. This drawing is subject to change without notice.
3. This package is a Pb-free bump design. Bump finish may vary. To determine the exact finish, refer to the device datasheet
C. This package is a Pb-free bump design. Bump finish may vary. To determine the exact finish, refer to the device data sheet or contact a
or contact a local TI representative.
local TI representative.
表7-1. Pin Configuration
POSITION
DESIGNATION
Pin 1
Gate
Pin 2
www.ti.com
Source
Pin 3
Drain
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7.2 Recommended Minimum PCB Layout
(0.15)
0.05 MIN
2X (0.25)
ALL AROUND
TYP
2X (0.15)
1
3
SYMM
(0.5)
(0.35)
2
(R0.05) TYP
SOLDER MASK
OPENING
TYP
PKG
(0.4)
METAL UNDER
SOLDER MASK
TYP
(0.175)
A. All dimensions are in millimeters.
B. For more information, see FemtoFET Surface Mount Guide (SLRA003D).
7.3 Recommended Stencil Pattern
2X (0.25)
(0.15)
2X (0.2)
1
3
SYMM
(0.4)
(0.5)
2
2X (0.15)
(R0.05) TYP
PKG
2X SOLDER MASK EDGE
(0.175)
(0.4)
A. All dimensions are in millimeters.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD25501F3
ACTIVE
ACTIVE
PICOSTAR
PICOSTAR
YJN
YJN
3
3
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
V
V
CSD25501F3T
NIAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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11-Jan-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD25501F3
PICOST
AR
YJN
YJN
3
3
3000
250
180.0
8.4
0.7
0.79
0.31
4.0
8.0
Q2
CSD25501F3T
PICOST
AR
180.0
8.4
0.7
0.79
0.31
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD25501F3
PICOSTAR
PICOSTAR
YJN
YJN
3
3
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
CSD25501F3T
Pack Materials-Page 2
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