CSD83325LT [TI]
采用 LGA 封装、具有栅极 ESD 保护的双路、5.9mΩ、12V、N 沟道 NexFET™ 功率 MOSFET | YJE | 6 | -55 to 150;
| 型号： | CSD83325LT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 LGA 封装、具有栅极 ESD 保护的双路、5.9mΩ、12V、N 沟道 NexFET™ 功率 MOSFET | YJE | 6 | -55 to 150 PC 栅 开关 晶体管 栅极 |
| 文件： | 总14页 (文件大小：1587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD83325L
ZHCSD72B –NOVEMBER 2014–REVISED FEBRUARY 2017
CSD83325L 12V 双路 N 通道 NexFET™ 功率 MOSFET
产品概要 (接下页)
1 特性
TA = 25°C
RS1S2(on)
VGS(th)
典型值
单位
mΩ
mΩ
mΩ
V
1
•
•
•
•
•
•
•
共漏极结构
VGS = 2.5V
VGS = 3.8V
VGS = 4.5V
17.5
10.9
9.9
低导通电阻
源极至源极导通电阻
阈值电压
2.2mm × 1.15mm 小外形封装
无铅
0.95
符合 RoHS 环保标准
无卤素
器件信息(1)
包装介质
器件
数量
封装
运输
栅极静电 (ESD) 保护
CSD83325L
3000
2.20mm × 1.15mm
接合栅格阵列 (LGA)
封装
卷带
封装
7 英寸卷带
2 应用
CSD83325LT
250
•
•
电池管理
电池保护
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
绝对最大额定值
3 说明
TA = 25°C
值
12
单位
V
此 12V、9.9mΩ、2.2mm × 1.15mm LGA 双路
NexFET™功率 MOSFET 旨在以小外形封装最大程度
地降低电阻和栅极电荷。该器件的外形尺寸较小并采用
共漏极配置，非常适合小型手持设备中 由电池供电的
应用。
VS1S2 源源电压
VGS
IS
栅源电压
±10
8
V
持续源极电流(1)
脉冲源极电流(2)
功率耗散
A
ISM
PD
52
A
2.3
2000
W
V
V(ESD) 人体模型 (HBM)
TJ，
Tstg
工作结温，
储存温度
俯视图
-55 至 150
°C
{1
D1
{1
{2
(1) 器件在 105ºC 温度下运行。
(2) RθJA = 150°C/W（覆铜面积最小时的典型值），脉冲持续时间
≤ 100μs，占空比 ≤ 1%。
D2
{2
.
.
配置
RDS(on) 与 VGS 间的关系
栅极电荷
30
8
7
6
5
4
3
2
1
0
TC = 25°C, I D = 5 A
TC = 125°C, I D = 5 A
IS1S2 = 5 A
VS1S2 = 6 V
27
{ource 1
{ource 2
24
21
18
15
12
9
Date 1
Date 2
6
3
产品概要
0
0
1
2
3
4
5
6
7
8
9
10
D007
0
2
4
6
8
10
12
14
16
D004
VGS - Gate-to-Source Voltage (V)
Qg - Gate Charge (nC)
TA = 25°C
VS1S2
Qg
典型值
12
单位
V
源源电压
栅极电荷总量 (4.5V)
8.4
nC
nC
Qgd
栅极电荷（栅极到漏极）
1.9
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS494
CSD83325L
ZHCSD72B –NOVEMBER 2014–REVISED FEBRUARY 2017
www.ti.com.cn
目录
6.1 接收文档更新通知 ..................................................... 7
6.2 社区资源.................................................................... 7
6.3 商标........................................................................... 7
6.4 静电放电警告............................................................. 7
6.5 Glossary.................................................................... 7
机械、封装和可订购信息 ......................................... 8
7.1 封装尺寸.................................................................... 8
7.2 推荐的 PCB 布局....................................................... 9
7.3 推荐的模板布局 ......................................................... 9
1
2
3
4
5
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information.................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
器件和文档支持........................................................ 7
7
6
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (January 2016) to Revision B
Page
•
•
•
Added Diode Characteristics (VF(S-S)) in the Electrical Characteristics table .......................................................................... 3
Added Figure 9 to Typical MOSFET Characteristics section ................................................................................................. 4
已添加 接收文档更新通知部分改为器件和文档支持部分 ........................................................................................................ 7
Changes from Original (November 2014) to Revision A
Page
•
•
Improved graph setup for readability...................................................................................................................................... 4
已添加 社区资源 .................................................................................................................................................................... 7
2
Copyright © 2014–2017, Texas Instruments Incorporated
CSD83325L
www.ti.com.cn
ZHCSD72B –NOVEMBER 2014–REVISED FEBRUARY 2017
5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVS1S2
IS1S2
Source-to-source voltage
VGS = 0 V, IS = 250 μA
12
V
Source-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VS1S2 = 9.6 V
VS1S2 = 0 V, VGS = 10 V
VS1S2 = VGS, IS = 250 μA
VGS = 2.5 V, IS = 5 A
VGS = 3.8 V, IS = 5 A
VGS = 4.5 V, IS = 5 A
VS1S2 = 1.2 V, IS = 5 A
1
10
μA
µA
V
IGSS
VGS(th)
0.75
14.0
8.8
0.95
17.5
10.9
9.9
1.25
23.0
13.0
11.9
mΩ
mΩ
mΩ
S
RS1S2(on) Source-to-source on resistance
7.9
gfs
Transconductance
36
DYNAMIC CHARACTERISTICS(1)
Ciss
Coss
Crss
Qg
Input capacitance
Output capacitance
Reverse transfer capacitance
Gate charge total (4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
902
187
111
8.4
1170
243
pF
pF
pF
nC
nC
nC
nC
nC
ns
VGS = 0 V, VS1S2 = 6 V, ƒ = 1 MHz
144
10.9
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
1.9
VS1S2 = 6 V, IS = 5 A
2.2
0.6
VS1S2 = 6 V, VGS = 0 V
2.9
Turnon delay time
Rise time
205
353
711
589
ns
VS1S2 = 6 V, VGS = 4.5 V,
IS1S2 = 5 A, RG = 0 Ω
td(off)
tf
Turnoff delay time
Fall time
ns
ns
DIODE CHARACTERISTICS
VF(S-S) Source-to-source diode forward voltage
ISS = 5 A, VG1S1 = 0 V, VG2S2 = 4.5 V
0.79
1.0
V
(1) Dynamic characteristics values specified are per single FET.
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-ambient thermal resistance(1)
Junction-to-ambient thermal resistance(2)
MIN
TYP
150
55
MAX UNIT
RθJA
°C/W
(1) Device mounted on FR4 material with minimum Cu mounting area.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
Copyright © 2014–2017, Texas Instruments Incorporated
3
CSD83325L
ZHCSD72B –NOVEMBER 2014–REVISED FEBRUARY 2017
www.ti.com.cn
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
50
45
40
35
30
25
20
15
10
5
50
TC = 125°C
TC = 25°C
TC = -55°C
45
40
35
30
25
20
15
10
VGS = 2.5 V
VGS = 3.8 V
VGS = 4.5 V
5
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.5
1
1.5
2
2.5
VS1S2 - Source-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
D002
D003
VS1S2 = 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
4
Copyright © 2014–2017, Texas Instruments Incorporated
CSD83325L
www.ti.com.cn
ZHCSD72B –NOVEMBER 2014–REVISED FEBRUARY 2017
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
10000
1000
100
8
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
7
6
5
4
3
2
1
0
10
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
Qg - Gate Charge (nC)
VS1S2 - Source-to-Source Voltage (V)
D004
D005
IS = 5 A
VS1S2 = 6 V
Figure 4. Gate Charge
Figure 5. Capacitance
30
27
24
21
18
15
12
9
1.25
1.15
1.05
0.95
0.85
0.75
0.65
0.55
0.45
TC = 25°C, I S = 5 A
TC = 125°C, I S = 5 A
6
3
0
0
-75 -50 -25
0
25
50
75 100 125 150 175
1
2
3
4
5
6
7
8
9
10
TC - Case Temperature (°C)
VGS - Gate-to-Source Voltage (V)
D006
D007
IS = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Source-to-Source Resistance vs Gate-to-
Source Voltage
100
1.5
1.4
1.3
1.2
1.1
1
TC = 25°C
TC = 125°C
VGS = 2.5 V
VGS = 3.8 V
VGS = 4.5 V
10
1
0.1
0.01
0.9
0.8
0.7
0.001
0.0001
-75 -50 -25
0
25
50
75 100 125 150 175
0
0.2
0.4
0.6
0.8
1
1.2
1.4
TC - Case Temperature (èC)
VSS - Source-to-Source Voltage (V)
D008
D009
IS = 5 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
Copyright © 2014–2017, Texas Instruments Incorporated
5
CSD83325L
ZHCSD72B –NOVEMBER 2014–REVISED FEBRUARY 2017
www.ti.com.cn
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
10
8
10
1
6
4
2
100 ms
10 ms
1 ms
100 µs
0.1
0.1
0
-50
1
10
100
-25
0
25
50
75
100 125 150 175
VS1S2 - Source-to-Source Voltage (V)
TC - Case Temperature (°C)
D009
D010
Single pulse, max RθJA = 150°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Maximum Source Current vs Temperature
6
版权 © 2014–2017, Texas Instruments Incorporated
CSD83325L
www.ti.com.cn
ZHCSD72B –NOVEMBER 2014–REVISED FEBRUARY 2017
6 器件和文档支持
6.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
6.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
6.3 商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2014–2017, Texas Instruments Incorporated
7
CSD83325L
ZHCSD72B –NOVEMBER 2014–REVISED FEBRUARY 2017
www.ti.com.cn
7 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
7.1 封装尺寸
0.65 TYP
1.15
1.07
A
0.325 TYP
B
2
1
PIN A1
CORNER
A
B
C
0.65
TYP
2.20
2.12
SYMM
2X
1.3
0.33
0.27
6X
0.015
C A
B
SYMM
0.200 ±0.02
C
SEATING PLANE
所有尺寸均以毫米为单位。
8
版权 © 2014–2017, Texas Instruments Incorporated
CSD83325L
www.ti.com.cn
ZHCSD72B –NOVEMBER 2014–REVISED FEBRUARY 2017
7.2 推荐的 PCB 布局
(0.65) TYP
1
6X
( 0.3)
2
A
(0.65) TYP
SYMM
B
C
SYMM
7.3 推荐的模板布局
(0.65) TYP
6X ( 0.3)
2
1
A
(0.65) TYP
SYMM
B
(R0.05) TYP
METAL
TYP
C
SYMM
所有尺寸的单位都是毫米。
版权 © 2014–2017, Texas Instruments Incorporated
9
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD83325L
ACTIVE
ACTIVE
PICOSTAR
PICOSTAR
YJE
YJE
6
6
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
83325L
83325L
CSD83325LT
NIAU
-55 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD83325L
PICOST
AR
YJE
YJE
6
6
3000
250
178.0
8.4
1.25
2.34
0.32
4.0
8.0
Q1
CSD83325LT
PICOST
AR
178.0
8.4
1.25
2.34
0.32
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD83325L
PICOSTAR
PICOSTAR
YJE
YJE
6
6
3000
250
220.0
220.0
220.0
220.0
35.0
35.0
CSD83325LT
Pack Materials-Page 2
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Copyright © 2022，德州仪器 (TI) 公司
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