CSD86356Q5DT [TI]

采用 5mm x 6mm SON 封装的 40A、25V、N 沟道同步降压 NexFET™ 功率 MOSFET 电源块 | DMV | 8 | -55 to 150;


型号：	CSD86356Q5DT
厂家：	TEXAS INSTRUMENTS
描述：	采用 5mm x 6mm SON 封装的 40A、25V、N 沟道同步降压 NexFET™ 功率 MOSFET 电源块 \| DMV \| 8 \| -55 to 150 开关光电二极管
文件：	总28页 (文件大小：1110K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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CSD86356Q5D

ZHCSHY1 –MARCH 2018

CSD86356Q5D 同步降压 NexFET™电源块

1 特性

3 说明

•

半桥电源块

CSD86356Q5D NexFET™电源块是面向同步降压应

用的优化设计方案，能够以 5mm × 6mm 的小巧外形

提供高电流、高效率以及高频率性能。该产品针对 5V

栅极驱动应用进行了优化，在与外部控制器/驱动器的

任一 5V 栅极驱动配套使用时，可提供一套灵活的解决

方案来实现高密度电源。

25A 电流下系统效率高达 93.0%

工作电流高达 40A

高频工作（高达 1.5MHz）

高密度 SON 5mm × 6mm 封装

针对 5V 栅极驱动进行了优化

开关损耗较低

超低电感封装

符合 RoHS 标准

俯视图

无卤素

V_IN

T_G

V_SW

无铅引脚镀层

P_GND

(Pin 9)

2 应用

•

同步降压转换器

T_GR

B_G

–

高频应用

P0116-01

高电流、低占空比应用

器件信息⁽¹⁾

数量

•

多相位同步降压转换器

器件

介质

封装

发货

负载点 (POL) 直流/直流转换器

IMVP、VRM 和 VRD 应用

CSD86356Q5D 13 英寸卷带 2500

CSD86356Q5DT 7 英寸卷带 250

5.00mm × 6.00mm

SON 塑料封装

卷带封

装

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

典型电路

典型电源块效率与功率损耗

100

V_IN

BOOT

V_DD

VDD

GND

V_IN

T_G

Control

FET

DRVH

V_SW

T_GR

V_IN= 12 V

_OUT= 1.3 V

V_SW= 5 V

V_OUT

ENABLE

PWM

ENABLE

PWM

Sync

FET

B_G

f_SW= 500 kHz

DRVL

P_GND

L_OUT= 0.3

T_A= 25

èC

CSD86356Q5D

Driver IC

Output Current (A)

D000

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLPS665

CSD86356Q5D

ZHCSHY1 –MARCH 2018

www.ti.com.cn

6.2 Typical Application .................................................. 14

Layout ................................................................... 17

7.1 Recommended Schematic Overview...................... 17

7.2 Recommended PCB Design Overview................... 18

器件和文档支持...................................................... 20

8.1 接收文档更新通知 ................................................... 20

8.2 社区资源.................................................................. 20

8.3 商标......................................................................... 20

8.4 静电放电警告........................................................... 20

8.5 Glossary.................................................................. 20

机械、封装和可订购信息 ....................................... 21

9.1 Q5D 封装尺寸 ......................................................... 21

9.2 引脚配置.................................................................. 21

9.3 焊盘图案建议........................................................... 22

9.4 模版建议.................................................................. 23

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Specifications......................................................... 3

5.1 Absolute Maximum Ratings ...................................... 3

5.2 Recommended Operating Conditions....................... 3

5.3 Thermal Information.................................................. 3

5.4 Power Block Performance ........................................ 3

5.5 Electrical Characteristics – Q1 Control FET ............. 4

5.6 Electrical Characteristics – Q2 Sync FET................. 5

5.7 Typical Power Block Device Characteristics............. 6

5.8 Typical Power Block MOSFET Characteristics......... 8

Application and Implementation ........................ 11

6.1 Application Information............................................ 11

4 修订历史记录

日期

修订版本

说明

2018 年 3 月

最初发布版本。

CSD86356Q5D

www.ti.com.cn

ZHCSHY1 –MARCH 2018

5 Specifications

5.1 Absolute Maximum Ratings

T_A= 25°C (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V_INto P_GND

V_SWto P_GND

–0.8

Voltage

V_SWto P_GND(10 ns)

T_Gto T_GR

–8

B_Gto P_GND

Pulsed current rating, IDM⁽²⁾

120

Power dissipation, P_D

Sync FET, I_D= 88 A, L = 0.1 mH

387

101

150

Avalanche

energy, E_AS

°C

Control FET, I_D= 45 A, L = 0.1 mH

T_Jand T_STG

Operating junction and storage temperature

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

(2) Pulse duration = 50 µS. Duty cycle = 0.01.

5.2 Recommended Operating Conditions

T_A= 25°C (unless otherwise noted)

MIN

MAX

UNIT

V_GS

V_IN

Gate drive voltage

4.5

Input supply voltage⁽¹⁾

Switching frequency C_BST= 0.1 µF (min)

Operating current

ƒ_SW

1500

kHz

T_J

Operating temperature

Storage temperature

125

°C

T_STG

(1) Operating at high V_INcan create excessive AC voltage overshoots on the switch node (V_SW) during MOSFET switching transients. For

reliable operation, the switch node (V_SW) to ground voltage must remain at or below the Absolute Maximum Ratings.

5.3 Thermal Information

T_A= 25°C (unless otherwise noted)

THERMAL METRIC

MIN

MAX

125

UNIT

°C/W

R_θJA

R_θJC

Junction-to-ambient thermal resistance (min Cu)⁽¹⁾

Junction-to-ambient thermal resistance (max Cu)^{(1) (2)}

Junction-to-case thermal resistance (top of package)⁽¹⁾

Junction-to-case thermal resistance (P_GNDpin)⁽¹⁾

1.8

(1)

_θJCis determined with the device mounted on a 1-in²(6.45-cm²), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in

(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. R_θJCis specified by design while R_θJAis determined by the user’s board

design.

(2) Device mounted on FR4 material with 1-in²(6.45-cm²) Cu.

5.4 Power Block Performance

T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

2.8

MAX

UNIT

V_IN= 12 V, V_GS= 5 V, V_OUT= 1.3 V, I_OUT= 25 A,

ƒ_SW= 500 kHz, L_OUT= 0.3 μH, T_J= 25°C

P_LOSS

I_QVIN

Power loss⁽¹⁾

V_INquiescent current⁽¹⁾

T_Gto T_GR= 0 V, B_Gto P_GND= 0 V

µA

(1) Measurement made with six 10-μF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins and

using a high-current 5-V driver IC.

CSD86356Q5D

ZHCSHY1 –MARCH 2018

www.ti.com.cn

5.5 Electrical Characteristics – Q1 Control FET

T_j= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

STATIC CHARACTERISTICS

BV_DSS

I_DSS

Drain-to-source voltage

V_GS= 0 V, I_DS= 250 µA

Drain-to-source leakage current

Gate-to-source leakage current

Gate-to-source threshold voltage

V_GS= 0 V, V_DS= 20 V

100

µA

I_GSS

V_DS= 0 V, V_GS= +10 / –8 V

V_DS= V_GS, I_DS= 250 µA

V_GS(th)

0.95

1.85

V_IN= 12 V, V_GS= 5 V, V_OUT= 1.3 V,

I_OUT= 20 A, ƒ_SW= 500 kHz,

L_OUT= 300 nH

Z_DS(on)Effective AC on-impedance

4.5

mΩ

g_fs

Transconductance

V_DS= 2.5 V, I_DS= 20 A

DYNAMIC CHARACTERISTICS

C_ISS

C_OSS

C_RSS

R_G

Input capacitance

803

548

1040

712

Output capacitance

Reverse transfer capacitance

Series gate resistance

Gate charge total (4.5 V)

Gate charge – gate-to-drain

Gate charge – gate-to-source

Gate charge at V_th

Output charge

V_GS= 0 V, V_DS= 12.5 V, ƒ = 1 Mhz

2.1

6.0

1.3

2.6

1.2

10.3

4.2

Q_g

7.9

Q_gd

Q_gs

Q_g(th)

Q_OSS

t_d(on)

t_r

V_DS= 12.5 V, I_DS= 20 A

V_DS= 12.5 V, V_GS= 0 V

Turn on delay time

Rise time

V_DS= 12.5 V, V_GS= 4.5 V, I_DS= 20 A,

R_G= 0 Ω

t_d(off)

t_f

Turn off delay time

Fall time

DIODE CHARACTERISTICS

V_SD

Q_rr

t_rr

Diode forward voltage

Reverse recovery charge

Reverse recovery time

I_DS= 20 A, V_GS= 0 V

0.84

0.95

V_DD= 12.5 V, I_F= 20 A, di/dt = 300 A/µs

CSD86356Q5D

www.ti.com.cn

ZHCSHY1 –MARCH 2018

5.6 Electrical Characteristics – Q2 Sync FET

T_j= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

STATIC CHARACTERISTICS

BV_DSS

I_DSS

Drain-to-source voltage

V_GS= 0 V, I_DS= 250 µA

Drain-to-source leakage current

Gate-to-source leakage current

Gate-to-source threshold voltage

V_GS= 0 V, V_DS= 20 V

100

1.5

µA

I_GSS

V_DS= 0 V, V_GS= +10 / –8 V

V_DS= V_GS, I_DS= 250 µA

V_GS(th)

0.9

V_IN= 12 V, V_GS= 5 V, V_OUT= 1.3 V,

I_OUT= 20 A, ƒ_SW= 500 kHz,

L_OUT= 300 nH

Z_DS(on)Effective AC on-impedance

0.8

mΩ

g_fs

Transconductance

V_DS= 2.5 V, I_DS= 20 A

106

DYNAMIC CHARACTERISTICS

C_ISS

C_OSS

C_RSS

R_G

Input capacitance

1930

1350

2510

1760

Output capacitance

Reverse transfer capacitance

Series gate resistance

Gate charge total (4.5 V)

Gate charge – gate-to-drain

Gate charge – gate-to-source

Gate charge at V_th

Output charge

V_GS= 0 V, V_DS= 12.5 V, ƒ = 1 Mhz

0.8

14.8

3.3

5.2

2.5

24.9

1.6

Q_g

19.3

Q_gd

Q_gs

Q_g(th)

Q_OSS

t_d(on)

t_r

V_DS= 12.5 V, I_DS= 20 A

V_DS= 12.5 V, V_GS= 0 V

Turn on delay time

Rise time

V_DS= 12.5 V, V_GS= 4.5 V, I_DS= 20 A,

R_G= 0 Ω

t_d(off)

t_f

Turn off delay time

Fall time

DIODE CHARACTERISTICS

V_SD

Q_rr

t_rr

Diode forward voltage

Reverse recovery charge

Reverse recovery time

I_DS= 20 A, V_GS= 0 V

0.79

0.95

V_DS= 12.5 V, I_F= 20 A, di/dt = 300 A/µs

Max R_θJA= 50°C/W

when mounted on 1-in²

(6.45-cm²) of

2-oz (0.071-mm) thick

Cu.

Max R_θJA= 125°C/W

when mounted on

minimum pad area of

2-oz (0.071-mm) thick

Cu.

LG HS

M0189-01

M0190-01

CSD86356Q5D

ZHCSHY1 –MARCH 2018

www.ti.com.cn

5.7 Typical Power Block Device Characteristics

T_J= 125°C, unless stated otherwise. The typical power block system characteristic curves and 图 3 are based on

measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz

copper thickness. See Application and Implementation section for detailed explanation.

1.05

0.95

0.9

0.85

0.8

0.75

-50

-25

100

125

150

Output Current (A)

Junction Temperature (èC)

D001

D002

V_IN= 12 V

ƒ_SW= 500 kHz

V_GS= 5 V

V_OUT= 1.3 V

V_IN= 12 V

ƒ_SW= 500 kHz

V_GS= 5 V

V_OUT= 1.3 V

I_OUT= 40 A

L_OUT= 0.3 µH

图 1. Power Loss vs Output Current

图 2. Normalized Power Loss vs Temperature

100

120

140

Board Temperature (èC)

D005

V_IN= 12 V

V_GS= 5 V

V_OUT= 1.3 V

ƒ_SW= 500 kHz

L_OUT= 0.3 µH

图 3. Typical Safe Operating Area (SOA)

CSD86356Q5D

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ZHCSHY1 –MARCH 2018

Typical Power Block Device Characteristics (接下页)

T_J= 125°C, unless stated otherwise. The typical power block system characteristic curves and 图 3 are based on

measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz

copper thickness. See Application and Implementation section for detailed explanation.

1.6

1.5

1.4

1.3

1.2

1.1

6.6

5.5

4.4

3.3

2.2

1.1

0.0

-1.1

-2.2

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

3.4

2.8

2.3

1.7

1.1

0.6

0.0

-0.6

-1.1

0.9

0.8

100

300

500

700

900 1100 1300 1500 1700

Switching Frequency (kHz)

Input Voltage (V)

D006

D007

V_IN= 12 V

L_OUT= 0.3 µH

V_GS= 5 V

V_OUT= 1.3 V

V_GS= 5 V

ƒ_SW= 500 kHz

V_OUT= 1.3 V

I_OUT= 40 A

L_OUT= 0.3 µH

I_OUT= 40 A

图 4. Normalized Power Loss vs Switching Frequency

图 5. Normalized Power Loss vs Input Voltage

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

9.0

1.04

1.03

1.02

1.01

0.4

7.9

6.7

5.6

4.5

3.4

2.2

1.1

0.0

-1.1

0.3

0.2

0.1

0.0

-0.1

-0.2

0.99

0.98

0.9

0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

Output Voltage (V)

150

300

450

600

750

900 1050 1200

Output Inductance (nH)

D008

D009

V_IN= 12 V

V_GS= 5 V ƒ_SW= 500 kHz

I_OUT= 40 A

V_IN= 12 V

ƒ_SW= 500 kHz

V_GS= 5 V

V_OUT= 1.3 V

L_OUT= 0.3 µH

I_OUT= 40 A

图 6. Normalized Power Loss vs Output Voltage

图 7. Normalized Power Loss vs Output Inductance

CSD86356Q5D

ZHCSHY1 –MARCH 2018

www.ti.com.cn

5.8 Typical Power Block MOSFET Characteristics

T_A= 25°C, unless stated otherwise.

100

V_GS= 4.5 V

V_GS= 6 V

V_GS= 8 V

V_GS= 4.5 V

V_GS= 6 V

V_GS= 8 V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.05

0.1

0.15

0.2

0.25

0.3

V_DS- Drain-to-Source Voltage (V)

D010

D011

图 8. Control MOSFET Saturation

图 9. Sync MOSFET Saturation

100

T_C= 125°C

T_C= 25°C

T_C= -55°C

T_C= 125°C

T_C= 25°C

T_C= -55°C

0.1

0.01

0.001

0.01

0.001

0.5

1.5

2.5

3.5

0.5

1.5

2.5

V_GS- Gate-to-Source Voltage (V)

D012

D013

V_DS= 5 V

图 10. Control MOSFET Transfer

图 11. Sync MOSFET Transfer

2.5

7.5 10 12.5 15 17.5 20 22.5 25

Q_g- Gate Charge (nC)

D014

D015

I_D= 20 A

V_DS= 12.5 V

I_D= 20 A

V_DS= 12.5 V

图 12. Control MOSFET Gate Charge

图 13. Sync MOSFET Gate Charge

CSD86356Q5D

www.ti.com.cn

ZHCSHY1 –MARCH 2018

Typical Power Block MOSFET Characteristics (接下页)

T_A= 25°C, unless stated otherwise.

10000

1000

100

10000

1000

100

C_iss= C_gd+ C_gs

C_oss= C_ds+ C_gd

C_rss= C_gd

C_iss= C_gd+ C_gs

C_oss= C_ds+ C_gd

C_rss= C_gd

V_DS- Drain-to-Source Voltage (V)

D016

D017

ƒ = 1 MHz

V_GS= 0

ƒ = 1 MHz

V_GS= 0

图 14. Control MOSFET Capacitance

图 15. Sync MOSFET Capacitance

1.8

1.6

1.4

1.2

1.6

1.4

1.2

0.8

0.6

0.4

0.8

0.6

-75 -50 -25

75 100 125 150 175

-75 -50 -25

75 100 125 150 175

T_C- Case Temperature (°C)

D018

D019

I_D= 250 µA

图 16. Control MOSFET V_GS(th)

图 17. Sync MOSFET V_GS(th)

T_C= 25°C, I _D= 20 A

T_C= 125°C, I _D= 20 A

T_C= 25°C, I _D= 20 A

T_C= 125°C, I _D= 20 A

V_GS- Gate-to-Source Voltage (V)

D020

D021

图 18. Control MOSFET R_DS(ON)vs V_GS

图 19. Sync MOSFET R_DS(ON)vs V_GS

CSD86356Q5D

ZHCSHY1 –MARCH 2018

www.ti.com.cn

Typical Power Block MOSFET Characteristics (接下页)

T_A= 25°C, unless stated otherwise.

1.5

1.4

1.3

1.2

1.1

1.5

V_GS= 4.5 V

V_GS= 8.0 V

V_GS= 4.5 V

V_GS= 8.0 V

1.4

1.3

1.2

1.1

0.9

0.8

0.7

0.9

0.8

0.7

-75 -50 -25

75 100 125 150 175

-75 -50 -25

75 100 125 150 175

T_C- Case Temperature (°C)

D022

D023

I_D= 20 A

图 20. Control MOSFET Normalized R_DS(ON)

图 21. Sync MOSFET Normalized R_DS(ON)

100

T_C= 25°C

T_C= 125°C

0.1

0.01

0.001

0.0001

0.01

0.001

0.0001

0.2

0.4

0.6

0.8

0.2

0.4

0.6

0.8

V_SD- Source-to-Drain Voltage (V)

D024

D025

图 22. Control MOSFET Body Diode

图 23. Sync MOSFET Body Diode

100

200

100

T_C= 25è C

T_C= 125è C

T_C= 25è C

T_C= 125è C

0.01

0.1

T_AV- Time in Avalanche (ms)

D026

D027

图 24. Control MOSFET Unclamped Inductive Switching

图 25. Sync MOSFET Unclamped Inductive Switching

CSD86356Q5D

www.ti.com.cn

ZHCSHY1 –MARCH 2018

6 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

6.1 Application Information

The CSD86356Q5D NexFET power block is an optimized design for synchronous buck applications using 5-V

gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and

highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems-

centric environment. System-level performance curves such as power loss, Safe Operating Area (SOA), and

normalized graphs allow engineers to predict the product performance in the actual application.

6.1.1 Equivalent System Performance

Many of today's high-performance computing systems require low-power consumption in an effort to reduce

system operating temperatures and improve overall system efficiency. This has created a major emphasis on

improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an

emphasis in improving the performance of the critical power semiconductor in the power stage of this application

(see 图 26). As such, optimization of the power semiconductors in these applications, needs to go beyond simply

reducing R_DS(ON)

Power Stage

Components

Power Block

Components

C_i

Input

Supply

Control

FET

Driver

PWM

L_o

I_L

Switch

Node

C_o

Sync

FET

Load

图 26. Synchronous Buck Topology

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ZHCSHY1 –MARCH 2018

www.ti.com.cn

Application Information (接下页)

The CSD86356Q5D is part of TI’s power block product family which is a highly optimized product for use in a

synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest

generation silicon which has been optimized for switching performance, as well as minimizing losses associated

with Q_GD, Q_GS, and Q_RR. Furthermore, TI’s patented packaging technology has minimized losses by nearly

eliminating parasitic elements between the control FET and sync FET connections (see 图 27). A key challenge

solved by TI’s patented packaging technology is the system-level impact of Common Source Inductance (CSI).

CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and

reduces system efficiency. As a result, the effects of CSI need to be considered during the MOSFET selection

process. In addition, standard MOSFET switching loss equations used to predict system efficiency need to be

modified in order to account for the effects of CSI. Further details behind the effects of CSI and modification of

switching loss equations are outlined in TI’s Application Note Power Loss Calculation With Common Source

Inductance Consideration for Synchronous Buck Converters (SLPA009).

Input

Supply

R_PCB

C_ESR

L_DRAIN

C_INPUT

Control

FET

Driver

PWM

C_ESL

L_SOURCE

L_o

C_o

I_L

Switch

Node

Load

L_DRAIN

C_TOTAL

Sync

FET

Driver

L_SOURCE

图 27. Elimination of Common Source Inductance

The combination of TI’s latest generation silicon and optimized packaging technology has created a

benchmarking solution that outperforms industry standard MOSFET chipsets of similar R_DS(ON)and MOSFET

chipsets with lower R_DS(ON). 图 28 and 图 29 compare the efficiency and power loss performance of the

CSD86356Q5D versus industry standard MOSFET chipsets commonly used in this type of application. This

comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The

performance of CSD86356Q5D clearly highlights the importance of considering the Effective AC On-Impedance

(Z_DS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET

R_DS(ON)specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block

technology.

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Application Information (接下页)

PowerBlock HS/LS R_DS(ON)= 4.5 mW/1.8 mW

Discrete HS/LS R_DS(ON)= 4.5 mW/1.8 mW

Discrete HS/LS R_DS(ON)= 4.5 mW/0.8 mW

PowerBlock HS/LS R_DS(ON)= 4.5 mW/1.8 mW

Discrete HS/LS R_DS(ON)= 4.5 mW/1.8 mW

Discrete HS/LS R_DS(ON)= 4.5 mW/0.8 mW

Output Current (A)

V_OUT= 1.3 V

V_DD= 5 V

Output Current (A)

V_OUT= 1.3 V

V_DD= 5 V

D030

D031

V_IN= 12 V

L_OUT= 0.3 µH

T_A= 25°C

V_IN= 12 V

L_OUT= 0.3 µH

T_A= 25°C

ƒ_SW= 500 kHz

图 28. Efficiency

图 29. Power Loss

Comparison of R_DS(ON)vs Z_DS(ON)compares the traditional DC measured R_DS(ON)of CSD86356Q5D versus its

Z_DS(ON). This comparison takes into account the improved efficiency associated with TI’s patented packaging

technology. As such, when comparing TI’s Power Block products to individually packaged discrete MOSFETs or

dual MOSFETs in a standard package, the in-circuit switching performance of the solution must be considered.

In this example, individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need

to have DC measured R_DS(ON)values that are equivalent to CSD86356Q5D’s Z_DS(ON)value in order to have the

same efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged

discrete MOSFETs or dual MOSFETs in a standard package.

6.1.1.1 Comparison of R_DS(ON)vs Z_DS(ON)

TYP

PARAMETER

UNIT

MAX

—

MAX

Effective AC on-impedance Z_DS(ON)(V_GS= 5 V)

DC measured R_DS(ON)(V_GS= 4.5 V)

4.5

0.8

1.8

—

mΩ

5.6

2.2 mΩ

6.1.2 Power Loss Curves

MOSFET centric parameters such as R_DS(ON)and Q_gdare needed to estimate the loss generated by the devices.

In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss

performance curves. 图 1 plots the power loss of the CSD86356Q5D as a function of load current. This curve is

measured by configuring and running the CSD86356Q5D as it would be in the final application (see 图 30).The

measured power loss is the CSD86356Q5D loss and consists of both input conversion loss and gate drive loss.

公式 1 is used to generate the power loss curve.

(V_IN× I_IN) + (V_DD× I_DD) – (V_{SW_AVG}× I_OUT) = Power loss

(1)

The power loss curve in 图 1 is measured at the maximum recommended junction temperatures of 125°C under

isothermal test conditions.

6.1.3 Safe Operating Area (SOA) Curves

The SOA curves in the CSD86356Q5D data sheet provides guidance on the temperature boundaries within an

operating system by incorporating the thermal resistance and system power loss. to 图 3 outline the temperature

and airflow conditions required for a given load current. The area under the curve dictates the safe operating

area. All the curves are based on measurements made on

a PCB design with dimensions of

4 in (W) × 3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.

CSD86356Q5D

ZHCSHY1 –MARCH 2018

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6.1.4 Normalized Curves

The normalized curves in the CSD86356Q5D data sheet provides guidance on the power loss and SOA

adjustments based on their application specific needs. These curves show how the power loss and SOA

boundaries will adjust for a given set of system conditions. The primary Y-axis is the normalized change in power

loss and the secondary Y-axis is the change in system temperature required in order to comply with the SOA

curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is

subtracted from the SOA curve.

6.2 Typical Application

Input Current (I_IN)

Gate Drive

Current (I_DD)

V_IN

BOOT

DRVH

V_DD

VDD

Input Voltage (V_IN)

V_IN

Control

FET

Gate Drive

Voltage (V_DD)

T_G

ENABLE

PWM

Output Current (I_OUT

V_OUT

)

V_SW

T_GR

Sync

FET

PWM

B_G

DRVL

GND

P_GND

Averaged Switch

V Node Voltage

Averaging

Circuit

CSD86356Q5D

Driver IC

(V_{SW_AVG}

)

图 30. Typical Application

CSD86356Q5D

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Typical Application (接下页)

6.2.1 Design Example: Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see Operating Conditions).

Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the

following procedure will outline the steps the user should take to predict product performance for any set of

system conditions.

6.2.2 Operating Conditions

•

Output current = 35 A

Input voltage = 5 V

Output voltage = 2 V

Switching frequency = 950 kHz

Inductor = 0.3 µH

6.2.2.1 Calculating Power Loss

•

Power loss at 35 A = 5.57 W (图 1)

Normalized power loss for input voltage ≈ 1.12 (图 5)

Normalized power loss for output voltage ≈ 1.13 (图 6)

Normalized power loss for switching frequency ≈ 1.21 (图 4)

Normalized power loss for output inductor ≈ 1 (图 7)

Final calculated power loss = 5.57 W × 1.12 × 1.13 × 1.21 × 1 ≈ 8.5 W

6.2.2.2 Calculating SOA Adjustments

•

SOA adjustment for input voltage ≈ 1.37°C (图 5)

SOA adjustment for output voltage ≈ 1.48°C (图 6)

SOA adjustment for switching frequency ≈ 2.34°C (图 4)

SOA adjustment for output inductor ≈ 0.03°C (图 7)

Final calculated SOA adjustment = 1.37 + 1.48 + 2.34 + 0.03 ≈ 5.2°C

In the previous design example, the estimated power loss of the CSD58915Q5D would increase to 8.5 W. In

addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.2°C. 图 31

graphically shows how the SOA curve would be adjusted accordingly.

1. Start by drawing a horizontal line from the application current to the SOA curve.

2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.

3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

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Typical Application (接下页)

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient

temperature of 5.2°C. In the event the adjustment value is a negative number, subtracting the negative number

would yield an increase in allowable board/ambient temperature.

图 31. Power Block SOA

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7 Layout

7.1 Recommended Schematic Overview

There are several critical components that must be used in conjunction with this power block device. 图 32

shows a portion of a schematic with the critical components needed for proper operation.

•

C22: Bypass capacitor for V_INto help with ringing reduction (recommend 3.3-nF, 0402, 50-V ceramic

capacitor)

•

C20: Bootstrap capacitor

C21: Bypass capacitor for V_DD

C7-C14: Bypass capacitors for V_IN(minimum of 40 µF)

C15: Electrolytic capacitor for V_IN

R14, R16: Place holder for gate resistor (optional)

R15: Place holder for bootstrap resistor (optional)

R17, C16: Place holder for snubber (optional)

+VIN

GND

Vin

Vsw

0603

R15

0603

V_OUT

Vsw

C20

0.1µF

BOOT

R16

0603

+PWM

PWM PHASE

ENABLE

Tgr

GND

FCCM

VCC

Pgnd

0603

+VDD

GND

CSD86356Q5D

C21

10µF

0603

GND

R14

0603

图 32. Recommended Schematic

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ZHCSHY1 –MARCH 2018

www.ti.com.cn

7.2 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and

thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief

description on how to address each parameter follows.

7.2.1 Electrical Performance

The power block has the ability to switch at voltage rates greater than 10 kV/μs. Special care must be taken with

the PCB layout design and placement of the input capacitors, inductor, driver IC and output capacitors.

•

The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see 图 33 and 图

34). It is recommended that one 3.3-nF (or similar), 0402, 50-V ceramic capacitor be placed on the top side

of the board as close as possible to VIN and PGND pins. In addition, a minimum of 40 μF of bulk ceramic

capacitance should be placed as close as possible to the power block in a design. For high-density design,

some of these ceramic capacitors can be placed on the bottom layer of PCB with appropriate number of vias

interconnecting both layers.

•

The driver IC should be placed relatively close to the power block gate pins. T_Gand B_Gshould connect to the

outputs of the driver IC. The T_GRpin serves as the return path of the high-side gate drive circuitry and should

be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for

the driver IC will also connect to this pin.

The switching node of the output inductor should be placed relatively close to the power block VSW pins.

Minimizing the node length between these two components will reduce the PCB conduction losses and

actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches

undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the

peak ring level. The recommended boost resistor value will range between 1.0 Ω to 4.7 Ω depending on the

output characteristics of driver IC used in conjunction with the power block. The RC snubber values can

range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to Snubber Circuits:

Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber values.

The RC snubber should be placed as close as possible to the VSW node and PGND (see 图 33 and 图 34).

(1)

(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

CSD86356Q5D

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ZHCSHY1 –MARCH 2018

Recommended PCB Design Overview (接下页)

7.2.2 Thermal Performance

The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

•

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

Use the smallest drill size allowed in your design. The examples in 图 33 and 图 34 use vias with a 10-mil drill

hole and a 16-mil capture pad.

•

Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

图 33. Recommended PCB Layout (Top Down View)

(2)

图 34. Recommended PCB Layout (Bottom View)

(2) The yellow box on 图 34 signifies an approximate location of the power block on the upper layer.

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www.ti.com.cn

8 器件和文档支持

8.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收

产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

8.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

8.3 商标

NexFET, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

8.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

8.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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9 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请参阅左侧的导航栏。

9.1 Q5D 封装尺寸

6.1

5.9

PIN 1 INDEX AREA

5.1

4.9

1.05 MAX

SEATING PLANE

0.08

0.05

0.00

3.16 0.1

EXPOSED

THERMAL PAD

4X (0.25)

4X (1)

(0.2) TYP

6X 1.27

SYMM

3.81

4.32 0.1

0.46

0.36

0.5

0.4

SYMM

0.71

0.51

0.71

0.51

0.1

0.05

C A B

4223291/A 10/2016

1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。

2. 本图如有变更，恕不另行通知。

3. 封装散热焊盘必须焊接在印刷电路板上，以实现最佳的散热和机械性能。

9.2 引脚配置

位置

名称

V_IN

引脚 1

引脚 2

引脚 3

引脚 4

引脚 5

引脚 6

引脚 7

引脚 8

引脚 9

V_IN

T_G

T_GR

B_G

V_SW

P_GND

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ZHCSHY1 –MARCH 2018

www.ti.com.cn

9.3 焊盘图案建议

(3.16)

0.05 MIN

TYP

4X (1.33)

2X (0.81)

(0.45)

6X (0.81)

(0.41)

2X (0.41)

METAL UNDER

SOLDER MASK

TYP

(0.7)

TYP

PKG

(1.41)

(4.32)

(1.91)

6X (1.27)

(R0.05) TYP

4X (0.54)

PKG

SOLDER MASK

OPENING

TYP

4X (0.25)

(

0.2) VIA

TYP

2X (2.25)

(5.59)

1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。

2. 此封装设计用于焊接到电路板的散热焊盘上。有关更多信息，请参阅《QFN/SON

(SLUA271)。

PCB

连接》应用报告

3. 根据应用决定是否选用过孔，详情请参见器件数据表。如果实现了部分或全部过孔，则会显示建议的过孔位

置。

CSD86356Q5D

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ZHCSHY1 –MARCH 2018

9.4 模版建议

6X (1.37)

METAL UNDER

SOLDER MASK

TYP

8X (0.81)

8X (0.41)

(0.79) TYP

(0.45)

2X (0.15)

(1.21)

(0.56)

(1.41)

PKG

2X (4.92)

SOLDER MASK

EDGE

6X (1.27)

TYP

(R0.05) TYP

(0.49)

EXPOSED METAL

TYP

PKG

4X (0.25)

2X (2.25)

(5.59)

1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。

2. 具有漏斗形壁和圆角的激光切割孔可提供更佳的锡膏脱离。IPC-7525 可能提供替代设计建议。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

2500

250

(1)

(2)

(3)

(4/5)

(6)

CSD86356Q5D

CSD86356Q5DT

ACTIVE

VSON-CLIP

DMV

RoHS-Exempt

& Green

Level-1-260C-UNLIM

-55 to 150

86356D

ACTIVE

DMV

RoHS-Exempt

& Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CSD86356Q5DT

VSON-

CLIP

DMV

250

330.0

12.4

5.3

6.3

1.2

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VSON-CLIP DMV

SPQ

Length (mm) Width (mm) Height (mm)

336.6 336.6 41.3

CSD86356Q5DT

250

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CSD86356Q5DT [TI]

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