CSD87335Q3D [TI]

采用 3mm x 3mm SON 封装的 25A、30V、N 沟道同步降压 NexFET™ 功率 MOSFET 电源块;


型号：	CSD87335Q3D
厂家：	TEXAS INSTRUMENTS
描述：	采用 3mm x 3mm SON 封装的 25A、30V、N 沟道同步降压 NexFET™ 功率 MOSFET 电源块开关光电二极管
文件：	总23页 (文件大小：850K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

CSD87335Q3D 同步降压 NexFET™ 电源块

1 特性

3 说明

•

半桥电源块

CSD87335Q3D NexFET™电源块是面向同步降压应

用的优化设计方案，能够以 3.3mm × 3.3mm 的小巧

外形提供高电流、高效率以及高频率性能。该产品针对

5V 栅极驱动应用进行了优化，可提供一套灵活的解决

方案，在与来自外部控制器或驱动器的任一 5V 栅极驱

动配套使用时，均可提供高密度电源。

V_IN高达 27V

15A 电流时系统效率达 93.5%

工作电流高达 25A

高频工作（高达 1.5MHz）

高密度小外形尺寸无引线 (SON) 3.3mm × 3.3mm

封装

俯视图

•

针对 5V 栅极驱动进行了优化

开关损耗较低

V_IN

T_G

V_SW

超低电感封装

符合 RoHS 标准

无卤素

P_GND

(Pin 9)

无铅引脚镀层

T_GR

B_G

2 应用

P0116-01

•

同步降压转换器

–

高频应用

器件信息⁽¹⁾

数量

高电流、低占空比应用

器件

介质

封装

发货

•

多相位同步降压转换器

CSD87335Q3D

CSD87335Q3DT

13 英寸卷带

7 英寸卷带

2500

250

SON

3.30mm × 3.30mm

塑料封装

卷带封

装

负载点 (POL) 直流/直流转换器

IMVP、VRM 和 VRD 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

典型电路

典型电源块效率与功率损耗

100

V_IN

BOOT

V_DD

VDD

GND

V_IN

T_G

Control

FET

DRVH

T_GR

B_G

4.5

V_SW

V_OUT

ENABLE

PWM

ENABLE

PWM

Sync

FET

V_GS= 5 V

V_IN= 12 V

DRVL

P_GND

_OUT= 1.3 V

L_OUT= 950 nH

_SW= 500 kHz

CSD87335Q3D

Driver IC

1.5

T_A= 25èC

Output Current (A)

D000

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLPS574

CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

www.ti.com.cn

6.4 Normalized Curves.................................................. 12

6.5 Calculating Power Loss and SOA .......................... 13

Recommended PCB Design Overview .............. 15

7.1 Electrical Performance............................................ 15

7.2 Thermal Performance ............................................. 16

器件和文档支持...................................................... 17

8.1 接收文档更新通知 ................................................... 17

8.2 社区资源.................................................................. 17

8.3 商标......................................................................... 17

8.4 静电放电警告........................................................... 17

8.5 Glossary.................................................................. 17

机械、封装和可订购信息 ....................................... 18

9.1 Q3D 封装尺寸 ......................................................... 18

9.2 焊盘布局建议........................................................... 19

9.3 模板建议.................................................................. 19

9.4 Q3D 卷带信息 ......................................................... 20

9.5 引脚配置.................................................................. 20

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Specifications......................................................... 3

5.1 Absolute Maximum Ratings ...................................... 3

5.2 Recommended Operating Conditions....................... 3

5.3 Thermal Information.................................................. 3

5.4 Power Block Performance ........................................ 3

5.5 Electrical Characteristics........................................... 4

5.6 Typical Power Block Device Characteristics............. 5

5.7 Typical Power Block MOSFET Characteristics......... 7

Applications and Implementation ...................... 10

6.1 Application Information............................................ 10

6.2 Power Loss Curves ................................................ 12

6.3 Safe Operating Curves (SOA) ................................ 12

4 修订历史记录

Changes from Revision A (October 2017) to Revision B

Page

•

Updated Figure 33 top layer showing pins 1 and 2 connected. .......................................................................................... 16

Changes from Original (February 2016) to Revision A

Page

•

Corrected X & Y axis labels on Figure 29 ............................................................................................................................ 11

Corrected X & Y axis labels on Figure 30 ............................................................................................................................ 11

CSD87335Q3D

www.ti.com.cn

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

5 Specifications

5.1 Absolute Maximum Ratings

T_A= 25°C (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V_INto P_GND

V_SWto P_GND

Voltage

V_SWto P_GND(10 ns)

T_Gto T_GR

–8

B_Gto P_GND

(2)

Pulsed current rating, I_DM

Power dissipation, P_D

Sync FET, I_D= 51 A, L = 0.1 mH

Control FET, I_D= 33 A, L = 0.1 mH

130

Avalanche energy, E_AS

°C

Operating junction and storage temperature, T_J, T_STG

–55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Pulse duration ≤ 50 µs, duty cycle ≤ 1%.

5.2 Recommended Operating Conditions

T_A= 25°C (unless otherwise noted)

MIN

MAX

UNIT

V_GS

V_IN

Gate drive voltage

Input supply voltage

Switching frequency

Operating current

4.5

ƒ_SW

C_BST= 0.1 µF (min)

1500

kHz

T_J

Operating temperature

125

°C

5.3 Thermal Information

T_A= 25°C (unless otherwise stated)

THERMAL METRIC

MIN

TYP

MAX UNIT

Junction-to-ambient thermal resistance (min Cu)⁽¹⁾

Junction-to-ambient thermal resistance (max Cu)⁽¹⁾⁽²⁾

Junction-to-case thermal resistance (top of package)⁽¹⁾

Junction-to-case thermal resistance (P_GNDpin)⁽¹⁾

135

°C/W

R_θJA

R_θJC

(1)

°C/W

2.5

_θJCis determined with the device mounted on a 1-in²(6.45-cm²), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in

(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. R_θJCis specified by design while R_θJAis determined by the user’s board

design.

(2) Device mounted on FR4 material with 1-in²(6.45-cm²) Cu.

5.4 Power Block Performance⁽¹⁾

T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

1.5

MAX UNIT

V_IN= 12 V, V_GS= 5 V, V_OUT= 1.3 V,

I_OUT= 15 A, ƒ_SW= 500 kHz,

L_OUT= 950 nH, T_J= 25°C

P_LOSS

I_QVIN

Power loss⁽¹⁾

V_INquiescent current

T_Gto T_GR= 0 V, B_Gto P_GND= 0 V

µA

(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins and

using a high-current 5-V driver IC.

CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

www.ti.com.cn

5.5 Electrical Characteristics

T_A= 25°C (unless otherwise stated)

Q1 Control FET

Q2 Sync FET

PARAMETER

TEST CONDITIONS

UNIT

MAX

MIN

TYP

MAX

MIN

TYP

STATIC CHARACTERISTICS

BV_DSS

Drain-to-source voltage

V_GS= 0 V, I_DS= 250 µA

V_GS= 0 V, V_DS= 24 V

Drain-to-source leakage

current

I_DSS

100

1.9

100

µA

Gate-to-source leakage

current

V_DS= 0 V,

V_GS= +10 V / –8 V

I_GSS

Gate-to-source threshold

voltage

V_GS(th)

V_DS= V_GS, I_DS= 250 µA

1.0

0.75

1.20

V_IN= 12 V, V_GS= 5 V,

V_OUT= 1.3 V, I_OUT= 15 A,

ƒ_SW= 500 kHz,

Z_DS(on)

Effective AC on-impedance

Transconductance

6.7

1.9

mΩ

L_OUT= 950 nH

g_fs

V_DS= 3 V, I_DS= 15 A

107

DYNAMIC CHARACTERISTICS

C_ISS

C_OSS

C_RSS

R_G

Input capacitance

805

412

1.2

5.7

1.1

2.1

1.1

1050

536

1620

783

2100

1020

V_GS= 0 V, V_DS= 15 V,

ƒ = 1 MHz

Output capacitance

Reverse transfer capacitance

Series gate resistance

Gate charge total (4.5 V)

Gate charge – gate-to-drain

Gate charge – gate-to-source

Gate charge at Vth

Output charge

2.4

0.6

10.7

1.7

2.8

1.4

1.2

Q_g

7.4

14.0

Q_gd

Q_gs

Q_g(th)

Q_OSS

t_d(on)

t_r

V_DS= 15 V,

I_DS= 15 A

V_DS= 15 V, V_GS= 0 V

Turnon delay time

Rise time

V_DS= 15 V, V_GS= 4.5 V,

I_DS= 15 A, R_G= 2 Ω

t_d(off)

t_f

Turnoff delay time

Fall time

DIODE CHARACTERISTICS

V_SD

Q_rr

t_rr

Diode forward voltage

Reverse recovery charge

Reverse recovery time

I_DS= 15 A, V_GS= 0 V

0.8

1.0

0.8

1.0

V_DS= 15 V, I_F= 15 A,

di/dt = 300 A/µs

Max R_θJA= 135°C/W

when mounted on

minimum pad area of

2-oz. (0.071-mm) thick

Cu.

Max R_θJA= 73°C/W

when mounted on 1 in²

(6.45 cm²) of 2-oz

(0.071-mm) thick Cu.

CSD87335Q3D

www.ti.com.cn

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

5.6 Typical Power Block Device Characteristics

Test conditions: V_IN= 12 V, V_DD= 5 V, ƒ_SW= 500 kHz, V_OUT= 1.3 V, L_OUT= 950 nH, I_OUT= 25 A, T_J= 125°C, unless stated

otherwise.

1.05

0.95

0.9

0.85

0.8

0.75

0.7

0.65

0.6

0.55

-50

-25

100

125

150

Output Current (A)

Junction Temperature (èC)

D001

D002

Figure 1. Power Loss vs Output Current

Figure 2. Power Loss vs Temperature

400 LFM

200 LFM

100 LFM

Nat. conv.

Ambient Temperature (èC)

D004

Figure 3. Safe Operating Area – PCB Horizontal Mount⁽¹⁾

(1) The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with

dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Applications and

Implementation section for detailed explanation.

CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

www.ti.com.cn

Typical Power Block Device Characteristics (continued)

Test conditions: V_IN= 12 V, V_DD= 5 V, ƒ_SW= 500 kHz, V_OUT= 1.3 V, L_OUT= 950 nH, I_OUT= 25 A, T_J= 125°C, unless stated

otherwise.

105 120 135

Board Temperature (èC)

D005

Figure 4. Typical Safe Operating Area⁽¹⁾

1.6

1.5

1.4

1.3

1.2

1.1

10.2

8.5

6.8

5.1

3.4

1.7

0.0

-1.7

-3.4

1.25

1.2

4.3

3.4

2.6

1.7

0.9

0.0

-0.9

-1.7

1.15

1.1

1.05

0.95

0.9

0.8

50 200 350 500 650 800 950 1100 1250 1400 1550

Input Voltage (V)

Switching Frequency (kHz)

D006

D007

Figure 5. Normalized Power Loss vs Switching Frequency

Figure 6. Normalized Power Loss vs Input Voltage

1.35

5.8

5.0

4.2

3.3

2.5

1.7

0.8

0.0

-0.8

-1.7

1.3

1.2

1.1

5.1

1.3

1.25

1.2

3.4

1.7

0.0

-1.7

-3.4

1.15

1.1

1.05

0.9

0.95

0.9

0.8

0.7

1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7

Output Voltage (V)

200

350

500

650

800

950

1100

Output Inductance (nH)

D008

D009

Figure 7. Normalized Power Loss vs Output Voltage

Figure 8. Normalized Power Loss vs Output Inductance

CSD87335Q3D

www.ti.com.cn

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

5.7 Typical Power Block MOSFET Characteristics

T_A= 25°C, unless stated otherwise.

100

V_GS= 4.5 V

V_GS= 6 V

V_GS= 8.0 V

V_GS= 4.5 V

V_GS= 6 V

V_GS= 8.0 V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.1

0.2

0.3

0.4

0.5

0.6

V_DS- Drain-to-Source Voltage (V)

D010

Figure 9. Control MOSFET Saturation

Figure 10. Sync MOSFET Saturation

100

T_C= 125°C

T_C= 25°C

T_C= -55°C

T_C= 125°C

T_C= 25°C

T_C= -55°C

0.1

0.01

0.001

0.01

0.001

0.5

1.5

2.5

0.5

1.5

2.5

3.5

V_GS- Gate-to-Source Voltage (V)

D011

V_DS= 5 V

Figure 12. Sync MOSFET Transfer

Figure 11. Control MOSFET Transfer

Q_g- Gate Charge (nC)

D012

I_D= 15 A

V_DD= 15 V

I_D= 15 A

V_DD= 15 V

Figure 13. Control MOSFET Gate Charge

Figure 14. Sync MOSFET Gate Charge

CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

www.ti.com.cn

Typical Power Block MOSFET Characteristics (continued)

T_A= 25°C, unless stated otherwise.

5000

10000

1000

100

1000

100

C_iss= C_gd+ C_gs

C_oss= C_ds+ C_gd

C_rss= C_gd

C_iss= C_gd+ C_gs

C_oss= C_ds+ C_gd

C_rss= C_gd

V_DS- Drain-to-Source Voltage (V)

D013

Figure 15. Control MOSFET Capacitance

Figure 16. Sync MOSFET Capacitance

1.8

1.6

1.4

1.2

1.3

1.2

1.1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.8

0.6

-75 -50 -25

75 100 125 150 175

-75 -50 -25

75 100 125 150 175

T_C- Case Temperature (°C)

D014

I_D= 250 µA

Figure 17. Control MOSFET V_GS(th)

Figure 18. Sync MOSFET V_GS(th)

T_C= 25°C, I _D= 15 A

T_C= 125°C, I _D= 15 A

T_C= 25°C, I _D= 15 A

T_C= 125°C, I _D= 15 A

V_GS- Gate-to-Source Voltage (V)

D014

Figure 19. Control MOSFET R_DS(on)vs V_GS

Figure 20. Sync MOSFET R_DS(on)vs V_GS

CSD87335Q3D

www.ti.com.cn

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

Typical Power Block MOSFET Characteristics (continued)

T_A= 25°C, unless stated otherwise.

1.6

1.4

1.2

1.6

1.4

1.2

V_GS= 4.5 V

V_GS= 8.0 V

V_GS= 4.5 V

V_GS= 8.0 V

0.8

0.6

0.8

0.6

-75 -50 -25

75 100 125 150 175

-75 -50 -25

75 100 125 150 175

T_C- Case Temperature (°C)

D016

I_D= 15 A

V_GS= 4.5 V

I_D= 15 A

V_GS= 4.5 V

Figure 21. Control MOSFET Normalized R_DS(on)

Figure 22. Sync MOSFET Normalized R_DS(on)

100

T_C= 25°C

T_C= 125°C

0.1

0.01

0.001

0.0001

0.01

0.001

0.0001

0.2

0.4

0.6

0.8

0.2

0.4

0.6

0.8

V_SD- Source-to-Drain Voltage (V)

D017

Figure 23. Control MOSFET Body Diode

Figure 24. Sync MOSFET Body Diode

100

T_C= 25è C

T_C= 125è C

T_C= 25è C

T_C= 125è C

0.01

0.1

0.01

0.1

T_AV- Time in Avalanche (ms)

D018

Figure 25. Control MOSFET Unclamped Inductive Switching

Figure 26. Sync MOSFET Unclamped Inductive Switching

CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

www.ti.com.cn

6 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

6.1 Application Information

6.1.1 Equivalent System Performance

Many of today’s high-performance computing systems require low-power consumption in an effort to reduce

system operating temperatures and improve overall system efficiency. This has created a major emphasis on

improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an

emphasis in improving the performance of the critical power semiconductor in the power stage of this application

(see Figure 27). As such, optimization of the power semiconductors in these applications, needs to go beyond

simply reducing R_DS(ON)

Power Stage

Components

Power Block

Components

C_i

Input

Supply

Control

FET

Driver

PWM

L_o

I_L

Switch

Node

C_o

Sync

FET

Load

Figure 27. Equivalent System Schematic

The CSD87335Q3D is part of TI’s power block product family which is a highly optimized product for use in a

synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest

generation silicon which has been optimized for switching performance, as well as minimizing losses associated

with Q_GD, Q_GS, and Q_RR. Furthermore, TI’s patented packaging technology has minimized losses by nearly

eliminating parasitic elements between the control FET and sync FET connections (see Figure 28). A key

challenge solved by TI’s patented packaging technology is the system level impact of Common Source

Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases

switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the

MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system

efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI

and modification of switching loss equations are outlined in Power Loss Calculation With Common Source

Inductance Consideration for Synchronous Buck Converters (SLPA009).

CSD87335Q3D

www.ti.com.cn

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

Application Information (continued)

Input

Supply

R_PCB

C_ESR

L_DRAIN

C_INPUT

Control

FET

Driver

PWM

C_ESL

L_SOURCE

Switch

Node

L_o

C_o

I_L

Load

L_DRAIN

C_TOTAL

Sync

FET

Driver

L_SOURCE

Figure 28. Elimination of Parasitic Inductances

The combination of TI’s latest generation silicon and optimized packaging technology has created a

benchmarking solution that outperforms industry standard MOSFET chipsets of similar R_DS(ON)and MOSFET

chipsets with lower R_DS(ON). Figure 29 and Figure 30 compare the efficiency and power loss performance of the

CSD87335Q3D versus industry standard MOSFET chipsets commonly used in this type of application. This

comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The

performance of CSD87335Q3D clearly highlights the importance of considering the effective AC on-impedance

(Z_DS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET

R_DS(ON)specifications is not an indicator of the actual in-circuit performance when using TI’s power block

technology.

6.0

5.5

5.0

4.5

4.0

3.5

PowerBlock HS/LS R_DS(ON)= 6.7 mW/3.1 mW

PowerBlock HS/LS R_DS(ON)= 6.7 mW/1.9 mW

V_GS= 5 V

V_IN= 12 V

V_OUT= 1.3 V

V_GS= 5 V

_IN= 12 V

V_OUT= 1.3 V

3.0 L_OUT= 950 nH

f_SW= 500 kHz

T_A= 25èC

L_OUT= 950 nH

_SW= 500 kHz

2.5

2.0

1.5

1.0

0.5

0.0

T_A= 25èC

PowerBlock HS/LS R_DS(ON)= 6.7 mW/3.1 mW

PowerBlock HS/LS R_DS(ON)= 6.7 mW/1.9 mW

Output Current (A)

D030

D031

Figure 29. Efficiency

Figure 30. Power Loss

CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

www.ti.com.cn

Application Information (continued)

Table 1 compares the traditional DC measured R_DS(ON)of CSD87335Q3D versus its Z_DS(ON). This comparison

takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when

comparing TI’s power block products to individually packaged discrete MOSFETs or dual MOSFETs in a

standard package, the in-circuit switching performance of the solution must be considered. In this example,

individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC

measured R_DS(ON)values that are equivalent to CSD87335Q3D’s Z_DS(ON)value in order to have the same

efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete

MOSFETs or dual MOSFETs in a standard package.

Table 1. Comparison of R_DS(ON)vs. Z_DS(ON)

PARAMETER

TYP

6.7

MAX

—

TYP

1.9

MAX

—

Effective AC on-impedance Z_DS(ON)(V_GS= 5 V)

DC measured R_DS(ON)(V_GS= 4.5 V)

6.7

8.1

3.1

3.9

The CSD87335Q3D NexFET™ power block is an optimized design for synchronous buck applications using 5-V

gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and

highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems-

centric environment. System-level performance curves such as power loss, Safe Operating Area (SOA), and

normalized graphs allow engineers to predict the product performance in the actual application.

6.2 Power Loss Curves

MOSFET centric parameters such as R_DS(ON)and Q_gdare needed to estimate the loss generated by the devices.

In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss

performance curves. Figure 1 plots the power loss of the CSD87335Q3D as a function of load current. This curve

is measured by configuring and running the CSD87335Q3D as it would be in the final application (see

Figure 31).The measured power loss is the CSD87335Q3D loss and consists of both input conversion loss and

gate drive loss. Equation 1 is used to generate the power loss curve.

(V_IN× I_IN) + (V_DD× I_DD) – (V_{SW_AVG}× I_OUT) = Power loss

(1)

The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C

under isothermal test conditions.

6.3 Safe Operating Curves (SOA)

The SOA curves in the CSD87335Q3D data sheet provides guidance on the temperature boundaries within an

operating system by incorporating the thermal resistance and system power loss. to Figure 4 outline the

temperature and airflow conditions required for a given load current. The area under the curve dictates the safe

operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) ×

3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.

6.4 Normalized Curves

The normalized curves in the CSD87335Q3D data sheet provides guidance on the power loss and SOA

adjustments based on their application specific needs. These curves show how the power loss and SOA

boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in

power loss and the secondary Y-axis is the change in system temperature required in order to comply with the

SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is

subtracted from the SOA curve.

CSD87335Q3D

www.ti.com.cn

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

Normalized Curves (continued)

Input Current (I_IN)

Gate Drive

Current (I_DD)

V_IN

BOOT

DRVH

V_DD

VDD

Input Voltage (V_IN)

V_IN

Control

Gate Drive

Voltage (V_DD)

T_G

FET

ENABLE

PWM

Output Current (I_OUT

V_OUT

)

V_SW

T_GR

Sync

FET

PWM

B_G

DRVL

GND

P_GND

Averaged Switch

V Node Voltage

Averaging

Circuit

CSD87335Q3D

Driver IC

(V_{SW_AVG}

)

Figure 31. Typical Application

6.5 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example section).

Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the

following procedure will outline the steps the user should take to predict product performance for any set of

system conditions.

6.5.1 Design Example

Operating conditions:

•

Output current = 15 A

Input voltage = 14 V

Output voltage = 1.4 V

Switching frequency = 750 kHz

Inductor = 600 nH

6.5.2 Calculating Power Loss

•

Power loss at 15 A = 1.92 W (Figure 1)

Normalized power loss for input voltage ≈ 1.01 (Figure 6)

Normalized power loss for output voltage ≈ 1.01 (Figure 7)

Normalized power loss for switching frequency ≈ 1.08 (Figure 5)

Normalized power loss for output inductor ≈ 1.01 (Figure 8)

Final calculated power loss = 1.92 W × 1.01 × 1.01 × 1.08 × 1.01 ≈ 2.14 W

6.5.3 Calculating SOA Adjustments

•

SOA adjustment for input voltage ≈ 0.14°C (Figure 6)

SOA adjustment for output voltage ≈ 0.17°C (Figure 7)

SOA adjustment for switching frequency ≈ 1.32°C (Figure 5)

SOA adjustment for output inductor ≈ 0.18°C (Figure 8)

Final calculated SOA adjustment = 0.14 + 0.17 + 1.32 + 0.18 ≈ 1.81°C

CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

www.ti.com.cn

Calculating Power Loss and SOA (continued)

In the design example above, the estimated power loss of the CSD87335Q3D would increase to 2.14 W. In

addition, the maximum allowable board and/or ambient temperature would have to decrease by 1.81°C.

Figure 32 graphically shows how the SOA curve would be adjusted accordingly.

1. Start by drawing a horizontal line from the application current to the SOA curve.

2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.

3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient

temperature of 1.81°C. In the event the adjustment value is a negative number, subtracting the negative number

would yield an increase in allowable board/ambient temperature.

Figure 32. Power Block SOA

CSD87335Q3D

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ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

7 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and

thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief

description on how to address each parameter is provided.

7.1 Electrical Performance

The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then

taken with the PCB layout design and placement of the input capacitors, driver IC, and output inductor.

•

The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 33).

The example in Figure 33 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).

Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias

interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and C8

should follow in order.

•

The driver IC should be placed relatively close to the power block gate pins. T_Gand B_Gshould connect to the

outputs of the driver IC. The T_GRpin serves as the return path of the high-side gate drive circuitry and should

be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for

the driver IC will also connect to this pin.

The switching node of the output inductor should be placed relatively close to the power block VSW pins.

Minimizing the node length between these two components will reduce the PCB conduction losses and

actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches

undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the

peak ring level. The recommended boost resistor value will range between 1 Ω to 4.7 Ω depending on the

output characteristics of driver IC used in conjunction with the power block. The RC snubber values can

range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to Snubber Circuits:

Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber values.

(1)

The RC snubber should be placed as close as possible to the Vsw node and PGND (see Figure 33).

(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

www.ti.com.cn

7.2 Thermal Performance

The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

•

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

Use the smallest drill size allowed in your design. The example in Figure 33 uses vias with a 10-mil drill hole

and a 16-mil capture pad.

•

Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

Figure 33. Recommended PCB Layout (Top Down)

CSD87335Q3D

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ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

8 器件和文档支持

8.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

8.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

8.3 商标

NexFET, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

8.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

8.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

www.ti.com.cn

9 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

9.1 Q3D 封装尺寸

毫米

最小值

英寸

最小值

DIM

最大值

1.500

0.400

最大值

0.059

0.016

1.400

0.280

0.055

0.011

0.310（标称值）

0.150

0.012（标称值）

0.006

0.250

1.040

0.260

0.250

0.350

0.275

3.400

2.750

3.400

1.850

0.010

0.041

0.010

0.014

0.011

0.134

0.108

0.134

0.073

0.150

0.006

0.940

0.037

0.160

0.006

0.150

0.006

0.250

0.010

0.175

0.007

3.200

0.126

2.650

0.104

3.200

0.126

3.200

0.126

1.750

0.069

0.650 典型值

0.400

0.026 典型值

0.016

0.500

—

0.020

—

0.00

—

0.300 典型值

0.012 典型值

CSD87335Q3D

www.ti.com.cn

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

9.2 焊盘布局建议

1.900 (0.075)

0.200

(0.008)

0.210

(0.008)

0.350 (0.014)

0.440

(0.017)

0.650

(0.026)

2.800

(0.110)

2.390

(0.094)

1.090

(0.043)

0.210

(0.008)

0.300 (0.012)

0.650 (0.026)

3.600 (0.142)

M0193-01

NOTE: 尺寸单位为 mm（英寸）。

9.3 模板建议

0.160 (0.005)

0.550 (0.022)

0.200 (0.008)

0.300 (0.012)

0.300

(0.012)

0.340

(0.013)

2.290

(0.090)

0.333

(0.013)

0.990

(0.039)

0.100

(0.004)

0.350 (0.014)

0.300 (0.012)

0.850 (0.033)

3.500 (0.138)

M0207-01

NOTE: 尺寸单位为 mm（英寸）。

如需了解针对 PCB 设计的建议电路布局，请参阅《通过 PCB 布局技巧来减少振铃》(SLPA005)。

CSD87335Q3D

ZHCSEO0B –FEBRUARY 2016–REVISED APRIL 2018

www.ti.com.cn

9.4 Q3D 卷带信息

4.00 0.ꢀ0 ꢁ(SS ꢂNoS ꢀ1

8.00 0.ꢀ0

2.00 0.0ꢃ

Ø ꢀ.ꢃ0

+0.ꢀ0

–0.00

3.60

M0ꢀ44-0ꢀ

NOTES: 1. 10 链轮孔距累积容差为 ±0.2

2. 每 100mm 长度的翘曲不能超过 1mm，在 250mm 长度上不累积。

3. 材料：黑色抗静电聚苯乙烯。

4. 全部尺寸单位为 mm，除非另外注明。

5. 厚度：0.3 ± 0.05mm。

6. 符合 MSL1 260°C（红外和对流）PbF 回流焊要求。

9.5 引脚配置

位置

名称

V_IN

引脚 1

引脚 2

引脚 3

引脚 4

引脚 5

引脚 6

引脚 7

引脚 8

引脚 9

V_IN

T_G

T_GR

B_G

V_SW

P_GND

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

2500

250

(1)

(2)

(3)

(4/5)

(6)

CSD87335Q3D

CSD87335Q3DT

ACTIVE

LSON-CLIP

DQZ

RoHS-Exempt

& Green

NIPDAU | SN

Level-1-260C-UNLIM

-55 to 150

87335D

ACTIVE

DQZ

RoHS-Exempt

& Green

NIPDAU | SN

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

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CSD87335Q3D [TI]

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