CSD87355Q5D [TI]
采用 5mm x 6mm SON 封装的 45A、30V、N 沟道同步降压 NexFET™ 功率 MOSFET 电源块;
| 型号： | CSD87355Q5D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 5mm x 6mm SON 封装的 45A、30V、N 沟道同步降压 NexFET™ 功率 MOSFET 电源块 开关 光电二极管 |
| 文件： | 总24页 (文件大小：988K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD87355Q5D
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
CSD87355Q5D 同步降压 NexFET™电源块
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
•
半桥电源块
CSD87355Q5D NexFET™电源块是面向同步降压 应
用 的优化设计方案，能够以 5mm × 6mm 的小巧外形
提供高电流、高效率以及高频率性能。该产品针对 5V
栅极驱动 应用进行了优化，在与外部控制器/驱动器的
任一 5V 栅极驱动配套使用时，可提供一套灵活的解决
方案来实现高密度电源。
25A 电流时系统效率达 92.5%
工作电流高达 45A
高频工作（高达 1.5MHz）
高密度 SON 5mm × 6mm 封装
针对 5V 栅极驱动进行了优化
低开关损耗
增加文本，调节间距
顶视图
超低电感封装
符合 RoHS 标准
VIN
VIN
TG
VSW
VSW
VSW
1
2
3
4
8
7
6
5
无卤素
无铅引脚镀层
PGND
(Pin 9)
2 应用范围
TGR
BG
•
同步降压转换器
P0116-01
–
–
高频 应用
.
高电流、低占空比 应用
订购信息(1)
数量
•
•
•
多相位同步降压转换器
器件
介质
封装
出货
卷带
负载点 (POL) 直流 - 直流转换器
CSD87355Q5D
13 英寸卷带 2500 5mm x 6mm 小外形
尺寸无引线 (SON)
IMVP、VRM 和 VRD 电感式触控不锈钢键盘参考
设计
CSD87355Q5DT
7 英寸卷带
250
塑料封装
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
增加文本，调节间距
增加文本，调节间距
增加文本，调节间距
典型电路
典型电源块效率与功率损耗
96
94
92
90
88
86
84
82
80
78
76
74
11
10
9
VIN
BOOT
DRVH
VDD
VDD
GND
VIN
Control
FET
TG
8
VSW
TGR
VOUT
7
LL
VGS = 5 V
ENABLE
PWM
ENABLE
PWM
V
IN = 12 V
6
Sync
FET
VOUT = 1.3 V
BG
DRVL
5
LOUT = 0.29
SW = 500 kHz
TA = 25
mH
PGND
f
CSD87355Q5D
4
Driver IC
èC
3
2
1
0
0
5
10
15
20
25
30
35
40
45
Output Current (A)
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS575
CSD87355Q5D
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
www.ti.com.cn
目录
6.1 Application Information............................................ 10
6.2 Typical Application .................................................. 13
Layout ................................................................... 15
7.1 Layout Guidelines ................................................... 15
7.2 Layout Example ...................................................... 16
器件和文档支持...................................................... 17
8.1 社区资源.................................................................. 17
8.2 商标......................................................................... 17
8.3 静电放电警告........................................................... 17
8.4 Glossary.................................................................. 17
机械、封装和可订购信息 ....................................... 18
9.1 Q5D 封装尺寸 ......................................................... 18
9.2 焊盘布局建议........................................................... 19
9.3 模板建议.................................................................. 19
1
2
3
4
5
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Specifications......................................................... 3
5.1 Absolute Maximum Ratings ...................................... 3
5.2 Handling Ratings....................................................... 3
5.3 Recommended Operating Conditions....................... 3
5.4 Thermal Information.................................................. 3
5.5 Power Block Performance ........................................ 3
5.6 Electrical Characteristics........................................... 4
5.7 Typical Power Block Device Characteristics............. 5
5.8 Typical Power Block MOSFET Characteristics......... 7
Application and Implementation ........................ 10
7
8
9
6
4 修订历史记录
Changes from Original (March 2016) to Revision A
Page
•
•
Added footnote for ZDS(ON) in the Electrical Characteristics table. ......................................................................................... 4
已删除 Q5D 卷带封装信息 部分............................................................................................................................................ 19
2
版权 © 2016–2017, Texas Instruments Incorporated
CSD87355Q5D
www.ti.com.cn
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted)(1)
MIN
–0.8
–8
MAX
30
UNIT
V
VIN to PGND
Voltage
TG to TGR
10
V
BG to PGND
–8
10
V
(2)
Pulsed current rating, IDM
Power dissipation, PD
120
12
A
W
Sync FET, ID = 89 A, L = 0.1 mH
Control FET, ID = 50 A, L = 0.1 mH
396
125
150
mJ
mJ
°C
Avalanche energy EAS
Operating junction temperature, TJ
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse duration ≤ 50 µS. Duty cycle ≤ 0.01.
5.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–55
150
°C
5.3 Recommended Operating Conditions
TA = 25° (unless otherwise noted)
MIN
MAX UNIT
VGS
VIN
Gate drive voltage
4.5
10
27
V
V
Input supply voltage
ƒSW
Switching frequency CBST = 0.1 μF (min)
Operating current
200
1500
45
kHz
A
TJ
Operating temperature
125
°C
5.4 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX UNIT
102 °C/W
50 °C/W
20 °C/W
Junction-to-ambient thermal resistance (min Cu)(1)(2)
Junction-to-ambient thermal resistance (max Cu)(1)(2)
Junction-to-case thermal resistance (top of package)(2)
Junction-to-case thermal resistance (PGND pin)(2)
RθJA
RθJC
2
°C/W
(1) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu.
(2)
θJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
R
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
5.5 Power Block Performance
TA = 25° (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
2.8
10
MAX
UNIT
W
VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 25 A, ƒSW = 500 kHz,
LOUT = 0.29 µH, TJ = 25ºC
(1)
Power loss, PLOSS
VIN quiescent current, IQVIN
TG to TGR = 0 V ,BG to PGND = 0 V
µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5 V driver IC.
Copyright © 2016–2017, Texas Instruments Incorporated
3
CSD87355Q5D
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
www.ti.com.cn
5.6 Electrical Characteristics
TA = 25°C (unless otherwise stated)
Q1 CONTROL FET
Q2 SYNC FET
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 μA
30
30
V
Drain-to-source leakage current
Gate-to-source leakage current
VGS = 0 V, VDS = 24 V
1
1
100
μA
VDS = 0 V,
VGS = +10 / –8 V
IGSS
100
nA
V
VGS(th)
Gate-to-source threshold voltage
Drain-to-source ON impedance
Transconductance
VDS = VGS, IDS = 250 μA
1.00
1.90 0.75
1.20
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 25 A,
ƒSW = 500 kHz,
(1)
ZDS(ON)
3.9
90
0.9
mΩ
LOUT = 0.29 µH
gfs
VDS = 3 V, IDS = 20 A
151
S
DYNAMIC CHARACTERISTICS
CISS
COSS
CRSS
RG
Input capacitance
1430
716
25
1860
930
32
3570 4640
1730 2240
pF
pF
pF
Ω
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge – gate-to-drain
Gate charge – gate-to-source
Gate charge at Vth
Output charge
52
67
0.6
10.5
2.3
3.2
1.7
18
1.2
0.7
1.4
Qg
13.7
24.3 31.5
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
QOSS
td(on)
tr
4.1
5.6
2.8
40
10
14
27
6
VDS = 15 V,
IDS = 20 A
VDS = 15 V, VGS = 0 V
Turn on delay time
Rise time
8
18
VDS = 15 V, VGS = 4.5 V,
IDS = 20 A, RG = 2 Ω
td(off)
tf
Turn off delay time
Fall time
13
3
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
IDS = 20 A, VGS = 0 V
0.8
43
1.0
0.8
82
1.0
V
Reverse recovery charge
Reverse recovery time
nC
ns
Vdd = 17 V, IF = 20 A,
di/dt = 300 A/μs
23.8
32.3
(1) Equivalent based on application testing. See Application and Implementation section for details.
HD
LD
HD
LD
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of
2 oz. (0.071-mm thick)
Cu.
Max RθJA = 102°C/W
when mounted on
minimum pad area of
2 oz. (0.071-mm thick)
Cu.
LG HS
LG HS
HG
LS
HG
LS
M0189-01
M0190-01
4
版权 © 2016–2017, Texas Instruments Incorporated
CSD87355Q5D
www.ti.com.cn
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
5.7 Typical Power Block Device Characteristics
TJ = 125°C, unless stated otherwise. The Typical Power Block System Characteristic curves 图 3, , and 图 4 are based on
measurements made on a PCB design with dimensions of 4” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1-oz. copper
thickness. See Application and Implementation for detailed explanation.
10
9
8
7
6
5
4
3
2
1
0
1.1
1
0.9
0.8
0.7
0.6
0.5
0
5
10
15
20
25
30
35
40
45
-50
-25
0
25
50
75
100
125
150
Output Current (A)
Junction Temperature (èC)
D001
D002
VIN = 12 V
ƒSW = 500 kHz
VGS = 5 V
VOUT = 1.3 V
VIN = 12 V
VGS = 5 V
VOUT = 1.3 V
LOUT = 0.29 µH
ƒSW = 500 kHz
LOUT = 0.29 µH
图 1. Power Loss vs Output Current
图 2. Normalized Power Loss vs Temperature
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
400 LFM
200 LFM
100 LFM
Nat. conv.
0
0
0
10
20
30
40
50
60
70
80
90
0
15
30
45
60
75
90
105 120 135
Ambient Temperature (èC)
Board Temperature (èC)
D003
D005
VIN = 12 V
ƒSW = 500 kHz
VGS = 5 V
VOUT = 1.3 V
VIN = 12 V
ƒSW = 500 kHz
VGS = 5 V
VOUT = 1.3 V
LOUT = 0.29 µH
LOUT = 0.29 µH
图 3. Safe Operating Area (SOA) – Thermal Airflow
图 4. Typical Safe Operating Area (SOA)
Measurement PCB Vertical Mount
版权 © 2016–2017, Texas Instruments Incorporated
5
CSD87355Q5D
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
www.ti.com.cn
Typical Power Block Device Characteristics (接下页)
TJ = 125°C, unless stated otherwise. The Typical Power Block System Characteristic curves 图 3, , and 图 4 are based on
measurements made on a PCB design with dimensions of 4” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1-oz. copper
thickness. See Application and Implementation for detailed explanation.
1.5
1.4
1.3
1.2
1.1
1
17.4
13.9
10.4
7.0
1.35
11.7
10.0
8.3
1.3
1.25
1.2
6.7
1.15
1.1
5.0
3.3
3.5
1.05
1
1.7
0.0
0.0
0.9
0.8
-3.5
-7.0
0.95
0.9
-1.7
-3.3
50 200 350 500 650 800 950 1100 1250 1400 1550
0
3
6
9
12
15
18
Switching Frequency (kHz)
Input Voltage (V)
D006
D007
VIN = 12 V
LOUT = 0.29 µH
VGS = 5 V
VOUT = 1.3 V
VIN = 12 V
VOUT = 1.3 V
IOUT = 45 A
LOUT = 0.29 µH
IOUT = 45 A
ƒSW = 500 kHz
图 5. Normalized Power Loss vs Switching Frequency
图 6. Normalized Power Loss vs Input Voltage
1.1
1.075
1.05
1.025
1
3.4
1.8
1.6
1.4
1.2
1
25.7
2.5
19.3
12.9
6.4
1.7
0.8
0.0
0.975
0.95
0.925
-0.8
-1.7
-2.5
0.0
0.8
-6.4
0.5
1.3
2.1
2.9
3.7
4.5
5.3
10
150
290
430
570
710
850
990 1130
Output Voltage (V)
Output Inductance (nH)
D008
D009
VIN = 12 V
VGS = 5 V
IOUT = 45 A
ƒSW = 500 kHz
VIN = 12 V
ƒSW = 500 kHz
VGS = 5 V VOUT = 1.3 V
LOUT = 0.29 µH
IOUT = 45 A
图 7. Normalized Power Loss vs. Output Voltage
图 8. Normalized Power Loss vs Output Inductance
6
版权 © 2016–2017, Texas Instruments Incorporated
CSD87355Q5D
www.ti.com.cn
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
5.8 Typical Power Block MOSFET Characteristics
TA = 25°C, unless stated otherwise.
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
20
VGS = 4.5 V
VGS = 6.0 V
VGS = 8.0 V
VGS = 4.5 V
VGS = 6.0 V
VGS = 8.0 V
10
0
0
0.1
0.2
0.3
0.4
0.5
0
0.04
0.08
0.12
0.16
0.2
VDS - Drain-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
D010
D011
图 9. Control MOSFET Saturation
图 10. Sync MOSFET Saturation
100
100
10
TC = 125°C
TC = 25°C
TC = -55°C
TC = 125°C
TC = 25°C
TC = -55°C
10
1
1
0.1
0.1
0.01
0.001
0.01
0.001
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
3
3.5
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
D013
D012
VDS = 5 V
VDS = 5 V
图 12. Sync MOSFET Transfer
图 11. Control MOSFET Transfer
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0
0
0
0
2
4
6
8
10
12
14
16
18
20
4
8
12 16 20 24 28 32 36 40 44
Qg - Gate Charge (nC)
Qg - Gate Charge (nC)
D014
D015
ID = 20 A
VDD = 15 V
ID = 20 A
VDD = 15 V
图 13. Control MOSFET Gate Charge
图 14. Sync MOSFET Gate Charge
版权 © 2016–2017, Texas Instruments Incorporated
7
CSD87355Q5D
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
www.ti.com.cn
Typical Power Block MOSFET Characteristics (接下页)
TA = 25°C, unless stated otherwise.
10000
1000
100
10
10000
1000
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
1
0
3
6
9
12
15
18
21
24
27
30
0
3
6
9
12
15
18
21
24
27
30
VDS - Drain-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
D016
D017
ƒ = 1 MHz
VGS = 0
ƒ = 1 MHz
VGS = 0
图 15. Control MOSFET Capacitance
图 16. Sync MOSFET Capacitance
1.8
1.6
1.4
1.2
1
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.8
0.6
-75 -50 -25
0
25
50
75 100 125 150 175
-75 -50 -25
0
25
50
75 100 125 150 175
TC - Case Temperature (°C)
TC - Case Temperature (°C)
D018
D019
ID = 250 µA
ID = 250 µA
图 17. Control MOSFET VGS(th)
图 18. Sync MOSFET VGS(th)
8
7
6
5
4
3
2
1
0
14
12
10
8
TC = 25°C, I D = 20 A
TC = 125°C, I D = 20 A
TC = 25°C, I D = 20 A
TC = 125°C, I D = 20 A
6
4
2
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
D020
D021
图 19. Control MOSFET RDS(ON) vs VGS
图 20. Sync MOSFET RDS(ON) vs VGS
8
版权 © 2016–2017, Texas Instruments Incorporated
CSD87355Q5D
www.ti.com.cn
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
Typical Power Block MOSFET Characteristics (接下页)
TA = 25°C, unless stated otherwise.
1.6
1.4
1.2
1
1.6
VGS = 4.5 V
VGS = 8.0 V
VGS = 4.5 V
VGS = 8.0 V
1.4
1.2
1
0.8
0.6
0.8
0.6
-75 -50 -25
0
25
50
75 100 125 150 175
-75 -50 -25
0
25
50
75 100 125 150 175
TC - Case Temperature (èC)
TC - Case Temperature (èC)
D022
D023
ID = 20 A
VGS = 8 V
ID = 20 A
VGS = 8 V
图 21. Control MOSFET Normalized RDS(ON)
图 22. Sync MOSFET Normalized RDS(ON)
100
100
TC = 25èC
TC = 125èC
TC = 25èC
TC = 125èC
10
1
10
1
0.1
0.1
0.01
0.001
0.0001
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
VSD - Source-to-Drain Voltage (V)
VSD - Source-to-Drain Voltage (V)
D024
D025
图 23. Control MOSFET Body Diode
图 24. Sync MOSFET Body Diode
1000
100
10
1000
100
10
TC = 25è C
TC = 125è C
TC = 25è C
TC = 125è C
1
0.01
0.1
1
0.01
0.1
1
TAV - Time in Avalanche (ms)
TAV - Time in Avalanche (ms)
D026
D027
图 25. Control MOSFET Unclamped Inductive Switching
版权 © 2016–2017, Texas Instruments Incorporated
图 26. Sync MOSFET Unclamped Inductive Switching
9
CSD87355Q5D
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
www.ti.com.cn
6 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
The CSD87355Q5D NexFET power block is an optimized design for synchronous buck applications using 5-V
gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems
centric environment. System level performance curves such as Power Loss, Safe Operating Area, and
normalized graphs allow engineers to predict the product performance in the actual application.
6.1.1 Equivalent System Performance
Many of today's high performance computing systems require low power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an
emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this
application (see 图 27). As such, optimization of the power semiconductors in these applications, needs to go
beyond simply reducing RDS(ON)
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10
版权 © 2016–2017, Texas Instruments Incorporated
CSD87355Q5D
www.ti.com.cn
ZHCSEU6A –MARCH 2016–REVISED SEPTEMBER 2017
Application Information (接下页)
The CSD87355Q5D is part of TI’s Power Block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the Control FET and Sync FET connections (see 图 28). A key challenge
solved by TI’s patented packaging technology is the system level impact of Common Source Inductance (CSI).
CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and
reduces system efficiency. As a result, the effects of CSI need to be considered during the MOSFET selection
process. In addition, standard MOSFET switching loss equations used to predict system efficiency need to be
modified in order to account for the effects of CSI. Further details behind the effects of CSI and modification of
switching loss equations are outlined in TI’s Application Note SLPA009.
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