CSD87503Q3E [TI]
采用 3mm x 3mm SON 封装的双路共源极、21.9mΩ、30V、N 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD87503Q3E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 3mm x 3mm SON 封装的双路共源极、21.9mΩ、30V、N 沟道 NexFET™ 功率 MOSFET 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总14页 (文件大小：920K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD87503Q3E
ZHCSGQ9 –SEPTEMBER 2017
CSD87503Q3E 30V N 沟道 NexFET™ 功率 MOSFET
1 特性
产品概要
1
•
•
•
•
•
•
•
•
双 N 沟道共源极 MOSFET
TA = 25°C
值
30
单位
V
针对 5V 栅极驱动器进行了优化
低热阻
VDS
Qg
漏源电压
总栅极电荷 (4.5V)
栅极电荷（栅极到漏极）
13.4
5.8
nC
nC
低 Qg 和 Qgd
Qgd
VGS = 4.5V
VGS = 10V
1.7
17.3
13.5
无铅引脚镀层
符合 RoHS 标准
无卤素
RDD(on)
VGS(th)
漏极到漏极导通电阻
阈值电压
mΩ
V
小外形尺寸无引线 (SON) 3.3mm × 3.3mm 塑料封
装
器件信息(1)
器件
CSD87503Q3E 2500 13 英寸卷带
CSD87503Q3ET 250 7 英寸卷带
数量
包装介质
封装
发货
SON
卷带封
装
2 应用
3.30mm × 3.30mm
塑料封装
•
•
•
USB Type-C/PDVBus 保护
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
电池保护
负载开关
绝对最大额定值
3 说明
TA = 25°C
VDS
值
30
单位
V
漏源电压
CSD87503Q3E 是一款 30V、13.5mΩ、共源极、双路
N 沟道器件，专为 USB Type-C/PD 和电池保护而设
计。此 3.3 × 3.3mm SON 器件具有低漏极至漏极导通
电阻，可最大限度地较少损耗，且具有较少的组件数
量，适用于空间受限的 应用。
VGS
栅源电压
±20
10
V
ID1, D2
持续漏极到漏极电流（受封装限制）
A
IDS
持续漏极到源极电流（受封装限制）
1.5
89
A
ID1, D2M 脉冲漏极到漏极电流(1)
A
PD
PD
功率耗散(2)
2.6
15.6
W
W
功耗，TC = 25°C
顶视图
TJ、
Tstg
工作结温、
储存温度
–55 至 150
°C
(1) 最大 RθJC = 8°C/W，脉冲持续时间 ≤ 100μs，占空比 ≤ 1%。
(2) 典型 RθJA = 50°C/W（当在 0.06 英寸 (1.52mm) 厚的 FR4
PCB 上将其安装在 1 平方英寸 (6.45cm2) 2oz (0.071mm) 厚的
铜焊盘上时）。
RDD(on) 与 VGS 之间的关系
40
TC = 25°C, I D1D2 = 6 A
TC = 125°C, I D1D2 = 6 A
35
30
25
20
15
10
5
电路图像
Gate 1
PIN 1
Gate 2
PIN 3
Drain 1
Drain 2
Pins 7, 8
Pins 5, 6
0
0
2
4
6
8
10
12
14
16
18
20
VG1, VG2 - Gate Voltage (V)
D007
Common Common
Source
Pin 2
Source
Pin 4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS661
CSD87503Q3E
ZHCSGQ9 –SEPTEMBER 2017
www.ti.com.cn
目录
6.1 接收文档更新通知 ..................................................... 7
6.2 社区资源.................................................................... 7
6.3 商标........................................................................... 7
6.4 静电放电警告............................................................. 7
6.5 Glossary.................................................................... 7
机械、封装和可订购信息 ......................................... 8
7.1 Q3 封装尺寸.............................................................. 8
7.2 建议 PCB 布局 .......................................................... 9
7.3 建议模板开口............................................................. 9
1
2
3
4
5
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information.................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
器件和文档支持........................................................ 7
7
6
4 修订历史记录
日期
修订版本
说明
2017 年 9 月
*
初始发行版。
2
Copyright © 2017, Texas Instruments Incorporated
CSD87503Q3E
www.ti.com.cn
ZHCSGQ9 –SEPTEMBER 2017
5
Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage(1)
VGS = 0 V, ID = 250 μA
30
V
μA
nA
V
Drain-to-source leakage current(1)
Gate-to-source leakage current(1)
Gate-to-source threshold voltage(1)
VGS = 0 V, VDS = 24 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 4.5 V, ID1D2 = 6 A
VGS = 10 V, ID1D2 = 6 A
VDS = 3 V, ID1D2 = 6 A
1
100
2.1
IGSS
VGS(th)
1.3
1.7
17.3
13.5
24
21.9
16.9
RDD(on)
gfs
Drain-to-drain on-resistance
Transconductance
mΩ
S
DYNAMIC CHARACTERISTICS
CISS
COSS
CRSS
Rg
Input capacitance
782
157
149
1.5
13.4
32.9
5.8
4.8
1.0
4.3
10
1020
204
194
3.0
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance(1)
Gate charge total (4.5 V)
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
VGS = 0 V, VD1D2 = 15 V, ƒ = 1 MHz
17.4
42.8
Qg
nC
Qgd
Qgs
Qg(th)
QOSS
td(on)
tr
VD1D2 = 15 V, ID1D2 = 6 A
nC
nC
nC
nC
ns
VD1D2 = 15 V, VGS = 0 V
Turnon delay time
Rise time
40
ns
VD1D2 = 15 V, VGS = 10 V, ID1D2 = 6 A,
RG = 0 Ω
td(off)
tf
Turnoff delay time
25
ns
Fall time
8
ns
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage(1)
Reverse recovery charge(1)
Reverse recovery time(1)
ID = 0.5 A, VGS = 0 V
0.75
9.2
14
0.95
V
nC
ns
VDS = 15 V, IF = 6 A, di/dt = 300 A/μs
(1) Parameter measured on both MOSFETs individually. Table values are for a single FET.
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance(1)
Junction-to-ambient thermal resistance(1)(2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJC
RθJA
8
60
(1)
R
θJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-
cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
Copyright © 2017, Texas Instruments Incorporated
3
CSD87503Q3E
ZHCSGQ9 –SEPTEMBER 2017
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Max RθJA = 60°C/W
when mounted on 1 in2
(6.45 cm2) of
2-oz (0.071-mm) thick
Cu.
Max RθJA = 185°C/W
when mounted on a
minimum pad area of
2-oz (0.071-mm) thick
Cu.
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
Copyright © 2017, Texas Instruments Incorporated
CSD87503Q3E
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ZHCSGQ9 –SEPTEMBER 2017
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
80
20
18
16
14
12
10
8
VG1, VG2 = 4.5 V
VG1, VG2 = 6 V
VG1, VG2 = 10 V
TC = 125°C
TC = 25°C
TC = -55°C
70
60
50
40
30
20
10
0
6
4
2
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
2
2.5
3
3.5
4
VD1D2 - Drain-to-Drain Voltage (V)
VG1, VG2 - Gate Voltage (V)
D002
D003
VD1D2 = 5 V
Note: Measurement taken with both gates tied together
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10
9
8
7
6
5
4
3
2
1
0
10000
1000
100
Ciss = CG1D1+CG1S1+CG2S2+CG2D2
Coss = CG1D1+1/(1/CD1S1+1/(CG1S1+CG2S2+CD2S2))
Crss = CG1D1+1/(1/CD1S1+1/(CG1S1+CG2S2))
10
0
5
10
15
20
25
30
35
0
3
6
9
12
15
18
21
24
27
30
Qg - Gate Charge (nC)
VD1D2 - Drain-to-Drain Voltage (V)
D004
D005
ID1D2 = 6 A
VD1D2 = 15 V
Figure 4. Gate Charge
Figure 5. Capacitance
40
35
30
25
20
15
10
5
2.1
1.9
1.7
1.5
1.3
1.1
0.9
TC = 25°C, I D1D2 = 6 A
TC = 125°C, I D1D2 = 6 A
0
0
-75 -50 -25
0
25
50
75 100 125 150 175
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (°C)
VG1, VG2 - Gate Voltage (V)
D006
D007
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
Copyright © 2017, Texas Instruments Incorporated
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CSD87503Q3E
ZHCSGQ9 –SEPTEMBER 2017
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
10
1
2
TC = 25èC
TC = 125èC
VG1, VG2 = 4.5 V
VG1, VG2 = 10 V
1.8
1.6
1.4
1.2
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
-75 -50 -25
0
25
50
75 100 125 150 175
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VD1D2 - Drain-To-Drain Voltage (V)
1
TC - Case Temperature (èC)
D008
D009
ID1D2 = 6 A
VD1D2 = 15 V
Note: Measurement taken with both gates tied together
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
1000
100
10
1
DC
10 ms
1 ms
100 µs
10 µs
TC = 25è C
TC = 125è C
100
10
1
0.1
0.1
1
10
100
0.01
0.1
1
VD1D2 - Drain-To-Drain Voltage (V)
TAV - Time in Avalanche (ms)
D010
D011
Single pulse, max RθJC = 8°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
14
12
10
8
6
4
2
0
-50
-25
0
25
50
75
100 125 150 175
TC - Case Temperature (°C)
D012
Figure 12. Maximum Drain Current vs Temperature
6
Copyright © 2017, Texas Instruments Incorporated
CSD87503Q3E
www.ti.com.cn
ZHCSGQ9 –SEPTEMBER 2017
6 器件和文档支持
6.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
6.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
6.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2017, Texas Instruments Incorporated
7
CSD87503Q3E
ZHCSGQ9 –SEPTEMBER 2017
www.ti.com.cn
7 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
7.1 Q3 封装尺寸
3.4
3.2
A
B
PIN 1 INDEX AREA
3.4
3.2
C
1 MAX
SEATING PLANE
0.08
C
2X 2.09 0.1
PKG
(0.2) TYP
0.53
0.33
0.05
0.00
4X
2X EXPOSED
THERMAL PAD
4
5
2X
1.175 0.1
10
SYMM
2X
1.95
0.35
0.25
8X
9
0.1
C A B
8
0.05
C
1
6X 0.65
0.53
0.33
4X
PIN 1 ID
(OPTIONAL)
4223409/A 12/2016
1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。
2. 本图如有变更，恕不另行通知。
3. 封装散热盘必须在印刷电路板上焊接，包装散热和机械性能。
表 1. 引脚配置
位置
引脚 1
名称
栅极 1
共源极
栅极 2
共源极
漏极 2
漏极 1
引脚 2
引脚 3
引脚 4
引脚 5、6
引脚 7、8
8
版权 © 2017, Texas Instruments Incorporated
CSD87503Q3E
www.ti.com.cn
ZHCSGQ9 –SEPTEMBER 2017
7.2 建议 PCB 布局
(0.325) TYP
(0.675) TYP
SOLDER MASK OPENING
TYP
(0.175)
PADS 9 & 10
4X (0.63)
4X (0.63)
8X (0.3)
1
8
9
(0.763)
TYP
SYMM
6X (0.65)
10
2X (1.18)
5
4
(R0.05) TYP
PKG
0.05 MIN
TYP
(
0.2) VIA
TYP
2X (2.09)
(3.07)
METAL UNDER
SOLDER MASK
TYP
1. 此封装设计用于焊接到电路板的散热焊盘上。更多信息，请参见《QFN/SON
号：SLUA271）。
PCB
连接》（文献编
2. 根据具体应用决定是否选用通孔，请参见器件产品说明书。如需实施任意通孔，请参见此视图上的通孔位置。
建议对焊锡膏下方的通孔进行填充、堵塞或包覆。
3. 本图如有变更，恕不另行通知。
7.3 建议模板开口
METAL UNDER
SOLDER MASK
TYP
PKG
SOLDER MASK
OPENING
TYP
(0.175)
4X (0.545)
4X (0.63)
1
9
8
8X (0.3)
2X
(0.763)
SYMM
6X (0.65)
2X (1.06)
10
5
4
(R0.05) TYP
2X (1.86)
EXPOSED METAL
TYP
(1.535)
(1.578)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PADS 9 & 10
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
1. 具有漏斗形壁和圆角的激光切割孔可提供更佳的锡膏脱离。IPC-7525 可能提供替代设计建议。
2. 本图如有变更，恕不另行通知。
版权 © 2017, Texas Instruments Incorporated
9
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD87503Q3E
CSD87503Q3ET
ACTIVE
ACTIVE
VSON
VSON
DTD
DTD
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
87503E
87503E
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD87503Q3E
CSD87503Q3ET
VSON
VSON
DTD
DTD
8
8
2500
250
330.0
178.0
12.4
13.5
3.6
3.6
3.6
3.6
1.2
1.2
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD87503Q3E
CSD87503Q3ET
VSON
VSON
DTD
DTD
8
8
2500
250
364.0
189.0
357.0
185.0
31.0
36.0
Pack Materials-Page 2
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不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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