CSD95373BQ5M [TI]

45A 同步降压 NexFET™ 智能功率级;


型号：	CSD95373BQ5M
厂家：	TEXAS INSTRUMENTS
描述：	45A 同步降压 NexFET™ 智能功率级
文件：	总13页 (文件大小：724K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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CSD95373BQ5M

ZHCSCK9A –JUNE 2014–REVISED JULY 2017

CSD95373BQ5M 同步降压 NexFET™智能功率级

1 特性

2 应用

•

持续工作电流可达 45A

•

多相位同步降压转换器

25A 电流下系统效率高达 92.7%

25A 电流下功耗损耗低至 2.6W

高频工作（高达 1.25MHz）

支持强制连续模式 (FCCM) 的二极管仿真模式

温度补偿双向电流感测

–

高频应用

高电流，针对具有宽占空比范围的应用进行优

化

•

多负载点 (POL) 直流/直流转换器

内存和图形卡

台式机和服务器 VR11.x / VR12.x V 内核和存储同

步转换器

模拟温度输出（0°C 时 600mV）

故障监控

–

高端短路、过流和过热保护

3 说明

•

3.3V 和 5V 脉宽调制 (PWM) 信号兼容

三态 PWM 输入

CSD95373BQ5M NexFET™智能功率级的设计针对高

功率、高密度同步降压转换器中的使用进行了高度优

化。此产品集成了驱动器 IC 和功率 MOSFET 以实现

功率级开关功能。该组合可在 5mm x 6mm 小型封装

中实现高电流、高效率以及高速切换功能。它还集成了

准确电流感测和温度感测功能，以简化系统设计并提高

准确度。此外，PCB 封装已经过优化，可帮助减少设

计时间并简化总体系统设计。

集成型自举二极管

用于击穿保护的经优化死区时间

高密度 5mm × 6mm SON 封装

超低电感封装

系统已优化的 PCB 封装

符合 RoHS 环保标准 – 无铅引脚镀层

无卤素

器件信息⁽¹⁾

包装介质

器件

数量

封装

运输

CSD95373BQ5M

2500

13 英寸卷带

SON

5.00mm × 6.00mm

封装

卷带

封装

CSD95373BQ5MT

250

7 英寸卷带

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

应用图表

典型功率级效率与功率损耗

ë_Lb

100

/{59ꢃ373.

ë_hÜÇ

ë_//

V_DD= 5V

V_IN= 12V

V_OUT= 1.2V

L_OUT= .225µH

f_SW= 500kHz

T_A= 25ºC

ë_//

tía1

+L_s1

-L_s2

ë_hÜÇ

{{

Ç{ꢄb

+L_s2

-L_s2

wÇ

tía2

Output Current (A)

G001

t_Db5

aulꢀipꢁꢂse

/onꢀroller

/{59ꢃ373.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLPS462

CSD95373BQ5M

ZHCSCK9A –JUNE 2014–REVISED JULY 2017

www.ti.com.cn

7.1 Typical Application .................................................... 5

器件和文档支持........................................................ 6

8.1 接收文档更新通知 ..................................................... 6

8.2 社区资源.................................................................... 6

8.3 商标........................................................................... 6

8.4 静电放电警告............................................................. 6

8.5 Glossary.................................................................... 6

机械、封装和可订购信息 ......................................... 7

9.1 机械制图.................................................................... 7

9.2 建议印刷电路板 (PCB) 焊盘图案............................... 8

9.3 建议模板开口............................................................. 8

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

Application Schematic .......................................... 5

4 修订历史记录

Changes from Original (June 2014) to Revision A

Page

•

Updated the CSD95373B parts in the Application Schematic................................................................................................ 5

已添加接收文档更新通知改为器件和文档支持部分 ............................................................................................................ 6

已添加社区资源改为器件和文档支持部分........................................................................................................................... 6

CSD95373BQ5M

www.ti.com.cn

ZHCSCK9A –JUNE 2014–REVISED JULY 2017

5 Pin Configuration and Functions

Top View

IOUT

REFIN

ENABLE

PGND

12 PWM

11 TAO/FAULT

10 FCCM

BOOT

VDD

BOOT_R

PGND

VSW

VIN

Pin Functions

DESCRIPTION

NAME

NO.

Bootstrap capacitor connection. Connect a minimum of 0.1-µF, 16-V, X7R ceramic capacitor from BOOT to

BOOT_R pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is

integrated.

BOOT

BOOT_R

ENABLE

Return path for HS gate driver, connected to V_SWinternally.

Enables device operation. If ENABLE = logic HIGH, turns on device. If ENABLE = logic LOW, the device is

turned off and both MOSFET gates are actively pulled low. An internal 100-kΩ pulldown resistor will pull the

ENABLE pin LOW if left floating.

This pin enables the Diode Emulation function. When this pin is held LOW, Diode Emulation Mode is enabled for

sync FET. When FCCM is HIGH, the device is operated in Forced Continuous Conduction Mode. An internal 5-

µA current source will pull the FCCM pin to 3.3 V if left floating.

FCCM

IOUT

P_GND

Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.

Power ground, connected directly to pin 13.

Power ground.

Pulse width modulated tri-state input from external controller. Logic LOW sets control FET gate low and sync

FET gate high. Logic HIGH sets control FET gate high and sync FET gate low. Open or Hi-Z sets both MOSFET

gates low if greater than the tri-state shutdown hold-off time (t_3HT).

PWM

REFIN

External reference voltage input for current sensing amplifier.

Temperature analog output. Reports a voltage proportional to the die temperature. An ORing diode is integrated

in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs.

Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown occurs. TAO

should be bypassed to P_GNDwith a 1-nF, 16-V, X7R ceramic capacitor.

TAO/

FAULT

V_DD

V_IN

Supply voltage to gate driver and internal circuitry.

Input voltage pin. Connect input capacitors close to this pin.

V_SW

Phase node connecting the HS MOSFET source and LS MOSFET drain - pin connection to the output inductor.

CSD95373BQ5M

ZHCSCK9A –JUNE 2014–REVISED JULY 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

T_A= 25°C (unless otherwise noted)⁽¹⁾

MIN

–0.3

–7

MAX

UNIT

V_INto P_GND

V_INto V_SW

V_INto V_SW(10 ns)

V_SWto P_GND

–0.3

–7

V_SWto P_GND(10 ns)

V_DDto P_GND

–0.3

V_DD+ 0.3 V

ENABLE, PWM, FCCM, TAO, IOUT, REFIN to P_GND

BOOT to BOOT_R⁽²⁾

Power dissipation, P_D

Operating junction temperature, T_J

Storage temperature, T_stg

°C

–55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Should not exceed 7 V.

6.2 ESD Ratings

MIN

–2000

–500

MAX

2000

500

UNIT

Human-body model (HBM)

V_(ESD)

Electrostatic discharge

Charged-device model (CDM)

6.3 Recommended Operating Conditions

T_A= 25°C (unless otherwise noted)

MIN

MAX

5.5

UNIT

V_DD

Gate drive voltage

4.5

V_IN

Input supply voltage⁽¹⁾

V_OUT

I_OUT

I_OUT-PK

ƒ_SW

Output voltage

5.5

Continuous output current

Peak output current⁽³⁾

Switching frequency

On-time duty cycle

V_IN= 12 V, V_DD= 5 V, V_OUT= 1.2 V, ƒ_SW= 500 kHz,

L_OUT= 0.225 µH⁽²⁾

C_BST= 0.1 µF (min)

ƒ_SW= 1 MHz

1250

85%

kHz

Minimum PWM on-time

Operating temperature

°C

–40

125

(1) Operating at high V_INcan create excessive AC voltage overshoots on the switch node (V_SW) during MOSFET switching transients. For

reliable operation, the switch node (V_SW) to ground voltage must remain at or below the Absolute Maximum Ratings.

(2) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins.

(3) System conditions as defined in Note 1. Peak output current is applied for t_p= 50 µs.

6.4 Thermal Information

T_A= 25°C (unless otherwise noted)

THERMAL METRIC

Junction-to-case thermal resistance (top of package)⁽¹⁾

Junction-to-board thermal resistance⁽²⁾

MIN

TYP

MAX

UNIT

R_θJC

R_θJB

°C/W

1.5

(1)

(2)

_θJCis determined with the device mounted on a 1-in²(6.45-cm²), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in, 0.06-in (1.52-mm)

thick FR4 board.

_θJBvalue based on hottest board temperature within 1 mm of the package.

CSD95373BQ5M

www.ti.com.cn

ZHCSCK9A –JUNE 2014–REVISED JULY 2017

7 Application Schematic

7.1 Typical Application

12ë

.hhÇ

.hhÇ_w

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TPS53661

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tíꢀ1

tíꢀ

V_{CORE_OUT}

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tDb5

ꢃë

[oad

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h/t-L

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tDb5

ꢃë

B-TMAX

9b!.[9

tDb5

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/{t2

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12ë

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tDb5

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9b!.[9

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LhÜÇ REFIN

SLEW-MODE

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tDb5

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9b!.[9

tDb5

LhÜÇ REFIN

{/[Y

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{5Lh

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12ë

ëw_IhÇ#

PMB_CLK

PMB_ALERT#

PMB_DIO

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L2/ or

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(hpꢂional)

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PWM5

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tDb5

ꢃë

9b!.[9

tDb5

LhÜÇ REFIN

VR_FAULT#

CSP5

12V

12ë

V12

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PWM6

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tDb5

ꢃë

9b!.[9

tDb5

LhÜÇ REFIN

3.3V

ë3w3

CSP6

Db5

CSD95373BQ5M

ZHCSCK9A –JUNE 2014–REVISED JULY 2017

www.ti.com.cn

8 器件和文档支持

8.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到任意产

品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。

8.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

8.3 商标

NexFET, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

8.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

8.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

CSD95373BQ5M

www.ti.com.cn

ZHCSCK9A –JUNE 2014–REVISED JULY 2017

9 机械、封装和可订购信息

以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时，

我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。

9.1 机械制图

Exposed tie clip may vary

0.300 x 45°

毫米

标称值

英寸

DIM

最小值

1.400

0.000

0.200

最大值

1.500

0.050

0.320

最小值

0.057

0.000

0.008

标称值

0.059

0.000

0.010

最大值

1.450

0.000

0.061

0.002

0.013

0.250

2.750 典型值

0.250

0.108 典型值

0.010

0.200

0.320

0.008

0.013

0.250 典型值

0.200

0.010 典型值

0.008

0.150

0.200

5.300

0.200

0.350

1.900

5.900

4.900

3.200

0.250

0.300

5.500

0.300

0.450

2.100

6.100

5.100

3.400

0.006

0.008

0.209

0.008

0.014

0.075

0.232

0.193

0.126

0.010

0.012

0.217

0.012

0.018

0.083

0.240

0.201

0.134

0.250

0.010

5.400

0.213

0.250

0.010

0.400

0.016

2.000

0.079

6.000

0.236

5.000

0.197

3.300

0.130

0.500 典型值

0.350 典型值

0.500

0.020 典型值

0.014 典型值

0.020

0.400

0.210

0.00

0.600

0.410

—

0.016

0.008

0.00

0.024

0.016

—

0.310

0.012

—

CSD95373BQ5M

ZHCSCK9A –JUNE 2014–REVISED JULY 2017

www.ti.com.cn

9.2 建议印刷电路板 (PCB) 焊盘图案

0.331(0.013)

0.370 (0.015)

1.000 (0.039)

0.410 (0.016)

0.550 (0.022)

0.300 (0.012)

2.800

(0.110)

6.300

(0.248)

5.300

(0.209)

5.639

(0.222)

0.500

(0.020)

0.300

(0.012)

R0.127 (R0.005)

3.400

(0.134)

5.900

(0.232)

1. 尺寸单位为 mm（英寸）。

9.3 建议模板开口

0.350(0.014)

2.750

(0.108)

0.250

(0.010)

1. 尺寸单位为 mm（英寸）。

2. 模板厚度为 100µm。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

2500

250

(1)

(2)

(3)

(4/5)

(6)

CSD95373BQ5M

CSD95373BQ5MT

ACTIVE

LSON-CLIP

DQP

RoHS-Exempt

& Green

NIPDAU | SN

Level-2-260C-1 YEAR

-55 to 150

95373BM

ACTIVE

DQP

RoHS-Exempt

& Green

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CSD95373BQ5M

CSD95373BQ5MT

LSON-

CLIP

DQP

2500

250

330.0

12.4

5.3

6.3

1.8

8.0

12.0

LSON-

CLIP

180.0

12.4

5.3

6.3

1.8

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CSD95373BQ5M

CSD95373BQ5MT

LSON-CLIP

DQP

2500

250

346.0

210.0

346.0

185.0

33.0

35.0

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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