CSD95377Q4M [TI]

20V 35A SON 3.5 x 4.5mm 同步降压 NexFET™ 功率级;


型号：	CSD95377Q4M
厂家：	TEXAS INSTRUMENTS
描述：	20V 35A SON 3.5 x 4.5mm 同步降压 NexFET™ 功率级开关光电二极管
文件：	总20页 (文件大小：827K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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CSD95377Q4M

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

CSD95377Q4M 同步降压 NexFET™ 功率级

1 特性

2 应用

•

电流为 15A 时的效率约为 94%

最大额定持续电流 35A

•

服务器、网络互联和电信系统中的负载点同步降压

多相 Vcore、双倍数据速率 (DDR) 和图形解决方案

•

高频运行（高达 2MHz）

高密度 3.5mm × 4.5mm SON 封装

超低电感封装

3 说明

CSD95377Q4M NexFET™功率级的设计针对高功

率、高密度同步降压转换器应用进行了高度优化。此产

品集成了驱动器 IC 和功率 MOSFET，从而可以实现

功率级开关功能。此驱动器 IC 具有内置可选二极管仿

真功能，该功能支持非连续导通模式 (DCM) 运行，从

而提高轻负载效率。该组合在小型 3.5mm x 4.5mm 外

形尺寸封装中提供高电流、高效率和高速开关功能。此

外，PCB 封装已经过优化，可帮助减少设计时间并简

化总体系统设计。

系统优化的 PCB 封装

兼容 3.3V 和 5V PWM 信号

支持强制连续传导模式 (FCCM) 的二极管仿真模式

输入电压最高可达 16V

三态 PWM 输入

集成型自举二极管

击穿保护

符合 RoHS 环保标准-无铅引脚镀层

无卤素

器件信息⁽¹⁾

器件

包装介质

13 英寸卷带 2500

7 英寸卷带 250

数量

封装

发货

CSD95377Q4M

CSD95377Q4MT

3.50mm × 4.50mm

SON 塑料封装

卷带

封装

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

应用图表

典型功率级效率与功率损耗

V_IN

100

CSD95377Q4M

7.5

V_OUT

V_CC

V_DD= 5 V

V_IN= 12 V

V_OUT= 1.8 V

L_OUT= 0.29 mH

f_SW= 500 kHz

T_A= 25èC

4.5

V_CC

PWM1

+I_s1

-I_s2

V_OUT

1.5

-I_s2

+I_s2

Output Current (A)

PWM2

D000

P_GND

Multi-Phase

Controller

CSD95377Q4M

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLPS584

CSD95377Q4M

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

www.ti.com.cn

8.1 Application Information.............................................. 9

8.2 Typical Application ................................................... 9

8.3 System Example ..................................................... 12

Layout ................................................................... 14

9.1 Layout Guidelines ................................................... 14

9.2 Layout Example ...................................................... 14

9.3 Thermal Considerations.......................................... 14

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

Detailed Description .............................................. 6

7.1 Overview ................................................................... 6

7.2 Functional Block Diagram ......................................... 6

7.3 Feature Description................................................... 6

7.4 Device Functional Modes.......................................... 8

Application and Implementation .......................... 9

10 器件和文档支持 ..................................................... 15

10.1 接收文档更新通知 ................................................. 15

10.2 社区资源................................................................ 15

10.3 商标....................................................................... 15

10.4 静电放电警告......................................................... 15

10.5 Glossary................................................................ 15

11 机械、封装和可订购信息....................................... 16

11.1 机械制图................................................................ 16

11.2 建议印刷电路板 (PCB) 焊盘图案........................... 17

11.3 建议模版开口......................................................... 17

4 修订历史记录

Changes from Revision A (January 2017) to Revision B

Page

•

将特性从“最大额定持续电流 30A”改为“最大额定持续电流 35A”............................................................................................. 1

更新了典型功率级效率和功率损耗图以反映 35A 最大电流。................................................................................................. 1

Changed the I_OUTContinuous output current MAX value From: 30 A To: 35 A in the Recommended Operating

Conditions table. .................................................................................................................................................................... 4

•

Updated Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, and Figure 15 to reflect 35

A maximum current. ............................................................................................................................................................ 10

Changed the calculating values in the Design Example to reflect 35 A maximum current. ................................................ 13

Changes from Original (December 2015) to Revision A

Page

•

Changed unit for Hysteresis parameter from mV : to V in the Electrical Characteristics table.............................................. 5

已添加接收文档更新通知部分至器件和文档支持部分.......................................................................................................... 15

CSD95377Q4M

www.ti.com.cn

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

5 Pin Configuration and Functions

SON 3.5 × 4.5 mm

Top View

SKIP#

V_DD

PWM

BOOT

P_GND

BOOT_R

P_GND

V_SW

V_IN

Pin Functions

DESCRIPTION

NO. NAME

This pin enables the diode emulation function. When this pin is held low, Diode Emulation Mode is enabled for the

sync FET. When SKIP# is high, the CSD95377Q4M operates in Forced Continuous Conduction Mode. A tri-state

voltage on SKIP# puts the driver into a very-low power state.

SKIP#

V_DD

Supply voltage to gate drivers and internal circuitry.

P_GND

V_SW

Power ground, needs to be connected to pin 9 and PCB.

Voltage switching node – pin connection to the output inductor.

Input voltage pin. Connect input capacitors close to this pin.

V_IN

BOOT_R

Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic capacitor from BOOT to BOOT_R

pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated.

BOOT

Boot_R is internally connected to V_SW

Pulse width modulated tri-state input from external controller. Logic low sets control FET gate low and sync FET gate

high. Logic high sets control FET gate high and sync FET gate low. Open or Hi-Z sets both MOSFET gates low if

greater than the tri-state shutdown hold-off time (t_3HT).

PWM

P_GND

Power ground.

CSD95377Q4M

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

T_A= 25°C (unless otherwise noted)⁽¹⁾

MIN

–0.3

–7

MAX

UNIT

V_INto P_GND

V_SWto P_GND, V_INto V_SW

V_SWto P_GND, V_INto V_SW(<10 ns)

V_DDto P_GND

–0.3

–2

PWM, SKIP# to P_GND

BOOT to P_GND

BOOT to P_GND(<10 ns)

BOOT to BOOT_R

–0.3

BOOT to BOOT_R (duty cycle < 0.2%)

P_D

T_J

Power dissipation

°C

Operating temperature

Storage temperature

–40

–55

150

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM)⁽¹⁾

Charged-device model (CDM)⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

T_A= 25°C (unless otherwise noted)

MIN

MAX UNIT

V_DD

Gate drive voltage

Input supply voltage

4.5

5.5

(1)

V_IN

I_OUT

I_OUT-PK

ƒ_SW

Continuous output current

Peak output current⁽²⁾⁽³⁾

Switching frequency

V_IN= 12 V, V_DD= 5 V, V_OUT= 1.8 V,

ƒ_SW= 500 kHz, L_OUT= 0.29 µH⁽²⁾

C_BST= 0.1 µF (min)

2000

85%

kHz

On-time duty cycle

Minimum PWM On-time

Operating temperature

°C

–40

125

(1) Operating at high V_INcan create excessive AC voltage overshoots on the switch node (V_SW) during MOSFET switching transients. For

reliable operation, the switch node (V_SW) to ground voltage must remain at or below the Absolute Maximum Ratings.

(2) Peak output current is applied for t_p= 10 ms, duty cycle ≤ 1%.

(3) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins.

6.4 Thermal Information

T_A= 25°C (unless otherwise noted)

THERMAL METRIC

Thermal resistance junction-to-case (top of package)⁽¹⁾

Junction-to-board thermal resistance⁽²⁾

MIN

TYP

MAX UNIT

22.8 °C/W

2.5 °C/W

R_θJC(top)

R_θJB

(1)

(2)

_θJCis determined with the device mounted on a 1-in²(6.45-cm²), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in, 0.06-in (1.52-mm)

thick FR4 board.

_θJBvalue based on hottest board temperature within 1 mm of the package.

CSD95377Q4M

www.ti.com.cn

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

6.5 Electrical Characteristics

T_A= 25°C, V_DD= POR to 5.5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

P_LOSS

V_IN= 12 V, V_DD= 5 V, V_OUT= 1.8 V, I_OUT= 15 A,

ƒ_SW= 500 kHz, L_OUT= 0.29 µH, T_J= 25°C

Power loss⁽¹⁾

1.6

1.8

V_IN= 12 V, V_DD= 5 V, V_OUT= 1.8 V, I_OUT= 15 A,

ƒ_SW= 500 kHz, L_OUT= 0.29 µH, T_J= 125°C

V_IN

I_Q

V_INquiescent current

PWM = float

µA

V_DD

PWM = float, V_SKIP#= V_DDor 0 V

V_SKIP#= float

130

I_DD

Standby supply current

Operating supply current

µA

PWM = 50% duty cycle, ƒ_SW= 500 kHz

8.6

POWER-ON RESET AND UNDERVOLTAGE LOCKOUT

V_DDrising

V_DDfalling

Power-on reset

UVLO

4.15

3.7

Hysteresis

0.2

PWM AND SKIP# I/O SPECIFICATIONS

Pullup to V_DD

1700

800

kΩ

R_I

Input impedance

Pulldown (to GND)

V_IH

Logic level high

2.65

1.3

V_IL

Logic level low

0.6

V_IHH

Hysteresis

0.2

V_TS

Tri-state voltage

t_THOLD(off1)

t_THOLD(off2)

t_TSKF

Tri-state activation time (falling) PWM

Tri-state activation time (rising) PWM

Tri-state activation time (falling) SKIP#

Tri-state activation time (rising) SKIP#

Tri-state exit time PWM⁽²⁾

Tri-state exit time SKIP#⁽²⁾

µs

t_TSKR

t_3RD(PWM)

t_3RD(SKIP#)

BOOTSTRAP SWITCH

V_FBSTForward voltage

I_RLEAK

Reverse leakage⁽²⁾

100

I_F= 10 mA

120

240

µA

V_BOOT– V_DD= 25 V

(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins.

(2) Specified by design.

CSD95377Q4M

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

www.ti.com.cn

7 Detailed Description

7.1 Overview

The CSD95377Q4M™ power stage is a highly-optimized design for use in a high-power, high-density

synchronous buck converter.

7.2 Functional Block Diagram

VDD

BOOT

VIN

DRVL

Control

FET

DRVH

Level Shift

V_UVLO

BOOT_R

VSW

VDD

1 V

1.7Meg

3-State

Logic

SKIP#

800k

VDD

1 V

1.7Meg

Sync

FET

3-State

Logic

DRVL

PWM

800k

PGND

7.3 Feature Description

7.3.1 Powering CSD95377Q4M and Gate Drivers

An external V_DDvoltage is required to supply the integrated gate driver IC and provide the necessary gate drive

power for the MOSFETs. TI recommends a 1-µF, 10-V, X5R or higher ceramic capacitor to bypass V_DDpin to

P_GND. A bootstrap circuit to provide gate drive power for the control FET is also included. The bootstrap supply to

drive the control FET is generated by connecting a 100-nF, 16-V, X5R ceramic capacitor between BOOT and

BOOT_R pins. An optional R_BOOTresistor can be used to slow down the turnon speed of the control FET and

reduce voltage spikes on the V_SWnode. A typical 1-Ω to 4.7-Ω value is a compromise between switching loss

and V_SWspike amplitude.

7.3.2 Undervoltage Lockout (UVLO) Protection

The UVLO comparator evaluates the VDD voltage level. As V_VDDrises, both the control FET and sync FET gates

hold actively low at all times until V_VDDreaches the higher UVLO threshold (V_{UVLO_H}). Then the driver becomes

operational and responds to PWM and SKIP# commands. If VDD falls below the lower UVLO threshold (V_{UVLO_L}

= V_{UVLO_H}– hysteresis), the device disables the driver and drives the outputs of the control FET and Sync FET

gates actively low. Figure 1 shows this function.

CAUTION

Do not start the driver in the very-low power mode (SKIP# = Tri-state).

CSD95377Q4M

www.ti.com.cn

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

Feature Description (continued)

UVLO_H

UVLO_L

VDD

Driver On

UDG-12218

Figure 1. UVLO Operation

7.3.3 PWM Pin

The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when

PWM is driven into the tri-state window and the driver enters a low-power state with zero exit latency. The pin

incorporates a weak pullup to maintain the voltage within the tri-state window during low-power modes.

Operation into and out of tri-state mode follows the timing diagram outlined in Figure 2.

When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The

window is defined as the PWM voltage range between PWM logic high (V_IH) and logic low (V_IL) thresholds. The

device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3-V

(typical) and 5-V (typical) PWM drive signals.

When the PWM exits tri-state, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP#

pin. Normal operation requires this time period for the auto-zero comparator to resume.

Figure 2. PWM Tri-State Timing Diagram

7.3.4 SKIP# Pin

The SKIP# pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP# is

low, the zero crossing (ZX) detection comparator is enabled, and DCM operation occurs if the load current is less

than the critical current. When SKIP# is high, the ZX comparator disables, and the converter enters FCCM mode.

When both SKIP# and PWM are tri-stated, normal operation forces the gate driver outputs low and the driver

enters a low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent current.

When SKIP# is pulled low, the driver wakes up and is able to accept PWM pulses in less than 50 µs.

CSD95377Q4M

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

www.ti.com.cn

Feature Description (continued)

Table 1 shows the logic functions of UVLO, PWM, SKIP#, the control FET gate, and the sync FET gate.

Table 1. Logic Functions of the Driver IC

CONTROL FET

UVLO

PWM

SKIP#

SYNC FET GATE

MODE

GATE

Low

High

Low

Active

Inactive

—

Low

—

Low

High⁽¹⁾

High

Low

Disabled

DCM⁽¹⁾

FCCM

Low

High

Tri-state

—

H or L

Tri-state

Low

LQ⁽²⁾

ULQ⁽³⁾

Low

(1) Until zero crossing protection occurs.

(2) Low-quiescent current (LQ).

(3) Ultra-low quiescent current (ULQ).

7.3.4.1 Zero Crossing (ZX) Operation

The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy

load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current,

which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects

the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the

rectifying MOSFET.

7.3.5 Integrated Boost-Switch

To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the

conventional diode between the VDD pin and the BST pin is replaced by a FET which is gated by the DRVL

signal.

7.4 Device Functional Modes

Table 1 shows the different functional modes of CSD95377. The diode emulation mode is enabled with SKIP#

pulled low, which improves light load efficiency. With PWM in tri-state, the power stage enters LQ mode and the

quiescent current is reduced to 130 µA. When SKIP# is held in tri-state, ULQ mode is enabled and the current is

decreased to 8 µA.

CSD95377Q4M

www.ti.com.cn

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The power stage CSD95377Q4M is a highly-optimized design for synchronous buck applications using NexFET

devices with a 5-V gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest

power loss and highest system efficiency. As a result, a rating method is used that is tailored toward a more

systems-centric environment. The high-performance gate driver IC integrated in the package helps minimize the

parasitics and results in extremely fast switching of the power MOSFETs. System-level performance curves such

as power loss, SOA, and normalized graphs allow engineers to predict the product performance in the actual

application.

8.2 Typical Application

Figure 3. Application Schematic

CSD95377Q4M

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

www.ti.com.cn

Typical Application (continued)

8.2.1 Application Curves

T_J= 125°C, unless stated otherwise.

1.05

Typ

Max

0.95

0.9

0.85

0.8

0.75

0.7

-50

-25

100

125

150

Output Current (A)

T_C- Junction Temperature (èC)

D001

D002

V_IN= 12 V

V_DD= 5 V

V_OUT= 1.8 V

V_IN= 12 V

ƒ_SW= 500 kHz

V_DD= 5 V

V_OUT= 1.8 V

ƒ_SW= 500 kHz

L_OUT= 0.29 µH

Figure 4. Power Loss vs Output Current

Figure 5. Power Loss vs Temperature

400 LFM

200 LFM

100 LFM

Nat. conv.

Min

Typ

90 100

100

120

140

Ambient Temperature (èC)

Board Temperature (èC)

D003

D004

V_IN= 12 V

ƒ_SW= 500 kHz

V_DD= 5 V

V_OUT= 1.8 V

V_IN= 12 V

V_DD= 5 V

V_OUT= 1.8 V

L_OUT= 0.29 µH

ƒ_SW= 500 kHz

L_OUT= 0.29 µH

(1)

Figure 6. Safe Operating Area – PCB Horizontal Mount ⁽¹⁾

Figure 7. Typical Safe Operating Area

1. The typical CSD95377Q4M system characteristic curves are based on measurements made on a PCB

design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.

See System Example for detailed explanation.

CSD95377Q4M

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ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

Typical Application (continued)

T_J= 125°C, unless stated otherwise.

1.35

4.8

4.1

3.4

2.8

2.1

1.4

0.7

0.0

-0.7

-1.4

1.2

1.16

1.12

1.08

1.04

3.2

2.5

1.9

1.3

0.6

0.0

-0.6

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.96

100

300

500

700

900 1100 1300 1500 1700

Switching Frequency (kHz)

Input Voltage (V)

D005

D006

V_IN= 12 V

I_OUT= 35 A

V_DD= 5 V

V_OUT= 1.8 V

I_OUT= 35 A

ƒ_SW= 500 kHz

V_DD= 5 V

V_OUT= 1.8 V

L_OUT= 0.29 µH

Figure 8. Normalized Power Loss vs Frequency

Figure 9. Normalized Power Loss vs Input Voltage

1.5

1.4

1.3

1.2

1.1

7.0

5.6

4.2

2.8

1.4

0.0

-1.4

-2.8

-4.2

-5.6

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

2.9

2.2

1.5

0.7

0.0

-0.7

-1.5

-2.2

0.9

0.8

0.7

0.6

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

Output Voltage (V)

3.3 3.6

145

290

435

580

725

870

1015 1160

Output Inductance (nH)

D007

D008

V_IN= 12 V

V_DD= 5 V

L_OUT= 0.29 µH

I_OUT= 35 A

V_IN= 12 V

ƒ_SW= 500 kHz

V_DD= 5 V

I_OUT= 35 A

ƒ_SW= 500 kHz

V_OUT= 1.8 V

Figure 10. Normalized Power Loss vs Output Voltage

Figure 11. Normalized Power Loss vs Output Inductance

10.2

10.1

9.9

9.8

9.7

9.6

9.5

9.4

9.3

400

800

1200

1600

-75

-50

-25

100 125 150

Switching Frequency (kHz)

T_C- Junction Temperature (èC)

D009

D010

V_IN= 12 V

L_OUT= 0.29 µH

V_DD= 5 V

I_OUT= 35 A

V_IN= 12 V

I_OUT= 35 A

V_DD= 5 V

V_OUT= 1.8 V

L_OUT= 0.29 µH

Figure 12. Driver Current vs Frequency

Figure 13. Driver Current vs Temperature

CSD95377Q4M

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

www.ti.com.cn

8.3 System Example

8.3.1 Power Loss Curves

MOSFET-centric parameters such as R_DS(ON)and Q_gdare primarily needed by engineers to estimate the loss

generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has

provided measured power loss performance curves. Figure 4 plots the power loss of the CSD95377Q4M as a

function of load current. This curve is measured by configuring and running the CSD95377Q4M as it would be in

the final application (see Figure 14). The measured power loss is the CSD95377Q4M device power loss which

consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Power loss = (V_IN× I_IN) + (V_DD× I_DD) – (V_{SW_AVG}× I_OUT

)

(1)

The power loss curve in Figure 4 is measured at the maximum recommended junction temperature of

T_J= 125°C under isothermal test conditions.

8.3.2 Safe Operating Area (SOA) Curves

The SOA curves in the CSD95377Q4M data sheet give engineers guidance on the temperature boundaries

within an operating system by incorporating the thermal resistance and system power loss. Figure 6 and Figure 7

outline the temperature and airflow conditions required for a given load current. The area under the curve

dictates the safe operating area. All the curves are based on measurements made on a PCB design with

dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.

8.3.3 Normalized Curves

The normalized curves in the CSD95377Q4M data sheet give engineers guidance on the power loss and SOA

adjustments based on their application specific needs. These curves show how the power loss and SOA

boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in

power loss and the secondary Y-axis is the change is system temperature required in order to comply with the

SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is

subtracted from the SOA curve.

CSD95377Q4M

Input Current (I_IN

)

Boot

Gate Drive

Current (I_DD

Vin

)

V_DD

V_IN

V_DD

BST

Cin

Input Voltage

C_Boot

Control

FET

(V_IN

)

HSgate

Gate Drive

Voltage (V_DD

DRVH

)

Boot_R

L_O

V_O

Vsw

V_SW

SKIP#

PWM

SKIP#

PWM

Sync

FET

Output Current

LSgate

(I_OUT

)

DRVL

GND

P_GND

Averaging

Circuit

Averaged Switched

Node Voltage

(V_{SW_AVG}

)

Figure 14. Power Loss Test Circuit

8.3.4 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).

Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the

following procedure will outline the steps engineers should take to predict product performance for any set of

system conditions.

CSD95377Q4M

www.ti.com.cn

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

System Example (continued)

8.3.4.1 Design Example

Operating conditions: Output current (l_OUT) = 25 A, input voltage (V_IN) = 7 V, output voltage (V_OUT) = 2 V,

switching frequency (ƒ_SW) = 800 kHz, output inductor (L_OUT) = 0.2 µH

8.3.4.2 Calculating Power Loss

•

Typical power loss at 25 A = 3.74 W (Figure 4)

Normalized power loss for switching frequency ≈ 1.02 (Figure 8)

Normalized power loss for input voltage ≈ 0.99 (Figure 9)

Normalized power loss for output voltage ≈ 1.04 (Figure 10)

Normalized power loss for output inductor ≈ 1.01 (Figure 11)

Final calculated Power Loss = 3.741 W × 1.02 × 0.99 × 1.04 × 1.01 ≈ 3.97 W

8.3.4.3 Calculating SOA Adjustments

•

SOA adjustment for switching frequency ≈ 0.3°C (Figure 8)

SOA adjustment for input voltage ≈ –0.12°C (Figure 9)

SOA adjustment for output voltage ≈ 0.62°C (Figure 10)

SOA adjustment for output inductor ≈ 0.25°C (Figure 11)

Final calculated SOA adjustment = 0.3 + (–0.12) + 0.62 + 0.25 ≈ 1.05°C

Figure 15. Power Stage CSD95377Q4M SOA

In the previous design example, the estimated power loss of the CSD95377Q4M would increase to 3.97 W. In

addition, the maximum allowable board and/or ambient temperature would have to decrease by 1.05°C.

Figure 15 graphically shows how the SOA curve would be adjusted accordingly.

1. Start by drawing a horizontal line from the application current to the SOA curve.

2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.

3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient

temperature of 1.05°C. In the event the adjustment value is a negative number, subtracting the negative number

would yield an increase in allowable board and ambient temperature.

CSD95377Q4M

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

www.ti.com.cn

9 Layout

9.1 Layout Guidelines

9.1.1 Recommended PCB Design Overview

Two key system-level parameters can be addressed with a proper PCB design: electrical and thermal

performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief description

follows on how to address each parameter.

9.1.2 Electrical Performance

The CSD95377Q4M has the ability to switch at voltage rates greater than 10 kV/µs. Take special care with the

PCB layout design and placement of the input capacitors, inductor, and output capacitors.

•

The placement of the input capacitors relative to V_INand P_GNDpins of the CSD95377Q4M device should have

the highest priority during the component placement routine. It is critical to minimize these node lengths. As

such, ceramic input capacitors need to be placed as close as possible to the V_INand P_GNDpins (see

Figure 16). The example in Figure 16 uses 1 × 1-nF 0402, 25-V and 3 × 10-µF 1206, 25-V ceramic capacitors

(TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of

the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement

next to the power stage C5, C8, C6, and C19 should follow in order.

•

The bootstrap capacitor C_BOOT0.1-µF 0603, 16-V ceramic capacitor should be closely connected between

BOOT and BOOT_R pins.

The switching node of the output inductor should be placed relatively close to the power stage

CSD95377Q4M V_SWpins. Minimizing the V_SWnode length between these two components will reduce the

(1)

PCB conduction losses and actually reduce the switching noise level.

9.2 Layout Example

Figure 16. Recommended PCB Layout (Top-Down View)

9.3 Thermal Considerations

The CSD95377Q4M has the ability to use the P_GNDplanes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

•

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

Use the smallest drill size allowed in your design. The example in Figure 16 uses vias with a 10-mil drill hole

and a 16-mil capture pad.

•

Tent the opposite side of the via with solder-mask.

The number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

CSD95377Q4M

www.ti.com.cn

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

10 器件和文档支持

10.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

10.3 商标

NexFET, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

10.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

10.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

CSD95377Q4M

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

www.ti.com.cn

11 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。

11.1 机械制图

0.300

(x45°)

毫米

英寸

标称值

DIM

最小值

0.800

0.000

0.150

2.000

0.150

3.850

4.400

3.400

2.000

标称值

0.900

0.000

0.200

2.200

0.200

3.950

4.500

3.500

2.100

最大值

1.000

0.080

0.250

2.400

0.250

4.050

4.600

3.600

2.200

最小值

0.031

0.000

0.006

0.079

0.006

0.152

0.173

0.134

0.079

最大值

0.039

0.003

0.010

0.095

0.010

0.160

0.181

0.142

0.087

0.035

0.000

0.008

0.087

0.008

0.156

0.177

0.138

0.083

0.400 典型值

0.300 典型值

0.400

0.016 典型值

0.012 典型值

0.016

0.300

0.180

0.00

0.500

0.280

—

0.012

0.007

0.00

0.020

0.011

—

0.230

0.009

—

CSD95377Q4M

www.ti.com.cn

ZHCSEI7B –DECEMBER 2015–REVISED DECEMBER 2017

11.2 建议印刷电路板 (PCB) 焊盘图案

(0.006)

0.150

(0.016)

0.400

(0.010)

0.250

(x18)

(0.006)

0.150

(0.024)

0.600 (x 2)

(0.008)

0.200

(x2)

(0.087)

2.200

R0.100

0.225 ( x 2)

(0.009)

(0.088)

2.250

(0.012)

0.300

(0.159)

4.050

11.3 建议模版开口

(0.016)

0.400

(0.029)

0.738 (x 8)

(0.008)

0.200

(0.008)

0.200

(0.015)

0.390

(0.014)

0.350

0.300

R0.100

(0.012)

0.850 (x8)

(0.033)

(0.012)

0.300

R0.100

(0.004)

0.115

0.440 (0.017)

(0.008)

0.200

(0.009)

0.225

0.200

(0.008)

(0.087)

2.200

NOTE: 尺寸单位为 mm（英寸）。

模版厚度为 100µm。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

2500

250

(1)

(2)

(3)

(4/5)

(6)

CSD95377Q4M

CSD95377Q4MT

ACTIVE

VSON-CLIP

DPC

RoHS-Exempt

& Green

NIPDAU | SN

Level-2-260C-1 YEAR

-40 to 150

95377M

ACTIVE

DPC

RoHS-Exempt

& Green

NIPDAU | SN

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

重要声明和免责声明

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CSD95377Q4M [TI]

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