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CSD95496QVM [TI]

采用 4x5 SON 小型封装的 40A 同步降压 NexFET 智能功率级;
CSD95496QVM
型号： CSD95496QVM
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

采用 4x5 SON 小型封装的 40A 同步降压 NexFET 智能功率级

开关 光电二极管 输出元件
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CSD95496QVM  
SLPS675 –JUNE 2017  
CSD95496QVM Synchronous Buck NexFET™ Smart Power Stage  
1 Features  
2 Applications  
1
•
•
•
•
•
40-A Continuous Operating Current Capability  
Over 93% System Efficiency at 20 A  
High-Frequency Operation (up to 1.25 MHz)  
Diode Emulation Function  
•
Multiphase Synchronous Buck Converters  
–
–
High-Frequency Applications  
High-Current, Low-Duty Cycle Applications  
•
•
•
POL DC-DC Converters  
Temperature Compensated Bi-Directional Current  
Sense  
Memory and Graphic Cards  
Desktop and Server VR12.x / VR13.x VRM  
Synchronous Buck Converters  
•
•
•
•
•
•
Analog Temperature Output  
Fault Monitoring  
3 Description  
3.3-V and 5-V PWM Signal Compatible  
Tri-State PWM Input  
The CSD95496QVM NexFET™ power stage is a  
highly optimized design for use in a high-power, high-  
density synchronous buck converter. This product  
integrates the driver IC and power MOSFETs to  
complete the power stage switching function. This  
combination produces high-current, high-efficiency,  
and high-speed switching capability in a small 4-mm  
× 5-mm outline package. It also integrates the  
accurate current sensing and temperature sensing  
functionality to simplify system design and improve  
accuracy. In addition, the PCB footprint has been  
optimized to help reduce design time and simplify the  
completion of the overall system design.  
Integrated Bootstrap Switch  
Optimized Dead Time for Shoot-Through  
Protection  
•
•
•
•
•
High-Density VSON 4-mm × 5-mm Footprint  
Ultra-Low-Inductance Package  
System Optimized PCB Footprint  
RoHS Compliant – Lead-Free Terminal Plating  
Halogen Free  
Device Information(1)  
Application Diagram  
DEVICE  
MEDIA  
QTY  
PACKAGE  
SHIP  
t12ë  
CSD95496QVM  
13-Inch Reel  
2500  
VSON  
4.00-mm × 5.00-mm  
Package  
Tape  
and  
Reel  
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!ë{t  
!ë{b  
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!{YLt#  
/{59ꢀ496vëa  
CSD95496QVMT  
7-Inch Reel  
250  
ꢁbꢂC//a  
tꢀë  
ë{í  
Ç!h  
ë55  
[h!5  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
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tꢀë  
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!tía2  
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/{59ꢀ496vëa  
Typical Power Stage Efficiency and Power Loss  
ꢁbꢂC//a  
ë{í  
Ç!h  
ë55  
100  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
8
[{ꢁÇ  
tDb5 LhÜÇ wꢁCLb  
ëwꢁC  
3ꢃ3ë  
7.2  
6.4  
5.6  
4.8  
4
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t12ë  
ꢁbꢂC//a  
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Ç!h  
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VDD = 5 V  
VIN = 12 V  
/{tLb  
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ë//Lh  
.ꢁb_ë//Lh  
VOUT = 1.2 V  
LOUT = 220 nH  
fSW = 500 kHz  
TA = 25èC  
3.2  
2.4  
1.6  
0.8  
0
{/[Y  
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!/{t3  
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3ꢃ3ë  
0
4
8
12  
16  
20  
24  
28  
32  
36  
40  
!/{t4  
!Db5  
Output Current (A)  
D000  
Copyright © 2016, Texas Instruments Incorporated  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
CSD95496QVM  
SLPS675 –JUNE 2017  
www.ti.com  
Table of Contents  
1
2
3
4
5
6
Features.................................................................. 1  
8
Device and Documentation Support.................... 6  
8.1 Receiving Notification of Documentation Updates.... 6  
8.2 Community Resources.............................................. 6  
8.3 Trademarks............................................................... 6  
8.4 Electrostatic Discharge Caution................................ 6  
8.5 Glossary.................................................................... 6  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
6.1 Absolute Maximum Ratings ...................................... 4  
6.2 ESD Ratings.............................................................. 4  
6.3 Recommended Operating Conditions....................... 4  
Application Schematic .......................................... 5  
9
Mechanical, Packaging, and Orderable  
Information ............................................................. 7  
9.1 Mechanical Drawing.................................................. 7  
9.2 Recommended PCB Land Pattern............................ 8  
9.3 Recommended Stencil Opening ............................... 9  
7
4 Revision History  
DATE  
REVISION  
NOTES  
June 2017  
*
Initial release.  
2
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Product Folder Links: CSD95496QVM  
 
CSD95496QVM  
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SLPS675 –JUNE 2017  
5 Pin Configuration and Functions  
Top View  
Pin Functions  
PIN  
DESCRIPTION  
NAME  
REFIN  
IOUT  
LSET  
VDD  
NO.  
1
2
External reference voltage input for current sensing amplifier.  
Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.  
3
A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry.  
Supply voltage for gate drivers and internal circuitry.  
4
VOS  
5
Output voltage sensing pin for the internal current sensing circuitry.  
SW  
6-9  
10-13  
14  
Phase node connecting the HS MOSFET Source and LS MOSFET drain – pin connection to the output inductor.  
Input voltage pin. Connect input capacitors close to this pin.  
VIN  
BOOTR  
Return path for HS gate driver. It is connected to VSW internally.  
Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic cap from BOOT to BOOTR pins.  
The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated.  
BOOT  
15  
Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high  
sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for  
greater than the tri-state shutdown holdoff time (t3HT).  
PWM  
16  
This dual function pin either enables the diode emulation function or can be used as a simple enable for the  
device. When this pin is driven into the tri-state window and held there for more than the tri-state holdoff time,  
Diode Emulation Mode is enabled for sync FET. When the pin is high, device operates in Forced Continuous  
Conduction Mode. When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left  
floating.  
EN/FCCM  
17  
Temperature Amplifier Output. Reports a voltage proportional to the IC temperature. An ORing diode is  
integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of  
all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown,  
LSOC, or HSS detection circuit is tripped.  
TAO/FAULT  
PGND  
18  
19  
Power ground.  
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CSD95496QVM  
SLPS675 –JUNE 2017  
www.ti.com  
6 Specifications  
6.1 Absolute Maximum Ratings  
TA = 25°C (unless otherwise stated)(1)  
MIN  
–0.3  
–0.3  
MAX  
UNIT  
V
VIN to PGND  
20  
VIN to VSW  
20  
V
VIN to VSW (10 ns)  
VSW to PGND  
23  
V
–0.3  
–7  
20  
V
VSW to PGND (10 ns)  
VDD to PGND  
23  
V
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–55  
–55  
7
VDD + 0.3  
7
V
(2)  
EN/FCCM, TAO/FLT, LSET to PGND  
IOUT, VOS, PWM to PGND  
REFIN  
V
V
3.6  
V
BOOT to BOOTR(2)  
VDD + 0.3  
30  
V
BOOT to PGND  
V
TJ  
Operating junction temperature  
Storage temperature  
150  
°C  
°C  
Tstg  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating  
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) Should not exceed 7 V.  
6.2 ESD Ratings  
VALUE  
±2000  
±500  
UNIT  
Human-body model (HBM)  
V(ESD)  
Electrostatic discharge  
V
Charged-device model (CDM)  
6.3 Recommended Operating Conditions  
TA = 25°C (unless otherwise stated)  
MIN  
4.5  
MAX  
5.5  
UNIT  
VDD  
Driver supply voltage  
Input supply voltage(1)  
Output voltage  
V
V
VIN  
4.5  
16  
VOUT  
PWM  
IOUT  
5.5  
V
PWM to PGND  
VDD  
40  
V
Continuous output current  
A
VIN = 12 V, VDD = 5 V, VOUT = 1.2 V,  
ƒSW = 500 kHz(2)  
IOUT-PK Peak output current(3)  
60  
A
ƒSW  
Switching frequency  
CBST = 0.1 µF (min), VOUT = 2.5 V (max)  
ƒSW = 1 MHz  
1250  
85%  
kHz  
On-time duty cycle  
Minimum PWM on-time  
Operating junction temperature  
20  
ns  
°C  
–40  
125  
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For  
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.  
(2) Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins.  
(3) System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs.  
4
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CSD95496QVM  
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SLPS675 –JUNE 2017  
7 Application Schematic  
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!Db5  
Copyright © 2016, Texas Instruments Incorporated  
Figure 1. Application Schematic  
Note: The schematic in Figure 1 is a conceptual drawing only. Actual designs may require additional components  
not shown.  
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CSD95496QVM  
SLPS675 –JUNE 2017  
www.ti.com  
8 Device and Documentation Support  
8.1 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on Alert me to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
8.2 Community Resources  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
8.3 Trademarks  
NexFET, E2E are trademarks of Texas Instruments.  
All other trademarks are the property of their respective owners.  
8.4 Electrostatic Discharge Caution  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
8.5 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
6
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CSD95496QVM  
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SLPS675 –JUNE 2017  
9 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
9.1 Mechanical Drawing  
4.1  
3.9  
B
A
PIN 1 INDEX AREA  
5.1  
4.9  
1.05 MAX  
C
SEATING PLANE  
0.08 C  
0.05  
0.00  
0.6  
0.4  
2X  
2.4 0.1  
(0.2) TYP  
EXPOSED  
THERMAL PAD  
2X (0.31)  
9
10  
2X  
4
4.4 0.1  
1
18  
0.3  
16X 0.5  
18X  
0.2  
0.1  
0.05  
0.6  
0.4  
10X  
PIN 1 ID  
C A B  
C
(OPTIONAL)  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning  
and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical  
performance.  
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SLPS675 –JUNE 2017  
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9.2 Recommended PCB Land Pattern  
(2.5)  
SYMM  
10X (0.7)  
1
18  
2X  
(1.275)  
10X (0.25)  
8X (0.5)  
2X  
(0.725)  
SYMM  
5
14  
13  
(4.5)  
6
(R0.05) TYP  
2X  
(1.85)  
METAL UNDER  
SOLDER MASK  
10  
9
SOLDER MASK  
OPENING  
2X (0.31)  
2X (0.8)  
2X (1)  
(
0.2) VIA  
TYP  
(3.7)  
0.05 MIN  
ALL AROUND  
0.05 MAX  
ALL AROUND  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
SOLDER MASK  
OPENING  
METAL  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning  
and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON  
PCB Attachment (SLUA271).  
8
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SLPS675 –JUNE 2017  
9.3 Recommended Stencil Opening  
SYMM  
METAL  
TYP  
10X (0.7)  
(0.655)  
(R0.05) TYP  
1
18  
10X (0.25)  
8X  
(0.5)  
(1.45)  
TYP  
SYMM  
5
6
14  
13  
2X (1.75)  
6X  
(1.25)  
10  
9
2X (0.31)  
2X (0.7)  
6X (1.11)  
(3.7)  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning  
and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525  
may have alternate design recommendations.  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
2500  
250  
(1)  
(2)  
(3)  
(4/5)  
(6)  
CSD95496QVM  
CSD95496QVMT  
ACTIVE  
VSON-CLIP  
VSON-CLIP  
DMH  
18  
18  
RoHS-Exempt  
& Green  
SN  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-55 to 150  
-55 to 150  
95496QM  
95496QM  
ACTIVE  
DMH  
RoHS-Exempt  
& Green  
SN  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2021  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CSD95496QVM  
CSD95496QVMT  
VSON-  
CLIP  
DMH  
DMH  
18  
18  
2500  
250  
330.0  
12.4  
4.3  
5.3  
1.3  
8.0  
12.0  
Q1  
VSON-  
CLIP  
180.0  
12.4  
4.3  
5.3  
1.3  
8.0  
12.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2021  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CSD95496QVM  
CSD95496QVMT  
VSON-CLIP  
VSON-CLIP  
DMH  
DMH  
18  
18  
2500  
250  
367.0  
213.0  
367.0  
191.0  
38.0  
35.0  
Pack Materials-Page 2  
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