CSD97394Q4MT [TI]

CSD97394Q4M Synchronous Buck NexFET Power Stage;


型号：	CSD97394Q4MT
厂家：	TEXAS INSTRUMENTS
描述：	CSD97394Q4M Synchronous Buck NexFET Power Stage 开关光电二极管
文件：	总22页 (文件大小：991K)
中文：	中文翻译
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CSD97394Q4M

SLPS542 –JANUARY 2015

CSD97394Q4M Synchronous Buck NexFET™ Power Stage

1 Features

2 Applications

•

90% System Efficiency at 15 A

Max Rated Continuous Current 20 A, Peak 45 A

High Frequency Operation (up to 2 MHz)

High Density – SON 3.5 × 4.5 mm Footprint

Ultra-Low Inductance Package

System Optimized PCB Footprint

Ultra-Low Quiescent (ULQ) Current Mode

3.3 V and 5 V PWM Signal Compatible

Diode Emulation Mode with FCCM

Input Voltages up to 24 V

•

Ultrabook/Notebook DC/DC Converters

Multiphase Vcore and DDR Solutions

Point-of-Load Synchronous Buck in Networking,

Telecom, and Computing Systems

3 Description

The CSD97394Q4M NexFET™ Power Stage is a

highly-optimized design for use in a high-power, high-

density synchronous buck converter. This product

integrates the driver IC and NexFET technology to

complete the power stage switching function. The

driver IC has a built-in selectable diode emulation

function that enables DCM operation to improve light

load efficiency. In addition, the driver IC supports

ULQ mode that enables connected standby for

Windows^®8. With the PWM input in tri-state,

quiescent current is reduced to 130 µA, with

immediate response. When SKIP# is held at tri-state,

the current is reduced to 8 µA (typically 20 µs is

required to resume switching). This combination

produces a high current, high efficiency, and high

speed switching device in a small 3.5 × 4.5 mm

outline package. In addition, the PCB footprint is

optimized to help reduce design time and simplify the

completion of the overall system design.

Tri-State PWM Input

Integrated Bootsrap Diode

Shoot Through Protection

RoHS Compliant – Lead Free Terminal Plating

Halogen Free

Device Information⁽¹⁾

ORDER NUMBER

CSD97394Q4M

PACKAGE

MEDIA AND QTY

13-inch reel

7-inch reel

2500

250

SON 3.5 × 4.5 mm

Plastic Package

CSD97394Q4MT

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

spacer

Application Diagram

Typical Power Stage Efficiency and Power Loss

V_IN

100

CSD97394

V_OUT

V_DD= 5 V

V_IN= 12 V

V_OUT= 1.8 V

L_OUT= 0.29 PH

f_SW= 500 kHz

T_A= 25qC

V_CC

PWM1

+I_s1

-I_s2

V_OUT

+NTC

-NTC

+I_s2

-I_s2

Output Current (A)

PWM2

D001

P_GND

Multi-Phase

Controller

CSD97394

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

CSD97394Q4M

SLPS542 –JANUARY 2015

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Table of Contents

Features.................................................................. 1

Application and Implementation .......................... 9

8.1 Application Information.............................................. 9

8.2 Typical Application ................................................... 9

8.1 System Example ..................................................... 12

Layout ................................................................... 14

9.1 Layout Guidelines ................................................... 14

9.2 Layout Example ...................................................... 14

9.3 Thermal Considerations.......................................... 14

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

Detailed Description .............................................. 6

7.1 Overview ................................................................... 6

7.2 Functional Block Diagram ......................................... 6

7.3 Feature Description................................................... 6

7.4 Device Functional Modes.......................................... 8

10 Device and Documentation Support ................. 15

10.1 Trademarks........................................................... 15

10.2 Electrostatic Discharge Caution............................ 15

10.3 Glossary................................................................ 15

11 Mechanical, Packaging, and Orderable

Information ........................................................... 16

11.1 Mechanical Drawing.............................................. 16

11.2 Recommended PCB Land Pattern........................ 17

11.3 Recommended Stencil Opening ........................... 17

4 Revision History

DATE

REVISION

NOTES

January 2015

Initial release.

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5 Pin Configuration and Functions

SON 3.5 × 4.5 mm

(Top View)

SKIP#

V_DD

PWM

BOOT

P_GND

BOOT_R

P_GND

V_SW

V_IN

Pin Functions

NAME

DESCRIPTION

NO.

This pin enables the Diode Emulation function. When this pin is held Low, Diode Emulation Mode is enabled for the

Sync FET. When SKIP# is High, the CSD95391Q4M operates in Forced Continuous Conduction Mode. A tri-state

voltage on SKIP# puts the driver into a very low power state.

SKIP#

V_DD

Supply voltage to gate drivers and internal circuitry.

P_GND

V_SW

Power ground, needs to be connected to Pin 9 and PCB

Voltage switching node – pin connection to the output inductor.

Input voltage pin. Connect input capacitors close to this pin.

V_IN

BOOT_R

Bootstrap capacitor connection. Connect a minimum 0.1 µF 16 V X5R, ceramic cap from BOOT to BOOT_R pins. The

bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated. Boot_R is

BOOT

internally connected to V_SW

Pulse Width modulated tri-state input from external controller. Logic Low sets Control FET gate low and Sync FET

gate high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates

PWM

P_GND

low if greater than the tri-state shutdown hold-off time (t_3HT

)

Power ground

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6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

T_A= 25°C (unless otherwise noted)

MIN

–0.3

–7

MAX

UNIT

V_INto P_GND

V_SWto P_GND, V_INto V_SW

V_SWto P_GND, V_INto V_SW(<10 ns)

V_DDto P_GND

–0.3

–2

PWM, SKIP# to P_GND

BOOT to P_GND

BOOT to P_GND(<10 ns)

BOOT to BOOT_R

–0.3

BOOT to BOOT_R (duty cycle <0.2%)

P_D

T_J

Power dissipation

°C

Operating temperature range

Storage temperature range

–40

–55

150

T_stg

(1) Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human Body Model (HBM)⁽¹⁾

Charged Device Model (CDM)⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

T_A= 25° (unless otherwise noted)

MIN

MAX UNIT

V_DD

Gate drive voltage

4.5

5.5

V_IN

Input supply voltage⁽¹⁾

Continuous output current

Peak output current⁽³⁾

Switching frequency

On time duty cycle

I_OUT

I_OUT-PK

ƒ_SW

V_IN= 12 V, V_DD= 5 V, V_OUT= 1.8 V,

ƒ_SW= 500 kHz, L_OUT= 0.29 µH⁽²⁾

C_BST= 0.1 µF (min)

2000

85%

kHz

Minimum PWM on time

Operating temperature

°C

–40

125

(1) Operating at high V_INcan create excessive AC voltage overshoots on the switch node (V_SW) during MOSFET switching transients. For

reliable operation, the switch node (V_SW) to ground voltage must remain at or below the Absolute Maximum Ratings.

(2) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins.

(3) System conditions as defined in Note 2. Peak Output Current is applied for t_p= 10 ms, duty cycle ≤ 1%

6.4 Thermal Information

T_A= 25°C (unless otherwise noted)

THERMAL METRIC

Junction-to-case (top of package) thermal resistance⁽¹⁾

Junction-to-board thermal resistance⁽²⁾

MIN

TYP

MAX UNIT

R_θJC

R_θJB

22.8

°C/W

2.5

(1)

(2)

_θJCis determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (0.071 mm thick) Cu pad on a 1.5 inch x 1.5 inch, 0.06 inch

(1.52 mm) thick FR4 board.

R_θJBvalue based on hottest board temperature within 1mm of the package.

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6.5 Electrical Characteristics

T_A= 25°C, V_DD= POR to 5.5 V (unless otherwise noted)

PARAMETER

P_LOSS

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN= 12 V, V_DD= 5 V, V_OUT= 1.8 V, I_OUT= 12 A,

ƒ_SW= 500 kHz, L_OUT= 0.29 µH , T_J= 25°C

Power

loss⁽¹⁾

2.2

2.4

3.0

V_IN= 19 V, V_DD= 5 V, V_OUT= 1.8 V, I_OUT= 12 A,

ƒ_SW= 500 kHz, L_OUT= 0.29 µH , T_J= 25°C

Power

loss⁽²⁾

V_IN= 19 V, V_DD= 5 V, V_OUT= 1.8 V, I_OUT= 12 A,

ƒ_SW= 500 kHz, L_OUT= 0.29 µH , T_J= 125°C

Power

loss⁽²⁾

V_IN

I_Q

V_INquiescent current

PWM = Floating, V_DD= 5 V, V_IN= 24 V

µA

V_DD

PWM = Float, SKIP# = V_DDor 0 V

SKIP# = Float

130

µA

I_DD

Standby supply current

Operating supply current

PWM = 50% Duty cycle, ƒ_SW= 500 kHz

5.3

POWER-ON RESET AND UNDERVOLTAGE LOCKOUT

V_DDRising Power-on reset

V_DDFalling UVLO

Hysteresis

PWM AND SKIP# I/O SPECIFICATIONS

4.15

3.7

0.2

Pull up to V_DD

1700

800

R_I

Input Impedance

kΩ

Pull down (to GND)

V_IH

V_IL

Logic level high

Logic level low

Hysteresis

2.65

1.3

0.6

V_IH

V_TS

0.2

Tri-state voltage

Tri-state activation time

(falling) PWM

t_THOLD(off1)

t_THOLD(off2)

t_TSKF

µs

Tri-state activation time (rising)

PWM

Tri-state activation time

(falling) SKIP#

Tri-state activation time (rising)

SKIP#

t_TSKR

(2)

t_3RD(PWM)

t_3RD(SKIP#)

Tri-state exit time PWM

100

µs

Tri-state exit time SKIP#⁽²⁾

BOOTSTRAP SWITCH

V_FBSTForward voltage

I_RLEAK

Reverse leakage⁽²⁾

I_F= 10 mA

120

240

µA

V_BST– V_DD= 25 V

(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins.

(2) Specified by design

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7 Detailed Description

7.1 Overview

The CSD97394Q4M NexFET™ Power Stage is a highly optimized design for use in a high-power, high-density

synchronous buck converter.

7.2 Functional Block Diagram

VDD

BOOT

VIN

DRVL

Control

FET

DRVH

Level Shift

V_UVLO

VDD

BOOT_R

VSW

1 V

1.7Meg

3-State

Logic

SKIP#

800k

VDD

1 V

1.7Meg

Sync

FET

3-State

Logic

PWM

DRVL

800k

PGND

7.3 Feature Description

7.3.1 Powering CSD97394Q4M And Gate Drivers

An external V_DDvoltage is required to supply the integrated gate driver IC and provide the necessary gate drive

power for the MOSFETS. A 1 µF 10 V X5R or higher ceramic capacitor is recommended to bypass V_DDpin to

P_GND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply

to drive the Control FET is generated by connecting a 100nF 16V X5R ceramic capacitor between BOOT and

BOOT_R pins. An optional R_BOOTresistor can be used to slow down the turn on speed of the Control FET and

reduce voltage spikes on the V_SWnode. A typical 1 Ω to 4.7 Ω value is a compromise between switching loss

and V_SWspike amplitude.

7.3.2 Undervoltage Lockout Protection (UVLO)

The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As V_VDDrises, both the Control

FET and Sync FET gates hold actively low at all times until V_VDDreaches the higher UVLO threshold (V_{UVLO_H}).,

Then the driver becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower

UVLO threshold (V_{UVLO_L}= V_{UVLO_H}– Hysteresis), the device disables the driver and drives the outputs of the

Control FET and Sync FET gates actively low. Figure 1 shows this function.

CAUTION

Do not start the driver in the very low power mode (SKIP# = Tri-state).

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Feature Description (continued)

UVLO_H

UVLO_L

VDD

Driver On

UDG-12218

Figure 1. UVLO Operation

7.3.3 PWM Pin

The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when

PWM is driven into the tri-state window and the driver enters a low power state with zero exit latency. The pin

incorporates a weak pull-up to maintain the voltage within the tri-state window during low-power modes.

Operation into and out of tri-state mode follows the timing diagram outlined in Figure 2.

When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The

window is defined the PWM voltage range between PWM logic high (V_IH) and logic low (V_IL) thresholds. The

device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3 V

(typical) and 5 V (typical) PWM drive signals.

When the PWM exits tri-state, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP#

pin. Normal operation requires this time period in order for the auto-zero comparator to resume.

V_IH

High-Z Window

V_IL

PWM

VSW

VOUT

t_3RD1

t_{HOLD_OFF1}

t_{HOLD_OFF2}

t_3RD2

t_pdLH

t_pdHL

Time

Figure 2. PWM Tri-State Timing Diagram

7.3.4 SKIP# Pin

The SKIP# pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP# is

low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current

is less than the critical current. When SKIP# is high, the ZX comparator disables, and the converter enters FCCM

mode. When both SKIP# and PWM are tri-stated, normal operation forces the gate driver outputs low and the

driver enters a low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent

current. When SKIP# is pulled low, the driver wakes up and is able to accept PWM pulses in less than 50 µs.

Table 1 shows the logic functions of UVLO, PWM, SKIP#, the Control FET Gate and the Sync FET Gate.

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Feature Description (continued)

Table 1. Logic Functions of the Driver IC

UVLO

Active

PWM

—

SKIP#

—

Sync FET Gate

Control FET Gate

MODE

Low

High

Low

Disabled

DCM⁽¹⁾

FCCM

Inactive

Low

High⁽¹⁾

High

Low

High

Tri-state

—

H or L

Tri-state

Low

ULQ

(1) Until zero crossing protection occurs.

7.3.4.1 Zero Crossing (ZX) Operation

The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy

load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current,

which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects

the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the

rectifying MOSFET.

7.3.5 Integrated Boost-Switch

To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the

conventional diode between the VDD pin and the BST pin is replaced by a FET which is gated by the DRVL

signal.

7.4 Device Functional Modes

Table 1 shows the different functional modes of CSD97394. The diode emulation mode is enabled with SKIP#

pulled low, which improves light load efficiency. With PWM in tri-state, Power Stage enters LQ mode and the

quiescent current is reduced to 130 µA. When SKIP# is held in tri-state, ULQ mode is enabled and the current is

decreased to 8 µA.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The Power Stage CSD97394Q4M is a highly optimized design for synchronous buck applications using NexFET

devices with a 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest

power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more

systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the

parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such

as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict the product performance

in the actual application.

8.2 Typical Application

Figure 3. Application Schematic

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Typical Application (continued)

8.2.1 Application Curves

T_J= 125°C, unless stated otherwise

1.1

0.9

0.8

0.7

0.6

0.5

Typ

Max

-50

-25

100

125

150

D003

Output Current (A)

T_C- Junction Temperature (qC)

D002

V_IN= 12 V

V_DD= 5 V

V_OUT= 1.8 V

V_IN= 12 V

V_DD= 5 V

V_OUT= 1.8 V

ƒ_SW= 500 kHz

L_OUT= 0.29 µH

ƒ_SW= 500 kHz

L_OUT= 0.29 µH

Figure 4. Power Loss vs Output Current

Figure 5. Power Loss vs Temperature

400 LFM

200 LFM

100 LFM

Nat. conv.

400 LFM

200 LFM

100 LFM

Nat. conv.

Ambient Temperature (qC)

D005

D004

V_IN= 12 V

V_DD= 5 V

V_OUT= 1.8 V

V_IN= 12 V

V_DD= 5 V

V_OUT= 1.8 V

ƒ_SW= 500 kHz

L_OUT= 0.29 µH

ƒ_SW= 500 kHz

L_OUT= 0.29 µH

Figure 7. Safe Operating Area – PCB Vertical Mount ⁽¹⁾

Figure 6. Safe Operating Area – PCB Horizontal Mount ⁽¹⁾

1.3

1.25

1.2

7.2

6.0

4.8

3.6

2.4

1.2

0.0

-1.2

-2.4

1.15

1.1

1.05

0.95

0.9

Min

Typ

400

800

1200

1600

2000

2400

100

120

140

Switching Frequency (kHz)

Board Temperature (

D006

D007

V_IN= 12 V

V_DD= 5 V

V_OUT= 1.8 V

V_IN= 12 V

V_DD= 5 V

V_OUT= 1.8 V

ƒ_SW= 500 kHz

L_OUT= 0.29 µH

I_OUT= 20 A

L_OUT= 0.29 µH

(1)

Figure 8. Typical Safe Operating Area

Figure 9. Normalized Power Loss vs Frequency

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Typical Application (continued)

T_J= 125°C, unless stated otherwise

1.3

7.2

6.0

4.8

3.6

2.4

1.2

0.0

-1.2

-2.4

1.4

1.3

1.2

1.1

9.7

7.3

4.9

2.4

0.0

-2.4

-4.9

-7.3

1.25

1.2

1.15

1.1

1.05

0.9

0.8

0.7

0.95

0.9

10 12 14 16 18 20 22 24

0.6

1.2

1.8

2.4

3.6

Input Voltage (V)

Output Voltage (V)

D008

D009

I_OUT= 20 A

V_DD= 5 V

L_OUT= 0.29 µH

V_OUT= 1.8 V

V_IN= 12 V

V_DD= 5 V

L_OUT= 0.29 µH

I_OUT= 20 A

ƒ_SW= 500 kHz

Figure 10. Normalized Power Loss vs Input Voltage

Figure 11. Normalized Power Loss vs Output Voltage

1.3

1.25

1.2

7.2

6.0

4.8

3.6

2.4

1.2

0.0

-1.2

-2.4

1.15

1.1

1.05

0.95

0.9

0.85

-3.6

100 200 300 400 500 600 700 800 900 1000 1100

400

800

1200

1600

2000

2400

Output Inductance (nH)

Switching Frequency (kHz)

D010

D011

V_IN= 12 V

ƒ_SW= 500 kHz

V_DD= 5 V

I_OUT= 20 A

V_IN= 12 V

V_DD= 5 V

I_OUT= 20 A

V_OUT= 1.8 V

L_OUT= 0.29 µH

V_OUT= 1.8 V

Figure 12. Normalized Power Loss vs Output Inductance

Figure 13. Driver Current vs Frequency

8.5

8.2

7.9

7.6

7.3

-50

-25

100

125

150

T_C- Junction Temperature (qC)

D012

V_IN= 12 V

I_OUT= 20 A

V_DD= 5 V

V_OUT= 1.8 V

L_OUT= 0.29 µH

Figure 14. Driver Current vs Temperature

1. The Typical CSD97394Q4M System Characteristic curves are based on measurements made on a PCB

design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz.

copper thickness. See the System Example section for detailed explanation.

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8.1 System Example

8.1.1 Power Loss Curves

MOSFET centric parameters such as R_DS(ON)and Q_gdare primarily needed by engineers to estimate the loss

generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has

provided measured power loss performance curves. Figure 4 plots the power loss of the CSD97394Q4M as a

function of load current. This curve is measured by configuring and running the CSD97394Q4M as it would be in

the final application (see Figure 15). The measured power loss is the CSD97394Q4M device power loss which

consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Power Loss = (V_INx I_IN) + (V_DDx I_DD) – (V_{SW_AVG}x I_OUT

)

(1)

The power loss curve in Figure 4 is measured at the maximum recommended junction temperature of

T_J= 125°C under isothermal test conditions.

8.1.2 Safe Operating Curves (SOA)

The SOA curves in the CSD97394Q4M datasheet give engineers guidance on the temperature boundaries within

an operating system by incorporating the thermal resistance and system power loss. Figure 6 and Figure 8

outline the temperature and airflow conditions required for a given load current. The area under the curve

dictates the safe operating area. All the curves are based on measurements made on a PCB design with

dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness.

8.1.3 Normalized Curves

The normalized curves in the CSD97394Q4M data sheet give engineers guidance on the Power Loss and SOA

adjustments based on their application specific needs. These curves show how the power loss and SOA

boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in

power loss and the secondary Y-axis is the change is system temperature required in order to comply with the

SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is

subtracted from the SOA curve.

CSD97394Q4M

Input Current (I_IN

)

Boot

Gate Drive

Current (I_DD

Vin

)

V_DD

V_IN

V_DD

BST

Cin

Input Voltage

C_Boot

Control

FET

(V_IN

)

HSgate

Gate Drive

Voltage (V_DD

DRVH

)

Boot_R

L_O

V_O

Vsw

V_SW

SKIP#

PWM

SKIP#

PWM

Sync

FET

Output Current

LSgate

(I_OUT

)

DRVL

GND

P_GND

Averaging

Circuit

Averaged Switched

Node Voltage

(V_{SW_AVG}

)

Figure 15. Power Loss Test Circuit

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System Example (continued)

8.1.3.1 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).

Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the

following procedure will outline the steps engineers should take to predict product performance for any set of

system conditions.

8.1.3.1.1 Design Example

Operating Conditions: Output Current (l_OUT) = 10 A, Input Voltage (V_IN) = 7 V, Output Voltage (V_OUT) = 1.5 V,

Switching Frequency (ƒ_SW) = 800 kHz, Output Inductor (L_OUT) = 0.2 µH

8.1.3.1.2 Calculating Power Loss

•

Typical Power Loss at 10 A = 2.1 W (Figure 4)

Normalized Power Loss for switching frequency ≈ 0.99 (Figure 9)

Normalized Power Loss for input voltage ≈ 1.10 (Figure 10)

Normalized Power Loss for output voltage ≈ 0.93 (Figure 11)

Normalized Power Loss for output inductor ≈ 1.10 (Figure 12)

Final calculated Power Loss = 2.1 W × 0.99 × 1.10 × 0.93 × 1.10 ≈ 2.3 W

8.1.3.1.3 Calculating SOA Adjustments

•

SOA adjustment for switching frequency ≈ –0.2°C (Figure 9)

SOA adjustment for input voltage ≈ 2.5°C (Figure 10)

SOA adjustment for output voltage ≈ 1.0°C (Figure 11)

SOA adjustment for output inductor ≈ 2.3°C (Figure 12)

Final calculated SOA adjustment = –0.2 + 2.5 + (–1.5) + 2.3 ≈ 3.1°C

Figure 16. Power Stage CSD97394Q4M SOA

In the design example above, the estimated power loss of the CSD97394Q4M would increase to 2.3 W. In

addition, the maximum allowable board and/or ambient temperature would have to decrease by 3.1°C. Figure 16

graphically shows how the SOA curve would be adjusted accordingly.

1. Start by drawing a horizontal line from the application current to the SOA curve.

2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.

3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient

temperature of 3.1°C. In the event the adjustment value is a negative number, subtracting the negative number

would yield an increase in allowable board/ambient temperature.

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9 Layout

9.1 Layout Guidelines

9.1.1 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and

thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below

is a brief description on how to address each parameter.

9.1.2 Electrical Performance

The CSD97394Q4M has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be then

taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.

•

The placement of the input capacitors relative to V_INand P_GNDpins of CSD97394Q4M device should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

ceramic input capacitors need to be placed as close as possible to the V_INand P_GNDpins (see Figure 17).

The example in Figure 17 uses 1 x 1 nF 0402 25V and 3 x 10 µF 1206 25 V ceramic capacitors (TDK part

number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board

with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the

Power Stage C5, C8 and C6, C19 should follow in order.

•

The bootstrap cap C_BOOT0.1 µF 0603 16 V ceramic capacitor should be closely connected between BOOT

and BOOT_R pins.

The switching node of the output inductor should be placed relatively close to the Power Stage

CSD97394Q4M V_SWpins. Minimizing the V_SWnode length between these two components will reduce the

(1)

PCB conduction losses and actually reduce the switching noise level.

9.2 Layout Example

Figure 17. Recommended PCB Layout (Top Down View)

9.3 Thermal Considerations

The CSD97394Q4M has the ability to use the GND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

•

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

Use the smallest drill size allowed in your design. The example in Figure 17 uses vias with a 10 mil drill hole

and a 16 mil capture pad.

•

Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

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10 Device and Documentation Support

10.1 Trademarks

NexFET is a trademark of Texas Instruments.

Windows is a registered trademark of Microsoft Corporation.

All other trademarks are the property of their respective owners.

10.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

10.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

11.1 Mechanical Drawing

ꢀ

0.300

(x45°)

MILLIMETERS

NOM

INCHES

NOM

DIM

MIN

MAX

1.000

0.080

0.250

2.400

0.250

4.050

4.600

3.600

2.200

MIN

MAX

0.039

0.003

0.010

0.095

0.010

0.160

0.181

0.142

0.087

0.800

0.000

0.150

2.000

0.150

3.850

4.400

3.400

2.000

0.900

0.031

0.000

0.006

0.079

0.006

0.152

0.173

0.134

0.079

0.035

0.000

0.200

0.008

2.200

0.087

0.200

0.008

0.200

0.008

3.950

0.156

4.500

0.177

3.500

0.138

2.100

0.083

0.400 TYP

0.300 TYP

0.400

0.016 TYP

0.012 TYP

0.016

0.300

0.180

0.00

0.500

0.280

—

0.012

0.007

0.00

0.020

0.011

—

0.230

0.009

—

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11.2 Recommended PCB Land Pattern

(0.006)

0.150

(0.016)

0.400

(0.010)

0.250

(x18)

(0.006)

0.150

(0.024)

0.600 (x 2)

(0.008)

0.200

(x2)

(0.087)

2.200

R0.100

0.225 ( x 2)

(0.009)

(0.088)

2.250

(0.012)

0.300

(0.159)

4.050

11.3 Recommended Stencil Opening

(0.016)

0.400

(0.029)

0.738 (x 8)

(0.008)

0.200

(0.008)

0.200

(0.015)

0.390

(0.014)

0.350

0.300

R0.100

(0.012)

0.850 (x8)

(0.033)

(0.012)

0.300

R0.100

(0.004)

0.115

0.440 (0.017)

(0.008)

0.200

(0.009)

0.225

0.200

(0.008)

(0.087)

2.200

NOTE: Dimensions are in mm (inches).

Stencil is 100 µm thick.

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PACKAGE OPTION ADDENDUM

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6-Feb-2015

PACKAGING INFORMATION

Orderable Device

CSD97394Q4M

CSD97394Q4MT

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

VSON-CLIP

DPC

2500 Pb-Free (RoHS

Exempt)

CU NIPDAU

Level-2-260C-1 YEAR

97394M

ACTIVE

DPC

250

Pb-Free (RoHS

Exempt)

CU NIPDAU

Level-2-260C-1 YEAR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

6-Feb-2015

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Sep-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CSD97394Q4M

CSD97394Q4MT

VSON-

CLIP

DPC

2500

250

330.0

12.4

3.71

4.71

1.1

8.0

12.0

VSON-

CLIP

180.0

12.4

3.71

4.71

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Sep-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CSD97394Q4M

CSD97394Q4MT

VSON-CLIP

DPC

2500

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

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CSD97394Q4MT [TI]

相关型号：

CSD97394Q4M_15

CSD97395Q4M

CSD97395Q4MT

CSD97395Q4M_15

CSD97396Q4M

CSD97396Q4MT

CSDA1AA

CSDA1AC

CSDA1BA

CSDA1BC

CSDA1DA

CSDA1DC