CY5474FCT480T [TI]

Dual 8-Bit Parity Generator/Checker; 双路8位奇偶校验发生器/校验器


型号：	CY5474FCT480T
厂家：	TEXAS INSTRUMENTS
描述：	Dual 8-Bit Parity Generator/Checker 双路8位奇偶校验发生器/校验器
文件：	总8页 (文件大小：84K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1CY54/74FCT480T

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

CY54/74FCT480T

Dual 8-Bit Parity Generator/Checker

SCCS025 - May 1993 - Revised March 2000

• Two 8-bit parity generator/checkers

Features

• Open drain Active LOW parity error output

• Function, pinout and drive compatible with FCT and F

• Expandable for larger word widths

logic

• FCT-A speed at 7.5 ns max. (Com’l)

FCT-B speed at 5.6 ns max. (Com’l)

Functional Description

The FCT480T is

high-speed dual 8-bit parity

• Reduced V_OH(typically = 3.3V) versions of equivalent

FCT functions

generator/checker. Each parity generator/checker accepts

eight data bits and one parity bit as inputs, and generates a

sum and parity error output. The FCT480T can be used in

ODD parity systems. The parity error output is open-drain,

designed for easy expansion of the word width by a wired-OR

connection of several FCT480T type devices. Since additional

logic is not needed, the parity generation or checking times

remain the same as for an individual FCT480T device.

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

• Power-off disable feature

• Matched rise and fall times

• ESD > 2000V

• Fully compatible with TTL input and output logic levels

• Sink Current

64 mA (Com’l),

32 mA (Mil)

The outputs are designed with a power-off disable feature to

allow for live insertion of boards.

Source Current 32 mA (Com’l),

12 mA (Mil)

LogicBlockDiagram

ODD

PAR

ERR

CHK/GEN

ODD

PAR

FCT480T–1

Pin Configurations

DIP/SOIC/QSOP

Top View

LCC

Top View

8 7 6 5

1110

CHK/GEN

ODD

GND

ODD

ERROR

PAR

CHK/GEN

PAR

1920 2122 23 24 25

ODD

ERROR

ODD

GND

FCT480T–2

FCT480T–3

CY54/74FCT480T

Function Table

Inputs

A₂to H₂

Outputs

A₁to H₁

CHK/GEN

PAR₁

PAR₂

ODD₁

ODD₂

ERROR

Number of A₁to H₁Inputs Number of A₂to H₂Inputs

HIGH is EVEN

Number of Inputs HIGH A₂

to H₂is ODD

Number of A₁to H₁Inputs Number of A₂to H₂Inputs

HIGH is ODD

HIGH is EVEN

Number of A₂to H₂Inputs

HIGH is ODD

Maximum Ratings^{[1, 2]}

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Operating Range

Storage Temperature .................................–65°C to +150°C

Ambient

Ambient Temperature with

Power Applied.............................................–65°C to +135°C

Range

Temperature

–40°C to +85°C

–55°C to +125°C

V_CC

Commercial All

Military^[3]

5V ± 5%

5V ± 10%

Supply Voltage to Ground Potential ............... –0.5V to +7.0V

DC Input Voltage............................................ –0.5V to +7.0V

DC Output Voltage......................................... –0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin).......120 mA

Power Dissipation ..........................................................0.5W

All

Notes:

1. Unless otherwise noted, these limits are over the operating free-air tem-

perature range.

2. Unused inputs must always be connected to an appropriate logic voltage

level, preferably either V_CCor ground.

3. T_Ais the “instant on” case temperature.

CY54/74FCT480T

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

V_CC= Min., I_OH= –32 mA

Min.

2.0

Typ.^[4]

Max.

Unit

V_OH

Output HIGH Voltage

Com’l

Mil

V_CC= Min., I_OH= –15 mA

V_CC= Min., I_OH= –12 mA

V_CC= Min., I_OL= 64 mA

V_CC= Min., I_OL= 32 mA

2.4

3.3

0.3

2.4

V_OL

Output LOW Voltage

Com’l

Mil

0.55

V_IH

V_IL

V_H

V_IK

I_I

Input HIGH Voltage

Input LOW Voltage

Hysteresis^[5]

2.0

0.8

All inputs

0.2

Input Clamp Diode Voltage

Input HIGH Current

Input LOW Current

V_CC= Min., I_IN= –18 mA

V_CC= Max., V_IN= V_CC

V_CC= Max., V_IN= 2.7V

V_CC= Max., V_IN= 0.5V

V_CC= Max., V_OUT= 2.7V

–0.7

–1.2

µA

I_IH

±1

I_IL

I_OZH

Off State HIGH-Level Output

Current

I_OZL

Off State LOW-Level

Output Current

V_CC= Max., V_OUT= 0.5V

–10

µA

I_OS

Output Short Circuit Current^[6]V_CC= Max., V_OUT= 0.0V

–60

–120

–225

I_OFF

Power-Off Disable

V_CC= 0V, V_OUT= 4.5V

±1

µA

Capacitance^[5]

Parameter

Description

Typ.^[4]

Max.

Unit

C_IN

Input Capacitance

Output Capacitance

C_OUT

Notes:

4. Typical values are at V_CC=5.0V, T_A=+25˚C ambient.

5. This parameter is speciﬁed but not tested.

6. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reﬂect operational values. Otherwise prolonged shorting of

a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter

tests, I_OStests should be performed last.

CY54/74FCT480T

Power Supply Characteristics

Parameter

Description

Test Conditions

V_CC=Max., V_IN< 0.2V,

_IN> V_CC–0.2V

Typ.^[4]

Max.

Unit

I_CC

Quiescent Power Supply Current

0.1

0.2

∆I_CC

Quiescent Power Supply Current

(TTL inputs HIGH)

V_CC=Max., V_IN=3.4V,^[7]

f₁=0, Outputs Open

0.5

2.0

I_CCD

Dynamic Power Supply Current^[8]

V_CC=Max., One Bit Toggling,

50% Duty Cycle, Outputs Open,

0.06

0.12

mA/

MHz

_IN< 0.2V or V_IN> V_CC–0.2V

I_C

Total Power Supply Current^[9]

V_CC=Max.,

50% Duty Cycle, Outputs Open,

One Bit Toggling at f₁=2.5 MHz,

0.7

1.0

2.5

6.5

1.4

2.4

_IN< 0.2V or V_IN> V_CC–0.2V

V_CC=Max.,

50% Duty Cycle, Outputs Open,

One Bit Toggling at f₁=2.5 MHz,

V_IN=3.4V or V_IN=GND

V_CC=Max.,

50% Duty Cycle, Outputs Open,

Sixteen Bits Toggling at f₁=2.5 MHz,

5.0^[10]

_IN< 0.2V or V_IN> V_CC–0.2V

V_CC=Max.,

21.0^[10]

50% Duty Cycle, Outputs Open,

Sixteen Bits Toggling at f₁=2.5 MHz,

V_IN=3.4V or V_IN=GND

Switching Characteristics Over the Operating Range

Description

FCT480AT

Com’l

FCT480BT

Military

Com’l

Unit

t_PLH

t_PHL

Propagation Delay

A to EVEN/ODD

7.5

7.0

6.6

5.6

[11]

t_PLH

t_PHL

Propagation Delay

A to ERROR

7.0

8.5

7.0

8.1

5.6

6.5

t_PLH

t_PHL

Propagation Delay

CHK/GEN to EVEN/ODD

6.5

7.5

6.3

7.4

5.9

t_PLH

t_PHL

Propagation Delay

CHK/GEN to ERROR

7.5

7.0

7.1

6.9

5.7

5.5

Notes:

7. Per TTL driven input (V_IN=3.4V); all other inputs at V_CCor GND.

8. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

9. I_C

I_C

I_QUIESCENT+ I_INPUTS+ I_DYNAMIC

I_CC+∆I_CCD_HN_T+I_CCD(f₀/2 + f₁N₁)

Quiescent Current with CMOS input levels

Power Supply Current for a TTL HIGH input (V_IN=3.4V)

Duty Cycle for TTL inputs HIGH

I_CC

∆I_CC

D_H

N_T

I_CCD

f₀

Number of TTL inputs at D_H

Dynamic Current caused by an input transition pair (HLH or LHL)

Clock frequency for registered devices, otherwise zero

Input signal frequency

f₁

N₁

Number of inputs changing at f₁

All currents are in milliamps and all frequencies are in megahertz.

10. Values for these conditions are examples of the I_CCformula. These limits are speciﬁed but not tested.

11. t_PLHis measured up to V_OUT=V_OL+0.3V

CY54/74FCT480T

Ordering Information

Speed

Package

Name

Operating

Range

(ns)

Ordering Code

Package Type

24-Lead (300-Mil) Molded DIP

24-Lead (150-Mil) QSOP

5.6

CY74FCT480BTPC

P13/13A

Q13

Commercial

CY74FCT480BTQCT

CY74FCT480BTSOC/SOCT

CY54FCT480BTLMB

CY74FCT480ATPC

S13

24-Lead (300-Mil) Molded SOIC

28-Square Leadless Chip Carrier

24-Lead (300-Mil) Molded DIP

24-Lead (150-Mil) QSOP

7.0

7.5

L64

Military

P13/13A

Q13

Commercial

CY74FCT480ATQCT

Document #: 38-00281-B

CY54/74FCT480T

Package Diagrams

28-Square Leadless Chip Carrier L64

MIL-STD-1835 C-4

24-Lead (300-Mil) Molded DIP P13/P13A

CY54/74FCT480T

Package Diagrams (continued)

24-Lead Quarter Size Outline Q13

24-Lead (300-Mil) Molded SOIC S13

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CY5474FCT480T [TI]

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