CY74FCT163500SSOP [TI]
18-Bit Registered Transceiver; 18位寄存收发器
| 型号： | CY74FCT163500SSOP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-Bit Registered Transceiver |
| 文件： | 总7页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163500
SCCS066 - June 1997 - Revised March 2000
18-Bit Registered Transceiver
Features
Functional Description
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
The CY74FCT163500 is an 18-bit universal bus transceiver
that can be operated in transparent, latched, or clock modes
by combining D-type latches and D-type flip-flops. Data flow in
each direction is controlled by output-enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock inputs
(CLKAB and CLKBA) inputs. For A-to-B data flow, the device
operates in transparent mode when LEAB is HIGH. When
LEAB is LOW, the A data is latched if CLKAB is held at a HIGH
or LOW logic level. If LEAB is LOW, the A bus data is stored in
the latch/flip-flop on the HIGH-to-LOW transition of CLKAB.
OEAB performs the output enable function on the B port. Data
flow from B-to-A is similar to that of A-to-B and is controlled by
OEBA, LEBA, and CLKBA.
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.6 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Volp (ground bounce) performance exceeds Mil
Std 883D
The CY74FCT163500 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce.The inputs
and outputs are capable of being driven by 5.0V busses,
allowing them to be used in mixed voltage systems as
translators. The outputs are also designed with a power off
disable feature enabling them to be used in applications
requiring live insertion.
• VCC = 2.7V to 3.6V
Logic Block Diagram
Pin Configuration
SSOP/TSSOP
Top View
GND
1
2
3
4
56
55
54
OEAB
LEAB
CLKAB
B
1
A
1
OEAB
GND
GND
53
52
51
50
B
2
A
2
5
6
CLKBA
B
V
A
3
3
V
CC
CC
LEBA
OEBA
7
B
A
4
4
5
6
49
48
47
46
8
A
A
B
B
5
6
9
CLKAB
LEAB
10
11
GND
GND
A
7
B
7
45
44
43
12
13
A
A
B
B
B
8
9
8
C
D
C
D
14
15
16
17
18
9
B
1
A
10
42
41
A
1
10
A
A
B
11
B
12
11
12
40
39
38
GND
GND
C
D
C
D
A
A
A
B
13
14
15
19
20
21
22
23
13
14
15
B
37
36
35
34
B
V
V
CC
CC
B
16
A
16
17
A
33
32
31
30
29
B
17
24
25
TO 17 OTHER CHANNELS
GND
GND
A
B
18
26
27
28
18
OEBA
LEBA
CLKBA
GND
Copyright © 2000, Texas Instruments Incorporated
CY74FCT163500
Maximum Ratings[5, 6]
Pin Summary
Name
Description
(Above which the useful life may be impaired. For user
guidelines, not tested.)
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
A
A-to-B Output Enable Input
Storage Temperature ................................ −55°C to +125°C
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
Ambient Temperature with
Power Applied................................................. −55°C to +125°C
B-to-A Latch Enable Input
Supply Voltage Range..................................... 0.5V to +4.6V
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
A-to-B Clock Input (Active LOW)
B-to-A Clock Input (Active LOW)
A-to-B Data Inputs or B-to-A Three-State Outputs
B-to-A Data Inputs or A-to-B Three-State Outputs
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
B
Power Dissipation..........................................................1.0W
Function Table[1, 2]
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Inputs
Outputs
Operating Range
OEAB
LEAB
CLKAB
A
X
L
B
Z
L
X
H
H
L
X
X
X
Ambient
Temperature
Range
Industrial
VCC
H
H
H
H
H
H
L
−40°C to +85°C
2.7V to 3.6V
H
L
H
L
L
H
X
X
H
L
H
L
B[3]
B[4]
L
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance.
2. A-to-B data flow is shown, B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
3. Output level before the indicated steady-state input conditions were established.
= HIGH-to-LOW Transition.
4. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW.
5. Operation beyond the limits set forth may impair the useful life of the device. Unless noted, these limits are over the operating free-air temperature range.
6. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
2
CY74FCT163500
Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Input HIGH Voltage
Test Conditions
All Inputs
Min.
Typ.[7]
Max.
5.5
Unit
V
VIH
VIL
VH
VIK
IIH
2.0
Input LOW Voltage
Input Hysteresis[8]
0.8
V
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
Input LOW Current
VCC=Min., IIN=−18 mA
VCC=Max., VI=5.5V
−0.7
−1.2
±1
µA
µA
µA
IIL
VCC=Max., VI=GND.
VCC=Max., VOUT=5.5V
±1
IOZH
High Impedance Output Current
(Three-State Output pins)
±1
IOZL
IODL
IODH
VOH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=GND
±1
µA
mA
mA
Output LOW Current[9]
Output HIGH Current[9]
Output HIGH Voltage
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
45
180
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
–45
–180
VCC=Min., IOH= –0.1 mA
VCC=3.0V, IOH= –8 mA
VCC=3.0V, IOH= –24 mA
VCC=Min., IOL= 0.1mA
VCC=Min., IOL= 24 mA
VCC=Max., VOUT=GND
VCC=0V, VOUT≤4.5V
VCC–0.2
2.4
V
V
V
V
3.0
3.0
2.0
VOL
Output LOW Voltage
0.2
0.5
0.3
IOS
Short Circuit Current[9]
Power-Off Disable
–60
–135
–240
±100
mA
IOFF
µA
Capacitance[8] (TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.[7] Max.
Unit
pF
CIN
VIN = 0V
VOUT = 0V
4.5
5.5
6.0
8.0
COUT
pF
Notes:
7. Typical values are at VCC=3.3V, TA = +25˚C ambient.
8. This parameter is specified but not tested.
9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
3
CY74FCT163500
Power Supply Characteristics
Parameter
Description
Test Conditions
VIN≤0.2V,
Typ.[7]
Max.
Unit
ICC
Quiescent Power Supply Cur-
rent
VCC=Max.
VCC=Max.
0.1
10
µA
VIN≥VCC−0.2V
VIN=VCC–0.6V[10]
∆ICC
Quiescent Power Supply Cur-
rent (TTL inputs HIGH)
2.0
50
30
75
µA
ICCD
Dynamic Power Supply
Current[11]
VCC=Max., One Input Toggling, VIN=VCC or
50%DutyCycle,OutputsOpen, VIN=GND
OEAB=OEBA=VCC or GND
µA/MHz
IC
Total Power Supply Current[12]
VCC=Max., f0=10 MHz
(CLKAB), f1=5 MHz, 50% Duty VIN=GND
Cycle, Outputs Open,
One Bit Toggling,
OEAB=OEBA=VCC
LEAB=GND
VIN=VCC or
0.5
0.5
0.8
0.8
mA
mA
VIN=VCC–0.6V or
VIN=GND
VCC=Max., f0=10 MHz,
f1=2.5 MHz, 50% Duty
Cycle, Outputs Open,
Eighteen Bits Toggling,
OEAB=OEBA=VCC
LEAB=GND
VIN=VCC or
VIN=GND
2.5
2.6
3.8[13]
4.1[13]
mA
mA
VIN=VCC–0.6V or
VIN=GND
Notes:
10. Per TTL driven input; all other inputs at VCC or GND.
11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
12. IC
=
=
=
=
=
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
IC
ICC+∆ICCDHNT+ICCD(f0NC /2 + f1N1)
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
ICC
∆ICC
DH
NT
ICCD
f0
NC
f1
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Number of clock inputs changing at f1
Input signal frequency
N1
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
4
CY74FCT163500
Switching Characteristics Over the Operating Range VCC = 3.0V to 3.6V[,14, 15]
CY74FCT163500A CY74FCT163500C
Parameter
Description
Min.
Max.
150
5.1
Min.
Max.
150
4.6
Unit
MHz
ns
Fig. No.[16]
fMAX
CLKAB or CLKBA frequency
tPLH
tPHL
Propagation Delay
A to B or B to A
1.5
1.5
1.5
1.5
1.5
3.0
0
1.5
1.5
1.5
1.5
1.5
3.0
0
1, 3
1, 5
1, 5
1, 7, 8
1, 7, 8
9
tPLH
tPHL
Propagation Delay
LEBA to A, LEAB to B
5.6
5.6
6.0
5.6
5.3
5.3
5.4
5.2
ns
ns
ns
ns
ns
ns
tPLH
tPHL
Propagation Delay
CLKBA to A, CLKAB to B
tPZH
tPZL
Output Enable Time
OEBA to A, OEAB to B
tPHZ
tPLZ
Output Disable Time
OEBA to A, OEAB to B
tSU
Set-Up Time, HIGH or LOW
A to CLKAB, B to CLKBA
tH
Hold Time, HIGH or LOW
A to CLKAB, B to CLKBA
9
tSU
Set-Up Time, HIGH or LOW
A to LEAB, B to LEBA
Clock HIGH
Clock LOW
3.0
1.5
1.5
3.0
1.5
1.5
ns
ns
ns
4
4
4
tH
Hold Time, HIGH or LOW
A to LEAB, B to LEBA
tW
LEAB or LEBA Pulse Width HIGH
3.0
3.0
2.5
3.0
ns
ns
ns
5
5
tW
CLKAB or CLKBA Pulse Width HIGH or LOW
Output Skew[17]
tSK(O)
0.5
0.5
Ordering Information CY74FCT163500
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
4.6
CY74FCT163500CPACT
Z56
O56
O56
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
Industrial
CY74FCT163500CPVC/PVCT
CY74FCT163500APVC/PVCT
5.1
Industrial
Notes:
14. Minimum limits are specified but not tested on Propagation Delays.
15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.
16. See “Parameter Measurement Information” in the General Information section.
17. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
5
CY74FCT163500
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
6
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Copyright 2000, Texas Instruments Incorporated
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