CY74FCT163646TSSOP [TI]
16-Bit Registered Transceiver; 16位寄存收发器
| 型号： | CY74FCT163646TSSOP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Registered Transceiver |
| 文件： | 总8页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY74FCT163646
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163646
SCCS058 - March 1997 - Revised March 2000
16-Bit Registered Transceiver
Features
Functional Description
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
The CY74FCT163646 16-bit transceiver is a three-state,
D-type register, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal registers. Data on the A or B bus will be clocked into
the registers as the appropriate clock pin goes to a HIGH logic
level. Output Enable (OE) and direction pins (DIR) are
provided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be stored
in either the A or B register, or in both. The select controls can
multiplex stored and real-time (transparent mode) data. The
direction control determines which bus will receive data when
the Output Enable (OE) is Active LOW. In the isolation mode
(Output Enable (OE) HIGH), A data may be stored in the B
register and/or B data may be stored in the A register.
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 5.4 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250 ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Volp (ground bounce) performance exceeds Mil
Std 883D
• VCC = 2.7V to 3.6V
The CY74FCT163646 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The inputs
and outputs were designed to be capable of being driven by
5.0V buses, allowing them to be used in mixed voltage
systems as translators. The outputs are also designed with a
power-off disable feature enabling them to be used in
applications requiring live insertion.
Logic Block Diagrams
OE
2
OE
1
DIR
2
DIR
CLKBA
SBA
CLKAB
1
CLKBA
2
1
SBA
CLKAB
2
1
2
1
SAB
2
SAB
1
B REG
D
B REG
D
C
C
A REG
D
B
2
1
A REG
D
B
1
1
A
2 1
A
1 1
C
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
Copyright © 2000, Texas Instruments Incorporated
CY74FCT163646
SSOP/TSSOP
Top View
Pin Configuration
DIR
OE
1
1
1
2
56
55
CLKBA
1
1
CLKAB
SAB
1
SBA
3
4
54
53
1
GND
GND
B
A
1 1
5
6
7
8
9
52
51
50
49
48
1
1
2
A
1 2
B
1
V
CC
V
CC
A
1 3
B
1
3
4
5
A
1 4
B
1
A
1 5
B
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
47
46
45
44
43
42
41
40
39
38
37
36
35
34
GND
GND
B
A
1 6
1
6
7
8
1
2
3
B
1
A
1 7
A
1 8
B
1
B
2
A
2 1
A
2 2
B
2
B
2
A
2 3
GND
GND
B
A
2 4
2
4
5
6
A
2 5
B
2
A
2 6
B
2
V
CC
V
CC
B
A
2 7
2
7
8
A
2 8
B
2
24
25
33
32
GND
SAB
GND
SBA
2
26
27
28
31
30
29
2
CLKAB
CLKBA
2
2
OE
2
DIR
2
Pin Description
Pin Names
Description
A
Data Register A Inputs Data Register B Outputs
Data Register B Inputs Data Register A Outputs
Clock Pulse Inputs
B
CLKAB, CLKBA
SAB, SBA
DIR
Output Data Source Select Inputs
Direction
OE
Output Enable (Active LOW)
Function Table[1]
Inputs
Data I/O[2]
Function
OE
DIR
CLKAB
CLKBA
SAB
SBA
A
B
H
H
X
X
H or L
H or L
X
X
X
X
Input
Input Isolation
Store A and B Data
L
L
L
L
X
X
X
X
X
L
H
Output Input Real Time B Data to A Bus
Stored B Data to A Bus
H or L
L
L
H
H
X
X
X
L
H
X
X
Input Output Real Time A Data to Bus
Stored A Data to B Bus
H or L
Notes:
1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care,
= LOW-to-HIGH Transition
2. The data output functions may be enabled or disabled by various signals at the OE or DIR inputs. Data input functions are always enabled, i.e., data at the
bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
2
CY74FCT163646
BUS A
BUS B
BUS A
BUS B
DIR
L
OE
L
CLKAB
X
CLKBA
X
SAB
X
SBA
L
DIR
H
OE
L
CLKAB
X
CLKBA
X
SAB
L
SBA
X
Real-Time Transfer
BusB to BusA
Real-Time Transfer
BusA to BusB
BUS A
BUS B
BUS A
BUS A
[3]
DIR
H
L
OE
L
L
H
SAB
SBA
X
X
DIR
L
H
OE
L
L
SAB
X
H
SBA
H
X
CLKAB
X
CLKBA
X
CLKAB
X
H or L
CLKBA
H or L
X
X
X
X
X
X
Storage from
A and/or B
Transfer Stored Data
to A and/or B
Maximum Ratings[4]
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ............................... −55°C to +125°C
Ambient Temperature with
Power Applied............................................ −55°C to +125°C
Operating Range
Supply Voltage Range ..................................... 0.5V to +4.6V
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
Ambient
Range
Industrial
Temperature
VCC
–40°C to +85°C
2.7V to 3.6V
Notes:
3. Cannot transfer data to A-bus and B-bus simultaneously.
4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
3
CY74FCT163646
Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Test Conditions
Min.
Typ.[5]
Max.
5.5
Unit
V
VIH
VIL
VH
VIK
IIH
Input HIGH Voltage
All Inputs
2.0
Input LOW Voltage
Input Hysteresis[6]
0.8
V
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
Input LOW Current
VCC=Min., IIN=−18 mA
VCC=Max., VI=5.5V
VCC=Max., VI=GND
VCC=Max., VOUT=5.5V
−0.7
−1.2
±1
µA
µA
µA
IIL
±1
IOZH
High Impedance Output Current
(Three-State Output pins)
±1
IOZL
IODL
IODH
VOH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=GND
±1
µA
mA
mA
V
Output LOW Dynamic Current[7]
Output HIGH Dynamic Current[7]
Output HIGH Voltage
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
45
180
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
–45
–180
VCC=Min., IOH= –0.1 mA
VCC=3.0V, IOH= –8 mA
VCC=3.0V, IOH= –24 mA
VCC=Min., IOL= 0.1mA
VCC=Min., IOL= 24 mA
VCC=Max., VOUT=GND
VCC=0V, VOUT≤4.5V
VCC–0.2
2.4[8]
2.0
3.0
3.0
VOL
Output LOW Voltage
0.2
0.5
V
0.3
IOS
Short Circuit Current[7]
Power-Off Disable
–60
–135
–240
±100
mA
IOFF
µA
Capacitance[5] (TA = +25˚C, f = 1.0 MHz)
Symbol
Description[9]
Conditions
VIN = 0V
Typ.
4.5
Max.
Unit
CIN
Input Capacitance
Output Capacitance
6.0
8.0
pF
pF
COUT
VOUT =0V
5.5
Notes:
5. Typical values are at VCC=3.3V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametrics tests. In any sequence of parameter
tests, IOS tests should be performed last.
8. VOH=VCC–0.6 V at rated current.
9. This parameter is measured at characterization but not tested.
4
CY74FCT163646
Power Supply Characteristics
Parameter
Description
Test Conditions
VIN<0.2V
Typ.[5]
Max.
Unit
ICC
Quiescent Power Supply Current VCC=Max.
0.1
10
µA
VIN>VCC−0.2V
∆ICC
Quiescent Power Supply Current VCC=Max.
TTL Inputs HIGH
VIN=VCC–0.6V[10]
2.0
50
30
75
µA
ICCD
Dynamic Power Supply
Current[11]
VCC=Max., Outputs Open
VIN=VCC or
VIN=GND
µA/MHz
DIR=OE=GND
One-Bit Toggling
50% Duty Cycle
IC
Total Power Supply Current[12]
VCC=Max.,Outputs Open
fo=10 MHz (CLKBA)
50% Duty Cycle
DIR=OE=GND
One-BitToggling, f1=5MHz,
VIN=VCC or
VIN=GND
0.5
0.5
0.8
0.8
mA
VIN=VCC–0.6V or
VIN=GND
50% Duty Cycle
VCC=Max., Outputs Open
fo=10 MHz (CLKBA)
50% Duty Cycle
DIR=OE=GND
Sixteen-Bits Toggling
f1=2.5 MHz
VIN=VCC or
VIN=GND
2.5
2.6
3.8[13]
4.1[13]
VIN=VCC–0.6V or
VIN=GND
50% Duty Cycle
Notes:
10. Per TTL driven input); all other inputs at VCC or GND.
11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
12. IC
IC
=
=
=
=
=
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
ICC+∆ICCDHNT+ICCD(f0NC /2 + f1N1)
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input
Duty Cycle for TTL inputs HIGH
ICC
∆ICC
DH
NT
ICCD
f0
NC
f1
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Number of clock inputs changing at f1
Input signal frequency
N1
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
5
CY74FCT163646
Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[14,15]
CY74FCT163646C
Parameter
Description
Propagation Delay Bus to Bus
Min.
Max.
Unit
Fig. No.[16]
tPLH
1.5
5.4
ns
1, 2
tPHL
tPZH
tPZL
Output Enable Time DIR or OE to Bus
Output Disable Time DIR or OE to Bus
Propagation Delay Clock to Bus
1.5
1.5
1.5
1.5
7.8
6.3
5.7
6.2
ns
ns
ns
ns
1, 7, 8
1, 7, 8
1, 5
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
Propagation Delay SBA or SAB to Bus
1,5
tSU
tH
Set-Up Time HIGH or LOW Bus to Clock
Hold Time HIGH or LOW Bus to Clock
Clock Pulse Width HIGH or LOW
Output Skew[17]
2.0
1.5
5.0
—
—
—
ns
ns
ns
ns
4
4
tW
—
6
tSK(O)
0.5
—
Ordering Information CY74FCT163646
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT163646CPACT
CY74FCT163646CPVC/PVCT
Package Type
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
5.4
Z56
O56
Industrial
Notes:
14. Minimum limits are specified but not tested on Propagation Delays.
15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.
16. See “Parameter Measurement Information” in the General Information section.
17. Skew any two outputs of the same package switching in the same direction. This parameter is ensured by design.
6
CY74FCT163646
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
7
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
相关型号：
CY74FCT16373ATPACR
IC FCT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
CYPRESS
©2020 ICPDF网 联系我们和版权申明