CY74FCT543TSOIC [TI]

8-Bit Latched Registered Transceiver; 8位锁存寄存收发器


型号：	CY74FCT543TSOIC
厂家：	TEXAS INSTRUMENTS
描述：	8-Bit Latched Registered Transceiver 8位锁存寄存收发器
文件：	总9页 (文件大小：76K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

CY54/74FCT543T

SCCS030 - May 1994 - Revised March 2000

8-Bit Latched Registered Transceiver

Features

Functional Description

• Function, pinout, and drive compatible with FCT and

The FCT543T octal latched transceiver contains two sets of

eight D-type latches with separate latch enable (LEAB, LEBA)

and output enable (OEAB, OEBA) controls for each set to

permit independent control of inputting and outputting in either

direction of data ﬂow. For data ﬂow from A to B, for example,

the A-to-B enable (CEAB) input must be LOW in order to enter

data from A or to take data from B, as indicated in the truth

table. With CEAB LOW, a LOW signal on the A-to-B latch

enable (LEAB) input makes the A-to-B latches transparent; a

subsequent LOW-to-HIGH transition of the LEAB signal puts

the A latches in the storage mode and their output no longer

change with the A inputs. With CEAB and OEAB both LOW,

the three-stage B output buffers are active and reﬂect the data

present at the output of the A latches. Control of data from B

to A is similar, but uses CEAB, LEAB, and OEAB inputs.

F logic

• FCT-C speed at 5.3 ns max. (Com’l)

FCT-A speed at 6.5 ns max. (Com’l)

• Reduced V_OH(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

• Power-off disable feature

• Matched rise and fall times

• Fully compatible with TTL input and output logic levels

• ESD > 2000V

• Sink current

Source current

64 mA (Com’l), 48 mA (Mil)

32 mA (Com’l), 12 mA (Mil)

• Separation controls for data ﬂow in each direction

• Back to back latches for storage

The outputs are designed with a power-off disable feature to

allow for live insertion of boards.

• Extended commercial range of −40˚C to +85˚C

Functional Block Diagram

Logic Block Diagram

DetailA

D Q

CEAB

OEAB

Q D

CEBA

LEAB

LEBA

OEBA

DetailA x 7

Pin Configurations

SOIC/QSOP

Top View

OEBA

OEAB

LEBA

OEBA

CEBA

LEBA

CEBA

CEAB

LEAB

CEAB

GND

LEAB

OEAB

CY54/74FCT543T

Maximum Ratings^{[4, 5]}

Pin Description

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Name

Description

OEAB

OEBA

CEAB

CEBA

LEAB

LEBA

A-to-B Output Enable Input (Active LOW)

B-to-A Output Enable Input (Active LOW)

A-to-B Enable Input (Active LOW)

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied............................................. –65°C to +135°C

B-to-A Enable Input (Active LOW)

Supply Voltage to Ground Potential............... –0.5V to +7.0V

DC Input Voltage ........................................... –0.5V to +7.0V

DC Output Voltage......................................... –0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin) ......120 mA

Power Dissipation..........................................................0.5W

A-to-B Latch Enable Input (Active LOW)

B-to-A Latch Enable Input (Active LOW)

A-to-B Data Inputs or B-to-A Three-State Outputs

B-to-A Data Inputs or A-to-B Three-State Outputs

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Function Table^{[1, 2]}

Inputs

Latch

OEAB A-to-B^[3]

Outputs

Operating Range

CEAB

LEAB

Ambient

Storing

High Z

Range

Temperature

V_CC

Commercial DT

0°C to +70°C

5V ± 5%

5V ± 10%

High Z

Commercial T, AT, CT

Military^[6]

–40°C to +85°C

–55°C to +125°C

Transpar- Current A Inputs

ent

All

Storing

Previous A Inputs

Notes:

1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.

2. A-to-B data ﬂow shown: B-to-A ﬂow control is the same, except using CEBA, LEBA, and OEBA.

3. Before LEAB LOW-to-HIGH Transition.

4. Unless otherwise noted, these limits are over the operating free-air temperature range.

5. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V_CCor ground.

6. T_Ais the “instant on” case temperature.

CY54/74FCT543T

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

V_CC=Min., I_OH=–32 mA

Min.

2.0

Typ.^[7]

Max.

Unit

V_OH

Output HIGH Voltage

Com’l

Mil

V_CC=Min., I_OH=–15 mA

V_CC=Min., I_OH=–12 mA

V_CC=Min., I_OL=64 mA

V_CC=Min., I_OL=48mA

2.4

3.3

0.3

2.4

V_OL

Output LOW Voltage

Com’l

Mil

0.55

V_IH

V_IL

V_H

V_IK

I_IH

Input HIGH Voltage

Input LOW Voltage

Hysteresis^[8]

2.0

0.8

All inputs

0.2

Input Clamp Diode Voltage

Input HIGH Current

Input HIGH Current^[8]

Input LOW Current^[8]

V_CC=Min., I_IN=–18 mA

V_CC=Max., V_IN=V_CC

V_CC=Max., V_IN=2.7V

V_CC=Max., V_IN=0.5V

V_CC=Max., V_OUT= 2.7V

–0.7

–1.2

µA

I_IH

±1

I_IL

I_OZH

Off State HIGH-Level Output

Current

I_OZL

Off State LOW-Level

Output Current

V_CC= Max., V_OUT= 0.5V

–10

µA

I_OS

Output Short Circuit Current^[9]V_CC=Max., V_OUT=0.0V

–60

–120

–225

I_OFF

Power-Off Disable

V_CC=0V, V_OUT=4.5V

±1

µA

Capacitance^[8]

Parameter

Description

Typ.^[7]

Max.

Unit

C_IN

Input Capacitance

Output Capacitance

C_OUT

Notes:

7. Typical values are at V_CC=5.0V, T_A=+25˚C ambient.

8. This parameter is speciﬁed but not tested.

9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reﬂect operational values. Otherwise prolonged shorting of

a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter

tests, I_OStests should be performed last.

CY54/74FCT543T

Power Supply Characteristics

Parameter

I_CC

Description

Test Conditions

Typ.^[7]

0.1

Max.

0.2

Unit

Quiescent Power Supply Current V_CC=Max., V_IN≤0.2V, V_IN≥V_CC–0.2V

Quiescent Power Supply Current V_CC=Max., V_IN=3.4V,^[10]

∆I_CC

0.5

2.0

(TTL inputs)

f₁=0, Outputs Open

I_CCD

Dynamic Power Supply Current^[11]V_CC=Max., One Input Toggling,

0.06

0.7

0.12

1.4

mA/MHz

50% Duty Cycle, Outputs Open,

CEAB and OEAB=LOW, CEBA=HIGH,

V_IN≤0.2V or V_IN≥V_CC–0.2V

I_C

Total Power Supply Current^[12]

V_CC=Max., f₀=10 MHz,

50% Duty Cycle, Outputs Open,

One Bit Toggling at f₁=5 MHz,

CEAB and OEAB=LOW,CEBA=HIGH,

f₀=LEAB = 10 MHz,

V_IN≤0.2V or V_IN≥V_CC–0.2V

V_CC=Max., f₀=10 MHz,

50% Duty Cycle, Outputs Open,

One Bit Toggling at f₁=5 MHz,

CEAB and OEAB=LOW, CEBA=HIGH,

f₀=LEAB = 10 MHz, V_IN=3.4V or V_IN=GND

1.2

2.8

3.4

V_CC=Max., f₀=10 MHz,

5.6^[13]

50% Duty Cycle, Outputs Open,

Eight Bits Toggling at f₁=5 MHz,

CEAB and OEAB=LOW, CEBA=HIGH,

f₀=LEAB = 10 MHz,

V_IN≤0.2V or V_IN≥V_CC–0.2V

V_CC=Max., f₀=10 MHz,

5.1

14.6^[13]

50% Duty Cycle, Outputs Open,

Eight Bits Toggling at f₁=5 MHz,

CEAB and OEAB=LOW, CEBA=HIGH,

f₀=LEAB = 10 MHz, V_IN=3.4V or V_IN=GND

Notes:

10. Per TTL driven input (V_IN=3.4V); all other inputs at V_CCor GND.

11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

12. I_C

I_C

I_QUIESCENT+ I_INPUTS+ I_DYNAMIC

I_CC+∆I_CCD_HN_T+I_CCD(f₀/2 + f₁N₁)

Quiescent Current with CMOS input levels

Power Supply Current for a TTL HIGH input (V_IN=3.4V)

Duty Cycle for TTL inputs HIGH

I_CC

∆I_CC

D_H

N_T

I_CCD

f₀

Number of TTL inputs at D_H

Dynamic Current caused by an input transition pair (HLH or LHL)

Clock frequency for registered devices, otherwise zero

Input signal frequency

f₁

N₁

Number of inputs changing at f₁

All currents are in milliamps and all frequencies are in megahertz.

13. Values for these conditions are examples of the I_CCformula. These limits are speciﬁed but not tested.

CY54/74FCT543T

Switching Characteristics Over the Operating Range^[14]

FCT543T

Commercial

Min.^[14]Max. Min.^[14]Max. Min.^[14]

FCT543AT

Military

Commercial

Parameter

Description

Propagation Delay

Transparent Mode A to B or B to A

Max.

Unit Fig. No.^[15]

t_PLH

t_PHL

2.0

2.5

2.0

10.0

14.0

2.5

2.0

8.5

2.5

2.0

6.5

1, 3

t_PLH

t_PHL

Propagation Delay

LEBA to A, LEAB to B

12.5

12.0

8.0

9.0

1, 5

t_PZH

t_PZL

Output Enable Time

OEBA or OEAB to A or B

CEBA or CEAB to A or B

1, 7, 8

t_PZH

t_PZL

Output Disable Time

OEBA or OEAB to A or B

CEBA or CEAB to A or B

2.0

13.0

2.0

9.0

2.0

7.5

1, 7, 8

t_S

Set-Up Time HIGH or LOW,

A or B to LEBA or LEAB

3.0

2.0

5.0

2.0

5.0

2.0

5.0

t_H

t_W

Hold Time HIGH or LOW,

A or B to LEBA or LEAB

Pulse Width LOW^[8]

LEBA or LEAB

FCT543CT

Commercial

Parameter

Description

Min.^[14]

Max.

5.3

Unit

Fig. No.^[15]

t_PLH

t_PHL

Propagation Delay

2.5

2.0

1, 3

Transparent Mode A to B or B to A

t_PLH

t_PHL

Propagation Delay

LEBA to A, LEAB to B

7.0

8.0

1, 5

t_PZH

t_PZL

Output Enable Time

OEBA or OEAB to A or B

CEBA or CEAB to A or B

1, 7, 8

t_PZH

t_PZL

Output Disable Time

OEBA or OEAB to A or B

CEBA or CEAB to A or B

2.0

6.5

1, 7, 8

t_S

t_H

Set-Up Time, HIGH or LOW,

A or B to LEBA or LEAB

2.0

5.0

Hold Time, HIGH or LOW,

A or B to LEBA or LEAB

Pulse Width LOW LEBA or LEAB^[8]

t_W

Notes:

14. Minimum limits are speciﬁed but not tested on Propagation Delays.

15. See “Parameter Measurement Information” in the General Information Section.

CY54/74FCT543T

Ordering Information

Speed

Package

Name

Operating

Range

(ns)

Ordering Code

Package Type

24-Lead (150-Mil) QSOP

5.3

CY74FCT543CTQCT

Q13

S13

Q13

S13

Q13

S13

D14

Commercial

Military

CY74FCT543CTSOC/SOCT

CY74FCT543ATQCT

24-Lead (300-Mil) Molded SOIC

24-Lead (150-Mil) QSOP

6.5

8.5

CY74FCT543ATSOC/SOCT

CY74FCT543TQCT

24-Lead (300-Mil) Molded SOIC

24-Lead (150-Mil) QSOP

CY74FCT543TSOC/SOCT

CY54FCT543TDMB

24-Lead (300-Mil) Molded SOIC

24-Lead (300-Mil) CerDIP

10.0

Document #: 38-00264-B

CY54/74FCT543T

Package Diagrams

24-Lead (300-Mil) CerDIP D14

MIL-STD-1835 D-9 Config.A

24-Lead Quarter Size Outline Q13

CY54/74FCT543T

Package Diagrams (continued)

24-Lead (300-Mil) Molded SOIC S13

IMPORTANT NOTICE

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

CY74FCT543TSOIC [TI]

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