CY74FCT573ATPC [TI]
8-Bit Latches; 8位锁存器型号: | CY74FCT573ATPC |
厂家: | TEXAS INSTRUMENTS |
描述: | 8-Bit Latches |
文件: | 总8页 (文件大小:83K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT373T
CY54/74FCT573T
SCCS021 - May 1994 - Revised February 2000
8-Bit Latches
Features
Functional Description
• Function and pinout compatible with FCT, and F logic
• FCT-C speed at 4.2 ns max. (Com’l),
FCT-A speed at 5.2 ns max. (Com’l)
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• ESD > 2000V
• Matched rise and fall times
• Extended commercial range of −40˚C to +85˚C
• Fully compatible with TTL input and output logic levels
The FCT373T and FCT573T consist of eight latches with
three-state outputs for bus organized applications. When latch
enable (LE) is HIGH, the flip-flops appear transparent to the
data. Data that meets the required set-up times are latched
when LE transitions from HIGH to LOW. Data appears on the
bus when the (OE) is LOW. When output enable is HIGH, the
bus output is in the impedance state. In this mode, data may
be entered into the latches. The FCT573T is identical to the
FCT373T except for the flow-through pinout, which simplifies
board design.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
• Sink current
64 mA (Com’l), 32 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)
Logic Block Diagram
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Pin Configurations
DIP/SOIC/QSOP
Top View
DIP/SOIC/QSOP
Top View
OE
1
2
3
4
5
6
7
8
9
10
V
OE
20
19
18
17
CC
1
2
3
4
5
6
7
8
9
10
V
20
19
18
17
CC
D
0
O
0
O
0
O
7
D
1
O
1
D
0
D
7
D
2
O
2
D
1
D
6
FCT573T
D
3
FCT373T
O
3
16
O
1
O
6
16
D
4
O
4
15
14
13
12
11
O
2
O
5
15
14
13
12
11
D
5
O
5
D
2
D
5
D
6
O
6
D
3
D
4
D
7
O
7
O
3
O
4
GND
LE
GND
LE
Logic Symbol
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Copyright © 2000, Texas Instruments Incorporated
CY54/74FCT373T
CY54/74FCT573T
Function Table[1]
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Input Voltage ........................................... –0.5V to +7.0V
DC Output Voltage......................................... –0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ......120 mA
Power Dissipation..........................................................0.5W
Inputs
Outputs
OE
L
LE
H
H
L
D
H
L
O
H
L
L
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
L
X
X
Q0
Z
H
X
Operating Range
Maximum Ratings[2, 3]
Ambient
Range
Range
Temperature
–40°C to +85°C
–55°C to +125°C
VCC
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Commercial T, AT, CT
Military[4]
5V ± 5%
5V ± 10%
Storage Temperature .................................–65°C to +150°C
All
Ambient Temperature with
Power Applied.............................................–65°C to +135°C
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VCC=Min., IOH=–32 mA
Min.
2.0
Typ.[5]
Max.
Unit
V
VOH
Output HIGH Voltage
Com’l
Com’l
Mil
VCC=Min., IOH=–15 mA
VCC=Min., IOH=–12 mA
VCC=Min., IOL=64 mA
VCC=Min., IOL=32 mA
2.4
3.3
3.3
0.3
0.3
V
2.4
V
VOL
Output LOW Voltage
Com’l
Mil
0.55
0.55
V
V
VIH
VIL
VH
VIK
II
Input HIGH Voltage
Input LOW Voltage
Hysteresis[6]
2.0
V
0.8
V
All inputs
0.2
V
Input Clamp Diode Voltage
Input HIGH Current
Input HIGH Current
Input LOW Current
VCC=Min., IIN=–18 mA
VCC=Max., VIN=VCC
VCC=Max., VIN=2.7V
VCC=Max., VIN=0.5V
VCC=Max., VOUT=2.7V
–0.7
–1.2
5
V
µA
µA
µA
µA
IIH
±1
±1
10
IIL
IOZH
Off State HIGH-Level Output
Current
IOZL
IOS
Off State LOW-Level
Output Current
Output Short Circuit Current[7] VCC=Max., VOUT=0.0V
VCC=Max., VOUT=0.5V
–10
µA
–60
–120
–225
mA
IOFF
Power-Off Disable VCC=0V, VOUT=4.5V
±1
µA
Notes:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = HIGH Impedance
Qn = Previous state of flip flops (Qn-1
)
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
4. TA is the “instant on” case temperature.
5. Typical values are at VCC=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
2
CY54/74FCT373T
CY54/74FCT573T
Capacitance[6]
Parameter
CIN
Description
Typ.[5]
Max.
10
Unit
pF
Input Capacitance
Output Capacitance
6
8
COUT
12
pF
Power Supply Characteristics
Parameter
ICC
Description
Test Conditions
Typ.[5]
0.1
Max.
Unit
Quiescent Power Supply Current
VCC=Max., VIN ≤ 0.2V, VIN ≥ VCC – 0.2V
VCC=Max., VIN=3.4V, f1=0, Outputs Open[8]
0.2
2.0
mA
mA
∆ICC
Quiescent Power Supply Current
(TTL inputs HIGH)
0.5
ICCD
Dynamic Power Supply Current[9] VCC=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
0.6
0.7
0.12
1.4
mA/MHz
mA
OE=GND, VIN ≤ 0.2V or VIN ≥ VCC – 0.2V
IC
Total Power Supply Current[10]
VCC=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=10 MHz,
OE=GND, LE=VCC
VIN ≤ 0.2V or VIN ≥ VCC – 0.2V
VCC=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=10 MHz,
OE=GND, LE=VCC, VIN=3.4V or VIN=GND
1.0
1.3
2.4
mA
mA
VCC=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=2.5 MHz,
2.6[11]
OE=GND, LE=VCC
,
V
IN ≤ 0.2V or VIN ≥ VCC – 0.2V
VCC=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=2.5 MHz,
3.3
10.6[11]
mA
OE=GND, LE=VCCVIN=3.4V or VIN=GND
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. IC
IC
= IQUIESCENT + IINPUTS + IDYNAMIC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
NT
= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0
f1
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
3
CY54/74FCT373T
CY54/74FCT573T
e
Switching Characteristics Over the Operating Range[12]
FCT373T/FCT573T
FCT373AT/FCT573AT
Military Commercial
Military
Commercial
Fig.
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit No.[13]
tPLH
tPHL
Propagation Delay
D to O
1.5
2.0
1.5
1.5
2.0
8.5
1.5
8.0
1.5
2.0
1.5
1.5
2.0
5.6
1.5
5.2
ns
ns
ns
ns
ns
1, 3
1, 5
tPLH
tPHL
Propagation Delay
LE to O
15.0
13.5
10.0
2.0
1.5
1.5
2.0
13.0
12.0
7.5
9.8
7.5
6.5
2.0
1.5
1.5
2.0
8.5
6.5
5.5
tPZH
tPZL
Output Enable Time
1, 7, 8
1, 7, 8
9
tPHZ
tPLZ
Output Disable Time
tS
Set-Up Time
HIGH to LOW
D to LE
tH
Set-Up Time
HIGH to LOW
D to LE
1.5
6.0
1.5
6.0
1.5
6.0
1.5
5.0
ns
ns
9
5
tW
LE Pulse
Width HIGH
FCT373CT/
FCT573CT
Commercial
Parameter
Description
Min.
Max.
Unit
Fig. No.[13]
tPLH
tPHL
Propagation Delay D to O
Propagation Delay LE to O
Output Enable Time
1.5
4.2
5.5
5.5
5.0
ns
ns
ns
ns
1, 3
tPLH
tPHL
2.0
1.5
1.5
1, 5
tPZH
tPZL
1, 7, 8
1, 7, 8
tPHZ
tPLZ
Output Disable Time
tS
tH
Set-Up Time, HIGH to LOW D to LE
Set-Up Time, HIGH to LOW D to LE
LE Pulse Width HIGH
2.0
1.5
5.0
ns
ns
ns
9
9
5
tW
Note:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
4
CY54/74FCT373T
CY54/74FCT573T
Ordering Information–FCT373T
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT373CTQCT
Package Type
20-Lead (150-Mil) QSOP
4.2
Q5
S5
Q5
S5
D6
S5
D6
Commercial
CY74FCT373CTSOC/SOCT
CY74FCT373ATQCT
20-Lead (300-Mil) Molded SOIC
20-Lead (150-Mil) QSOP
5.2
Commercial
CY74FCT373ATSOC/SOCT
CY54FCT373ATDMB
20-Lead (300-Mil) Molded SOIC
20-Lead (300-Mil) CerDIP
5.6
8.0
8.5
Military
CY74FCT373TSOC/SOCT
CY54FCT373TDMB
20-Lead (300-Mil) Molded SOIC
20-Lead (300-Mil) CerDIP
Commercial
Military
Ordering Information—FCT573T
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT573CTQCT
CY74FCT573CTSOC/SOCT
CY74FCT573ATPC
Package Type
20-Lead (150-Mil) QSOP
4.2
Q5
S5
P5
Q5
S5
Q5
S5
D6
Commercial
20-Lead (300-Mil) Molded SOIC
20-Lead (300-Mil) Molded DIP
20-Lead (150-Mil) QSOP
5.2
Commercial
CY74FCT573ATQCT
CY74FCT573ATSOC/SOCT
CY74FCT573TQCT
20-Lead (300-Mil) Molded SOIC
20-Lead (150-Mil) QSOP
8.0
8.5
Commercial
Military
CY74FCT573TSOC/SOCT
CY54FCT573TDMB
20-Lead (300-Mil) Molded SOIC
20-Lead (300-Mil) CerDIP
Document #: 38-00272-B
5
CY54/74FCT373T
CY54/74FCT573T
Package Diagrams
20-Lead (300-Mil) CerDIP D6
MIL-STD-1835
D-8 Config.A
20-Lead (300-Mil) Molded DIP P5
6
CY54/74FCT373T
CY54/74FCT573T
Package Diagrams (continued)
20-Lead Quarter Size Outline Q5
20-Lead (300-Mil) Molded SOIC S5
7
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 2000, Texas Instruments Incorporated
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