CY74FCT652ATSOCG4 [TI]
FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24;型号: | CY74FCT652ATSOCG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24 光电二极管 输出元件 逻辑集成电路 触发器 |
文件: | 总16页 (文件大小:569K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001
Q OR SO PACKAGE
(TOP VIEW)
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced V
Equivalent FCT Functions
(Typically = 3.3 V) Version of
CPAB
SAB
V
CC
CPBA
OH
1
24
23
22
21
20
19
18
17
16
15
14
13
2
GAB
SBA
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
3
A
GBA
4
1
A
2
B
5
1
A
B
2
6
3
I
Supports Partial-Power-Down Mode
off
A
4
B
7
Operation
3
A
B
4
8
5
Matched Rise and Fall Times
A
6
B
9
5
Fully Compatible With TTL Input and
Output Logic Levels
A
B
6
10
11
7
A
8
GND 12
B
7
64-mA Output Sink Current
32-mA Output Source Current
B
8
Independent Register for A and B Buses
Multiplexed Real-Time and Stored Data
Transfer
3-State Outputs
description
The CY74FCT652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or from the internal storage registers. GAB and GBA
inputs control the transceiver functions. Select-control (SAB and SBA) inputs select either real-time or
stored-data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-time data. A low input level selects real-time data,
and a high input level selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions
of the appropriate clock (CPAB or CPBA) inputs, regardless of the select or enable levels of the control pins.
When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal
D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration, each output reinforces its
input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus
lines remains at its last state.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001
ORDERING INFORMATION
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
QSOP – Q
SOIC – SO
QSOP – Q
SOIC – SO
QSOP – Q
Tape and reel
Tube
5.4
5.4
5.4
6.3
6.3
6.3
9
CY74FCT652CTQCT
CY74FCT652CTSOC
CY74FCT652CTSOCT
CY74FCT652ATQCT
CY74FCT652ATSOC
CY74FCT652ATSOCT
CY74FCT652TQCT
FCT652C
FCT652C
FCT652A
FCT652A
FCT652
Tape and reel
Tape and reel
Tube
–40°C to 85°C
Tape and reel
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR
FUNCTION
GAB
L
GBA
H
CPAB
CPBA
SAB
X
SBA
X
A –A
B –B
1 8
1
8
H or L
H or L
Input
Input
Input
Input
Isolation
L
H
↑
↑
X
X
Store A and B data
§
X
H
↑
H or L
X
X
Input
Unspecified
Output
Input
Store A, hold B
‡
X
H
L
H
↑
↑
X
Input
Store A in both registers
Hold A, store B
§
X
H or L
↑
X
X
Unspecified
Output
Output
Output
Input
‡
X
L
L
↑
X
↑
X
X
X
X
L
Input
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
L
L
Input
L
L
X
H or L
X
H
X
X
Input
H
H
H
X
Output
Output
H
H or L
X
H
Input
Stored A data to B bus and
Stored B data to A bus
H
L
H or L
H or L
H
H
Output
Output
H = High logic level, L = Low logic level, X = Don’t care, ↑ = Low-to-high transition
‡
Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both
registers.
ThedataoutputfunctionscanbeenabledordisabledbyvarioussignalsattheGABandGBAinputs. Datainputfunctions
always are enabled, i.e., data at the bus pins are stored on every low-to-high transition of the clock inputs.
§
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001
3
GAB
L
21
GBA
L
1
23
2
22
SBA
L
3
GAB
H
21
GBA
H
1
CPAB
X
23
2
22
SBA
X
CPAB CPBA SAB
CPBA SAB
X
X
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
3
21
23
2
22
3
GAB
H
21
GBA
L
1
23
CPBA SAB
H or L
2
22
SBA
H
1
CPAB CPBA SAB
SBA
X
CPAB
H or L
GAB
GBA
H
X
L
L
X
↑
X
X
X
H
↑
X
X
X
H
X
↑
↑
STORE DATA
FROM A AND/OR B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001
logic diagram (positive logic)
21
GBA
3
GAB
23
CPBA
22
SBA
1
CPAB
2
SAB
One of Eight Channels
1D
C1
4
A
1
20
B
1
1D
C1
To Seven Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θ (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
JA
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperatingconditions”isnotimplied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.75
2
5
5.25
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
IH
0.8
–32
64
V
IL
I
mA
mA
°C
OH
OL
I
T
A
–40
85
NOTE 2: All unused inputs of the device must be held at V
or GND to ensure proper device operation.
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
= 4.75 V,
= 4.75 V
= 4.75 V,
I
I
I
I
= –18 mA
–0.7
–1.2
V
IK
CC
CC
CC
IN
= –32 mA
= –15 mA
= 64 mA
2
OH
OH
OL
V
OH
V
2.4
3.3
0.3
0.2
V
V
0.55
V
OL
All inputs
V
hys
I
I
I
I
I
I
I
I
V
V
V
V
V
V
V
V
V
V
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 0 V,
V
V
V
V
V
V
V
V
= V
CC
5
±1
µA
µA
µA
µA
µA
mA
µA
mA
mA
I
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
IN
IN
IN
= 2.7 V
= 0.5 V
IH
±1
IL
= 2.7 V
= 0.5 V
= 0 V
10
OZH
OZL
OUT
OUT
OUT
OUT
–10
–225
±1
‡
–60
–120
OS
= 4.5 V
off
= 5.25 V,
≤ 0.2 V,
V ≥ V
IN CC
– 0.2 V
0.1
0.5
0.2
2
CC
IN
§
∆I
= 5.25 V, V = 3.4 V , f = 0, Outputs open
IN
CC
1
= 5.25 V, One input switching at 50% duty cycle, Outputs open,
– 0.2 V
mA/
MHz
¶
0.06
0.12
I
CCD
GAB or GBA = GND, V ≤ 0.2 V or V ≥ V
IN IN CC
V
V
≤ 0.2 V or
One bit switching
IN
IN
0.7
1.2
2.8
1.4
3.4
V
= 5.25 V,
CC
= 10 MHz,
≥ V
– 0.2 V
at f = 5 MHz
CC
1
f
0
at 50% duty cycle
Eight bits switching
V
IN
= 3.4 V or GND
Outputs open,
#
mA
I
C
GAB = GBA = GND,
SAB = CPAB = GND,
SBA = V
CC
V
IN
V
IN
≤ 0.2 V or
||
||
5.6
≥ V
– 0.2 V
at f = 5 MHz
CC
1
at 50% duty cycle
V
IN
= 3.4 V or GND
5.1
5
14.6
C
C
10
12
pF
pF
i
9
o
†
‡
Typical values are at V
CC
= 5 V, T = 25°C.
A
Notmorethanoneoutputshouldbeshortedatatime.Durationofshortshouldnotexceedonesecond.Theuseofhigh-speedtestapparatusand/or
sample-and-holdtechniquesarepreferabletominimizeinternalchipheatingandmoreaccuratelyreflectoperationalvalues.Otherwise,prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, I
Per TTL-driven input (V = 3.4 V); all other inputs at V
tests should be performed last.
OS
§
¶
#
or GND
IN CC
This parameter is derived for use in total power-supply calculations.
= I + ∆I × D × N + I (f /2 + f × N )
I
C
CC
CC
H
T
CCD
0
1
1
Where:
I
I
∆I
D
N
= Total supply current
= Power-supply current with CMOS input levels
C
CC
CC
H
T
= Power-supply current for a TTL high input (V = 3.4 V)
IN
= Duty cycle for TTL inputs high
= Number of TTL inputs at D
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
CCD
0
1
N
= Number of inputs changing at f
1
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
CC
formula.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
CY74FCT652T CY74FCT652AT CY74FCT652CT
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
w
t
su
t
h
Pulse duration, clock high or low
Setup time, before CPAB↑ or CPBA↑
Hold time, after CPAB↑ or CPBA↑
6
5
5
ns
ns
ns
4
2
2
A or B
A or B
2
1.5
1.5
switching characteristics over operating free-air temperature range (see Figure 2)
CY74FCT652T CY74FCT652AT CY74FCT652CT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
9
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
6.3
6.3
9.8
9.8
6.3
6.3
6.3
6.3
7.7
7.7
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
5.4
5.4
7.8
7.8
6.3
6.3
5.7
5.7
6.2
6.2
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
A or B
B or A
A or B
A or B
A or B
A or B
9
14
14
9
ns
GAB or GBA
GAB or GBA
CPAB or CPBA
SBA or SAB
ns
9
9
ns
9
11
11
ns
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
S1
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
TEST
/t
S1
t
Open
7 V
PLH PHL
C
= 50 pF
C
= 50 pF
L
L
500 Ω
500 Ω
t
/t
PLZ PZL
/t
(see Note A)
(see Note A)
t
Open
PHZ PZH
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
t
PLH
PHL
PLH
PZL
PZH
PLZ
≈3.5 V
V
Output
Waveform 1
(see Note B)
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
t
t
PHL
PHZ
V
V
V
OH
OH
Output
Waveform 2
(see Note B)
Out-of-Phase
Output
– 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2007
PACKAGING INFORMATION
Orderable Device
CY74FCT652ATQCT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CY74FCT652ATQCTE4
CY74FCT652ATQCTG4
CY74FCT652ATSOC
CY74FCT652ATSOCE4
CY74FCT652ATSOCG4
CY74FCT652ATSOCT
CY74FCT652ATSOCTE4
CY74FCT652ATSOCTG4
CY74FCT652CTQCT
CY74FCT652CTQCTE4
CY74FCT652CTQCTG4
CY74FCT652CTSOC
CY74FCT652CTSOCE4
CY74FCT652CTSOCG4
CY74FCT652CTSOCT
CY74FCT652CTSOCTE4
CY74FCT652CTSOCTG4
CY74FCT652TQCT
SSOP/
QSOP
DBQ
DBQ
DW
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
DBQ
DBQ
DBQ
DW
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
DBQ
DBQ
DBQ
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CY74FCT652TQCTE4
CY74FCT652TQCTG4
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2007
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CY74FCT652ATQCT
SSOP/
QSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CY74FCT652ATSOCT
CY74FCT652CTQCT
SOIC
DW
24
24
2000
2500
330.0
330.0
24.4
16.4
10.75
6.5
15.7
9.0
2.7
2.1
12.0
8.0
24.0
16.0
Q1
Q1
SSOP/
QSOP
DBQ
CY74FCT652CTSOCT
CY74FCT652TQCT
SOIC
DW
24
24
2000
2500
330.0
330.0
24.4
16.4
10.75
6.5
15.7
9.0
2.7
2.1
12.0
8.0
24.0
16.0
Q1
Q1
SSOP/
QSOP
DBQ
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CY74FCT652ATQCT
CY74FCT652ATSOCT
CY74FCT652CTQCT
CY74FCT652CTSOCT
CY74FCT652TQCT
SSOP/QSOP
SOIC
DBQ
DW
24
24
24
24
24
2500
2000
2500
2000
2500
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
41.0
33.0
41.0
33.0
SSOP/QSOP
SOIC
DBQ
DW
SSOP/QSOP
DBQ
Pack Materials-Page 2
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