CY74FCT827ATQCTG4 [TI]
10-BIT BUFFERS WITH 3-STATE OUTPUTS; 具有三态输出的10位缓冲器
| 型号： | CY74FCT827ATQCTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-BIT BUFFERS WITH 3-STATE OUTPUTS |
| 文件： | 总11页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY54FCT827T, CY74FCT827T
10-BIT BUFFERS
WITH 3-STATE OUTPUTS
SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001
CY74FCT827T . . . Q OR SO PACKAGE
(TOP VIEW)
Function, Pinout, and Drive Compatible
With FCT, F, and AM29827 Logic
Reduced V
of Equivalent FCT Functions
(Typically = 3.3 V) Versions
OE
D
D
D
D
D
D
D
D
D
D
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1
24
23
22
21
20
19
18
17
16
15
14
OH
1
0
1
2
3
4
5
6
7
8
9
CC
0
2
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
3
1
4
2
5
3
6
4
I
Supports Partial-Power-Down Mode
off
7
Operation
5
8
6
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
9
7
10
11
8
9
– 1000-V Charged-Device Model (C101)
GND 12
13 OE
2
3-State Outputs
Matched Rise and Fall Times
CY74FCT827T . . . L PACKAGE
(TOP VIEW)
Fully Compatible With TTL Input and
Output Logic Levels
CY54FCT827T
– 32-mA Output Sink Current
– 12-mA Output Source Current
4
3
2
1
28 27 26
25
5
D
D
D
Y
Y
Y
2
3
4
2
3
4
CY74FCT827T
– 64-mA Output Sink Current
– 32-mA Output Source Current
6
24
23
22
21
20
19
7
8
NC
NC
9
D
D
D
Y
Y
Y
5
6
7
5
6
7
description
10
11
The ’FCT827T devices are 10-bit bus drivers that
provide high-performance bus-interface buffering
for wide data/address paths or buses carrying
parity. The 10-bit buffers have NANDed output
enables for maximum control flexibility. The
12 13 14 15 16 17 18
NC – No internal connection
’FCT827T
devices
are
designed
for
high-capacitance-load drive capability, while
providing low-capacitance bus loading at both
inputs and outputs. All outputs are designed for
low-capacitance
bus
loading
in
the
high-impedance state.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT827T, CY74FCT827T
10-BIT BUFFERS
WITH 3-STATE OUTPUTS
SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001
ORDERING INFORMATION
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QSOP – Q
SOIC – SO
QSOP – Q
SOIC – SO
Tape and reel
Tube
4.4
4.4
4.4
8
CY74FCT827CTQCT
CY74FCT827CTSOC
CY74FCT827CTSOCT
CY74FCT827ATQCT
CY74FCT827ATSOC
CY74FCT827ATSOCT
CY54FCT827ATLMB
FCT827C
FCT827C
FCT827A
FCT827A
Tape and reel
Tape and reel
Tube
–40°C to 85°C
8
Tape and reel
Tube
8
–55°C to 125°C LCC – L
9
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUT
Y
FUNCTION
Transparent
3-state
OE
L
OE
L
D
L
1
2
L
H
Z
Z
L
L
H
X
X
H
X
X
H
H = High logic level, L = Low logic level, X = Don’t care,
Z = High-impedance state
logic diagram (positive logic)
1
OE
OE
1
2
13
2
23
D
Y
0
0
To Nine Other Channels
Pin numbers shown are for the Q and SO packages.
‡
absolute maximum rating over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θ (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
JA
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperatingconditions”isnotimplied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT827T, CY74FCT827T
10-BIT BUFFERS
WITH 3-STATE OUTPUTS
SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001
recommended operating conditions (see Note 2)
CY54FCT827T
MIN NOM MAX
CY74FCT827T
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–12
32
0.8
–32
64
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–55
125
–40
85
NOTE 2: All unused inputs of the device must be held at V
or GND to ensure proper device operation.
CC
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CY54FCT827T
CY74FCT827T
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
= 4.75 V,
= 4.5 V,
I
I
I
I
I
I
I
= –18 mA
= –18 mA
–0.7
–1.2
CC
CC
CC
IN
V
V
IK
–0.7
–1.2
IN
= –12 mA
= –32 mA
= –15 mA
= 32 mA
= 64 mA
2.4
3.3
OH
OH
OH
OL
OL
V
OH
2
V
V
CC
= 4.75 V
2.4
3.3
V
V
= 4.5 V,
0.3
0.2
0.55
CC
V
V
V
V
OL
= 4.75 V,
0.3
0.2
0.55
CC
All inputs
hys
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 0 V,
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= V
= V
5
±1
IN
IN
IN
IN
IN
IN
CC
CC
I
I
I
I
I
µA
I
5
±1
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
µA
µA
µA
µA
IH
±1
IL
±1
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
= 0 V
10
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OZH
OZL
10
–10
–225
–10
–60
–120
‡
mA
µA
I
I
I
OS
= 0 V
–60
–120
–225
±1
= 4.5 V
±1
off
= 5.5 V,
= 5.25 V,
≤ 0.2 V,
V
V
≥ V
≥ V
– 0.2 V
– 0.2 V
0.1
0.5
0.2
IN
IN
IN
CC
mA
CC
≤ 0.2 V,
0.1
0.5
0.2
2
IN
CC
§
= 5.5 V, V = 3.4 V , f = 0, Outputs open
IN
2
1
∆I
CC
mA
§
= 5.25 V, V = 3.4 V , f = 0, Outputs open
IN
1
†
‡
Typical values are at V
CC
= 5 V, T = 25°C.
A
Notmorethanoneoutputshouldbeshortedatatime.Durationofshortshouldnotexceedonesecond.Theuseofhigh-speedtestapparatusand/or
sample-and-holdtechniquesarepreferabletominimizeinternalchipheatingandmoreaccuratelyreflectoperationalvalues.Otherwise,prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, I
Per TTL-driven input (V = 3.4 V); all other inputs at V
tests should be performed last.
OS
§
or GND
IN CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT827T, CY74FCT827T
10-BIT BUFFERS
WITH 3-STATE OUTPUTS
SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CY54FCT827T
CY74FCT827T
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
= 5.5 V, One input switching at 50% duty cycle,
CC
Outputs open, OE or OE = GND,
0.06
0.12
1
2
V
IN
≤ 0.2 V or V ≥ V
– 0.2 V
IN CC
mA/
MHz
¶
I
CCD
V
= 5.25 V, One input switching at 50% duty cycle,
CC
Outputs open, OE or OE = GND,
0.06
0.12
1
2
V
IN
≤ 0.2 V or V ≥ V
– 0.2 V
IN
CC
V
V
≤ 0.2 V or
One bit switching
at f = 10 MHz
1
at 50% duty cycle
IN
IN
0.7
1
1.4
2.4
≥ V
– 0.2 V
CC
V
= 5.5 V,
CC
V
IN
= 3.4 V or GND
Outputs open,
V
V
≤ 0.2 V or
10 bits switching
at f = 2.5 MHz
1
at 50% duty cycle
IN
IN
||
OE or OE = GND
1.6
3.2
1
2
≥ V
– 0.2 V
CC
||
4.1 13.2
V
IN
= 3.4 V or GND
#
I
C
mA
V
V
≤ 0.2 V or
One bit switching
at f = 10 MHz
1
at 50% duty cycle
IN
IN
0.7
1
1.4
2.4
≥ V
– 0.2 V
CC
V
= 5.25 V,
CC
V
IN
= 3.4 V or GND
Outputs open,
OE or OE = GND
V
IN
V
IN
≤ 0.2 V or
10 bits switching
at f = 2.5 MHz
1
at 50% duty cycle
||
3.2
1.6
1
2
≥ V
– 0.2 V
CC
||
4.1 13.2
V
IN
= 3.4 V or GND
C
C
5
9
10
12
5
9
10
12
pF
pF
i
o
¶
#
This parameter is derived for use in total power-supply calculations.
I
C
= I
+ ∆I
CC
× D × N + I
(f /2 + f × N )
CCD 0 1 1
CC
H
T
Where:
I
I
∆I
D
N
= Total supply current
= Power-supply current with CMOS input levels
= Power-supply current for a TTL high input (V = 3.4 V)
IN
= Duty cycle for TTL inputs high
C
CC
CC
H
T
= Number of TTL inputs at D
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
CCD
0
1
N
= Number of inputs changing at f
1
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
CC
formula.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT827T, CY74FCT827T
10-BIT BUFFERS
WITH 3-STATE OUTPUTS
SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001
switching characteristics over operating free-air temperature range (see Figure 1)
CY54FCT827AT
CY74FCT827AT
CY74FCT827CT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST LOAD
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
4.4
4.4
10
10
7
t
t
t
t
t
t
t
t
t
t
t
t
9
8
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PHL
PHZ
PHL
C
R
= 50 pF,
= 500 Ω
L
L
D
Y
Y
Y
Y
Y
Y
9
17
17
13
13
25
25
9
8
15
15
12
12
23
23
9
C
R
= 300 pF,
L
D
ns
= 500 Ω
L
C
R
= 50 pF,
= 500 Ω
L
L
ns
OE
OE
OE
OE
7
14
14
5.7
5.7
6
C
R
= 300 pF,
L
ns
= 500 Ω
L
C
= 5 pF,
= 500 Ω
L
ns
R
9
9
L
10
10
10
10
C
R
= 50 pF,
= 500 Ω
L
L
ns
6
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT827T, CY74FCT827T
10-BIT BUFFERS
WITH 3-STATE OUTPUTS
SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
S1
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
TEST
/t
S1
t
Open
7 V
PLH PHL
C
= 50 pF
C
= 50 pF
L
L
500 Ω
500 Ω
t
/t
PLZ PZL
/t
(see Note A)
(see Note A)
t
Open
PHZ PZH
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
t
PLH
PHL
PLH
PZL
PZH
PLZ
≈3.5 V
V
Output
Waveform 1
(see Note B)
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
t
t
PHL
PHZ
V
V
V
OH
OH
Output
Waveform 2
(see Note B)
Out-of-Phase
Output
– 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9224701M3A
ACTIVE
ACTIVE
LCCC
FK
28
24
1
TBD
POST-PLATE N / A for Pkg Type
CY74FCT827ATQCT
SSOP/
QSOP
DBQ
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CY74FCT827ATQCTE4
CY74FCT827ATQCTG4
CY74FCT827ATSOC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP/
QSOP
DBQ
DBQ
DW
DW
DW
DW
DW
DW
DBQ
DBQ
DBQ
DW
DW
DW
DW
DW
DW
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CY74FCT827ATSOCE4
CY74FCT827ATSOCG4
CY74FCT827ATSOCT
CY74FCT827ATSOCTE4
CY74FCT827ATSOCTG4
CY74FCT827CTQCT
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CY74FCT827CTQCTE4
CY74FCT827CTQCTG4
CY74FCT827CTSOC
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CY74FCT827CTSOCE4
CY74FCT827CTSOCG4
CY74FCT827CTSOCT
CY74FCT827CTSOCTE4
CY74FCT827CTSOCTG4
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2007
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CY74FCT827ATQCT
SSOP/
QSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CY74FCT827ATSOCT
CY74FCT827CTQCT
SOIC
DW
24
24
2000
2500
330.0
330.0
24.4
16.4
10.75
6.5
15.7
9.0
2.7
2.1
12.0
8.0
24.0
16.0
Q1
Q1
SSOP/
QSOP
DBQ
CY74FCT827CTSOCT
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CY74FCT827ATQCT
CY74FCT827ATSOCT
CY74FCT827CTQCT
CY74FCT827CTSOCT
SSOP/QSOP
SOIC
DBQ
DW
24
24
24
24
2500
2000
2500
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
41.0
33.0
41.0
SSOP/QSOP
SOIC
DBQ
DW
Pack Materials-Page 2
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相关型号：
CY74FCT827BTSOCR
Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOIC-24
CYPRESS
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