CY74FCT841BTPC [TI]
10-Bit Latch; 10位锁存器
| 型号： | CY74FCT841BTPC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-Bit Latch |
| 文件： | 总8页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT841T
SCCS035 - September 1994 - Revised March 2000
10-Bit Latch
• High-speed parallel latches
• Buffered common latch enable input
Features
• Function, pinout, and drive compatible with FCT, F, and
AM29841 logic
• FCT-C speed at 5.5 ns max. (Com’l)
FCT-B speed at 6.5 ns max. (Com’l)
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
Functional Description
The FCT841T bus interface latch is designed to eliminate the
extra packages required to buffer existing latches and provide
extra data width for wider address/data paths or buses
carrying parity. The FCT841T is a buffered 10-bit wide version
of the FCT373 function.
The FCT841T high-performance interface is designed for
high-capacitance load drive capability while providing
low-capacitance bus loading at both inputs and outputs.
Outputs are designed for low-capacitance bus loading in the
high impedance state and are designed with a power-off
disable feature to allow for live insertion of boards.
• Power-off disable feature
• Matched rise and fall times
• ESD > 2000V
• Fully compatible with TTL input and output logic levels
• Sink current
64 mA (Com’l),
32 mA (Mil)
Source current 32 mA (Com’l),
12 mA (Mil)
Functional Block Diagram
D
0
D
1
D
2
D
D
4
D
D
D
N
3
5
N- 1
D
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
Q
LE
LE
LE
LE
LE
LE
LE
LE
LE
OE
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
N- 1
Y
N
Logic Block Diagram
Pin Configurations
DIP/QSOP/SOIC
Top View
10
D
D
10
Q
Y
24
23
22
21
OE
1
2
3
4
LE
V
CC
LE
D
0
Y
0
Y
1
D
1
OE
Y
2
D
2
Y
20
19
18
17
16
D
3
5
3
D
4
Y
4
6
D
5
Y
5
7
Y
6
D
6
8
D
7
9
Y
7
Y
D
8
10
11
8
15
14
13
Y
9
D
9
LE
GND
12
Copyright © 2000, Texas Instruments Incorporated
CY54/74FCT841T
Pin Description
Name
I/O
Description
D
I
I
The latch data inputs.
LE
The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the
HIGH-to-LOW transition.
Y
O
I
The three-state latch outputs.
OE
The output enable control. When the OE is LOW, the outputs are enabled. When OE is HIGH, the outputs
Y1 are in the high impedance (off) state.
Function Table[1]
Inputs
LE
Internal Outputs
OE
D
O
Y
Function
H
H
H
X
H
H
X
L
H
X
L
H
Z
Z
Z
High Z
H
L
X
NC
Z
Latched (High Z)
Transparent
L
L
H
H
L
H
L
H
L
H
L
L
X
NC
NC
Latched
Maximum Ratings[2, 3]
DC Output Current (Maximum Sink Current/Pin) ......120 mA
Power Dissipation..........................................................0.5W
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–65°C to +135°C
Operating Range
Ambient
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
DC Output Voltage......................................... –0.5V to +7.0V
Range
Commercial All
Military[4]
All
Range
Temperature
–40°C to +85°C
–55°C to +125°C
VCC
5V ± 5%
5V ± 10%
Notes:
1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, NC = No Change, Z = High Impedance.
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
4. TA is the “instant on” case temperature.
2
CY54/74FCT841T
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VCC= Min., IOH = −32 mA
Min.
2.0
Typ.[5]
Max.
Unit
V
VOH
Output HIGH Voltage
Com’l
Com’l
Mil
VCC= Min., IOH = −15 mA
VCC= Min., IOH = −12 mA
VCC= Min., IOL = 64 mA
VCC= Min., IOL = 32 mA
2.4
3.3
3.3
0.3
0.3
V
2.4
V
VOL
Output LOW Voltage
Com’l
Mil
0.55
0.55
V
V
VIH
VIL
VH
VIK
II
Input HIGH Voltage
Input LOW Voltage
Hysteresis[6]
2.0
V
0.8
V
All inputs
0.2
V
Input Clamp Diode Voltage
Input HIGH Current
Input HIGH Current
Input LOW Current
VCC= Min., IIN= −18 mA
VCC= Max., VIN= VCC
VCC= Max., VIN= 2.7V
VCC= Max., VIN= 0.5V
VCC = Max., VOUT = 2.7V
−0.7
−1.2
5
V
µA
µA
µA
µA
IIH
±1
±1
10
IIL
IOZH
Off State HIGH-Level Output
Current
IOZL
Off State LOW-Level
Output Current
VCC = Max., VOUT = 0.5V
−10
µA
IOS
Output Short Circuit Current[7] VCC = Max., VOUT = 0.0V
−60
−120
−225
±1
mA
IOFF
Power-Off Disable
VCC = 0V, VOUT = 4.5V
µA
Capacitance[6]
Parameter
Description
Typ.[5]
Max.
10
Unit
CIN
Input Capacitance
Output Capacitance
5
9
pF
pF
COUT
12
Notes:
5. Typical values are at VCC=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
3
CY54/74FCT841T
Power Supply Characteristics
Parameter
ICC
Description
Test Conditions
Typ.[5]
0.1
Max.
0.2
Unit
mA
mA
Quiescent Power Supply Current VCC = Max., VIN ≤ 0.2V, VIN ≥ VCC-0.2V
Quiescent Power Supply Current VCC = Max., VIN = 3.4V, f1 = 0, Outputs Open[8]
(TTL inputs HIGH)
∆ICC
0.5
2.0
ICCD
Dynamic Power Supply Current[9] VCC = Max., 50% Duty Cycle, Outputs Open,
0.06
0.7
0.12
1.4
mA/MHz
mA
One Input Toggling, OE =GND, LE = VCC
,
VIN ≤ 0.2V or VIN ≥ VCC−0.2V
IC
Total Power Supply Current[10]
VCC=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=10 MHz,
OE = GND, LE = VCC
,
V
IN ≤ 0.2V or VIN ≥ VCC−0.2V
VCC = Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f1 =10 MHz,
1.0
1.0
4.1
2.4
mA
mA
mA
OE = GND, LE = VCC
,
V
IN = 3.4V or VIN = GND
VCC = Max., 50% Duty Cycle, Outputs Open,
Ten Bits Toggling at f1 = 2.5 MHz,
3.2[11]
OE =GND, LE = VCC
,
V
IN ≤ 0.2V or VIN ≥ VCC−0.2V
VCC=Max., 50% Duty Cycle, Outputs Open,
Ten Bits Toggling at f1 = 2.5 MHz,
13.2[11]
OE = GND, LE = VCC
,
V
IN = 3.4V or VIN = GND
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. IC
IC
=
=
=
=
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
ICC
∆ICC
DH
NT
ICCD
f0
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair HLH or LHL)
Clock frequency for registered devices, otherwise zero
Input signal frequency
f1
N1
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
4
CY54/74FCT841T
Switching Characteristics Over the Operating Range[12]
FCT841AT
Military
Test Load Min. Max. Min. Max. Min. Max. Min. Max. Unit No.[13]
FCT841BT
FCT841CT
Commercial Commercial Commercial
Fig.
Parameter
Description
tPLH
tPHL
Propagation Delay
D1 to Y1 (L =HIGH)
CL = 50 pF
RL = 500Ω
1.5
10.0
1.5
1.5
2.5
2.5
1.5
1.5
4.0
1.5
1.5
1.5
1.5
9.0
1.5
1.5
2.5
2.5
1.5
1.5
4.0
1.5
1.5
1.5
1.5
6.5
1.5
1.5
2.5
2.5
1.5
1.5
4.0
1.5
1.5
1.5
1.5
5.5
ns
1, 3
1, 3
9
Propagation Delay
D1 to Y1 (LE=HIGH)
CL = 300 pF 1.5
RL = 500Ω
15.0
13.0
13.0
13.0 ns
tSU
tH
Data to LE Set-Up
Time
CL = 50 pF
RL = 500Ω
2.5
3.0
1.5
ns
ns
Data to LE Hold Time CL = 50 pF
9
RL = 500Ω
tPLH
tPHL
Propagation Delay
LE to Y1
CL = 50 pF
RL = 500Ω
13.0
20.0
12.0
16.0
8.0
6.4
ns
1, 3
1, 3
5
Propagation Delay
CL = 300 pF 1.5
RL = 500Ω
15.5
15.0 ns
ns
[12]
LE to Y1
tW
LE Pulse Width (HIGH) CL = 50 pF
5.0
1.5
RL = 500Ω
tPZH
tPZL
Output Enable Time
OE to Y1
CL = 50 pF
RL = 500Ω
13.0
25.0
9.0
11.5
23.0
7.0
8.0
14.0
6.0
6.5
12.0 ns 1, 7, 8
ns 1, 7, 8
Output Enable Time
CL = 300 pF 1.5
RL = 500Ω
[12]
OE to Y1
tPHZ
tPLZ
Output Disable Time
CL = 5 pF
RL = 500Ω
1.5
1.5
5.7
6.0
ns 1, 7, 8
ns 1, 7, 8
[12]
OE to Y1
Output Disable Time
OE to Y1
CL = 50 pF
RL = 500Ω
10.0
8.0
7.0
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT841CTQCT
Package Type
5.5
Q13
S13
24-Lead (150-Mil) QSOP
Commercial
CY74FCT841CTSOC/SOCT
CY74FCT841BTPC
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) CerDIP
6.5
9.0
P13/P13A
S13
Commercial
Commercial
Military
CY74FCT841ATSOC/SOCT
CY54FCT841ATDMB
10.0
D14
Notes:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
Document #: 38-00273-B
5
CY54/74FCT841T
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9Config.A
24-Lead (300-Mil) Molded DIP P13/P13A
6
CY54/74FCT841T
Package Diagrams (continued)
24-Lead Quarter Size Outline Q13
24-Lead (300-Mil) Molded SOIC S13
7
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Copyright 2000, Texas Instruments Incorporated
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