D24066QM96G4Q1 [TI]
HIGH-SPEED CMOS LOGIC QUAD BILATERAL SWITCH; 高速CMOS逻辑四路双向开关
| 型号： | D24066QM96G4Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED CMOS LOGIC QUAD BILATERAL SWITCH |
| 文件： | 总13页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HCT4066-Q1
HIGH-SPEED CMOS LOGIC
QUAD BILATERAL SWITCH
SCLS581B − APRIL 2004 − REVISED APRIL 2008
D
D
D
D
D
Qualified for Automotive Applications
Low ON Resistance
D
D
Direct LSTTL Input Logic Compatibility:
V
IL
= 0.8 V Max, V = 2 V Min
IH
− 25 W Typical (V = 4.5 V)
CMOS Input Compatibility: I v 1 mA at V
,
CC
I
OL
V
OH
Fast Switching and Propagation Speeds
Low OFF Leakage Current
M OR PW PACKAGE
(TOP VIEW)
Wide Operating Temperature Range: −405C
to 1255C
1Y
1Z
2Z
2Y
2E
VCC
1E
4E
1
2
3
4
5
6
7
14
13
12
description/ordering information
11 4Y
10 4Z
The CD74HCT4066 contains four independent
digitally controlled analog switches that use
silicon-gate CMOS technology to achieve operation
speeds similar to LSTTL, with the low power
consumption of standard CMOS integrated circuits.
3E
GND
9
8
3Z
3Y
These switches feature the characteristic linear ON
resistance of the metal-gate CD4066B. Each switch
is turned on by a high-level voltage on its control
input.
{
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
A
PACKAGE
§
SOIC − M
Reel of 2500
CD74HCT4066QM96Q1
HCT4066Q
−40°C to 125°C
TSSOP − PW Reel of 2000
CD74HCT4066QPWRQ1 HK4066Q
†
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
The suffix 96 denotes tape and reel.
‡
§
FUNCTION TABLE
INPUT
SWITCH
nE
L
Off
On
H
H = High level
L = Low level
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74HCT4066-Q1
HIGH-SPEED CMOS LOGIC
QUAD BILATERAL SWITCH
SCLS581B − APRIL 2004 − REVISED APRIL 2008
logic diagram (positive logic)
nY
p
p
n
n
nZ
nE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to +7 V
CC
Input clamp current, I (V < −0.5 V or V > V + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I (V < −0.5 V or V > V + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O
O
CC
Switch current, I (see Note 2) (V > −0.5 V or V < V + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
O
O
O
CC
Output source or sink current per output pin, I (V > −0.5 V or V < V + 0.5 V) . . . . . . . . . . . . . . 25 mA
O
O
O
CC
Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages referenced to GND unless otherwise specified.
2. In certain applications, the external load-resistor current may include both V and signal-line components. To avoid drawing V
CC
CC
current when switch current flows into the transmission gate inputs (terminals 1, 4, 8, and 11), the voltage drop across the
bidirectional switch must not exceed 0.6 V (calculated from r values shown in the electrical characteristics table). No V current
on
CC
flows through R if the switch current flows into terminals 2, 3, 9, and 10.
L
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74HCT4066-Q1
HIGH-SPEED CMOS LOGIC
QUAD BILATERAL SWITCH
SCLS581B − APRIL 2004 − REVISED APRIL 2008
recommended operating conditions (see Note 4)
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
V
Supply voltage
5.5
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
V
0
0
V
CC
V
CC
V
Output voltage
V
O
t
Input transition (rise and fall) time
Operating free-air temperature
V
CC
= 4.5 V
0
500
125
ns
°C
t
T
−40
A
NOTES: 4. All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= −40°C
A
T
A
= 25°C
TO 125°C
PARAMETER
TEST CONDITIONS
V
I
V
CC
UNIT
MIN
TYP
MAX
MIN MAX
V
CC
I
I
Any control
= V or GND
or
GND
5.5 V
0.1
1
µA
µA
IL
V
IS
V
IL
5.5 V
4.5 V
4.5 V
4.5 V
0.1
80
95
1
128
142
IZ
CC
V
V
= V or GND
V
CC
V
CC
V
CC
V
CC
25
35
1
IS
CC
I
O
= 1 mA,
r
Ω
Ω
on
See Figure 7
= V to GND
IS
CC
∆r
Between any two switches
on
I
or
GND
5.5 V
2
40
µA
CC
4.5 V
to
5.5 V
Per input pin: 1 unit load,
See Note 5
V
2.1 V
−
CC
∆I
100
360
10
490
10
µA
CC
C
Control inputs
pF
I
NOTE 5: For dual-supply systems, theoretical worst case (V = 2.4 V, V = 5.5 V) specification is 1.8 mA.
I
CC
HCT input loading
†
INPUT
UNIT LOADS
All
1
†
Unit load is ∆I limit specified in the electrical
CC
characteristics table, e.g., 360 µA max at 25°C.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74HCT4066-Q1
HIGH-SPEED CMOS LOGIC
QUAD BILATERAL SWITCH
SCLS581B − APRIL 2004 − REVISED APRIL 2008
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 6)
T
= −40°C
A
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
TO 125°C
PARAMETER
V
UNIT
CC
MIN
TYP
MAX
12
MIN
MAX
C = 15 pF
L
5 V
4.5 V
5 V
4
t
Y or Z
Z or Y
Y or Z
Y or Z
ns
ns
ns
pd
en
dis
C = 50 pF
L
18
36
53
C = 15 pF
L
9
t
t
E
E
C = 50 pF
L
4.5 V
5 V
24
C = 15 pF
L
14
C = 50 pF
L
4.5 V
35
operating characteristics, VCC = 5 V, TA = 25°C, input tr, tf = 6 ns
PARAMETER
TYP
UNIT
C
Power dissipation capacitance (see Note 6)
38
pF
pd
NOTE 6:
C
P
is used to determine the dynamic power consumption (P ), per package.
pd D
2
2
= (C × V
× f ) + Σ (C + C ) × V
× f
CC O
D
pd
CC
I
L
S
f
O
= output frequency
f = input frequency
I
C = output load capacitance
L
C
= switch capacitance
S
V
CC
= supply voltage
analog channel characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
V
TYP
200
−72
0.023
130
−72
5
UNIT
MHz
dB
CC
f
Switch frequency response bandwidth at −3 dB
Crosstalk between any two switches
Total harmonic distortion
See Figure 2 and Figure 8 and Notes 7 and 8
See Figure 1 and Figure 9 and Notes 8 and 9
4.5 V
4.5 V
4.5 V
4.5 V
4.5 V
max
See Figure 3, 1 kHz, V = 4 V
%
IS
P-P
See Figure 4
mV
dB
Control to switch feedthrough noise
Switch OFF signal feedthrough
Switch input capacitance
See Figure 5 and Figure 9 and Notes 8 and 9
C
pF
S
NOTES: 7. Adjust input voltage to obtain 0 dBm at output, f = 1 MHz.
8. is centered at V /2.
9. Adjust input for 0 dBm at V .
V
IS
CC
IS
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74HCT4066-Q1
HIGH-SPEED CMOS LOGIC
QUAD BILATERAL SWITCH
SCLS581B − APRIL 2004 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
V
V
CC
CC
V
IS
R
R
V
OS2
SWITCH
OFF
SWITCH
ON
V
OS1
0.1 mF
INPUT
dB
METER
V
/2
CC
C
C
R
R
f
IS
= 1-MHz Sine Wave
R = 50 W
C = 10 pF
V
/2
V
/2
CC
CC
Figure 1. Crosstalk Between Two Switches Test Circuit
V
CC
V
CC
V
IS
V
= V
IH
I
Sine
Wave
SWITCH
ON
V
OS
SWITCH
ON
V
OS
V
IS
10 mF
V
IS
10k Ω
50 pF
DISTORTION
METER
0.1 mF
dB
METER
50 Ω
10 pF
V
/2
CC
f
IS
= 1 kHz to 10 kHz
V
/2
CC
Figure 2. Frequency-Response Test Circuit
Figure 3. Total Harmonic Distortion Test Circuit
E
f
≥ 1-MHz Sine Wave
IS
V
CC
V
P−P
R = 50 Ω
C = 10 pF
V
V
OS
CC
SWITCH
ALTERNATING
ON AND OFF
600 Ω
0.1 µF
V
V
V
= V
R
C
OS
V
IL
OS
SWITCH
OFF
V
IS
t , t ≤ 6 ns
r
f
V
/2
CC
f
= 1 MHz
600 Ω
50 pF
CONT
dB
50% DUTY
CYCLE
SCOPE
R
C
METER
V
/2
CC
V
/2
/2
CC
CC
Figure 4. Control-to-Switch Feedthrough Noise
Test Circuit
Figure 5. Switch OFF Signal Feedthrough
Test Circuit
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74HCT4066-Q1
HIGH-SPEED CMOS LOGIC
QUAD BILATERAL SWITCH
SCLS581B − APRIL 2004 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
S1
S2
t
Open
Closed
Open
Closed
Open
PZH
S1
S2
t
en
Test
t
t
t
PZL
PHZ
PLZ
Point
R = 1 kΩ
L
From Output
Under Test
Closed
t
t
dis
pd
C
Closed
Open
Open
Open
L
(see Note A)
LOAD CIRCUIT
3 V
0 V
3 V
0 V
Input
1.3 V
1.3 V
Output
Control
1.3 V
1.3 V
t
t
PLH
PHL
t
t
PLZ
PZL
V
OH
In-Phase
Output
90%
90%
≈V
CC
Output
Waveform 1
(see Note B)
1.3 V
10%
1.3 V
10%
1.3 V
V
OL
10%
V
OL
t
t
r
f
t
t
PHL
PLH
t
t
PHZ
PZH
V
V
OH
90%
90%
Out-of-Phase
Output
1.3 V
1.3 V
10%
Output
Waveform 2
(see Note B)
V
OH
10%
90%
1.3 V
OL
t
t
≈0 V
f
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured with the input duty cycle at 50%.
max
E. The outputs are measured one at a time, with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
dis
are the same as t
PZH
en
are the same as t .
PHL
pd
Figure 6. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74HCT4066-Q1
HIGH-SPEED CMOS LOGIC
QUAD BILATERAL SWITCH
SCLS581B − APRIL 2004 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
60
50
40
30
20
10
1
T
= 255C
A
GND = 0 V
0
V
CC
= 4.5 V, PIN 1 TO 2
−1
−2
C = 10 pF
L
V
CC
= 4.5 V
−3
−4
R = 50 Ω
L
T
= 255C
A
Pin 4 to 3
0
1
2
3
4 4.5 5
6
7
8
9
4
5
6
7
8
10
10
10
Frequency − Hz
10
10
Input Signal Voltage − V
Figure 8. Switch Frequency Response, V = 4.5 V
Figure 7. Typical ON Resistance vs
Input Signal Voltage
CC
0
C = 10 pF
L
V
CC
= 4.5 V
R = 50 Ω
L
−20
−40
T
= 255C
A
Pin 4 to 3
−60
−80
−100
4
5
6
7
8
10
10
10
10
10
f − Frequency − Hz
Figure 9. Switch-OFF Signal Feedthrough and
Crosstalk vs Frequency, V = 4.5 V
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CD74HCT4066QM96Q1
CD74HCT4066QPWRQ1
D24066QM96G4Q1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
TSSOP
SOIC
D
PW
D
14
14
14
14
2500
2000
2500
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
HCT4066QPWRG4Q1
TSSOP
PW
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD74HCT4066-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2011
Catalog: CD74HCT4066
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
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