DAC081C085CIMM/NOPB [TI]
具有 I2C 兼容接口和外部参考的 8 位微功耗 DAC | DGK | 8 | -40 to 125;
| 型号： | DAC081C085CIMM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C 兼容接口和外部参考的 8 位微功耗 DAC | DGK | 8 | -40 to 125 光电二极管 转换器 |
| 文件： | 总42页 (文件大小：1453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
DAC081C08x 8-Bit Micro Power Digital-to-Analog Converter With An I2C-Compatible
Interface
1 Features
3 Description
The DAC081C08x device is an 8-bit, single-channel,
voltage-output digital-to-analog converter (DAC) that
operates from a 2.7-V to 5.5-V supply. The output
amplifier allows rail-to-rail output swing and has an
4.5-µsec settling time. The DAC081C081 uses the
supply voltage as the reference to provide the widest
dynamic output range and typically consumes 132 µA
while operating at 5 V. It is available in 6-lead SOT
and WSON packages and provides three address
options (pin selectable).
As an alternative, the DAC081C085 provides nine I2C
addressing options and uses an external reference. It
has the same performance and settling time as the
DAC081C081. It is available in an 8-lead VSSOP.
1
•
Ensured Monotonicity to 8-bits
•
•
•
Low Power Operation: 156 µA Maximum at 3.3 V
Extended Power Supply Range (2.7 V to 5.5 V)
I2C-Compatible 2-Wire Interface Which Supports
Standard (100-kHz), Fast (400-kHz), and High-
Speed (3.4-MHz) Modes
•
•
•
•
•
•
•
•
•
Rail-to-Rail Voltage Output
Very Small Package
Resolution 8 Bits
INL ±0.6 LSB (Maximum)
DNL ±0.1 LSB (Maximum)
Settling Time 4.5 μs (Maximum)
Zero Code Error +10 mV (Maximum)
Full-Scale Error −0.7 %FS (Maximum)
Supply Power
The DAC081C081 and DAC081C085 use a 2-wire,
I2C-compatible serial interface that operates in all
three speed modes, including high-speed mode (3.4
MHz). An external address selection pin allows up to
three DAC081C081 or nine DAC081C085 devices
per 2-wire bus. Pin-compatible alternatives to the
DAC081C081 are available that provide additional
address options.
–
Normal
–
–
380 μW (3 V)
730 μW (5 V) Typical
–
Power Down
Table 1. Device Information(1)
–
–
0.5 μW (3 V)
0.9 μW (5 V) Typical
PART NUMBER
PACKAGE
WSON (6)
BODY SIZE (NOM)
2.20 mm × 2.50 mm
1.60 mm × 2.90 mm
3.00 mm × 3.00 mm
DAC081C081
SOT (6)
2 Applications
DAC081C085
VSSOP (8)
•
•
•
•
•
Industrial Process Control
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Portable Instruments
Digital Gain and Offset Adjustments
Programmable Voltage and Current Sources
Test Equipment
Figure 1. Block Diagram
V *
A
V
*
REF
GND
DAC081C081 / DAC081C085
POWER-ON
RESET
REF
DAC
REGISTER
8 BIT DAC
V
OUT
BUFFER
8
8
2.5k
100k
POWER-DOWN
CONTROL
LOGIC
2
I
C
INTERFACE
* NOTE: ADR1 and V
are for the DAC081C085 only. The DAC081C085 uses an external
), whereas, the DAC081C081 uses the supply (V ) as the reference.
REF
reference (V
REF
A
ADR1* ADR0
SCL
SDA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
Table of Contents
8.5 Programming........................................................... 18
8.6 Registers................................................................. 22
Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Application ................................................. 25
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Description (continued)......................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions ...................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 AC and Timing Characteristics ............................... 10
7.7 Typical Characteristics............................................ 13
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 18
9
10 Power Supply Recommendations ..................... 26
10.1 Using References as Power Supplies ................. 26
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 30
12.1 Device Support .................................................... 30
12.2 Related Links ........................................................ 31
12.3 Community Resources.......................................... 31
12.4 Trademarks........................................................... 31
12.5 Electrostatic Discharge Caution............................ 31
12.6 Glossary................................................................ 31
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (January 2016) to Revision F
Page
•
Added column to Table 1. ................................................................................................................................................... 21
Changes from Revision D (March 2013) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Added addresses that the DAC responds to on the I2C bus. ............................................................................................. 21
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 29
2
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
5 Description (continued)
The DAC081C081 and DAC081C085 each have a 16-bit register that controls the mode of operation, the power-
down condition, and the output voltage. A power-on reset circuit ensures that the DAC output powers up to zero
volts. A power-down feature reduces power consumption to less than a microWatt. Their low power consumption
and small packages make these DACs an excellent choice for use in battery-operated equipment. Each DAC
operates over the extended industrial temperature range of −40°C to +125°C.
The DAC081C081 and DAC081C085 are each part of a family of pin-compatible DACs that also provide 12- and
10-bit resolution. For 12-bit DACs see the DAC121C081 and DAC121C085. For 10-bit DACs see the
DAC101C081 and DAC101C085.
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
6 Pin Configuration and Functions
NGF Package
6-Pin WSON
Top View
DDC Package
6-Pin SOT
Top View
ADR0
SCL
1
2
3
6
5
4
V
V
OUT
A
1
2
3
6
5
4
ADR0
SCL
V
OUT
WSON
SOT
V
A
SDA
GND
GND
SDA
DAC081C081
DAC081C081
DGK Package
8-Pin VSSOP
Top View
ADR0
ADR1
1
2
8
7
V
V
OUT
REF
VSSOP
SCL
SDA
3
4
6
5
V
A
GND
DAC081C085
Table 2. Pin Functions
PIN
EQUIVALENT
CIRCUIT
TYPE
DESCRIPTION
NAME
WSON
SOT
VSSOP
Tri-state Address Selection Input. Sets the two Least
Significant Bits (A1 and A0) of the 7-bit slave address.
(see Table 3)
Digital Input,
three levels
V+
ADR0
1
6
1
PIN
41.5k
2.1k
D1
Snap
Back
41.5k
Digital Input,
three levels
Tri-state Address Selection Input. Sets Bits A6 and A3
of the 7-bit slave address. (see Table 3)
ADR1
GND
—
4
—
3
2
5
GND
Ground
Ground for all on-chip circuitry.
Exposed die attach pad can be connected to ground
or left floating. Soldering the pad to the PCB offers
optimal thermal performance and enhances package
self-alignment during reflow.
(WSON
only)
PAD
SCL
—
5
—
3
Ground
Serial Clock Input. SCL is used together with SDA to
control the transfer of data in and out of the device.
2
3
Digital Input
PIN
Serial Data bidirectional connection. Data is clocked
into or out of the internal 16-bit register relative to the
clock edges of SCL. This is an open drain data line
that must be pulled to the supply (VA) by an external
pullup resistor.
D1
Snap
Back
Digital
Input/Output
SDA
4
4
GND
Power supply input. For the SOT and WSON versions,
this supply is used as the reference. Must be
decoupled to GND.
VA
5
6
2
1
6
8
7
Supply
Analog
Output
VOUT
Analog Output Voltage
Unbufferred reference voltage. For the VSSOP-8, this
supply is used as the reference. VREF must be free of
noise and decoupled to GND.
VREF
—
—
Supply
4
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
7 Specifications
7.1 Absolute Maximum Ratings
(1)(2)(3)
See
MIN
−0.3
−0.3
MAX
6.5
UNIT
V
Supply voltage, VA
Voltage on any Input Pin
Input current at any pin(4)
Package input current(4)
Power consumption at TA = 25°C
Junction temperature
6.5
V
±10
±20
mA
mA
(5)
See
150
150
°C
°C
Storage temperature, Tstg
−65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 20-mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10
mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / RθJA. The values for maximum power dissipation will be reached only when the device is operated in a severe
fault condition (for example, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).
7.2 ESD Ratings
VALUE
UNIT
DAC081C081 in NGF Package
All pins except 2 and 3
Pins 2 and 3
±2500
±5000
±1000
±1000
±250
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001
All pins except 2 and 3
Pins 2 and 3
Charged-device model (CDM), per JEDEC
specification JESD22-C101
V(ESD)
Electrostatic discharge
V
All pins except 2 and 3
Pins 2 and 3
Machine model (MM)
±350
DAC081C081 in DDC Package
All pins except 4 and 5
Pins 4 and 5
±2500
±5000
±1000
±1000
±250
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001
All pins except 4 and 5
Pins 4 and 5
Charged-device model (CDM), per JEDEC
specification JESD22-C101
V(ESD)
Electrostatic discharge
V
All pins except 4 and 5
Pins 4 and 5
Machine model (MM)
±350
DAC081C085 in DGK Package
All pins except 3 and 4
Pins 3 and 4
±2500
±5000
±1000
±1000
±250
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001
All pins except 3 and 4
Pins 3 and 4
Charged-device model (CDM), per JEDEC
specification JESD22-C101
V(ESD)
Electrostatic discharge
V
All pins except 3 and 4
Pins 3 and 4
Machine model (MM)
±350
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
7.3 Recommended Operating Conditions
(1)
See
MIN
−40
2.7
1
NOM
MAX
125
5.5
UNIT
°C
V
Operating Temperature
Supply Voltage, VA
Reference Voltage, VREFIN
Digital Input Voltage(2)
Output Load
TA
VA
V
5.5
V
0
1500
pF
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(2) The inputs are protected as shown below. Input voltage magnitudes up to 5.5 V, regardless of VA, will not cause errors in the conversion
result. For example, if VA is 3 V, the digital input pins can be driven with a 5V logic device.
L/h
Çh LbÇ9wb![
ꢀLwꢀÜLÇwò
Db5
7.4 Thermal Information
DAC081C081
DAC081C085
DGK (VSSOP)
8 PINS
THERMAL METRIC(1)(2)
NGF (WSON)
DDC (SOT)
6 PINS
250
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
190
240
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging.
Reflow temperature profiles are different for lead-free packages.
6
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
7.5 Electrical Characteristics
The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, CL = 200 pF to GND, input code range 3 to 252. All
Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified.
PARAMETER
STATIC PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP(1)
MAX(1)
UNIT
8
8
Bits
Bits
Monotonicity
INL
0.14
−0.14
0.04
−0.02
1.1
0.6
0.1
LSB
Integral non-linearity
−0.6
−0.1
LSB
LSB
DNL
Differential non-linearity
LSB
ZE
Zero code error
Full-scale error
Gain error
IOUT = 0
10
−0.7
−0.7
mV
FSE
GE
IOUT = 0
−0.1
−0.2
−20
%FSR
%FSR
µV/°C
ppm FSR/°C
ppm FSR/°C
All ones loaded to DAC register
ZCED
Zero code error drift
VA = 3 V
VA = 5 V
−0.7
−1
TC GE
Gain error tempco
ANALOG OUTPUT CHARACTERISTICS (VOUT
)
DAC081C085
0
0
VREF
VA
V
V
Output voltage range(2)
DAC081C081
VA = 3 V, IOUT = 200 µA
VA = 5 V, IOUT = 200 µA
VA = 3 V, IOUT = 200 µA
VA = 5 V, IOUT = 200 µA
1.3
7
mV
mV
V
ZCO
FSO
Zero code output
2.984
4.989
Full-scale output
V
VA = 3 V, VOUT = 0 V, input code =
FFFh.
56
69
mA
mA
mA
mA
mA
Output short circuit current
IOS
(ISOURCE
)
VA = 5 V, VOUT = 0 V, input code =
FFFh.
VA = 3 V, VOUT = 3 V, input code =
000h.
−52
−75
Output short circuit current
(ISINK
IOS
)
VA = 5 V, VOUT = 5 V, input code =
000h.
Continuous output
current(2)
IO
Available on the DAC output
11
RL = ∞
1500
1500
7.5
pF
pF
Ω
CL
Maximum load capacitance
DC output impedance
RL = 2kΩ
ZOUT
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
(2) This parameter is ensured by design and/or characterization and is not tested in production.
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
Electrical Characteristics (continued)
The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, CL = 200 pF to GND, input code range 3 to 252. All
Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX(1)
UNIT
REFERENCE INPUT CHARACTERISTICS- (DAC081C085 only)
Input range minimum
1
0.2
V
V
VREF
Input range maximum
Input impedance
VA
120
kΩ
LOGIC INPUT CHARACTERISTICS (SCL, SDA)
VIH
Input high voltage
Input low voltage
Input current
0.7 × VA
V
V
VIL
0.3 × VA
IIN
±1
3
µA
pF
V
CIN
VHYST
Input pin capacitance(2)
Input hysteresis
0.1 × VA
VA – 0.5
LOGIC INPUT CHARACTERISTICS (ADR0, ADR1)
VIH
VIL
IIN
Input high voltage
Input low voltage
Input current
V
V
0.5
±1
µA
LOGIC OUTPUT CHARACTERISTICS (SDA)
ISINK = 3 mA
ISINK = 6 mA
0.4
0.6
V
V
VOL
IOZ
Output low voltage
High-impedence output
leakage current
±1
µA
POWER REQUIREMENTS
Supply voltage minimum
Supply voltage maximum
NORMAL -- VOUT SET TO MIDSCALE. 2-WIRE INTERFACE QUIET (SCL = SDA = VA) (OUTPUT UNLOADED)
2.7
VA
V
5.5
VA = 2.7 V to 3.6 V
VA = 4.5 V to 5.5 V
VA = 2.7 V to 3.6 V
VA = 4.5 V to 5.5 V
VA = 2.7 V to 3.6 V
VA = 4.5 V to 5.5 V
VA = 3 V
105
132
86
156
214
118
152
43
µA
µA
µA
µA
µA
µA
µW
µW
IST_VA-1
IST_VA-5
IST_VREF
PST
VA DAC081C081 supply current
VA DAC081C085 supply current
98
37
VREF supply current
(DAC081C085 only)
53
61
380
730
Power consumption
(VA & VREF for DAC081C085)
VA = 5 V
CONTINUOUS OPERATION -- 2-WIRE INTERFACE ACTIVELY ADDRESSING THE DAC AND WRITING TO THE DAC REGISTER
(OUTPUT UNLOADED)
VA = 2.7 V to
3.6 V
134
192
225
374
220
300
320
500
µA
µA
µA
µA
fSCL = 400 kHz
fSCL = 3.4 MHz
VA = 4.5 V to
5.5 V
ICO_VA-1
VA DAC081C081 supply current
VA = 2.7 V to
3.6 V
VA = 4.5 V to
5.5 V
8
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
Electrical Characteristics (continued)
The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, CL = 200 pF to GND, input code range 3 to 252. All
Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX(1)
UNIT
VA = 2.7 V to
3.6 V
101
155
µA
fSCL = 400 kHz
fSCL = 3.4 MHz
VA = 4.5 V to
5.5 V
142
193
325
33.5
49.5
220
235
410
55
µA
µA
µA
µA
µA
ICO_VA-5
VA DAC081C085 supply current
VA = 2.7 V to
3.6 V
VA = 4.5 V to
5.5 V
VA = 2.7 V to
3.6 V
VREF supply current
(DAC081C085 only)
ICO_VREF
VA = 4.5 V to
5.5 V
71.4
VA = 3 V
VA = 5 V
VA = 3 V
VA = 5 V
480
1.06
810
µW
mW
µW
fSCL = 400 kHz
fSCL = 3.4 MHz
Power consumption
(VA and VREF for DAC081C085)
PCO
2.06
mW
POWER DOWN -- 2-WIRE INTERFACE QUIET (SCL = SDA = VA) AFTER PD MODE WRITTEN TO DAC REGISTER (OUTPUT
UNLOADED)
VA = 2.7 V to
3.6 V
0.13
0.15
1.52
3.25
µA
µA
Supply current
(VA and VREF for DAC081C085) modes
All power-down
IPD
VA = 4.5 V to
5.5 V
VA = 3 V
VA = 5 V
0.5
0.9
µW
µW
Power consumption
(VA and VREF for DAC081C085) modes
All power-down
PPD
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
7.6 AC and Timing Characteristics
The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, RL = Infinity, CL = 200 pF to GND. All Maximum and
Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS(1)
MIN
TYP(2)
MAX(1)(2)
UNIT
40h to C0h code change
RL = 2 kΩ, CL = 200 pF
ts
Output voltage settling time(3)
3
4.5
µs
SR
Output slew rate
1
12
V/µs
nV-sec
nV-sec
kHz
Glitch impulse
Code change from 80h to 7Fh
VREF = 2.5 V ± 0.1 Vpp
Digital feedthrough
Multiplying bandwidth(4)
0.5
160
VREF = 2.5 V ± 0.1 Vpp
input frequency = 10 kHz
Total harmonic distortion(4)
70
dB
VA = 3 V
VA = 5 V
0.8
0.5
µsec
µsec
tWU
Wake-up time
DIGITAL TIMING SPECS (SCL, SDA)
Standard mode
100
400
3.4
kHz
MHz
µs
Fast mode
fSCL
Serial clock frequency
SCL low time
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
1.7
4.7
1.3
160
320
4
Fast mode
tLOW
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
ns
µs
Fast mode
0.6
60
tHIGH
SCL high time
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
ns
120
250
100
10
tSU;DAT Data set-up time
Fast mode
ns
High-speed mode
Standard mode
0
3.45
0.9
µs
ns
Fast mode
0
tHD;DAT Data hold time
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
0
70
0
150
4.7
0.6
160
4
µs
ns
µs
ns
µs
Set-up time for a start or a
repeated start condition
tSU;STA
Fast mode
High-speed mode
Standard mode
Hold time for a start or a
repeated start condition
tHD;STA
Fast mode
0.6
160
4.7
1.3
4
High-speed mode
Standard mode
Bus free time between a stop
and start condition
tBUF
Fast mode
Standard mode
µs
ns
tSU;STO Set-up time for a stop condition
Fast mode
0.6
160
High-speed mode
(1) Cb refers to the capacitance of one bus line. Cb is expressed in pF units.
(2) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
(3) This parameter is ensured by design and/or characterization and is not tested in production.
(4) Applies to the Multiplying DAC configuration. In this configuration, the reference is used as the analog input. The value loaded in the
DAC Register will digitally attenuate the signal at Vout.
10
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
AC and Timing Characteristics (continued)
The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, RL = Infinity, CL = 200 pF to GND. All Maximum and
Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS(1)
MIN
TYP(2)
MAX(1)(2)
1000
300
80
UNIT
Standard mode
Fast mode
20 + 0.1 Cb
trDA
tfDA
trCL
trCL1
tfCL
Rise time of SDA signal
ns
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
10
20
160
250
250
80
Fast mode
20 + 0.1 Cb
Fall time of SDA signal
Rise time of SCL signal
ns
ns
ns
ns
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
10
20
160
1000
300
40
Fast mode
20 + 0.1 Cb
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
10
20
80
1000
300
80
Rise time of SCL signal after a
repeated start condition and after
an acknowledge bit.
Fast mode
20 + 0.1 Cb
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
10
20
160
300
300
40
Fast mode
20 + 0.1 Cb
Fall time of a SCL signal
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
10
20
80
Capacitive load for each bus line
(SCL and SDA)
Cb
400
pF
ns
Fast mode
50
10
Pulse width of spike
suppressed(5)(3)
tSP
High-speed mode
Fast mode
87
38
270
60
SDA output delay (see Additional
toutz
ns
Timing Information: toutz
)
High-speed mode
(5) Spike suppression filtering on SCL and SDA will supress spikes that are less than 50ns for standard-fast mode and less than 10ns for
hs-mode.
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
FSE
255 x V
256
REF
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
255
DIGITAL INPUT CODE
Figure 2. Input / Output Transfer Characteristic
SDA
SCL
t
BUF
t
t
LOW
f
t
t
r
HD;STA
t
t
r
t
f
SP
t
t
SU;STA
t
SU;STO
HD;STA
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
REPEATED
START
START
Figure 3. Serial Timing Diagram
12
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
7.7 Typical Characteristics
VREF = VA, fSCL = 3.4 MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated.
Figure 4. INL
Figure 5. DNL
Figure 6. INL/DNL vs Temperature at VA = 3 V
Figure 7. INL/DNL vs Temperature at VA = 5 V
Figure 8. INL/DNL vs VREFIN at VA = 3 V
Figure 9. INL/DNL vs VREFIN at VA = 5 V
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
Typical Characteristics (continued)
VREF = VA, fSCL = 3.4 MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated.
Figure 10. INL/DNL vs VA
Figure 11. Zero Code Error vs VA
Figure 12. Zero Code Error vs Temperature
Figure 13. Full Scale Error vs VA
Figure 14. Full Scale Error vs Temperature
Figure 15. Total Supply Current vs VA
14
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
Typical Characteristics (continued)
VREF = VA, fSCL = 3.4 MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated.
Figure 17. Total Supply Current vs Temperature at VA = 3 V
Figure 16. VREF Supply Current vs VA
Figure 18. Total Supply Current vs Temperature at VA = 5 V
Figure 19. 5-V Glitch Response
Figure 20. Power-ON Reset
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
8 Detailed Description
8.1 Overview
The DAC081C081 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer.
8.2 Functional Block Diagram
V *
A
V
*
REF
GND
DAC081C081 / DAC081C085
POWER-ON
RESET
REF
DAC
REGISTER
8 BIT DAC
V
OUT
BUFFER
8
8
2.5k
100k
POWER-DOWN
CONTROL
LOGIC
2
I C
INTERFACE
* NOTE: ADR1 and V
are for the DAC081C085 only. The DAC081C085 uses an external
), whereas, the DAC081C081 uses the supply (V ) as the reference.
REF
reference (V
REF
A
ADR1* ADR0
SCL
SDA
8.3 Feature Description
8.3.1 DAC Section
For simplicity, a single resistor string is shown in Figure 21. This string consists of 256 equal-valued resistors
with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight
binary with an ideal output voltage of Equation 1:
VOUT = VREF × (D / 256)
where
•
D is the decimal equivalent of the binary code that is loaded into the DAC register.
(1)
D can take on any integer value between 0 and 255. This configuration ensures that the DAC is monotonic.
16
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
Feature Description (continued)
V
REF
R
R
R
To Output Amplifier
R
R
Figure 21. DAC Resistor String
8.3.2 Output Amplifier
The output amplifier is rail-to-rail, providing an output voltage range of 0 V to VA when the reference is VA. All
amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA,
in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the
reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the
amplifier are described in the Electrical Characteristics.
The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to VA. The zero-
code and full-scale outputs for given load currents are available in the Electrical Characteristics.
8.3.3 Reference Voltage
The DAC081C081 uses the supply (VA) as the reference. With that said, VA must be treated as a reference. The
Analog output will only be as clean as the reference (VA). It is recommended that the reference be driven by a
voltage source with low output impedance.
The DAC081C085 comes with an external reference supply pin (VREF). For the DAC081C085, it is important that
VREF be kept as clean as possible.
The Application and Implementation section describes a handful of ways to drive the reference appropriately.
Refer to Using References as Power Supplies for details.
8.3.4 Power-On Reset
The power-on reset circuit controls the output voltage of the DAC during power up. Upon application of power,
the DAC register is filled with zeros and the output voltage is 0 Volts. The output remains at 0 V until a valid write
sequence is made to the DAC.
When resetting the device, it is crucial that the VA supply be lowered to a maximum of 200 mV before the supply
is raised again to power up the device. Dropping the supply to within 200 mV of GND during a reset will ensure
the ADC performs as specified.
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
Feature Description (continued)
8.3.5 Simultaneous Reset
The broadcast address allows the I2C master to write a single word to multiple DACs simultaneously. Provided
that all of the DACs exist on a single I2C bus, every DAC will update when the broadcast address is used to
address the bus. This feature allows the master to reset all of the DACs on a shared I2C bus to a specific digital
code. For instance, if the master writes a power-down code to the bus with the broadcast address, all of the
DACs will power-down simultaneously.
8.3.6 Additional Timing Information: toutz
The toutz specification is provided to aid the design of the I2C bus. After the SCL bus is driven low by the I2C
master, the SDA bus will be held for a short time by the DAC081C081. This time is referred to as toutz. The
following figure illustrates the relationship between the fall of SCL, at the 30% threshold, to the time when the
DAC begins to transition the SDA bus. The toutz specification only applies when the DAC is in control of the SDA
bus. The DAC is only in control of the bus during an ACK by the DAC081C081 or a data byte read from the DAC
(see Figure 26).
SCL
SDA
t
outz
Figure 22. Data Output Timing
The toutz specification is typically 87 ns in standard-fast mode and 38 ns in Hs-Mode.
8.4 Device Functional Modes
8.4.1 Power-Down Modes
The DAC081C081 has three power-down modes. In power-down mode, the supply current drops to 0.13 µA at 3
V and 0.15 µA at 5 V (typical). The DAC081C081 is put into power-down mode by writing a one to PD1 and/or
PD0. The outputs can be set to high impedance, terminated by 2.5 kΩ to GND, or terminated by 100 kΩ to GND
(see Figure 27).
The bias generator, output amplifier, resistor string, and other linear circuitry are all shut down in any of the
power-down modes. When the DAC081C081 is powered down, the value written to the DAC register, including
the power-down bits, is saved. While the DAC is in power-down, the saved DAC register contents can be read
back. When the DAC is brought out of power-down mode, the DAC register contents will be overwritten and VOUT
will be updated with the new 8-bit data value.
The time to exit power-down (wake-up time) is typically 0.8 µs at 3 V and 0.5 µs at 5 V.
8.5 Programming
8.5.1 Serial Interface
The I2C-compatible interface operates in all three speed modes. Standard mode (100 kHz) and fast mode (400
kHz) are functionally the same and will be referred to as standard-fast mode in this document. High-speed mode
(3.4 MHz) is an extension of standard-fast mode and will be referred to as Hs-mode in this document. The
following diagrams describe the timing relationships of the clock (SCL) and data (SDA) signals. Pullup resistors
or current sources are required on the SCL and SDA busses to pull them high when they are not being driven
low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output and
allowing it to be pulled up externally. The appropriate pullup resistor values will depend upon the total bus
capacitance and operating speed.
18
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
Programming (continued)
8.5.2 Basic I2C Protocol
The I2C interface is bidirectional and allows multiple devices to operate on the same bus. To facilitate this bus
configuration, each device has a unique hardware address which is referred to as the slave address. To
communicate with a particular device on the bus, the controller (master) sends the slave address and listens for
a response from the slave. This response is referred to as an acknowledge bit. If a slave on the bus is addressed
correctly, it acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's
slave address, it not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs also occur on the
bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is
successfully received. When the master is reading data, the master ACKs after every data byte is received to let
the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the
last data byte and creates a Stop condition on the bus.
All communication on the bus begins with either a start condition or a repeated start condition. The protocol for
starting the bus varies between standard-fast mode and Hs-mode. In standard-fast mode, the master generates
a start condition by driving SDA from high to low while SCL is high. In Hs-mode, starting the bus is more
complicated. Please refer to High-Speed (Hs) Mode for the full details of a Hs-mode start condition. A repeated
start is generated to either address a different device, or switch between read and write modes. The master
generates a repeated start condition by driving SDA low while SCL is high. Following the repeated start, the
master sends out the slave address and a read/write bit as shown in Figure 23. The bus continues to operate in
the same speed mode as before the repeated start condition.
All communication on the bus ends with a stop condition. In either standard-fast mode or Hs-Mode, a stop
condition occurs when SDA is pulled from low to high while SCL is high. After a stop condition, the bus remains
idle until a master generates a start condition.
Please refer to the Phillips I2C Specification (Version 2.1 Jan, 2000) for a detailed description of the serial
interface.
ACK
MSB
N/ACK
SDA
SCL
MSB
LSB
LSB
R/W
Direction
Bit
7-bit Slave Address
Data Byte
Acknowledge
from the Device
*Acknowledge
or Not-ACK
8
9
8
9
1
2
6
7
1
2
Repeated for the Lower Data Byte
and Additional Data Transfers
START or
REPEATED
START
STOP
*Note: In continuous mode, this bit must be an ACK from
the data receiver. Immediately preceding a STOP
condition, this bit must be a NACK from the master.
Figure 23. Basic Operation
8.5.3 Standard-Fast Mode
In standard-fast mode, the master generates a start condition by driving SDA from high to low while SCL is high.
The start condition is always followed by a 7-bit slave address and a read/write bit. After these eight bits have
been transmitted by the master, SDA is released by the master and the DAC081C081 either ACKs or NACKs the
address. If the slave address matches, the DAC081C081 ACKs the master. If the address doesn't match, the
DAC081C081 NACKs the master.
For a write operation, the master follows the ACK by sending the upper eight data bits to the DAC081C081.
Then the DAC081C081 ACKs the transfer by driving SDA low. Next, the lower eight data bits are sent by the
master. The DAC081C081 then ACKs the transfer. At this point, the DAC output updates to reflect the contents
of the 16-bit DAC register. Next, the master either sends another pair of data bytes, generates a stop condition to
end communication, or generates a repeated start condition to communicate with another device on the bus.
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
Programming (continued)
For a read operation, the DAC081C081 sends out the upper eight data bits of the DAC register. This is followed
by an ACK by the master. Next, the lower eight data bits of the DAC register are sent to the master. The master
then produces a NACK by letting SDA be pulled high. The NACK is followed by a master-generated stop
condition to end communication on the bus, or a repeated start to communicate with another device on the bus.
8.5.4 High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communication differ slightly from standard-fast mode. Figure 24
describes this in further detail. Initially, the bus begins running in standard-fast mode. The master generates a
start condition and sends the 8-bit Hs master code (00001XXX) to the DAC081C081. Next, the DAC081C081
responds with a NACK. Once the SCL line has been pulled to a high level, the master switches to Hs-mode by
increasing the bus speed and generating a repeated start condition (driving SDA low while SCL is pulled high).
At this point, the master sends the slave address to the DAC081C081, and communication continues as shown
above in the "basic operation" diagram (see Figure 23).
When the master generates a repeated start condition while in Hs-mode, the bus stays in Hs-mode awaiting the
slave address from the master. The bus continues to run in Hs-mode until a stop condition is generated by the
master. When the master generates a stop condition on the bus, the bus must be started in standard-fast mode
again before increasing the bus speed and switching to Hs-mode.
NACK
SDA
MSB
8-bit Master code —00001xxx“
7-bit Slave
Address
Not-Acknowledge
from the Device
8
9
1
2
6
7
1
2
SCL
5
Repeated
START
START
Standard-Fast Mode
Hs-Mode
Figure 24. Beginning Hs-Mode Communication
20
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
Programming (continued)
8.5.5 I2C Slave (Hardware) Address
The DAC has a seven-bit I2C slave address. For the VSSOP-8 version of the DAC, this address is configured by
the ADR0 and ADR1 address selection inputs. For the DAC081C081, the address is configured by the ADR0
address selection input. ADR0 and ADR1 can be grounded, left floating, or tied to VA. If desired, the address
selection inputs can be set to VA/2 rather than left floating. The state of these inputs sets the address the DAC
responds to on the I2C bus (see Table 3). In addition to the selectable slave address, there is also a broadcast
address (1001000) for all DAC081C081s and DAC081C085s on the 2-wire bus. When the bus is addressed by
the broadcast address, all the DAC081C081's and DAC081C085's will respond and update synchronously.
Figure 25 and Figure 26 describe how the master device should address the DAC through the I2C-compatible
interface.
Keep in mind that the address selection inputs (ADR0 and ADR1) are only sampled until the DAC is correctly
addressed with a non-broadcast address. At this point, the ADR0 and ADR1 inputs TRI-STATE and the slave
address is locked. Changes to ADR0 and ADR1 will not update the selected slave address until the device is
power-cycled.
Table 3. Slave Addresses
DAC101C081 (SOT &
DAC101C085 (VSSOP-8)
Do Not Use(2)
WSON)(1)
ADR0
Floating
GND
VA
SLAVE ADDRESS
[A6 - A0]
ADR1
ADR0
0001100
0001101
0001110
0001000
0001001
0001010
1001100
1001101
1001110
1001000
Floating
Floating
Floating
GND
GND
GND
VA
Floating
1000110
1000110
1000111
1000100
1000100
1000101
1100110
1100110
1100111
1100100
GND
VA
Floating
—
GND
—
VA
Floating
—
—
VA
GND
—
VA
VA
—
Broadcast Address
(1) Pin-compatible alternatives to the DAC101C081 options are available with additional address options.
(2) These addresses should not be used by other I2C devices on the I2C bus. Using these addresses can cause the DAC081C081/085 to
not respond when addressed by the assigned Slave Address.
8.5.6 Writing to the DAC Register
To write to the DAC, the master addresses the part with the correct slave address (A6-A0) and writes a zero to
the read/write bit. If addressed correctly, the DAC returns an ACK to the master. The master then sends out the
upper data byte. The DAC responds by sending an ACK to the master. Next, the master sends the lower data
byte to the DAC. The DAC responds by sending an ACK again. At this point, the master either sends the upper
byte of the next data word to be converted by the DAC, generates a Stop condition to end communication, or
generates a repeated start condition to begin communication with another device on the bus. Until generating a
stop condition, the master can continuously write the upper and lower data bytes to the DAC register. This allows
for a maximum DAC conversion rate of 188.9 kilo-conversions per second in Hs-mode.
1
9
1
9
1
9
SCL
SDA
R/W
A6 A5 A4 A3 A2 A1 A0
0
0
PD1 PD0 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Start by
Master
ACK
by
ACK
by
ACK Stop by
by
Master
DAC081C081
DAC081C081
DAC081C081
Frame 1
Address Byte
from Master
Frame 2
Data Byte from
Master
Frame 3
Data Byte from
Master
Repeat Frames
2 and 3 for
Continuous Mode
Figure 25. Typical Write to the DAC Register
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
8.5.7 Reading from the DAC Register
To read from the DAC register, the master addresses the part with the correct slave address (A6-A0) and writes
a one to the read/write bit. If addressed correctly, the DAC returns an ACK to the master. Next, the DAC sends
out the upper data byte. The master responds by sending an ACK to the DAC to indicate that it wants to receive
another data byte. Then the DAC sends the lower data byte to the master. Assuming only one 16-bit data word is
read, the master sends a NACK after receiving the lower data byte. At this point, the master either generates a
stop condition to end communication, or a repeated start condition to begin communication with another device
on the bus.
1
9
1
9
1
9
SCL
SDA
R/W
A6 A5 A4 A3 A2 A1 A0
0
0
PD1 PD0 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
ACK
by
DAC081C081
ACK
by
Master
NACK
by
Master
Start by
Master
Stop by
Master
Frame 1
Frame 2
Frame 3
Address Byte
from Master
Data Byte from
DAC081C081
Data Byte from
DAC081C081
Figure 26. Typical Read from the DAC Register
8.6 Registers
8.6.1 DAC Register
The DAC register, Figure 27, has sixteen bits. The first two bits are always zero. The next two bits determine the
mode of operation (normal mode or one of three power-down modes). The final twelve bits of the shift register
are the data bits. The data format is straight binary (MSB first, LSB last), with twelve 0's corresponding to an
output of 0V and twelve 1's corresponding to a full-scale output of VA – 1 LSB. When writing to the DAC
Register, VOUT will update on the rising edge of the ACK following the lower data byte.
MSB
LSB
0
X
X
PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
DATA BITS
0
0
1
1
0
1
0
1
Normal Operation.
2.5 kÖ to GND.
100 kÖ to GND.
High Impedance.
Power-Down Modes
Figure 27. DAC Register Contents
22
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Bipolar Operation
The DAC081C081 is designed for single-supply operation and thus has a unipolar output. However, a bipolar
output may be obtained with the circuit in Figure 28. This circuit will provide an output voltage range of ±5 Volts.
A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5 V.
10 pF
R
2
+5V
R
+5V
1
+
-
10 mF
0.1 mF
±5V
+
DAC081C081
-5V
V
SDA
SCL
OUT
Figure 28. Bipolar Operation
The output voltage of this circuit for any code is found to be
VO = (VA × (D / 256) × ((R1 + R2) / R1) – VA × R2 / R1)
where
•
D is the input code in decimal form.
(2)
(3)
With VA = 5V and R1 = R2,
VO = (10 × D / 256) – 5 V
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 4.
Table 4. Some Rail-to-Rail Amplifiers
AMP
PKGS
SOT23-5
SC70-5
TYP VOS
37 uV
TYP ISUPPLY
0.79 mA
1 mA
LMP7701
LMV841
LMC7111
50 uV
SOT23-5
0.9 mV
25 µA
SO-8
SOT23-5
LM7301
LM8261
0.03 mV
0.7 mV
620 µA
1 mA
SOT23-5
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
9.1.2 DSP/Microprocessor Interfacing
Interfacing the DAC081C081 to microprocessors and DSPs is quite simple. The following guidelines are offered
to simplify the design process.
9.1.2.1 Interfacing to the 2-Wire Bus
Figure 29 shows a microcontroller interfacing to the DAC081C081 through the 2-wire bus. Pullup resistors (Rp)
should be chosen to create an appropriate bus rise time and to limit the current that will be sunk by the open-
drain outputs of the devices on the bus. Please refer to the I2C Specification for further details. Typical pullup
values to use in standard-fast mode bus applications are 2 kΩ to 10 kΩ. SCL and SDA series resisters (RS) near
the DAC081C081 are optional. If high-voltage spikes are expected on the 2-wire bus, series resistors should be
used to filter the voltage on SDA and SCL. The value of the series resistance must be picked to ensure the VIL
threshold can be achieved. If used, RS is typically 51 Ω.
Regulated Supply
V
V
REF
V
A
DD
mController
DAC081C081/5
R
R
P
P
R
R
*
*
S
SDA
SCL
SDA
SCL
S
ADC081C021
SDA
SCL
I2C Device
SDA
SCL
*NOTE: R is optional.
S
Figure 29. Serial Interface Connection Diagram
9.1.2.2 Interfacing to a Hs-mode Bus
Interfacing to a Hs-mode bus is very similar to interfacing to a standard-fast mode bus. In Hs-mode, the specified
rise time of SCL is shortened. To create a faster rise time, the master device (microcontroller) can drive the SCL
bus high and low. In other words, the microcontroller can drive the line high rather than leaving it to the pullup
resistor. It is also possible to decrease the value of the pullup resistors or increase the pullup current to meet the
tighter timing specs. Please refer to the I2C Specification for further details.
24
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
9.2 Typical Application
2
SDA
4
5
VA
SC
L
ADR0
1
VOUT
DAC081C081CIMK
3
6
+5
LM4132-3.3
4
120pF
5
3
+5
A2
.1uF
1uF
2
3
4
+
-
5
1
180
+3.3
+5
.2uF
2
100K
1
9
10
VA
8
SCLK
470pF
2
VREF
VIO
+IN
DOUT
/CS
7
6
ADC161S626
AV = 100
2.02K
-IN
3
4,
5
+5
.2uF
100K
3
-
470pF
5
180
1
A1
Pressure
Sensor
4
+
2
0.2mV/Volt/PSI
A1 and A2 = LMP7701
Figure 30. Pressure Sensor Gain Adjust
9.2.1 Design Requirements
A positive supply only data acquisition system capable of digitizing a pressure sensor output. In addition to
digitizing the pressure sensor output, the system designer can use the DAC081C081 to correct for gain errors in
the pressure sensor output by adjusting the bias voltage to the bridge pressure sensor.
9.2.2 Detailed Design Procedure
As shown in Equation 4, the output of the pressure sensor is relative to the imbalance of the resistive bridge
times the output of the DAC081C081, thus providing the desired gain correction.
Pressure Sensor Output = (DAC_Output × [(R2 / (R1 + R2) – (R4 / (R3 + R4)]
(4)
Likewise for the ADC161S626, Equation 5 shows that the ADC output is function of the pressure sensor output
times relative to the ratio of the ADC input divided by the DAC081C081 output voltage.
ADC161S626 Output = (Pressure Sensor Output × 100 /(2 × VREF) ) × 216
(5)
9.2.3 Application Curve
Figure 31. INL vs Input Code
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
10 Power Supply Recommendations
10.1 Using References as Power Supplies
While the simplicity of the DAC081C081 implies ease of use, it is important to recognize that the path from the
reference input (VA for the DAC081C081 and VREF for the DAC081C085) to VOUT will have essentially zero
Power Supply Rejection Ratio (PSRR). Therefore, it is necessary to provide a noise-free supply voltage to the
reference. In order to use the full dynamic range of the DAC081C085, the supply pin (VA) and VREF can be
connected together and share the same supply voltage. Since the DAC081C081 consumes very little power, a
reference source may be used as the supply voltage. The advantages of using a reference source over a voltage
regulator are accuracy and stability. Some low noise regulators can also be used. Listed below are a few
reference and power supply options for the DAC081C081. When using the DAC081C081, it is important to treat
the analog supply (VA) as the reference.
10.1.1 LM4132
The LM4132, with its 0.05% accuracy over temperature, is a good choice as a reference source for the
DAC081C081. The 4.096-V version is useful if a 0 to 4.095-V output range is desirable or acceptable. Bypassing
the LM4132 VIN pin with a 0.1-µF capacitor and the VOUT pin with a 2.2-µF capacitor will improve stability and
reduce output noise. The LM4132 comes in a space-saving 5-pin SOT23.
Input
Voltage
LM4132-4.1
C2
C3
C1
2.2 mF
0.1 mF
0.1 mF
V
A
V
REF
DAC081C081/5
V
OUT
= 0V to 4.092V
SDA
SCL
Figure 32. The LM4132 as a Power Supply
10.1.2 LM4050
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the
DAC081C081. It is available in 4.096-V and 5-V versions and comes in a space-saving 3-pin SOT23.
Input
Voltage
R
I
DAC
V
Z
I
Z
0.1 mF
0.47 mF
V
V
REF
LM4050-4.1
or
LM4050-5.0
A
DAC081C081/5
V
OUT
= 0V to 5V
SDA
SCL
Figure 33. The LM4050 as a Power Supply
26
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
Using References as Power Supplies (continued)
The minimum resistor value in the circuit of Figure 33 must be chosen such that the maximum current through
the LM4050 does not exceed its 15-mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, and the DAC081C081 drawing zero current. The maximum
resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum
DAC081C081 current in full operation. The conditions for minimum current include the input voltage at its
minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the
DAC081C081 draws its maximum current. These conditions can be summarized as
R(min) = ( VIN(max) − VZ(min) ) /IZ(max)
(6)
and
R(max) = ( VIN(min) − VZ(max) ) / ( (IDAC(max) + IZ(min) )
where
•
VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over
temperature,
•
•
•
IZ(max) is the maximum allowable current through the LM4050,
IZ(min) is the minimum current required by the LM4050 for proper regulation,
and IDAC(max) is the maximum DAC081C081 supply current.
(7)
10.1.3 LP3985
The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC081C081. It comes in 3-V, 3.3-V and
5-V versions, among others, and sports a low 30-µV noise specification at low frequencies. Since low frequency
noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes
in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.
Input
LP3985
Voltage
0.1 mF
0.1 mF
1 mF
0.01 mF
V
V
REF
A
DAC081C081/5
V
OUT
= 0V to 5V
SDA
SCL
Figure 34. Using the LP3985 Regulator
An input capacitance of 1 µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic
capacitor with an ESR requirement of 5 mΩ to 500 mΩ is required at the output. Careful interpretation and
understanding of the capacitor specification is required to ensure correct device operation.
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
Using References as Power Supplies (continued)
10.1.4 LP2980
The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon
grade. It is available in 3-V, 3.3-V and 5-V versions, among others.
V
IN
Input
V
OUT
Voltage
LP2980
1 mF
ON /
OFF
0.1 mF
V
A
V
REF
DAC081C081/5
V
OUT
= 0V to 5V
SDA
SCL
Figure 35. Using the LP2980 Regulator
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1 µF over temperature, but values of 2.2 µF or more will provide even better performance. The
ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid
tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to
their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic
capacitors are typically not a good choice due to their large size and have ESR values that may be too high at
low temperatures.
28
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
11 Layout
11.1 Layout Guidelines
For best accuracy and minimum noise, the printed-circuit-board containing the DAC081C081 should have
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.
Both of these planes should be located on the same board layer. There should be a single ground plane. A
single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently
a single ground plane design will use a fencing technique to prevent the mixing of analog and digital ground
current. Separate ground planes should only be used when the fencing technique is inadequate. The separate
ground planes must be connected in one place, preferably near the DAC081C081. Special care is required to
ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a
continuous return path below their traces.
The DAC081C081 power supply should be bypassed with a 4.7-µF and a 0.1-µF capacitor as close as possible
to the device with the 0.1 µF right at the device supply pin. The 4.7-µF capacitor should be a tantalum type and
the 0.1-µF capacitor should be a low ESL, low ESR type. The power supply for the DAC081C081 should only be
used for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. These clock and data lines should have controlled impedances.
11.2 Layout Example
ADR0
VOUT
SCL
VA
SOT
C1
SDA
GND
Figure 36. Typical Layout
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For development support, see the following:
•
•
•
•
12-Bit Micro Power Digital-to-Analog Converter with an I2C-Compatible Interface, DAC121C081
12-Bit Micro Pwr DAC w/ I2C-Compatible Interface & External Reference, DAC121C085
10-Bit Micro Power Digital-to-Analog Converter with an I2C-Compatible Interface, DAC101C081
10-Bit Micro Pwr DAC w/ I2C-Compatible Interface & External Reference, DAC101C085
12.1.2 Device Nomenclature
12.1.2.1 Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 256 = VA / 256.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC output is not updated. It is measured with a full-scale code change on the
data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded
into the DAC and the value of VA x 255 / 256.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is
Zero Error.
GLITCH IMPULSEis the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL)is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line
is measured from the center of that code value. The end point method is used. INL for this product
is specified over a limited range, per the Electrical Tables.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value
is LSB = VREF / 2n where VREF is the supply voltage for this product, and "n" is the DAC resolution
in bits, which is 8 for the DAC081C081.
MAXIMUM LOAD CAPACITANCEis the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VA.
MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave
on VREFIN with a full-scale code loaded into the DAC.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents is the power consumed
by the device without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
TOTAL HARMONIC DISTORTION (THD)is the measure of the harmonics present at the output of the DACs
with an ideal sine wave applied to VREFIN. THD is measured in dB.
WAKE-UP TIME is the time for the output to exit power-down mode. This time is measured from the rising edge
of SCL during the ACK bit of the lower data byte to the time the output voltage deviates from the
30
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: DAC081C081 DAC081C085
DAC081C081, DAC081C085
www.ti.com
SNAS449F –FEBRUARY 2008–REVISED MAY 2017
Device Support (continued)
power-down voltage of 0V.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DAC081C081
DAC081C085
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: DAC081C081 DAC081C085
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC081C081CIMK/NOPB
DAC081C081CIMKX/NOPB
DAC081C081CISD/NOPB
DAC081C081CISDX/NOPB
DAC081C085CIMM/NOPB
DAC081C085CIMMX/NOPB
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
NGF
NGF
DGK
DGK
6
6
6
6
8
8
1000 RoHS & Green
3000 RoHS & Green
1000 RoHS & Green
4500 RoHS & Green
1000 RoHS & Green
3500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
X86C
X86C
X89
NIPDAU
SN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
VSSOP
VSSOP
SN
X89
SN
X92C
X92C
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC081C081CIMK/NOPB SOT-23-
THIN
DDC
DDC
6
6
1000
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
DAC081C081CIMKX/
NOPB
SOT-23-
THIN
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
DAC081C081CISD/NOPB WSON
NGF
NGF
6
6
1000
4500
178.0
330.0
12.4
12.4
2.8
2.8
2.5
2.5
1.0
1.0
8.0
8.0
12.0
12.0
Q1
Q1
DAC081C081CISDX/
NOPB
WSON
VSSOP
VSSOP
DAC081C085CIMM/
NOPB
DGK
DGK
8
8
1000
3500
178.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
DAC081C085CIMMX/
NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC081C081CIMK/NOPB
SOT-23-THIN
SOT-23-THIN
DDC
DDC
6
6
1000
3000
210.0
210.0
185.0
185.0
35.0
35.0
DAC081C081CIMKX/
NOPB
DAC081C081CISD/NOPB
WSON
WSON
NGF
NGF
6
6
1000
4500
210.0
367.0
185.0
367.0
35.0
35.0
DAC081C081CISDX/
NOPB
DAC081C085CIMM/NOPB
VSSOP
VSSOP
DGK
DGK
8
8
1000
3500
210.0
367.0
185.0
367.0
35.0
35.0
DAC081C085CIMMX/
NOPB
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
NGF0006A
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明