DAC0830MWC [TI]

暂无描述;


型号：	DAC0830MWC
厂家：	TEXAS INSTRUMENTS
描述：	暂无描述转换器模数转换器
文件：	总29页 (文件大小：1597K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

DAC0830/DAC0832 8-Bit μP Compatible, Double-Buffered D to A Converters

Check for Samples: DAC0830, DAC0832

FEATURES

KEY SPECIFICATIONS

234

•

Double-Buffered, Single-Buffered or Flow-

Through Digital Data Inputs

•

Current Settling Time: 1 μs

Resolution: 8 bits

•

Easy Interchange and Pin-Compatible with 12-

bit DAC1230 Series

Linearity: 8, 9, or 10 bits (Ensured Over

Temp.)

•

Direct Interface to All Popular

Microprocessors

•

Gain Tempco: 0.0002% FS/°C

Low Power Dissipation: 20 mW

Single Power Supply: 5 to 15 V_DC

Linearity Specified with Zero and Full Scale

Adjust Only—NOT BEST STRAIGHT LINE FIT.

Works with ±10V Reference-Full 4-Quadrant

Multiplication

DESCRIPTION

The DAC0830 is an advanced CMOS/Si-Cr 8-bit

multiplying DAC designed to interface directly with the

8080, 8048, 8085, Z80^®, and other popular

microprocessors. A deposited silicon-chromium R-2R

resistor ladder network divides the reference current

and provides the circuit with excellent temperature

tracking characteristics (0.05% of Full Scale Range

maximum linearity error over temperature). The circuit

uses CMOS current switches and control logic to

achieve low power consumption and low output

leakage current errors. Special circuitry provides TTL

logic input voltage level compatibility.

•

Can Be Used in the Voltage Switching Mode

Logic Inputs Which Meet TTL Voltage Level

Specs (1.4V Logic Threshold)

•

Operates “STAND ALONE” (without μP) if

Desired

Available in 20-Pin SOIC or PLCC Package

Double buffering allows these DACs to output a

voltage corresponding to one digital word while

holding the next digital word. This permits the

simultaneous updating of any number of DACs.

The DAC0830 series are the 8-bit members of a

family of microprocessor-compatible DACs (MICRO-

DAC).

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

BI-FET is a trademark of Texas Instruments.

Z80 is a registered trademark of Zilog Corporation.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

Connection Diagrams

(Top Views)

Figure 1. PDIP, CDIP, and SOIC Packages

Figure 2. PLCC Package

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings^(1)(2)(3)

Supply Voltage (V_CC

)

17 V_DC

V_CCto GND

±25V

Voltage at Any Digital Input

Voltage at V_REFInput

Storage Temperature Range

−65°C to +150°C

Package Dissipation at

T_A=25°C⁽⁴⁾

500 mW

DC Voltage Applied to

−100 mV to V_CC

(5)

I_OUT1or I_OUT2

ESD Susceptability⁽⁵⁾⁽⁶⁾

800V

260°C

300°C

215°C

220°C

Lead

PDIP Package (plastic)

Temperature

(Soldering, 10

sec.)

CDIP Package (ceramic)

SOIC Package

Vapor Phase (60 sec.)

Infrared (15 sec.)

(1) All voltages are measured with respect to GND, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not

apply when operating the device beyond its specified operating conditions.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by T_JMAX, θ_JA, and the ambient temperature,

T_A. The maximum allowable power dissipation at any temperature is P_D= (T_JMAX− T_A)/θ_JAor the number given in the Absolute

Maximum Ratings, whichever is lower. For this device, T_JMAX= 125°C (plastic) or 150°C (ceramic), and the typical junction-to-ambient

thermal resistance of the J package when board mounted is 80°C/W. For the NFH package, this number increases to 100°C/W and for

the FN package this number is 120°C/W.

(5) For current switching applications, both I_OUT1and I_OUT2must go to ground or the “Virtual Ground” of an operational amplifier. The

linearity error is degraded by approximately V_OS÷ V_REF. For example, if V_REF= 10V then a 1 mV offset, V_OS, on I_OUT1or I_OUT2will

introduce an additional 0.01% linearity error.

(6) Human body model, 100 pF discharged through a 1.5 kΩ resistor.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

Operating Conditions

Temperature Range

T_MIN≤T_A≤T_MAX

Part numbers with “LCN” suffix

0°C to +70°C

Part numbers with “LCWM” suffix

Part numbers with “LCV” suffix

Part numbers with “LCJ” suffix

Part numbers with “LJ” suffix

Voltage at Any Digital Input

0°C to +70°C

−40°C to +85°C

−55°C to +125°C

V_CCto GND

Electrical Characteristics

V_REF=10.000 V_DCunless otherwise noted. Boldface limits apply over temperature, T_MIN≤T_A≤T_MAX.

⁽¹⁾For all other limits

T_A=25°C.

V_CC= 5 V_DC±5%

V_CC= 12 V_DC±5%

to 15 V_DC±5%

V_CC= 4.75 V_DC

V_CC= 15.75 V_DC

See

Note

Limit

Parameter

Conditions

Units⁽²⁾

Tested

Design

Limit⁽⁵⁾

Typ⁽³⁾

Limit⁽⁴⁾

CONVERTER CHARACTERISTICS

Resolution

bits

Linearity Error Max

Zero and full scale adjusted

−10V≤V_REF≤+10V

See⁽⁶⁾

and

(2)

DAC0830LJ & LCJ

DAC0832LJ & LCJ

0.05

0.2

0.05

0.2

% FSR

DAC0830LCN, LCWM &

LCV

0.05

DAC0831LCN

0.1

0.2

0.1

0.2

% FSR

DAC0832LCN, LCWM &

LCV

Differential Nonlinearity

Max

Zero and full scale adjusted

−10V≤V_REF≤+10V

See⁽⁶⁾

and

(2)

DAC0830LJ & LCJ

DAC0832LJ & LCJ

0.1

0.4

0.1

0.4

0.1

% FSR

DAC0830LCN, LCWM &

LCV

DAC0831LCN

0.2

0.4

0.2

0.4

% FSR

DAC0832LCN, LCWM &

LCV

Monotonicity

−10V≤V_REF

LJ & LCJ

See⁽⁶⁾

See⁽⁷⁾

bits

≤+10V

LCN, LCWM & LCV

Gain Error Max

Using Internal R_fb

−10V≤V_REF≤+10V

±0.2

±1

% FS

FS/°C

Gain Error Tempco Max

Using internal R_fb

0.0002

0.0006

(1) Boldface tested limits apply to the LJ and LCJ suffix parts only.

(2) The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate

dependence on a particular V_REFvalue and to indicate the true performance of the part. The “Linearity Error” specification of the

DAC0830 is “0.05% of FSR (MAX)”. This ensures that after performing a zero and full scale adjustment (see sections Zero Adjustment

and Full-Scale Adjustment), the plot of the 256 analog voltage outputs will each be within 0.05%×V_REFof a straight line which passes

through zero and full scale.

(3) Typicals are at 25°C and represent most likely parametric norm.

(4) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).

(5) Ensured, but not 100% production tested. These limits are not used to calculate outgoing quality levels.

(6) For current switching applications, both I_OUT1and I_OUT2must go to ground or the “Virtual Ground” of an operational amplifier. The

linearity error is degraded by approximately V_OS÷ V_REF. For example, if V_REF= 10V then a 1 mV offset, V_OS, on I_OUT1or I_OUT2will

introduce an additional 0.01% linearity error.

(7) Specified at V_REF=±10 V_DCand V_REF=±1 V_DC

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

Electrical Characteristics (continued)

V_REF=10.000 V_DCunless otherwise noted. Boldface limits apply over temperature, T_MIN≤T_A≤T_MAX

(1)

For all other limits

T_A=25°C.

V_CC= 5 V_DC±5%

V_CC= 12 V_DC±5%

to 15 V_DC±5%

V_CC= 4.75 V_DC

V_CC= 15.75 V_DC

See

Note

Limit

Parameter

Conditions

Units⁽²⁾

Tested

Design

Limit⁽⁵⁾

Typ⁽³⁾

Limit⁽⁴⁾

Power Supply Rejection

All digital inputs latched high

V_CC=14.5V to 15.5V

11.5V to 12.5V

0.0002

0.0006

0.013

0.0025

FSR/V

4.5V to 5.5V

0.015

Reference

Input

Max

Min

kΩ

Output Feedthrough Error V_REF=20 Vp-p, f=100 kHz

All data inputs latched low

mVp-p

Output Leakage I_OUT1

Current Max⁽⁸⁾

All data inputs LJ & LCJ

See⁽⁸⁾

100

latched low

LCN, LCWM & LCV

I_OUT2

All data inputs LJ & LCJ

100

latched high

All data inputs

latched low

LCN, LCWM & LCV

Output

Capacitance

I_OUT1

I_OUT2

I_OUT1

I_OUT2

115

130

All data inputs

latched high

DIGITAL AND DC CHARACTERISTICS

Digital Input

Voltages

Max

Logic Low

LJ: 4.75V

0.6

0.8

LJ: 15.75V

LCJ: 4.75V

LCJ: 15.75V

LCN, LCWM, LCV

LJ & LCJ

0.7

V_DC

0.8

0.95

2.0

0.8

2.0

Min

Logic High

V_DC

LCN, LCWM, LCV

LJ & LCJ

1.9

2.0

Digital Input

Currents

Max

Digital inputs

<0.8V

−50

0.1

1.2

−200

−160

+10

−200

+10

3.5

μA

LCN, LCWM, LCV

LJ & LCJ

Digital

inputs>2.0V

LCN, LCWM, LCV

LJ & LCJ

Supply Current

Drain

Max

3.5

LCN, LCWM, LCV

1.7

2.0

(8) A 100nA leakage current with R_fb=20k and V_REF=10V corresponds to a zero error of (100×10⁻⁹×20×10³)×100/10 which is 0.02% of FS.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

Electrical Characteristics

V_REF=10.000 V_DCunless otherwise noted. Boldface limits apply over temperature, T_MIN≤T_A≤T_MAX

⁽¹⁾For all other limits

T_A=25°C.

V_CC=12 V_DC±5%

to 15 V_DC±5%

V_CC=5

V_DC±5%

V_CC=15.75 V_DC

V_CC=4.75 V_DC

See

Note

Limit

Units

Symbol

Parameter

Conditions

Tested

Typ⁽²⁾

Tested

Design

Limit⁽⁴⁾

Design Limit⁽⁴⁾

Typ⁽²⁾

Limit⁽³⁾

AC CHARACTERISTICS⁽⁵⁾

t_s

Current Setting

Time

V_IL=0V, V_IH=5V

1.0

μs

t_W

Write and XFER

Pulse Width Min

Data Setup Time

V_IL=0V, V_IH=5V See⁽

100

250

320

250

375

600

900

600

See⁽

320

900

t_DS

t_DH

t_CS

t_CH

V_IL=0V, V_IH=5V See⁽

100

375

Min

320

900

Data Hold Time

V_IL=0V, V_IH=5V See⁽

Min

Control Setup

Time

V_IL=0V, V_IH=5V See⁽

110

250

600

900

Min

320

1100

Control Hold Time V_IL=0V, V_IH=5V See⁽

Min

(1) Boldface tested limits apply to the LJ and LCJ suffix parts only.

(2) Typicals are at 25°C and represent most likely parametric norm.

(3) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).

(4) Ensured, but not 100% production tested. These limits are not used to calculate outgoing quality levels.

(5) The entire write pulse must occur within the valid data interval for the specified t_W, t_DS, t_DH, and t_Sto apply.

Switching Waveform

Definition of Package Pinouts

Control Signals

(All control signals level actuated)

CS: Chip Select (active low). The CS in combination with ILE will enable WR₁.

ILE: Input Latch Enable (active high). The ILE in combination with CS enables WR₁.

WR₁: Write 1. The active low WR₁is used to load the digital input data bits (DI) into the input latch. The data in

the input latch is latched when WR₁is high. To update the input latch–CS and WR₁must be low while ILE

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

is high.

WR₂: Write 2 (active low). This signal, in combination with XFER, causes the 8-bit data which is available in the

input latch to transfer to the DAC register.

XFER: Transfer control signal (active low). The XFER will enable WR₂.

Other Pin Functions

DI₀-DI₇: Digital Inputs. DI₀is the least significant bit (LSB) and DI₇is the most significant bit (MSB).

I_OUT1: DAC Current Output 1. I_OUT1is a maximum for a digital code of all 1's in the DAC register, and is zero for

all 0's in DAC register.

I_OUT2: DAC Current Output 2. I_OUT2is a constant minus I_OUT1, or I_OUT1+ I_OUT2= constant (I full scale for a fixed

reference voltage).

R_fb: Feedback Resistor. The feedback resistor is provided on the IC chip for use as the shunt feedback

resistor for the external op amp which is used to provide an output voltage for the DAC. This on-chip

resistor should always be used (not an external resistor) since it matches the resistors which are used in

the on-chip R-2R ladder and tracks these resistors over temperature.

V_REF: Reference Voltage Input. This input connects an external precision voltage source to the internal R-2R

ladder. V_REFcan be selected over the range of +10 to −10V. This is also the analog voltage input for a 4-

quadrant multiplying DAC application.

V_CC

Digital Supply Voltage. This is the power supply pin for the part. V_CCcan be from +5 to +15V_DC.

Operation is optimum for +15V_DC

GND: The pin 10 voltage must be at the same ground potential as I_OUT1and I_OUT2for current switching

applications. Any difference of potential (V_OSpin 10) will result in a linearity change of :

(1)

For example, if V_REF= 10V and pin 10 is 9mV offset from I_OUT1and I_OUT2the linearity change will be 0.03%.

Pin 3 can be offset ±100mV with no linearity change, but the logic input threshold will shift.

Linearity Error

Figure 3. a) End Point Test After

Zero and fs adj.

Figure 4. b) Best Straight Line

Figure 5. c) Shifting fs adj. to

Pass

Best Straight Line Test

Definition of Terms

Resolution: Resolution is directly related to the number of switches or bits within the DAC. For example, the

DAC0830 has 2⁸or 256 steps and therefore has 8-bit resolution.

Linearity Error: Linearity Error is the maximum deviation from a straight line passing through the endpoints of

the DAC transfer characteristic. It is measured after adjusting for zero and full-scale. Linearity error is a

parameter intrinsic to the device and cannot be externally adjusted.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

TI's linearity “end point test” (a) and the “best straight line” test (b,c) used by other suppliers are illustrated above.

The “end point test'' greatly simplifies the adjustment procedure by eliminating the need for multiple iterations of

checking the linearity and then adjusting full scale until the linearity is met. The “end point test'' ensures that

linearity is met after a single full scale adjust. (One adjustment vs. multiple iterations of the adjustment.) The “end

point test'' uses a standard zero and F.S. adjustment procedure and is a much more stringent test for DAC

linearity.

Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the

DAC full-scale output.

Settling Time: Settling time is the time required from a code transition until the DAC output reaches within

±½LSB of the final output value. Full-scale settling time requires a zero to full-scale or full-scale to zero output

change.

Full Scale Error: Full scale error is a measure of the output error between an ideal DAC and the actual device

output. Ideally, for the DAC0830 series, full scale is V_REF−1LSB. For V_REF= 10V and unipolar operation, V_FULL-

_SCALE= 10,0000V–39mV 9.961V. Full-scale error is adjustable to zero.

Differential Nonlinearity: The difference between any two consecutive codes in the transfer curve from the

theoretical 1 LSB to differential nonlinearity.

Monotonic: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. An 8-

bit DAC which is monotonic to 8 bits simply means that increasing digital input codes will produce an increasing

analog output.

Figure 6. DAC0830 Functional Diagram

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

Typical Performance Characteristics

Digital Input Threshold

vs.

Temperature

Digital Input Threshold

vs.

V_CC

Figure 7.

Figure 8.

Gain and Linearity Error Variation

vs.

Temperature

Supply Voltage

Figure 9.

Figure 10.

Write Pulse Width

Data Hold Time

Figure 11.

Figure 12.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

DAC0830 SERIES APPLICATION HINTS

These DAC's are the industry's first microprocessor compatible, double-buffered 8-bit multiplying D to A

converters. Double-buffering allows the utmost application flexibility from a digital control point of view. This 20-

pin device is also pin for pin compatible (with one exception) with the DAC1230, a 12-bit MICRO-DAC. In the

event that a system's analog output resolution and accuracy must be upgraded, substituting the DAC1230 can

be easily accomplished. By tying address bit A₀to the ILE pin, a two-byte μP write instruction (double precision)

which automatically increments the address for the second byte write (starting with A₀=“1”) can be used. This

allows either an 8-bit or the 12-bit part to be used with no hardware or software changes. For the simplest 8-bit

application, this pin should be tied to V_CC(also see other uses in Double-Buffered Operation).

Analog signal control versatility is provided by a precision R-2R ladder network which allows full 4-quadrant

multiplication of a wide range bipolar reference voltage by an applied digital word.

DIGITAL CONSIDERATIONS

A most unique characteristic of these DAC's is that the 8-bit digital input byte is double-buffered. This means that

the data must transfer through two independently controlled 8-bit latching registers before being applied to the R-

2R ladder network to change the analog output. The addition of a second register allows two useful control

features. First, any DAC in a system can simultaneously hold the current DAC data in one register (DAC register)

and the next data word in the second register (input register) to allow fast updating of the DAC output on

demand. Second, and probably more important, double-buffering allows any number of DAC's in a system to be

updated to their new analog output levels simultaneously via a common strobe signal.

The timing requirements and logic level convention of the register control signals have been designed to

minimize or eliminate external interfacing logic when applied to most popular microprocessors and development

systems. It is easy to think of these converters as 8-bit “write-only” memory locations that provide an analog

output quantity. All inputs to these DAC's meet TTL voltage level specs and can also be driven directly with high

voltage CMOS logic in non-microprocessor based systems. To prevent damage to the chip from static discharge,

all unused digital inputs should be tied to V_CCor ground. If any of the digital inputs are inadvertantly left floating,

the DAC interprets the pin as a logic “1”.

Double-Buffered Operation

Updating the analog output of these DAC's in a double-buffered manner is basically a two step or double write

operation. In a microprocessor system two unique system addresses must be decoded, one for the input latch

controlled by the CS pin and a second for the DAC latch which is controlled by the XFER line. If more than one

DAC is being driven, Figure 13, the CS line of each DAC would typically be decoded individually, but all of the

converters could share a common XFER address to allow simultaneous updating of any number of DAC's. The

timing for this operation is shown, Figure 14.

It is important to note that the analog outputs that will change after a simultaneous transfer are those from the

DAC's whose input register had been modified prior to the XFER command.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

*TIE TO LOGIC 1 IF NOT NEEDED (SEE Double-Buffered Operation).

Figure 13. Controlling Mutiple DACs

Figure 14.

The ILE pin is an active high chip select which can be decoded from the address bus as a qualifier for the normal

CS signal generated during a write operation. This can be used to provide a higher degree of decoding unique

control signals for a particular DAC, and thereby create a more efficient addressing scheme.

Another useful application of the ILE pin of each DAC in a multiple DAC system is to tie these inputs together

and use this as a control line that can effectively “freeze” the outputs of all the DAC's at their present value.

Pulling this line low latches the input register and prevents new data from being written to the DAC. This can be

particularly useful in multiprocessing systems to allow a processor other than the one controlling the DAC's to

take over control of the data bus and control lines. If this second system were to use the same addresses as

those decoded for DAC control (but for a different purpose) the ILE function would prevent the DAC's from being

erroneously altered.

In a “Stand-Alone” system the control signals are generated by discrete logic. In this case double-buffering can

be controlled by simply taking CS and XFER to a logic “0”, ILE to a logic “1” and pulling WR₁low to load data to

the input latch. Pulling WR₂low will then update the analog output. A logic “1” on either of these lines will prevent

the changing of the analog output.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

ILE=LOGIC “1”; WR2 and XFER GROUNDED

Figure 15.

Single-Buffered Operation

In a microprocessor controlled system where maximum data throughput to the DAC is of primary concern, or

when only one DAC of several needs to be updated at a time, a single-buffered configuration can be used. One

of the two internal registers allows the data to flow through and the other register will serve as the data latch.

Digital signal feedthrough (see Section Digital Signal Feedthrough) is minimized if the input register is used as

the data latch. Timing for this mode is shown in Figure 15.

Single-buffering in a “stand-alone” system is achieved by strobing WR₁low to update the DAC with CS, WR₂and

XFER grounded and ILE tied high.

Flow-Through Operation

Though primarily designed to provide microprocessor interface compatibility, the MICRO-DAC's can easily be

configured to allow the analog output to continuously reflect the state of an applied digital input. This is most

useful in applications where the DAC is used in a continuous feedback control loop and is driven by a binary up-

down counter, or in function generation circuits where a ROM is continuously providing DAC data.

Simply grounding CS, WR₁, WR₂, and XFER and tying ILE high allows both internal registers to follow the

applied digital inputs (flow-through) and directly affect the DAC analog output.

Control Signal Timing

When interfacing these MICRO-DAC to any microprocessor, there are two important time relationships that must

be considered to insure proper operation. The first is the minimum WR strobe pulse width which is specified as

900 ns for all valid operating conditions of supply voltage and ambient temperature, but typically a pulse width of

only 180ns is adequate if V_CC=15V_DC. A second consideration is that the specified minimum data hold time of

50ns should be met or erroneous data can be latched. This hold time is defined as the length of time data must

be held valid on the digital inputs after a qualified (via CS) WR strobe makes a low to high transition to latch the

applied data.

If the controlling device or system does not inherently meet these timing specs the DAC can be treated as a slow

memory or peripheral and utilize a technique to extend the write strobe. A simple extension of the write time, by

adding a wait state, can simultaneously hold the write strobe active and data valid on the bus to satisfy the

minimum WR pulsewidth. If this does not provide a sufficient data hold time at the end of the write cycle, a

negative edge triggered one-shot can be included between the system write strobe and the WR pin of the DAC.

This is illustrated in Figure 16 for an exemplary system which provides a 250ns WR strobe time with a data hold

time of less than 10ns.

The proper data set-up time prior to the latching edge (LO to HI transition) of the WR strobe, is insured if the WR

pulsewidth is within spec and the data is valid on the bus for the duration of the DAC WR strobe.

Digital Signal Feedthrough

When data is latched in the internal registers, but the digital inputs are changing state, a narrow spike of current

may flow out of the current output terminals. This spike is caused by the rapid switching of internal logic gates

that are responding to the input changes.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

There are several recommendations to minimize this effect. When latching data in the DAC, always use the input

improvement in the magnitude of the feedthrough, but at the expense of internal logic switching speed. Finally,

increasing C_C(Figure 19) to a value consistent with the actual circuit bandwidth requirements can provide a

substantial damping effect on any output spikes.

Figure 16. Accommodating a High Speed System

ANALOG CONSIDERATIONS

The fundamental purpose of any D to A converter is to provide an accurate analog output quantity which is

representative of the applied digital word. In the case of the DAC0830, the output, I_OUT1, is a current directly

proportional to the product of the applied reference voltage and the digital input word. For application versatility, a

second output, I_OUT2, is provided as a current directly proportional to the complement of the digital input.

Basically:

where the digital input is the decimal (base 10) equivalent of the applied 8-bit binary word (0 to 255), V_REFis the

voltage at pin 8 and 15 kΩ is the nominal value of the internal resistance, R, of the R-2R ladder network

(discussed in Section The Current Switching R-2R Ladder).

Several factors external to the DAC itself must be considered to maintain analog accuracy and are covered in

subsequent sections.

The Current Switching R-2R Ladder

The analog circuitry, Figure 17, consists of a silicon-chromium (SiCr or Si-chrome) thin film R-2R ladder which is

deposited on the surface oxide of the monolithic chip. As a result, there are no parasitic diode problems with the

ladder (as there may be with diffused resistors) so the reference voltage, V_REF, can range −10V to +10V even if

V_CCfor the device is 5V_DC

The digital input code to the DAC simply controls the position of the SPDT current switches and steers the

available ladder current to either I_OUT1or I_OUT2as determined by the logic input level (“1” or “0”) respectively, as

shown in Figure 17. The MOS switches operate in the current mode with a small voltage drop across them and

can therefore switch currents of either polarity. This is the basis for the 4-quadrant multiplying feature of this

DAC.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

Basic Unipolar Output Voltage

To maintain linearity of output current with changes in the applied digital code, it is important that the voltages at

both of the current output pins be as near ground potential (0V_DC) as possible. With V_REF=+10V every millivolt

appearing at either I_OUT1or I_OUT2will cause a 0.01% linearity error. In most applications this output current is

converted to a voltage by using an op amp as shown in Figure 18.

The inverting input of the op amp is a “virtual ground” created by the feedback from its output through the internal

15 kΩ resistor, R_fb. All of the output current (determined by the digital input and the reference voltage) will flow

through R_fbto the output of the amplifier. Two-quadrant operation can be obtained by reversing the polarity of

V_REFthus causing I_OUT1to flow into the DAC and be sourced from the output of the amplifier. The output voltage,

in either case, is always equal to I_OUT1×R_fband is the opposite polarity of the reference voltage.

The reference can be either a stable DC voltage source or an AC signal anywhere in the range from −10V to

+10V. The DAC can be thought of as a digitally controlled attenuator: the output voltage is always less than or

equal to the applied reference voltage. The V_REFterminal of the device presents a nominal impedance of 15 kΩ

to ground to external circuitry.

Always use the internal R_fbresistor to create an output voltage since this resistor matches (and tracks with

temperature) the value of the resistors used to generate the output current (I_OUT1).

Figure 17.

Figure 18.

Op Amp Considerations

The op amp used in Figure 18 should have offset voltage nulling capability (See Section Zero Adjustment).

The selected op amp should have as low a value of input bias current as possible. The product of the bias

current times the feedback resistance creates an output voltage error which can be significant in low reference

voltage applications. BI-FET™ op amps are highly recommended for use with these DACs because of their very

low input current.

Transient response and settling time of the op amp are important in fast data throughput applications. The largest

stability problem is the feedback pole created by the feedback resistance, R_fb, and the output capacitance of the

DAC. This appears from the op amp output to the (−) input and includes the stray capacitance at this node.

Addition of a lead capacitance, C_Cin Figure 19, greatly reduces overshoot and ringing at the output for a step

change in DAC output current.

Finally, the output voltage swing of the amplifier must be greater than V_REFto allow reaching the full scale output

voltage. Depending on the loading on the output of the amplifier and the available op amp supply voltages (only

±12 volts in many development systems), a reference voltage less than 10 volts may be necessary to obtain the

full analog output voltage range.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

Bipolar Output Voltage with a Fixed Reference

The addition of a second op amp to the previous circuitry can be used to generate a bipolar output voltage from

a fixed reference voltage. This, in effect, gives sign significance to the MSB of the digital input word and allows

two-quadrant multiplication of the reference voltage. The polarity of the reference can also be reversed to realize

full 4-quadrant multiplication: ±V_REF×±Digital Code=±V_OUT. This circuit is shown in Figure 20.

This configuration features several improvements over existing circuits for bipolar outputs with other multiplying

DACs. Only the offset voltage of amplifier 1 has to be nulled to preserve linearity of the DAC. The offset voltage

error of the second op amp (although a constant output voltage error) has no effect on linearity. It should be

nulled only if absolute output accuracy is required. Finally, the values of the resistors around the second amplifier

do not have to match the internal DAC resistors, they need only to match and temperature track each other. A

thin film 4-resistor network available from Beckman Instruments, Inc. (part no. 694-3-R10K-D) is ideally suited for

this application. These resistors are matched to 0.1% and exhibit only 5 ppm/°C resistance tracking temperature

coefficient. Two of the four available 10 kΩ resistors can be paralleled to form R in Figure 20 and the other two

can be used independently as the resistances labeled 2R.

Zero Adjustment

For accurate conversions, the input offset voltage of the output amplifier must always be nulled. Amplifier offset

errors create an overall degradation of DAC linearity.

The fundamental purpose of zeroing is to make the voltage appearing at the DAC outputs as near 0V_DCas

possible. This is accomplished for the typical DAC — op amp connection (Figure 18) by shorting out R_fb, the

amplifier feedback resistor, and adjusting the V_OSnulling potentiometer of the op amp until the output reads zero

volts. This is done, of course, with an applied digital code of all zeros if I_OUT1is driving the op amp (all one's for

I_OUT2). The short around R_fbis then removed and the converter is zero adjusted.

Figure 19.

t_s

OP Amp

C_C

(O to Full Scale)

LF356

LF351

LF357⁽¹⁾

22 pF

10 pF

4 μs

5 μs

2 μs

(1) 2.4 kΩ RESISTOR ADDED FROM−INPUT TO GROUND TO

INSURE STABILITY

*THESE RESISTORS ARE AVAILABLE FROM BECKMAN INSTRUMENTS, INC. AS THEIR PART NO. 694-3-R10K-

Figure 20.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

Input Code

IDEAL V_OUT

MSB

1 1

1 0

0 1

0 0

LSB

+V_REF

−V_REF

Full-Scale Adjustment

In the case where the matching of R_fbto the R value of the R-2R ladder (typically ±0.2%) is insufficient for full-

scale accuracy in a particular application, the V_REFvoltage can be adjusted or an external resistor and

potentiometer can be added as shown in Figure 21 to provide a full-scale adjustment.

The temperature coefficients of the resistors used for this adjustment are of an important concern. To prevent

degradation of the gain error temperature coefficient by the external resistors, their temperature coefficients

ideally would have to match that of the internal DAC resistors, which is a highly impractical constraint. For the

values shown in Figure 21, if the resistor and the potentiometer each had a temperature coefficient of ±100

ppm/°C maximum, the overall gain error temperature coefficent would be degraded a maximum of 0.0025%/°C

for an adjustment pot setting of less than 3% of R_fb.

Using the DAC0830 in a Voltage Switching Configuration

The R-2R ladder can also be operated as a voltage switching network. In this mode the ladder is used in an

inverted manner from the standard current switching configuration. The reference voltage is connected to one of

the current output terminals (I_OUT1for true binary digital control, I_OUT2is for complementary binary) and the output

voltage is taken from the normal V_REFpin. The converter output is now a voltage in the range from 0V to 255/256

V_REFas a function of the applied digital code as shown in Figure 22.

Figure 21. Adding Full-Scale Adjustment

Figure 22. Voltage Mode Switching

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

This configuration offers several useful application advantages. Since the output is a voltage, an external op amp

is not necessarily required but the output impedance of the DAC is fairly high (equal to the specified reference

input resistance of 10 kΩ to 20 kΩ) so an op amp may be used for buffering purposes. Some of the advantages

of this mode are illustrated in Figure 23, Figure 24, Figure 25, and Figure 26.

There are two important things to keep in mind when using this DAC in the voltage switching mode. The applied

reference voltage must be positive since there are internal parasitic diodes from ground to the I_OUT1and I_OUT2

terminals which would turn on if the applied reference went negative. There is also a dependence of conversion

linearity and gain error on the voltage difference between V_CCand the voltage applied to the normal current

output terminals. This is a result of the voltage drive requirements of the ladder switches. To ensure that all 8

switches turn on sufficiently (so as not to add significant resistance to any leg of the ladder and thereby introduce

additional linearity and gain errors) it is recommended that the applied reference voltage be kept less than +5V_DC

and V_CCbe at least 9V more positive than V_REF. These restrictions ensure less than 0.1% linearity and gain error

change. Figure 27, Figure 28, and Figure 29 characterize the effects of bringing V_REFand V_CCcloser together as

well as typical temperature performance of this voltage switching configuration.

•

Voltage switching mode eliminates output signal inversion and therefore a need for a negative power supply.

Zero code output voltage is limited by the low level output saturation voltage of the op amp. The 2 kΩ pull-down

resistor helps to reduce this voltage.

•

V_OSof the op amp has no effect on DAC linearity.

Figure 23. Single Supply DAC

Figure 24. Obtaining a Bipolar Output from a Fixed Reference with a Single Op Amp

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

Figure 25. Bipolar Output with Increased Output Voltage Swing

Figure 26. Single Supply DAC with Level Shift and Span- Adjustable Output

Gain and Linearity Error Variation

vs.

Supply Voltage

Reference Voltage

Note: For these curves, V_REFis the voltage applied to pin 11 (I_OUT1

)

with pin 12 (I_OUT2) grounded.

Figure 27.

Figure 28.

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

Gain and Linearity Error Variation

vs.

Temperature

Figure 29.

Miscellaneous Application Hints

These converters are CMOS products and reasonable care should be exercised in handling them to prevent

catastrophic failures due to static discharge.

Conversion accuracy is only as good as the applied reference voltage so providing a stable source over time and

temperature changes is an important factor to consider.

A “good” ground is most desirable. A single point ground distribution technique for analog signals and supply

returns keeps other devices in a system from affecting the output of the DACs.

During power-up supply voltage sequencing, the −15V (or −12V) supply of the op amp may appear first. This will

cause the output of the op amp to bias near the negative supply potential. No harm is done to the DAC, however,

as the on-chip 15 kΩ feedback resistor sufficiently limits the current flow from I_OUT1when this lead is internally

clamped to one diode drop below ground.

Careful circuit construction with minimization of lead lengths around the analog circuitry, is a primary concern.

Good high frequency supply decoupling will aid in preventing inadvertant noise from appearing on the analog

output.

Overall noise reduction and reference stability is of particular concern when using the higher accuracy versions,

the DAC0830 and DAC0831, or their advantages are wasted.

GENERAL APPLICATION IDEAS

The connections for the control pins of the digital input registers are purposely omitted. Any of the control formats

discussed in Digital Considerations of the accompanying text will work with any of the circuits shown. The

method used depends on the overall system provisions and requirements.

The digital input code is referred to as D and represents the decimal equivalent value of the 8-bit binary input, for

example:

Binary Input

Pin 13

MSB

Pin 7

LSB

Decimal

Equivalent

255

128

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

Applications

Figure 30. DAC Controlled Amplifier (Volume Control)

Figure 31. Capacitance Multiplier

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

Figure 32. Variable f_O, Variable Q_O, Constant BW Bandpass Filter

Figure 33. DAC Controlled Function Generator

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

www.ti.com

SNAS534B –MAY 1999–REVISED MARCH 2013

Figure 34. Two Terminal Floating 4 to 20 mA Current Loop Controller

•

DAC0830 linearly controls the current flow from the input terminal to the output terminal to be 4 mA (for D=0)

to 19.94 mA (for D=255).

•

Circuit operates with a terminal voltage differential of 16V to 55V.

P₂adjusts the magnitude of the output current and P₁adjusts the zero to full scale range of output current.

Digital inputs can be supplied from a processor using opto isolators on each input or the DAC latches can

flow-through (connect control lines to pins 3 and 10 of the DAC) and the input data can be set by SPST

toggle switches to ground (pins 3 and 10).

Figure 35. DAC Controlled Exponential Time Response

•

Output responds exponentially to input changes and automatically stops when V_OUT=V_IN

Output time constant is directly proportional to the DAC input code and capacitor C

Input voltage must be positive (See Using the DAC0830 in a Voltage Switching Configuration

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

DAC0830, DAC0832

SNAS534B –MAY 1999–REVISED MARCH 2013

www.ti.com

REVISION HISTORY

Changes from Revision A (March 2013) to Revision B

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 21

Submit Documentation Feedback

Product Folder Links: DAC0830 DAC0832

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

DAC0830LCN

ACTIVE

PDIP

NFH

TBD

Call TI

0 to 70

DAC0830LCN

DAC0830LCN/NOPB

ACTIVE

NFH

Pb-Free

(RoHS)

Level-1-NA-UNLIM

DAC0830LCN

DAC0832LCN

ACTIVE

PDIP

NFH

TBD

Call TI

0 to 70

DAC0832LCN

DAC0832LCN/NOPB

Green (RoHS

& no Sb/Br)

Level-1-NA-UNLIM

DAC0832LCWM

DAC0832LCWM/NOPB

DAC0832LCWMX

ACTIVE

SOIC

TBD

Call TI

CU SN

Call TI

CU SN

Call TI

0 to 70

DAC0832

LCWM

Green (RoHS

& no Sb/Br)

Level-3-260C-168 HR

Call TI

DAC0832

LCWM

1000

TBD

DAC0832

LCWM

DAC0832LCWMX/NOPB

Green (RoHS

& no Sb/Br)

Level-3-260C-168 HR

DAC0832

LCWM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Mar-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC0832LCWMX

SOIC

1000

330.0

24.4

10.9

13.3

3.25

12.0

24.0

DAC0832LCWMX/NOPB

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Mar-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC0832LCWMX

SOIC

1000

367.0

45.0

DAC0832LCWMX/NOPB

Pack Materials-Page 2

MECHANICAL DATA

NFH0020A

N0020A

N20A (Rev G)

www.ti.com

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DAC0830MWC [TI]

相关型号：

DAC0831

DAC0831LCN

DAC0831LCN/A+

DAC0831LCN/B+

DAC0832

DAC0832LCD

DAC0832LCJ

DAC0832LCM

DAC0832LCMX

DAC0832LCN

DAC0832LCN

DAC0832LCN/A+