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DAC101S101QCMKX/NOPB [TI]

10 位微功耗、RRO 数模转换器 | DDC | 6 | -40 to 125;
DAC101S101QCMKX/NOPB
型号： DAC101S101QCMKX/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

10 位微功耗、RRO 数模转换器 | DDC | 6 | -40 to 125

光电二极管 转换器 数模转换器
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DAC101S101, DAC101S101-Q1  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
DAC101S101 and DAC101S101Q-1 10-Bit Micro Power, RRO Digital-to-Analog Converter  
1 Features  
3 Description  
The DAC101S101 is a full-featured, general purpose  
10-bit voltage-output digital-to-analog converter  
(DAC) that can operate from a single +2.7 V to 5.5 V  
supply and consumes just 175 µA of current at 3.6  
Volts. The on-chip output amplifier allows rail-to-rail  
output swing and the three wire serial interface  
operates at clock rates up to 30 MHz over the  
specified supply voltage range and is compatible with  
standard SPI, QSPI, MICROWIRE and DSP  
interfaces. Competitive devices are limited to 20 MHz  
clock rates at supply voltages in the 2.7 V to 3.6 V  
range.  
1
•
DAC101S101Q is AEC-Q100 Grade 1 Qualified  
and is Manufactured on an Automotive Grade  
Flow.  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ensured Monotonicity  
Low Power Operation  
Rail-to-Rail Voltage Output  
Power-on Reset to Zero Volts Output  
Wide Temperature Range of −40°C to +125°C  
Wide Power Supply Range of 2.7 V to 5.5 V  
Small Packages  
The supply voltage for the DAC101S101 serves as its  
voltage reference, providing the widest possible  
output dynamic range. A power-on reset circuit  
ensures that the DAC output powers up to zero volts  
and remains there until there is a valid write to the  
Power Down Feature  
Resolution 10 bits  
DNL +0.15, –0.05 LSB (typical)  
Output Settling Time 8 μs (typical)  
Zero Code Error 3.3 mV (typical)  
Full-Scale Error −0.06 %FS (typical)  
Power Consumption  
device.  
A
power-down feature reduces power  
consumption to less than a microWatt.  
Device Information(1)  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
–
Normal Mode, 0.63 mW (3.6 V) / 1.41 mW (5.5  
V) typical  
DAC101S101  
VSSOP (8)  
3.00 mm × 3.00 mm  
DAC101S101,  
DAC101S101-Q1  
–
Power Down Mode, 0.14 μW (3.6 V) / 0.33 μW  
(5.5 V) typical  
SOT-23 (6)  
1.60 mm × 2.90 mm  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
2 Applications  
•
•
•
•
•
Battery-Powered Instruments  
Digital Gain and Offset Adjustment  
Programmable Voltage & Current Sources  
Programmable Attenuators  
Automotive  
DNL at VA = 3 V  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
DAC101S101, DAC101S101-Q1  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
www.ti.com  
Table of Contents  
8.4 Device Functional Modes........................................ 18  
8.5 Programming .......................................................... 19  
Application and Implementation ........................ 21  
9.1 Application Information............................................ 21  
9.2 Typical Application .................................................. 21  
1
2
3
4
5
6
7
Features.................................................................. 1  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Description (continued)......................................... 3  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
7.1 Absolute Maximum Ratings ...................................... 4  
7.2 ESD Ratings DAC101S101 ...................................... 4  
7.3 ESD Ratings DAC101S101-Q1 ................................ 4  
7.4 Recommended Operating Conditions ...................... 5  
7.5 Thermal Information.................................................. 5  
7.6 Electrical Characteristics.......................................... 6  
7.7 A.C. and Timing Requirements................................ 9  
7.8 Typical Characteristics............................................ 11  
Detailed Description ............................................ 17  
8.1 Overview ................................................................. 17  
8.2 Functional Block Diagram ....................................... 17  
8.3 Feature Description................................................. 17  
9
10 Power Supply Recommendations ..................... 23  
10.1 Using References as Power Supplies................... 23  
11 Layout................................................................... 26  
11.1 Layout Guidelines ................................................. 26  
11.2 Layout Example .................................................... 26  
12 Device and Documentation Support ................. 27  
12.1 Device Support .................................................... 27  
12.2 Related Links ........................................................ 28  
12.3 Community Resources.......................................... 28  
12.4 Trademarks........................................................... 28  
12.5 Electrostatic Discharge Caution............................ 28  
12.6 Glossary................................................................ 28  
8
13 Mechanical, Packaging, and Orderable  
Information ........................................................... 28  
4 Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision F (March 2013) to Revision G  
Page  
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,  
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and  
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1  
Updated Operating Conditions table to a Recommended Operating Conditions table.......................................................... 5  
Updated Layout, Grounding, and Bypassing section to a Layout Guidelines section.......................................................... 26  
•
•
Changes from Revision E (March 2013) to Revision F  
Page  
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 26  
2
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Copyright © 2005–2016, Texas Instruments Incorporated  
Product Folder Links: DAC101S101 DAC101S101-Q1  
 
DAC101S101, DAC101S101-Q1  
www.ti.com  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
5 Description (continued)  
The low power consumption and small packages of the DAC101S101 make it an excellent choice for use in  
battery operated equipment.  
The DAC101S101 is a direct replacement for the AD5310 and is one of a family of pin compatible DACs,  
including the 8-bit DAC081S101 and the 12-bit DAC121S101. The DAC101S101 operates over the extended  
industrial temperature range of −40°C to +105°C while the DAC101S101Q operates over the Grade 1 automotive  
temperature range of −40°C to +125°C. The DAC101S101 is available in a 6-lead SOT and an 8-lead VSSOP  
and the DAC101S101Q is availabe in the 6-lead SOT only.  
6 Pin Configuration and Functions  
DAC101S101 and DAC101S101-Q1 DDC Package  
DAC101S101 DGK Package  
6-Pin (SOT-23)  
8-Pin (VSSOP)  
Top View  
Top View  
V
1
2
3
6
5
4
SYNC  
SCLK  
OUT  
V
1
2
3
4
8
7
6
5
GND  
!
GND  
NC  
NC  
D
IN  
V
!
D
IN  
SCLK  
SYNC  
V
OUT  
Pin Functions  
PIN  
DAC101S101  
SOT-23 VSSOP  
DAC101S101-Q1  
SOT-23  
I/O(1)  
DESCRIPTION  
NAME  
Serial Data Input. Data is clocked into the 16-bit shift register on the  
falling edges of SCLK after the fall of SYNC.  
DIN  
4
7
4
I
GND  
NC  
2
–
8
2
–
G
–
Ground reference for all on-chip circuitry.  
2,3  
No Connect. There is no internal connection to these pins.  
Serial Clock Input. Data is clocked into the input shift register on the  
falling edges of this pin.  
SCLK  
5
6
5
I
Frame synchronization input for the data input. When this pin goes low, it  
enables the input shift register and data is transferred on the falling  
edges of SCLK. The DAC is updated on the 16th clock cycle unless  
SYNC is brought high before the 16th clock, in which case the rising  
edge of SYNC acts as an interrupt and the write sequence is ignored by  
the DAC.  
SYNC  
6
5
6
I
VA  
3
1
1
4
3
1
S
Power supply and Reference input. Should be decoupled to GND.  
DAC Analog Output Voltage.  
VOUT  
O
(1) G = Ground, I = Input, O = Output, S = Supply  
Copyright © 2005–2016, Texas Instruments Incorporated  
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Product Folder Links: DAC101S101 DAC101S101-Q1  
DAC101S101, DAC101S101-Q1  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
www.ti.com  
7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)  
(1)(2)(3)  
MIN  
MAX  
UNIT  
Supply voltage, VA  
6.5  
V
Voltage on any input pin  
–0.3  
(VA + 0.3)  
10  
V
(4)  
Input current at any pin  
mA  
mA  
(4)  
Package input current  
20  
(5)  
Power consumption at TA = 25°C  
Storage temperature, Tstg  
See  
−65  
150  
°C  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the  
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may  
degrade when the device is not operated under the listed test conditions.  
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and  
specifications.  
(3) All voltages are measured with respect to GND = 0V, unless otherwise specified  
(4) When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should  
be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power  
supplies with an input current of 10 mA to two.  
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by  
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula  
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe  
fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).  
Obviously, such conditions should always be avoided.  
7.2 ESD Ratings DAC101S101  
VALUE  
±2500  
±250  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2)  
Machine Model  
V(ESD)  
Electrostatic discharge  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO  
Ohms.  
7.3 ESD Ratings DAC101S101-Q1  
VALUE  
±2500  
±250  
UNIT  
Human-body model (HBM), per AEC Q100-002(1)  
Machine Model  
V(ESD)  
Electrostatic discharge  
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.  
4
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Copyright © 2005–2016, Texas Instruments Incorporated  
Product Folder Links: DAC101S101 DAC101S101-Q1  
DAC101S101, DAC101S101-Q1  
www.ti.com  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
7.4 Recommended Operating Conditions(1) (2)  
MIN  
MAX  
−40°C ≤ TA ≤ +105°C  
−40°C ≤ TA ≤ +125°C  
5.5  
UNIT  
DAC101S101  
Operating temperature  
DAC101S101-Q1  
(3)  
Supply voltage, VA  
2.7  
–0.1  
0
V
V
(4)  
Any input voltage  
(VA + 0.1)  
Output load  
1500  
pF  
SCLK frequency  
Up to 30 MHz  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the  
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may  
degrade when the device is not operated under the listed test conditions.  
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified  
(3) To ensure accuracy, it is required that VA be well bypassed.  
(4) The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not  
damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV.  
For example, if VA is 2.7VDC, ensure that −100mV ≤ input voltages ≤2.8VDC to ensure accurate conversions.  
L/h  
Çh LbÇ9wb![  
ꢀLwꢀÜLÇwò  
Db5  
7.5 Thermal Information  
DAC101S101,  
DAC101S101  
DAC101S101-Q1  
THERMAL METRIC(1)  
UNIT  
DDC (SOT-23)  
6 PINS  
250  
DGK (VSSOP)  
8 PINS  
240  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
58.8  
70.0  
30.6  
100.2  
11.3  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
1.6  
ψJB  
30.1  
98.7  
RθJC(bot)  
N/A  
N/A  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report, SPRA953.  
Copyright © 2005–2016, Texas Instruments Incorporated  
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DAC101S101, DAC101S101-Q1  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
www.ti.com  
7.6 Electrical Characteristics  
The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input  
code range 12 to 1011, TA = 25°C, unless otherwise specified.  
(1)  
(1)  
PARAMETER  
STATIC PERFORMANCE  
Resolution  
TEST CONDITIONS  
MIN(1)  
TYP  
MAX  
UNIT  
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
10  
10  
Bits  
Bits  
Monotonicity  
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
±0.6  
−0.05/+0.15  
3.3  
Over decimal  
codes 12 to  
1011  
INL  
DNL  
ZE  
Integral non-linearity  
LSB  
LSB  
DAC101S101: −40°C ≤ TA ≤ +105°C,  
DAC101S101Q: −40°C ≤ TA ≤ +125°C  
–2.8  
2.8  
0.35  
15  
Differential  
non-linearity  
VA = 2.7 V to  
5.5 V  
DAC101S101: −40°C ≤ TA ≤ +105°C,  
DAC101S101Q: −40°C ≤ TA ≤ +125°C  
−0.2  
Zero code error  
Full-scale error  
IOUT = 0  
mV  
DAC101S101: −40°C ≤ TA ≤ +105°C,  
DAC101S101Q: −40°C ≤ TA ≤ +125°C  
−0.06  
FSE  
IOUT = 0  
%FSR  
%FSR  
DAC101S101: −40°C ≤ TA ≤ +105°C,  
DAC101S101Q: −40°C ≤ TA ≤ +125°C  
–1  
−0.1  
All ones  
Loaded to  
DAC register  
GE  
Gain error  
DAC101S101: −40°C ≤ TA ≤ +105°C,  
DAC101S101Q: −40°C ≤ TA ≤ +125°C  
–1  
1
ZCED  
Zero code error drift  
−20  
−0.7  
−1  
µV/°C  
ppm/°C  
ppm/°C  
VA = 3 V  
VA = 5 V  
TC GE Gain error tempco  
OUTPUT CHARACTERISTICS  
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
Output voltage range  
0
VA  
V
(2)  
VA = 3 V, IOUT = 10 µA  
VA = 3 V, IOUT = 100 µA  
VA = 5 V, IOUT = 10 µA  
VA = 5 V, IOUT = 100 µA  
VA = 3 V, IOUT = 10 µA  
VA = 3 V, IOUT = 100 µA  
VA = 5 V, IOUT = 10 µA  
VA = 5 V, IOUT = 100 µA  
RL = ∞  
1.8  
5
mV  
mV  
mV  
mV  
V
ZCO  
FSO  
Zero code output  
Full scale output  
3.7  
5.4  
2.997  
2.99  
4.995  
4.992  
1500  
1500  
1.3  
V
V
V
pF  
pF  
Ω
Maximum load  
capacitance  
RL = 2 kΩ  
DC output Impedance  
VA = 5 V, VOUT = 0 V,  
Input code = 3FFh  
−63  
−50  
74  
mA  
mA  
mA  
mA  
VA = 3 V, VOUT = 0 V,  
Input code = 3FFh  
Output short circuit  
current  
IOS  
VA = 5 V, VOUT = 5 V,  
Input code = 000h  
VA = 3 V, VOUT = 3 V,  
Input code = 000h  
53  
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing  
Quality Level).  
(2) This parameter is ensured by design and/or characterization and is not tested in production.  
6
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Product Folder Links: DAC101S101 DAC101S101-Q1  
 
DAC101S101, DAC101S101-Q1  
www.ti.com  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
Electrical Characteristics (continued)  
The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input  
code range 12 to 1011, TA = 25°C, unless otherwise specified.  
(1)  
(1)  
PARAMETER  
LOGIC INPUT  
TEST CONDITIONS  
MIN(1)  
TYP  
MAX  
UNIT  
DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q:  
–40°C ≤ TA ≤ +125°C  
(2)  
IIN  
Input current  
–1  
1
µA  
V
VA = 5 V, DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: –40°C ≤ TA ≤ +125°C  
0.8  
0.5  
(2)  
VIL  
Input low voltage  
VA = 3 V, DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: −40°C ≤ TA ≤ +125°C  
V
VA = 5 V, DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: –40°C ≤ TA ≤ +125°C  
2.4  
2.1  
V
(2)  
VIH  
CIN  
Input high voltage  
Input capacitance  
VA = 3 V, DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: –40°C ≤ TA ≤ +125°C  
V
DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q:  
–40°C ≤ TA ≤ +125°C  
(2)  
3
pF  
POWER REQUIREMENTS  
256  
174  
221  
154  
DAC101S101: –40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
–40°C ≤ TA ≤ +125°C  
VA = 5.5 V  
VA = 3.6 V  
VA = 5.5 V  
VA = 3.6 V  
µA  
µA  
µA  
µA  
332  
226  
297  
207  
Normal Mode  
fSCLK = 30  
MHz  
DAC101S101: −40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
DAC101S101: −40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
Normal Mode  
fSCLK = 20  
MHz  
−40°C ≤ TA ≤ +125°C  
DAC101S101: −40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
Supply current  
(output unloaded)  
IA  
VA = 5.5 V  
VA = 3.6 V  
VA = 5 V  
145  
113  
83  
Normal Mode  
fSCLK = 0  
µA  
µA  
All PD  
Modes,  
fSCLK = 30  
MHz  
VA = 3 V  
VA = 5 V  
VA = 3 V  
42  
56  
All PD  
Modes,  
fSCLK = 20  
MHz  
µA  
µA  
28  
0.06  
DAC101S101: −40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
VA = 5.5 V  
VA = 3.6 V  
1
1
All PD  
−40°C ≤ TA ≤ +125°C  
Modes,  
fSCLK = 0  
(2)  
0.04  
DAC101S101: −40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
µA  
−40°C ≤ TA ≤ +125°C  
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DAC101S101, DAC101S101-Q1  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
www.ti.com  
Electrical Characteristics (continued)  
The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input  
code range 12 to 1011, TA = 25°C, unless otherwise specified.  
(1)  
(1)  
PARAMETER  
TEST CONDITIONS  
MIN(1)  
TYP  
MAX  
UNIT  
1.41  
0.63  
1.22  
0.55  
DAC101S101: −40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
VA = 5.5 V  
VA = 3.6 V  
VA = 5.5 V  
VA = 3.6 V  
mW  
1.83  
0.81  
1.63  
0.74  
Normal Mode  
fSCLK = 30  
MHz  
DAC101S101: −40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
mW  
mW  
mW  
−40°C ≤ TA ≤ +125°C  
DAC101S101: −40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
Normal Mode  
fSCLK = 20  
MHz  
−40°C ≤ TA ≤ +125°C  
DAC101S101: −40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
Power consumption  
(output unloaded)  
PC  
VA = 5.5 V  
VA = 3.6 V  
VA = 5 V  
0.8  
0.41  
0.42  
µW  
µW  
µW  
Normal Mode  
fSCLK = 0  
All PD  
Modes,  
fSCLK = 30  
MHz  
VA = 3 V  
VA = 5 V  
VA = 3 V  
0.13  
0.28  
0.08  
0.33  
µW  
µW  
µW  
All PD  
Modes,  
fSCLK = 20  
MHz  
DAC101S101: –40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
VA = 5.5 V  
VA = 3.6 V  
µW  
µW  
5.5  
3.6  
All PD  
–40°C ≤ TA ≤ +125°C  
Modes,  
fSCLK = 0  
(2)  
0.14  
DAC101S101: –40°C  
≤ TA ≤ +105°C,  
DAC101S101Q:  
–40°C ≤ TA ≤ +125°C  
VA = 5 V  
VA = 3 V  
91%  
94%  
IOUT / IA Power efficiency  
ILOAD = 2 mA  
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7.7 A.C. and Timing Requirements  
The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input  
code range 12 to 1011, TA = 25°C, unless otherwise specified.  
MIN(1)  
TYP(1)  
MAX(1) UNIT  
DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: –40°C ≤ TA ≤ +125°C  
fSCLK  
SCLK Frequency  
30  
MHz  
5
CL  
200  
pF  
≤
Output voltage  
settling time  
100h to 300h code change,  
RL = 2 kΩ  
DAC101S101: –40°C ≤ TA  
+105°C, DAC101S101Q:  
–40°C ≤ TA ≤ +125°C  
≤
ts  
µs  
(2)  
7.5  
SR  
Output slew rate  
Glitch impulse  
1
12  
0.5  
6
V/µs  
nV-sec  
nV-sec  
µs  
Code change from 200h to 1FFh  
Digital feedthrough  
VA = 5 V  
VA = 3 V  
tWU  
Wake-up time  
39  
µs  
1/fSCL  
K
DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: –40°C ≤ TA ≤ +125°C  
SCLK Cycle time  
33  
13  
13  
0
ns  
5
5
tH  
SCLK High time  
SCLK Low time  
ns  
DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: –40°C ≤ TA ≤ +125°C  
tL  
ns  
ns  
ns  
ns  
DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: –40°C ≤ TA ≤ +125°C  
−15  
2.5  
2.5  
0
Set-up time SYNC  
to SCLK rising  
edge  
tSUCL  
tSUD  
tDHD  
DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: –40°C ≤ TA ≤ +125°C  
Data set-up time  
Data hold time  
DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: –40°C ≤ TA ≤ +125°C  
5
DAC101S101: –40°C ≤ TA ≤ +105°C,  
DAC101S101Q: –40°C ≤ TA ≤ +125°C  
4.5  
DAC101S101: −40°C ≤ TA  
+105°C, DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
≤
≤
≤
≤
VA = 5 V  
ns  
ns  
ns  
ns  
3
1
SCLK fall to rise of  
SYNC  
tCS  
−2  
9
DAC101S101: −40°C ≤ TA  
+105°C, DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
VA = 3 V  
DAC101S101: −40°C ≤ TA  
+105°C, DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
2.7 ≤ VA ≤ 3.6  
3.6 ≤ VA ≤ 5.5  
20  
tSYNC SYNC High time  
5
DAC101S101: −40°C ≤ TA  
+105°C, DAC101S101Q:  
−40°C ≤ TA ≤ +125°C  
10  
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing  
Quality Level).  
(2) This parameter is ensured by design and/or characterization and is not tested in production.  
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FSE  
1023 x V  
1024  
A
GE = FSE - ZE  
FSE = GE + ZE  
hÜÇtÜÇ  
ëh[Ç!D9  
ZE  
0
0
1023  
5LDLÇ![ LbtÜÇ /h59  
Figure 1. Input / Output Transfer Characteristic  
1
f
CLK  
{/[Y  
1
2
13  
14  
1ꢀ  
16  
t
L
t
SUCL  
t
SYNC  
t
H
t
CS  
{òb/  
t
DHD  
D
IN  
5.1ꢀ  
5.0  
t
SUD  
Figure 2. Serial Timing Diagram  
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7.8 Typical Characteristics  
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated  
Figure 3. DNL at VA = 3 V  
Figure 5. INL at VA = 3 V  
Figure 7. TUE at VA = 3 V  
Figure 4. DNL at VA = 5 V  
Figure 6. INL at VA = 5 V  
Figure 8. TUE at VA = 5 V  
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Typical Characteristics (continued)  
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated  
Figure 9. DNL vs. VA  
Figure 10. INL vs. VA  
Figure 11. 3-V DNL vs. fSCLK  
Figure 12. 5-V DNL vs. fSCLK  
Figure 13. 3-V DNL vs. Clock Duty Cycle  
Figure 14. 5-V DNL vs. Clock Duty Cycle  
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Typical Characteristics (continued)  
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated  
Figure 15. 3-V DNL vs. Temperature  
Figure 16. 5-V DNL vs. Temperature  
Figure 17. 3-V INL vs. fSCLK  
Figure 18. 5-V INL vs. fSCLK  
Figure 19. 3-V INL vs. Clock Duty Cycle  
Figure 20. 5-V INL vs. Clock Duty Cycle  
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Typical Characteristics (continued)  
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated  
Figure 21. 3-V INL vs. Temperature  
Figure 22. 5-V INL vs. Temperature  
Figure 23. Zero Code Error vs. fSCLK  
Figure 24. Zero Code Error vs. Clock Duty Cycle  
Figure 25. Zero Code Error vs. Temperature  
Figure 26. Full-Scale Error vs. fSCLK  
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Typical Characteristics (continued)  
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated  
Figure 27. Full-Scale Error vs. Clock Duty Cycle  
Figure 28. Full-Scale Error vs. Temperature  
Figure 29. Supply Current vs. VA  
Figure 30. Supply Current vs. Temperature  
Figure 31. 5-V Glitch Response  
Figure 32. Power-On Reset  
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Typical Characteristics (continued)  
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated  
Figure 33. 3-V Wake-Up Time  
Figure 34. 5-V Wake-Up Time  
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8 Detailed Description  
8.1 Overview  
The DAC101S101 is a full-featured, general purpose 10-bit voltage-output digital-to-analog converter (DAC)  
that can operate from a single +2.7 V to 5.5 V supply and consumes just 175 µA of current at 3.6 Volts. The  
on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock  
rates up to 30 MHz over the specified supply voltage range and is compatible with standard SPI, QSPI,  
MICROWIRE and DSP interfaces.  
The supply voltage for the DAC101S101 serves as its voltage reference, providing the widest possible output  
dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains  
there until there is a valid write to the device. A power-down feature reduces power consumption to less than  
a microWatt.  
8.2 Functional Block Diagram  
V
A
GND  
thí9w-hb  
w9{9Ç  
5!/101{101  
w9C(+) w9C(-)  
10-.LÇ 5!/  
5!/  
w9DL{Ç9w  
.ÜCC9w  
V
OUT  
10  
10  
thí9w-5híb  
/hbÇwh[  
[hDL/  
LbtÜÇ  
/hbÇwh[  
[hDL/  
1k  
100k  
{/[Y  
{òb/  
D
IN  
8.3 Feature Description  
8.3.1 DAC Section  
The DAC101S101 is fabricated on a CMOS process with an architecture that consists of a resistor string and  
switches that are followed by an output buffer. The power supply serves as the reference voltage. The input  
coding is straight binary with an ideal output voltage of:  
VOUT = VA x (D / 1024)  
where  
•
D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value  
between 0 and 1023 (1)  
8.3.2 Resistor String  
The resistor string is shown in Figure 35. This string consists of 1024 equal valued resistors in series with a  
switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register  
determines which switch is closed, connecting the proper node to the amplifier. This configuration ensures that  
the DAC is monotonic.  
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Feature Description (continued)  
V
A
R
R
R
To Output Amplifier  
R
R
Figure 35. DAC Resistor String  
8.3.3 Output Amplifier  
The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0V to VA. All amplifiers, even  
rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For  
this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the  
amplifier are described in the Electrical Characteristics Tables.  
8.3.4 Power-On Reset  
The power-on reset circuit controls the output voltage during power-up. The DAC register is filled with zeros and  
the output voltage is 0 Volts and remains there until a valid write sequence is made to the DAC.  
8.4 Device Functional Modes  
8.4.1 Power-Down Modes  
The DAC101S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the  
control register.  
Table 1. Modes of Operation  
DB13  
DB12  
OPERATING MODE  
0
0
1
1
0
1
0
1
Normal Operation  
Power-Down with 1 kΩ to GND  
Power-Down with 100 kΩ to GND  
Power-Down with Hi-Z  
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When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of  
these bits the supply current drops to its power-down level and the output is pulled down with either a 1kΩ or a  
100KΩ resistor, or is in a high impedance state, as described in Table 1.  
The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the  
power-down modes. However, the contents of the DAC register are unaffected when in power-down. Minimum  
power consumption is achieved in the power-down mode with SCLK disabled and SYNC and DIN idled low. The  
time to exit power-down (Wake-Up Time) is typically tWU µsec as stated in the A.C. and Timing Requirements  
Table.  
8.5 Programming  
8.5.1 Serial Interface  
The three-wire interface is compatible with SPI, QSPI and MICROWIRE as well as most DSPs. See the Serial  
Timing Diagram for information on a write sequence.  
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked  
into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is  
clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register  
contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be  
brought high for the minimum specified time before the next write sequence so that a falling edge of SYNC can  
initiate the next write cycle.  
Because the SYNC and DIN buffers draw more current when they are high, they should be idled low between  
write sequences to minimize power consumption.  
8.5.2 Input Shift Register  
The input shift register, Figure 36, has sixteen bits. The first two bits are "don't cares" and are followed by two  
bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the  
serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Figure 2.  
a{.  
[{.  
ó
ó
t51 t50 59 58 57 56 5ꢀ 54 53 52 51 50  
ó
ó
5!Ç! .LÇ{  
0
0
1
1
0
1
0
1
bormꢁl hperꢁꢂion  
1 kW ꢂo Db5  
100 kW ꢂo Db5  
Iigꢃ Lmpedꢁnce  
tower-5own aodes  
Figure 36. Input Register Contents  
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th  
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and  
the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation.  
8.5.3 DSP/Microprocessor Interfacing  
Interfacing the DAC101S101 to microprocessors and DSPs is quite simple. The following guidelines are offered  
to hasten the design process.  
8.5.3.1 ADSP-2101/ADSP2103 Interfacing  
Figure 37 shows a serial interface between the DAC101S101 and the ADSP-2101/ADSP2103. The DSP should  
be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control  
register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.  
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.  
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Programming (continued)  
!5{t-2101/  
!5{t2103  
5!ꢀ101{101  
{òb/  
ÇC{  
5Ç  
5Lb  
{/[Y  
{/[Y  
Figure 37. ADSP-2101/2103 Interface  
8.5.3.2 80C51/80L51 Interface  
A serial interface between the DAC101S101 and the 80C51/80L51 microcontroller is shown in Figure 38. The  
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line  
P3.3. This line is taken low when data is to transmitted to the DAC101S101. Since the 80C51/80L51 transmits 8-  
bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must  
be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of  
data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the  
80C51/80L51 transmits data with the LSB first while the DAC101S101 requires data with the MSB first.  
80/51ꢀ80[51  
t3.3  
ꢁ!/101{101  
{òb/  
Çó5  
wó5  
{/[Y  
5Lb  
Figure 38. 80C51/80L51 Interface  
8.5.3.3 68HC11 Interface  
A serial interface between the DAC101S101 and the 68HC11 microcontroller is shown in Figure 39. The SYNC  
line of the DAC101S101 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.  
The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration  
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the  
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB  
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the  
second byte of data to the DAC, after which PC7 should be raised to end the write sequence.  
68I/11  
5!/101{101  
{òb/  
t/7  
{/Y  
{/[Y  
ah{L  
5Lb  
Figure 39. 68HC11 Interface  
8.5.3.4 Microwire Interface  
Figure 40 shows an interface between a Microwire compatible device and the DAC101S101. Data is clocked out  
on the rising edges of the SCLK signal.  
aL/whíLw9  
59ëL/9  
5!/101{101  
{òb/  
/{  
{Y  
{h  
{/[Y  
5Lb  
Figure 40. Microwire Interface  
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9 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
9.1 Application Information  
The DAC101S101 is designed for single supply operation and thus has a unipolar output. However, a bipolar  
output may be obtained with the circuit in Figure 41. This circuit will provide an output voltage range of ±5 Volts.  
A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V.  
9.2 Typical Application  
10 pC  
R
2
+ꢀë  
+ꢀë  
R
1
+
-
10 mF  
0.1 mF  
±5V  
+
5!/101{101  
-ꢀë  
{òb/  
V
OUT  
5Lb  
{/[Y  
Figure 41. Bipolar Operation  
9.2.1 Design Requirements  
•
•
•
The DAC101S101 will use a single supply.  
The output is required to be bipolar with a voltage range of ±5 V.  
Dual supplies will be used for the output amplifier.  
9.2.2 Detailed Design Procedure  
The output voltage of this circuit for any code is found to be  
VO = (VA x (D / 1024) x ((R1 + R2) / R1) - VA x R2 / R1)  
where  
•
•
D is the input code in decimal form  
With VA = 5V and R1 = R2  
(2)  
(3)  
VO = (10 x D / 1024) - 5V  
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.  
Table 2. Some Rail-To-Rail Amplifiers  
AMP  
PKGS  
Typ VOS  
Typ ISUPPLY  
LMC7111  
SOT-23-5  
0.9 mV  
25 µA  
SOIC-8  
SOT-23-5  
LM7301  
LM8261  
0.03 mV  
0.7 mV  
620 µA  
1 mA  
SOT-23-5  
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9.2.3 Application Curve  
5V  
hÜÇtÜÇ  
ëh[Ç!D9  
-5V  
0
1023  
5LDLÇ![ LbtÜÇ /h59  
Figure 42. Bipolar Input / Output Transfer Characteristic  
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10 Power Supply Recommendations  
The simplicity of the DAC101S101 implies ease of use. However, it is important to recognize that any data  
converter that utilizes its supply voltage as its reference voltage will have essentially zero PSRR (Power Supply  
Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device.  
10.1 Using References as Power Supplies  
Since the DAC101S101 consumes very little power, a reference source may be used as the supply voltage. The  
advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise  
regulators can also be used for the power supply of the DAC101S101. Listed below are a few power supply  
options for the DAC101S101.  
10.1.1 LM4130  
The LM4130 reference, with its 0.05% accuracy over temperature, is a good choice as a power source for the  
DAC101S101. Its primary disadvantage is the lack of a 3V and 5V versions. However, the 4.096V version is  
useful if a 0 to 4.095V output range is desirable or acceptable. Bypassing the VIN pin with a 0.1µF capacitor and  
the VOUT pin with a 2.2µF capacitor will improve stability and reduce output noise. The LM4130 comes in a  
space-saving 5-pin SOT-23.  
Lnput  
ëoltage  
[a4130-4.1  
C2  
C1  
2.2 mF  
0.1 mF  
5!/101{101  
V
OUT  
= 0V to 4.092V  
{òb/  
5Lb  
{/[Y  
Figure 43. The LM4130 as a Power Supply  
10.1.2 LM4050  
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a power regulator for the  
DAC101S101. It does not come in a 3 Volt version, but 4.096V and 5V versions are available. It comes in a  
space-saving 3-pin SOT-23.  
Lnput  
ëoltage  
w
V
Z
0.47 mF  
ꢀ!/101{101  
{òb/  
5Lb  
{/[Y  
[a4050-4.1  
or  
[a4050-5.0  
V
OUT  
= 0V to 5V  
Figure 44. The LM4050 as a Power Supply  
The minimum resistor value in the circuit of Figure 44 should be chosen such that the maximum current through  
the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at  
its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the  
DAC101S101 draws zero current. The maximum resistor value must allow the LM4050 to draw more than its  
minimum current for regulation plus the maximum DAC101S101 current in full operation. The conditions for  
minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value  
at its maximum due to tolerance, and the DAC101S101 draws its maximum current. These conditions can be  
summarized as  
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Using References as Power Supplies (continued)  
R(min) = ( VIN(max) − VZ(min) / (IA(min) + IZ(max))  
where  
•
•
•
VZ(min) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature  
IZ(max) is the maximum allowable current through the LM4050  
IA(min) is the minimum DAC101S101 supply current  
(4)  
(5)  
and  
R(max) = ( VIN(min) − VZ(max) / (IA(max) + IZ(min) )  
where  
•
•
•
VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature  
IZ(min) is the minimum current required by the LM4050 for proper regulation  
IA(max) is the maximum DAC101S101 supply current  
10.1.3 LP3985  
The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good  
choice for applications that do not require a precision reference for the DAC101S101. It comes in 3.0V, 3.3V and  
5V versions, among others, and sports a low 30 µV noise specification at low frequencies. Because low  
frequency noise is relatively difficult to filter, this specification could be important for some applications. The  
LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump micro SMD packages.  
Lnput  
ëoltage  
[t3985  
0.1 mF  
1 mF  
0.01 mF  
ꢀ!/101{101  
{òb/  
V
OUT  
= 0V to 5V  
5Lb  
{/[Y  
Figure 45. Using The Lp3985 Regulator  
An input capacitance of 1 µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic  
capacitor with an ESR requirement of 5 mΩ to 500 mΩ is required at the output. Careful interpretation and  
understanding of the capacitor specification is required to ensure correct device operation.  
10.1.4 LP2980  
The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon  
grade. It is available in 3 V, 3.3 V and 5 V versions, among others.  
V
IN  
hCC  
Lnput  
ëoltage  
V
OUT  
[t2980  
hb ꢀ  
1 mF  
5!/101{101  
{òb/  
V
OUT  
= 0V to 5V  
5Lb  
{/[Y  
Figure 46. Using The Lp2980 Regulator  
24  
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Copyright © 2005–2016, Texas Instruments Incorporated  
Product Folder Links: DAC101S101 DAC101S101-Q1  
DAC101S101, DAC101S101-Q1  
www.ti.com  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
Using References as Power Supplies (continued)  
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor  
must be at least 1-µF over temperature, but values of 2.2 µF or more provide better performance. The ESR of  
this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum  
capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small  
size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors  
are typically not a good choice due to their large size and have ESR values that may be too high at low  
temperatures.  
Copyright © 2005–2016, Texas Instruments Incorporated  
Submit Documentation Feedback  
25  
Product Folder Links: DAC101S101 DAC101S101-Q1  
DAC101S101, DAC101S101-Q1  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
www.ti.com  
11 Layout  
11.1 Layout Guidelines  
For best accuracy and minimum noise, the printed circuit board containing the DAC101S101 should have  
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.  
Both of these planes should be located in the same board layer. There should be a single ground plane. A single  
ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a  
single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground  
current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate  
ground planes must be connected in one place, preferably near the DAC101S101. Special care is required to  
ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a  
continuous return path below their traces.  
The DAC101S101 power supply should be bypassed with a 10-µF and a 0.1-µF capacitor as close as possible to  
the device with the 0.1-µF right at the device supply pin. The 10-µF capacitor should be a tantalum type and the  
0.1-µF capacitor should be a low ESL, low ESR type. The power supply for the DAC101S101 should only be  
used for analog circuits.  
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the  
board. The clock and data lines should have controlled impedances.  
11.2 Layout Example  
Figure 47. Layout Example  
26  
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Copyright © 2005–2016, Texas Instruments Incorporated  
Product Folder Links: DAC101S101 DAC101S101-Q1  
DAC101S101, DAC101S101-Q1  
www.ti.com  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
12 Device and Documentation Support  
12.1 Device Support  
12.1.1 Device Nomenclature  
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1  
LSB, which is VREF / 1024 = VA / 1024.  
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital  
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the  
data bus.  
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (3FFh) loaded  
into the DAC and the value of VA x 1023 / 1024.  
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and  
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is  
Zero Error.  
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register  
changes. It is specified as the area of the glitch in nanovolt-seconds.  
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line  
through the input to output transfer function. The deviation of any given code from this straight line  
is measured from the center of that code value. The end point method is used. INL for this product  
is specified over a limited range, per the Electrical Characteristics Tables.  
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value  
is  
LSB = VREF / 2n  
where  
•
•
VREF is the supply voltage for this product  
"n" is the DAC resolution in bits, which is 10 for the DAC101S101  
(6)  
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output  
stability maintained.  
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when  
the output code increases.  
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is  
1/2 of VREF  
.
Copyright © 2005–2016, Texas Instruments Incorporated  
Submit Documentation Feedback  
27  
Product Folder Links: DAC101S101 DAC101S101-Q1  
DAC101S101, DAC101S101-Q1  
SNAS321G –JUNE 2005–REVISED APRIL 2016  
www.ti.com  
Device Support (continued)  
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from  
the power supply. The difference between the supply and output currents, is the power consumed  
by the device without a load.  
SETTLING TIME is the time for the output to settle within 1/2 LSB of the final value.  
WAKE-UP TIME is the time for the output to settle within 1/2 LSB of the final value after the device is  
commanded to the active mode from any of the power down modes.  
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been  
entered.  
12.2 Related Links  
The table below lists quick access links. Categories include technical documents, support and community  
resources, tools and software, and quick access to sample or buy.  
Table 3. Related Links  
TECHNICAL  
DOCUMENTS  
TOOLS &  
SOFTWARE  
SUPPORT &  
COMMUNITY  
PARTS  
PRODUCT FOLDER  
SAMPLE & BUY  
DAC101S101  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
DAC101S101-Q1  
12.3 Community Resources  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
12.4 Trademarks  
E2E is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
12.5 Electrostatic Discharge Caution  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
12.6 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
13 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
28  
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Copyright © 2005–2016, Texas Instruments Incorporated  
Product Folder Links: DAC101S101 DAC101S101-Q1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
DAC101S101CIMK/NOPB  
DAC101S101CIMKX/NOPB  
DAC101S101CIMM/NOPB  
DAC101S101QCMK/NOPB  
DAC101S101QCMKX/NOPB  
ACTIVE SOT-23-THIN  
ACTIVE SOT-23-THIN  
DDC  
DDC  
DGK  
DDC  
DDC  
6
6
8
6
6
1000 RoHS & Green  
3000 RoHS & Green  
1000 RoHS & Green  
1000 RoHS & Green  
3000 RoHS & Green  
SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 105  
-40 to 105  
-40 to 105  
-40 to 125  
-40 to 125  
X63C  
X63C  
X62C  
X63Q  
X63Q  
SN  
SN  
SN  
SN  
ACTIVE  
VSSOP  
ACTIVE SOT-23-THIN  
ACTIVE SOT-23-THIN  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF DAC101S101, DAC101S101-Q1 :  
Catalog: DAC101S101  
•
Automotive: DAC101S101-Q1  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects  
•
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
DAC101S101CIMK/NOPB SOT-23-  
THIN  
DDC  
DDC  
6
6
1000  
3000  
178.0  
8.4  
3.2  
3.2  
1.4  
4.0  
8.0  
Q3  
DAC101S101CIMKX/  
NOPB  
SOT-23-  
THIN  
178.0  
8.4  
3.2  
3.2  
1.4  
4.0  
8.0  
Q3  
DAC101S101CIMM/NOPB VSSOP  
DGK  
DDC  
8
6
1000  
1000  
178.0  
178.0  
12.4  
8.4  
5.3  
3.2  
3.4  
3.2  
1.4  
1.4  
8.0  
4.0  
12.0  
8.0  
Q1  
Q3  
DAC101S101QCMK/  
NOPB  
SOT-23-  
THIN  
DAC101S101QCMKX/ SOT-23-  
NOPB THIN  
DDC  
6
3000  
178.0  
8.4  
3.2  
3.2  
1.4  
4.0  
8.0  
Q3  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
DAC101S101CIMK/NOPB  
SOT-23-THIN  
SOT-23-THIN  
DDC  
DDC  
6
6
1000  
3000  
210.0  
210.0  
185.0  
185.0  
35.0  
35.0  
DAC101S101CIMKX/  
NOPB  
DAC101S101CIMM/NOPB  
VSSOP  
DGK  
DDC  
DDC  
8
6
6
1000  
1000  
3000  
210.0  
210.0  
210.0  
185.0  
185.0  
185.0  
35.0  
35.0  
35.0  
DAC101S101QCMK/NOPB SOT-23-THIN  
DAC101S101QCMKX/  
NOPB  
SOT-23-THIN  
Pack Materials-Page 2  
PACKAGE OUTLINE  
DDC0006A  
SOT-23 - 1.1 max height  
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR  
3.05  
2.55  
1.1  
0.7  
1.75  
1.45  
0.1 C  
B
A
PIN 1  
INDEX AREA  
1
6
4X 0.95  
1.9  
3.05  
2.75  
4
3
0.5  
0.3  
0.1  
6X  
TYP  
0.0  
0.2  
C A B  
C
0 -8 TYP  
0.25  
GAGE PLANE  
SEATING PLANE  
0.20  
0.12  
TYP  
0.6  
0.3  
TYP  
4214841/C 04/2022  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Reference JEDEC MO-193.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DDC0006A  
SOT-23 - 1.1 max height  
SMALL OUTLINE TRANSISTOR  
SYMM  
6X (1.1)  
1
6
6X (0.6)  
SYMM  
4X (0.95)  
4
3
(R0.05) TYP  
(2.7)  
LAND PATTERN EXAMPLE  
EXPLOSED METAL SHOWN  
SCALE:15X  
METAL UNDER  
SOLDER MASK  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL  
EXPOSED METAL  
EXPOSED METAL  
0.07 MIN  
ARROUND  
0.07 MAX  
ARROUND  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
SOLDERMASK DETAILS  
4214841/C 04/2022  
NOTES: (continued)  
4. Publication IPC-7351 may have alternate designs.  
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DDC0006A  
SOT-23 - 1.1 max height  
SMALL OUTLINE TRANSISTOR  
SYMM  
6X (1.1)  
1
6
6X (0.6)  
SYMM  
4X(0.95)  
4
3
(R0.05) TYP  
(2.7)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 THICK STENCIL  
SCALE:15X  
4214841/C 04/2022  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
7. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you  
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these  
resources.  
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for  
TI products.  
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2022, Texas Instruments Incorporated  

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