DAC34H84_14 [TI]
Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC);型号: | DAC34H84_14 |
厂家: | TEXAS INSTRUMENTS |
描述: | Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC) |
文件: | 总80页 (文件大小:1306K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)
Check for Samples: DAC34H84
1
FEATURES
DESCRIPTION
The DAC34H84 is a very low power, high dynamic
range, quad-channel, 16-bit digital-to-analog
converter (DAC) with a sample rate as high as 1.25
GSPS.
•
•
•
Very Low Power: 1.4 W at 1.25 GSPS
Multi-DAC Synchronization
Selectable 2x, 4x, 8x, 16x Interpolation Filter
–
Stop-Band Attenuation > 90 dBc
The device includes features that simplify the design
of complex transmit architectures: 2x to 16x digital
interpolation filters with over 90 dB of stop-band
attenuation simplify the data interface and
reconstruction filters. Independent complex mixers
allow flexible carrier placement. A high-performance
low jitter clock multiplier simplifies clocking of the
device without significant impact on the dynamic
range. The digital Quadrature Modulator Correction
(QMC) enables complete IQ compensation for gain,
offset, phase and group delay between channels in
direct up-conversion applications.
•
Flexible On-chip Complex Mixing
–
–
Two Independent Fine Mixers with 32-bit
NCOs
Power Saving Coarse Mixers: ± n×Fs/8
•
•
High Performance, Low Jitter Clock
Multiplying PLL
Digital I and Q Correction
–
Gain, Phase, Offset, and Group Delay
Correction
•
•
Digital Inverse Sinc Filters
32-Bit DDR Flexible LVDS Input Data Bus
Digital data is input to the device through a 32-bit
wide LVDS data bus with on-chip termination. The
wide bus allows the processing of very high
bandwidth signals. The device includes a FIFO, data
pattern checker and parity test to ease the input
–
–
–
–
8 Sample Input FIFO
Supports Data Rates up to 625 MSPS
Data Pattern Checker
Parity Check
interface.
The
interface
also
allows
full
•
•
•
Temperature Sensor
Differential Scalable Output: 10mA to 30mA
196-Ball, 12x12mm BGA (GREEN / Pb-Free)
synchronization of multiple devices.
The device is characterized for operation over the
entire industrial temperature range of –40°C to 85°C
and is available in a 196-ball, 12x12mm, 0.8mm pitch
BGA package.
APPLICATIONS
•
•
•
Cellular Base Stations
Diversity Transmit
Wideband Communications
The DAC34H84 very low power, high bandwidth
support, superior crosstalk, high dynamic range and
features are an ideal fit for next generation
communication systems.
spacing
spacing
spacing
spacing
spacing
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
DACCLKP
EXTIO
BIASJ
Low Jitter
PLL
LVPECL
LVDS
Clock Distribution
1.2-V
Reference
DACCLKN
DATACLKP
AB
32-Bit NCO
Programmable
Delay
QMC
A-offset
cos
sin
DATACLKN
DAB15P
FIR0
FIR1
FIR2
FIR3
FIR4
LVDS
IOUTA1
IOUTA2
x
16-b
DACA
x2
x2
x2
x2
sin(x)
16
DAB15N
A-Group
Delay
•
•
•
•
•
•
•
•
•
AB-Channel
B-Group
Delay
59 taps
x2
23 taps
11 taps
11 taps
x2
9 taps
LVDS
LVDS
DAB0P
IOUTB1
IOUTB2
x
16-b
DACB
x2
x2
sin(x)
16
16
DAB0N
QMC
B-offset
DCD15P
DCD15N
CMIX Control
( nꢀFs/8)
DAC
Gain
2x–16x Interpolation
•
•
•
•
•
•
•
•
•
QMC
C-offset
FIR0
x2
FIR1
FIR2
FIR3
x2
FIR4
LVDS
LVDS
LVDS
LVDS
DCD0P
IOUTC1
IOUTC2
x
16-b
DACC
x2
x2
sin(x)
16
DCD0N
SYNCP
C-Group
Delay
CD-Channel
D-Group
Delay
SYNCN
59 taps
x2
23 taps
11 taps
11 taps
x2
9 taps
IOUTD1
IOUTD2
x
PARITYCDP
16-b
DACD
x2
x2
sin(x)
PARITYCDN
QMC
D-offset
cos
sin
ISTR/PARITYABP
CD
32-Bit NCO
ISTR/PARITYABN
OSTRP
Temp
Sensor
AVDD
LVPECL
Control Interface
OSTRN
B0460-01
2
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
PINOUT
ZAY Package
(Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
IOUT
AP
IOUT
AN
IOUT
BN
IOUT
BP
IOUT
CP
IOUT
CN
IOUT
DN
IOUT
DP
14
13
12
11
10
9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DAC
CLKP
CLK
VDD
CLK
VDD
IO
VDD2
LPF
PLL
GND EXTIO BIASJ
GND ALARM SDO
DAC
CLKN
PLL
AVDD AVDD
TEST
MODE
AVDD AVDD AVDD AVDD AVDD AVDD
GND SLEEP SDIO
RESET
DAC
VDD
DAC
VDD
DAC
VDD
DAC
VDD
DAC
VDD
DAC
VDD
GND
GND
GND
GND
AVDD
AVDD
GND
SDENB
B
OSTR OSTR
N
DAC
VDD
DAC
VDD
DAC
VDD
DAC
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND TXENA SCLK
P
SYNC SYNC
P
PARITY PARITY
GND
8
GND
GND
GND
GND
N
CDP
CDN
DAB
15P
DAB
15N
DIG
VDD
DIG
VDD
DCD
0P
DCD
0N
7
GND VFUSE
VFUSE GND
DAB
14P
DAB
14N
IO
GND
DIG
VDD
DIG
VDD
IO
DCD
1P
DCD
1N
6
GND
VDD
VDD
DAB
13P
DAB
13N
IO
GND
DIG
VDD
DIG
VDD
IO
VDD
IO
VDD
DIG
VDD
DIG
VDD
IO
DCD
2P
DCD
2N
5
GND
VDD
VDD
DAB
12P
DAB
12N
DAB
8P
DAB
6P
DAB
4P
DAB
2P
DAB
0P
DCD
15P
DCD
14P
DCD
12P
DCD
10P
DCD
8P
DCD
3P
DCD
3N
4
DAB
11P
DAB
11N
DAB
8N
DAB
6N
DAB
4N
DAB
2N
DAB
0N
DCD
15N
DCD
14N
DCD
12N
DCD
10N
DCD
8N
DCD
4P
DCD
4N
3
ISTR/
PARITY
ABP
DAB
10P
DAB
10N
DAB
7P
DAB
5P
DAB
3P
DAB
1P
DATA
CLKP
DCD
13P
DCD
11P
DCD
9P
DCD
7P
DCD
5P
DCD
5N
2
ISTR/
PARITY
ABN
DAB
9P
DAB
9N
DAB
7N
DAB
5N
DAB
3N
DAB
1N
DATA
CLKN
DCD
13N
DCD
11N
DCD
9N
DCD
7N
DCD
6P
DCD
6N
1
DAC Output
Clock Input
Data Input
3.3V Supply
1.2V Supply
(except for IOVDD2)
CMOS Pins
Miscellaneous
Sync/Parity Input
Ground
P0134-01
Copyright © 2011, Texas Instruments Incorporated
3
DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
D10, E11,
F11, G11,
H11, J11,
K11, L10
AVDD
I
Analog supply voltage. (3.3 V)
CMOS output for ALARM condition. The ALARM output functionality is defined through the config7
register. Default polarity is active low, but can be changed to active high via config0 alarm_out_pol
control bit.
ALARM
N12
O
Full-scale output current bias. For 30mA full-scale output current, connect 1.28kΩ to ground. Change
the full-scale output current through coarse_dac(3:0) in config3, bit<15:12>
BIASJ
H12
O
I
Internal clock buffer supply voltage. (1.2 V). It is recommended to isolate this supply from DIGVDD
and DACVDD.
CLKVDD
C12, K12
LVDS positive input data bits 0 through 15 for the AB-channel path. Internal 100 Ω termination
resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR).
A7, A6, A5,
A4, A3, A2,
A1, C4, C2,
D4, D2, E4,
E2, F4, F2,
G4
DAB15P is most significant data bit (MSB)
DAB0P is least significant data bit (LSB)
DAB[15..0]P
DAB[15..0]N
DCD[15..0]P
DCD[15..0]N
I
I
I
I
The order of the bus can be reversed via config2 revbus bit.
B7, B6, B5,
B4, B3, B2,
B1, C3, C1,
D3, D1, E3,
E1, F3, F1,
G3
LVDS negative input data bits 0 through 15 for the AB-channel path. (See DAB[15:0]P description
above)
H4, J4, J2,
K4, K2, L4,
L2, M4, M2,
N1, N2, N3,
N4, N5, N6,
N7
LVDS positive input data bits 0 through 15 for the CD-channel path. Internal 100 Ω termination
resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR).
DCD15P is most significant data bit (MSB)
DCD0P is least significant data bit (LSB)
The order of the bus can be reversed via config2 revbus bit.
H3, J3, J1,
K3, K1, L3,
L1, M3, M1,
P1, P2, P3,
P4, P5, P6,
P7
LVDS negative input data bits 0 through 15 for the CD-channel path. (See DCD[15:0]P description
above)
DACCLKP
DACCLKN
A12
A11
I
I
Positive external LVPECL clock input for DAC core with a self-bias.
Complementary external LVPECL clock input for DAC core. (see the DACCLKP description)
D9, E9, E10,
F10, G10,
H10, J10,
DAC core supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and
DIGVDD.
DACVDD
I
K10, K9, L9
LVDS positive input data clock. Internal 100 Ω termination resistor. Input data DAB[15:0]P/N and
DCD[15:0]P/N are latched on both edges of DATACLKP/N (Double Data Rate).
DATACLKP
DATACLKN
G2
G1
I
I
LVDS negative input data clock. (See DATACLKP description)
E5, E6, E7,
F5, J5, K5,
K6, K7
DIGVDD
EXTIO
I
Digital supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and DACVDD.
Used as external reference input when internal reference is disabled through config27 extref_ena =
G12
I/O ‘1’. Used as internal reference output when config27 extref_ena = ‘0’ (default). Requires a 0.1 μF
decoupling capacitor to AGND when used as reference output.
LVDS input strobe positive input. Internal 100 Ω termination resistor.
The main functions of this input are to sync the FIFO pointer, to provide a sync source to the digital
blocks, and/or to act as a parity input for the AB-data bus.
These functions are captured with the rising edge of DATACLKP/N. This signal should be
edge-aligned with DAB[15:0]P/N and DCD[15:0]P/N.
The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface
when setting the rev_interface bit in register config1.
ISTRP/
PARITYABP
H2
H1
I
I
ISTRN/
PARITYABN
LVDS input strope negative input. (See the ISTRP/PARITYABP description)
4
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
NAME
SLAS751A –MARCH 2011–REVISED JUNE 2011
PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
NO.
A10, A13,
A14, B10,
B11, B12,
B13, C5, C6,
C7, C8, C9,
C10, C13,
D8, D13,
D14, E8,
E12, E13,
F6, F7, F8,
F9, F12, F13,
G6, G7, G8,
G9, G13,
GND
I
These pins are ground for all supplies.
G14, H6, H7,
H8, H9, H13,
H14, J6, J7,
J8, J9, J12,
J13, K8, K13,
L8, L13, L14,
M5, M6, M7,
M8, M9,
M10, M11,
M12, M13,
N13, P13,
P14
IOUTAP
IOUTAN
IOUTBP
IOUTBN
IOUTCP
IOUTCN
IOUTDP
IOUTDN
B14
C14
F14
E14
J14
O
O
O
O
O
O
O
O
A-Channel DAC current output. Connect directly to ground if unused.
A-Channel DAC complementary current output. Connect directly to ground if unused.
B-Channel DAC current output. Connect directly to ground if unused.
B-Channel DAC complementary current output. Connect directly to ground if unused.
C-Channel DAC current output. Connect directly to ground if unused.
K14
N14
M14
C-Channel DAC complementary current output. Connect directly to ground if unused.
D-Channel DAC current output. Connect directly to ground if unused.
D-Channel DAC complementary current output. Connect directly to ground if unused.
D5, D6, G5,
H5, L5. L6
IOVDD
I
I
Supply voltage for all LVDS I/O. (3.3 V)
Supply voltage for all CMOS I/O. (1.8 to 3.3V) This supply can range from 1.8V to 3.3V to change the
input and output level of the CMOS I/O.
IOVDD2
LPF
L12
D12
I/O PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left unconnected.
Optional LVPECL output strobe positive input. This positive/negative pair is captured with the rising
OSTRP
OSTRN
A9
B9
I
edge of DACCLKP/N. It is used to sync the divided-down clocks and FIFO output pointer in Dual Sync
Sources Mode. If unused it can be left unconnected.
I
Optional LVPECL output strobe negative input. (See the OSTRP description)
Optional LVDS positive input parity bit for the CD-data bus. The PARITYCDP/N LVDS pair has an
internal 100 Ω termination resistor. If unused it can be left unconnected.
The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface
when setting the rev_interface bit in register config1.
PARITYCDP N8
PARITYCDN P8
I
I
I
I
I
Optional LVDS negative input parity bit for the CD-data bus.
PLL analog supply voltage. (3.3 V)
PLLAVDD
SCLK
C11, D11
P9
Serial interface clock. Internal pull-down.
SDENB
P10
Active low serial data enable, always an input to the DAC34H84. Internal pull-up.
Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional 4-pin mode. Internal
pull-down.
SDIO
P11
1/O
Uni-directional serial interface data in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode
(default).
SDO
P12
N11
O
I
SLEEP
Active high asynchronous hardware power-down input. Internal pull-down.
Copyright © 2011, Texas Instruments Incorporated
5
DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
LVDS SYNC positive input. Internal 100 Ω termination resistor. If unused it can be left unconnected.
The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface
when setting the rev_interface bit in register config1.
SYNCP
A8
I
SYNCN
B8
I
I
LVDS SYNC negative input.
RESETB
N10
Active low input for chip RESET. Internal pull-up.
Transmit enable active high input. Internal pull-down.
To enable analog output data transmission, set sif_txenable in register config3 to “1” or pull CMOS
TXENA
N9
I
TXENA pin to high.
To disable analog output, set sif_txenable to “0” and pull CMOS TXENA pin to low. The DAC output
is forced to midscale.
TESTMODE L11
VFUSE D7, L7
I
I
This pin is used for factory testing. Internal pull-down. Leave unconnected for normal operation.
Digital supply voltage. This supply pin is also used for factory fuse programming. Connect to
DACVDD or DIGVDD for normal operation.
ORDERING INFORMATION(1)
TA
–40°C to 85°C
ORDER CODE
DAC34H84IZAY
DAC34H84IZAYR
PACKAGE DRAWING/TYPE(2)
TRANSPORT MEDIA
Tray
QUANTITY
160
ZAY / 196 NFBGA
Tape and Reel
1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) MSL Peak Temperature: Level-3-260C-168 HR
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
UNIT
MIN
–0.5
–0.5
–0.5
–0.5
MAX
1.5
1.5
4
DACVDD, DIGVDD, CLKVDD
VFUSE
V
V
V
V
Supply voltage
range(2)
IOVDD, IOVDD2
AVDD, PLLAVDD
4
DAB[15..0]P/N, DCD[15..0]P/N, DATACLKP/N, ISTRP/N, PARITYCDP/N,
SYNCP/N
–0.5
–0.5
–0.5
IOVDD + 0.5
CLKVDD + 0.5
IOVDD2 + 0.5
V
V
V
DACCLKP/N, OSTRP/N
ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE,
TXENA
Pin voltage range(2)
IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/N
–1.0
–0.5
–0.5
AVDD + 0.5
V
V
EXTIO, BIASJ
LPF
AVDD + 0.5
PLLAVDD + 0.5
V
Peak input current (any input)
20
–30
85
mA
mA
°C
°C
Peak total input current (all inputs)
Operating free-air temperature range, TA: DAC34H84
Storage temperature range
–40
–65
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to GND.
6
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
THERMAL INFORMATION
DAC34H84
THERMAL METRIC(1)
BGA
UNITS
(196 ball) PINS
TJ
Maximum junction temperature
125
37.6
6.8
°C
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-case (bottom) thermal resistance(4)
Junction-to-board thermal resistance(5)
Junction-to-top characterization parameter(6)
Junction-to-board characterization parameter(7)
θJCtop
θJCbot
θJB
N/A
16.8
0.2
°C/W
ψJT
ψJB
16.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
Copyright © 2011, Texas Instruments Incorporated
7
DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS(1)
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Resolution
16
Bits
DC ACCURACY
DNL
INL
Differential nonlinearity
Integral nonlinearity
±2
±4
LSB
LSB
1 LSB = IOUTFS/216
ANALOG OUTPUT
Coarse gain linearity
±0.04
±0.001
±2
LSB
%FSR
%FSR
%FSR
%FSR
mA
Offset error
Mid code offset
With external reference
With internal reference
With internal reference
Gain error
±2
Gain mismatch
±2
Full scale output current
Output compliance range
Output resistance
10
20
30
–0.5
0.6
V
300
5
kΩ
Output capacitance
pF
REFERENCE OUTPUT
VREF
Reference output voltage
Reference output current(2)
1.2
V
100
nA
REFERENCE INPUT
VEXTIO Input voltage range
0.6
1.2 1.25
V
External Reference Mode
Input resistance
1
472
100
MΩ
kHz
pF
Small signal bandwidth
Input capacitance
TEMPERATURE COEFFICIENTS
Offset drift
±1
±15
±30
±8
ppm/°C
ppm/°C
ppm/°C
ppm/°C
with external reference
with internal reference
Gain drift
Reference voltage drift
POWER SUPPLY
AVDD, IOVDD, PLLAVDD
CLKVDD, DACVDD, DIGVDD
IOVDD2
3.14
1.14
1.71
3.3 3.46
1.2 1.26
3.3 3.45
V
V
V
PSRR
Power supply rejection ratio
DC tested
±0.25
%FSR/V
POWER CONSUMPTION
I(AVDD)
I(DIGVDD)
I(DACVDD)
I(CLKVDD)
P
Analog supply current(3)
135 165
740 820
mA
mA
mA
mA
mW
mA
mA
mA
mA
mW
MODE 1
Digital supply current
DAC supply current
Clock supply current
Power dissipation
Analog supply current(3)
Digital supply current
DAC supply current
Clock supply current
Power dissipation
fDAC = 1.25GSPS, 2x interpolation, Mixer on,
QMC on, invsinc on, PLL enabled, 20mA FS
output, IF = 200MHz
40
60
100 120
1500 1750
I(AVDD)
I(DIGVDD)
I(DACVDD)
I(CLKVDD)
P
125
740
45
MODE 2
fDAC = 1.25GSPS, 2x interpolation, Mixer on,
QMC on, invsinc on, PLL disabled, 20mA FS
output, IF = 200MHz
75
1440
(1) Measured differentially across IOUTP/N with 25 Ω each to GND.
(2) Use an external buffer amplifier with high impedance input to drive any external load.
(3) Includes AVDD, PLLAVDD, and IOVDD
8
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
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SLAS751A –MARCH 2011–REVISED JUNE 2011
ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS(1) (continued)
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted)
PARAMETER
Analog supply current(3)
Digital supply current
DAC supply current
Clock supply current
Power dissipation
Analog supply current(3)
Digital supply current
DAC supply current
Clock supply current
Power dissipation
Analog supply current(3)
Digital supply current
DAC supply current
Clock supply current
Power dissipation
Analog supply current(3)
Digital supply current
DAC supply current
Clock supply current
Power dissipation
TEST CONDITIONS
MIN
TYP MAX
120
370
25
UNIT
mA
mA
mA
mA
mW
mA
mA
mA
mA
mW
mA
mA
mA
mA
mW
mA
mA
mA
mA
mW
mA
mA
mA
mA
mW
°C
I(AVDD)
I(DIGVDD)
I(DACVDD)
I(CLKVDD)
P
MODE 3
fDAC = 625MSPS, 2x interpolation, Mixer on,
QMC on, invsinc off, PLL disabled, 20mA FS
output, IF = 200MHz
45
925
50
I(AVDD)
I(DIGVDD)
I(DACVDD)
I(CLKVDD)
P
MODE 4
750
40
fDAC = 1.25GSPS, 2x interpolation, Mixer on,
QMC on, invsinc on, PLL enabled, Channels
A/B/C/D output sleep, IF = 200MHz,
100
1240
40
I(AVDD)
I(DIGVDD)
I(DACVDD)
I(CLKVDD)
P
Mode 5
10
Power-Down mode: No clock, DAC on sleep
mode (clock receiver sleep),
Channels A/B/C/D output sleep, static data
pattern
5
15
150
140
360
30
I(AVDD)
I(DIGVDD)
I(DACVDD)
I(CLKVDD)
P
Mode 6
fDAC = 1GSPS, 2x interpolation, Mixer off,
QMC off, invsinc off, PLL enabled, 20mA FS
output, IF = 200MHz
90
1040
120
370
30
I(AVDD)
I(DIGVDD)
I(DACVDD)
I(CLKVDD)
P
Analog supply current(3)
Digital supply current
DAC supply current
Clock supply current
Power dissipation
Mode 7
fDAC = 1GSPS, 2x interpolation, Mixer off,
QMC off, invsinc off, PLL disabled, 20mA FS
output, IF = 200MHz
65
960
Operating Range
–40
25
85
Copyright © 2011, Texas Instruments Incorporated
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DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LVDS INPUTS: DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N, PARITYCDP/N(1)
Logic high differential input voltage
threshold
VA,B+
200
mV
Logic low differential input voltage
threshold
VA,B–
–200
mV
VCOM
ZT
Input Common Mode
Internal termination
1.0
85
1.2
110
2
1.6
V
Ω
135
CL
LVDS Input capacitance
Interleaved LVDS data transfer rate
Input data rate
pF
fINTERL
fDATA
1250 MSPS
625 MSPS
CLOCK INPUT (DACCLKP/N)
Duty cycle
40%
0.4
60%
V
Differential voltage(2)
DACCLKP/N Input Frequency
OUTPUT STROBE (OSTRP/N)
1.0
1250
MHz
MHz
V
fOSTR = fDACCLK / (n x 8 x Interp) where
n is any positive integer,
fDACCLK is DACCLK frequency in MHz
fDACCLK
/
fOSTR
Frequency
(8 x interp)
Duty cycle
50%
1.0
Differential voltage
0.4
CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA
0.7 x
IOVDD2
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
0.3 x
IOVDD2
IIH
IIL
CI
High-level input current
Low-level input current
CMOS Input capacitance
-40
-40
40
40
µA
µA
pF
2
IOVDD2 –
Iload = –100 μA
Iload = –2 mA
V
V
0.2
VOH
ALARM, SDO, SDIO
ALARM, SDO, SDIO
0.8 x
IOVDD2
Iload = 100 μA
0.2
0.5
V
V
VOL
Iload = 2 mA
DIGITAL INPUT TIMING SPECIFICATIONS
Timing LVDS inputs: DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N, PARITYCDP/N, double edge latching
Setup time, DAB[15:0]P/N,
DCD[15:0]P/N, ISTRP/N, SYNCP/N, ISTRP/N and SYNCP/N reset latched
ts(DATA)
150
ps
ps
and PARITYCDP/N, valid to either
edge of DATACLKP/N
only on rising edge of DATACLKP/N
Hold time, DAB[15:0]P/N,
DCD[15:0]P/N, ISTRP/N, SYNCP/N ISTRP/N and SYNCP/N reset latched
and PARITYCDP/N valid after either only on rising edge of DATACLKP/N
edge of DATACLKP/N
th(DATA)
400
t(ISTR_SYNC)
t(align)
ISTRP/N and SYNCP/N pulse width fDATACLK is DATACLK frequency in MHz
Maximum offset between
1/2fDATACLK
ns
ps
DATACLKP/N and DACCLKP/N
rising edges
FIFO Bypass Mode only
±300
(1) See LVDS INPUTS section for terminology.
(2) Driving the clock input with a differential voltage lower than 1 V may result in degraded performance.
10
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
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SLAS751A –MARCH 2011–REVISED JUNE 2011
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING(3)
Setup time, OSTRP/N valid to rising
edge of DACCLKP/N
ts(OSTR)
–100
ps
ps
Hold time, OSTRP/N valid after
th(OSTR)
500
rising edge of DACCLKP/N
(4)
TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING
Setup time, SYNCP/N valid to rising
ts(SYNC_PLL)
200
300
ps
ps
edge of DACCLKP/N
Hold time, SYNCP/N valid after
th(SYNC_PLL)
rising edge of DACCLKP/N
TIMING SERIAL PORT
Setup time, SDENB to rising edge
ts(SDENB)
of SCLK
20
10
5
ns
ns
ns
Setup time, SDIO valid to rising
edge of SCLK
ts(SDIO)
Hold time, SDIO valid to rising edge
of SCLK
th(SDIO)
Register config6 read (temperature
sensor read)
1
µs
ns
ns
ns
t(SCLK)
Period of SCLK
All other registers
100
Data output delay after falling edge
of SCLK
td(Data)
tRESET
10
25
Minimum RESETB pulsewidth
(3) OSTR is required in Dual Sync Sources mode. In order to minimize the skew it is recommended to use the same clock distribution
device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the DAC34H84 devices in the system.
Swap the polarity of the DACCLK outputs with respect to the OSTR ones to establish proper phase relationship.
(4) SYNC is required to synchronize the PLL circuit in mulitple devices. The SYNC signal must meet the timing relationship with respect to
the reference clock (DACCLKP/N) of the on-chip PLL circuit.
Copyright © 2011, Texas Instruments Incorporated
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DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS / COMMENTS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT(1)
fDAC
Maximum DAC rate
1250
MSPS
ns
ts(DAC)
Output settling time to 0.1%
Transition: Code 0x0000 to 0xFFFF
10
2
DAC outputs are updated on the falling edge of DAC
clock. Does not include Digital Latency (see below).
tpd
Output propagation delay
ns
tr(IOUT)
tf(IOUT)
Output rise time 10% to 90%
Output fall time 90% to 10%
220
220
ps
ps
No interpolation, FIFO on, Mixer off, QMC off, Inverse
sinc off
128
2x Interpolation
216
376
726
1427
24
4x Interpolation
DAC clock
cycles
8x Interpolation
Digital Latency
16x Interpolation
Fine Mixer
QMC
16
Inverse Sinc
20
DAC Wake-up Time from Deep Sleep
DAC Deep Sleep Time
IOUT current settling to 1% of IOUTFS
IOUT current settling to less than 1% of IOUTFS
90
Power-up
Time
μs
90
AC PERFORMANCE(2)
fDAC = 1.25 GSPS, fOUT = 20 MHz
fDAC = 1.25 GSPS, fOUT = 50 MHz
fDAC = 1.25 GSPS, fOUT = 70 MHz
fDAC = 1.25 MSPS, fOUT = 30 ± 0.5 MHz
fDAC = 1.25 GSPS, fOUT = 50 ± 0.5 MHz
fDAC = 1.25 GSPS, fOUT = 100 ± 0.5 MHz
fDAC = 1.25 GSPS, fOUT = 10 MHz
fDAC = 1.25 GSPS, fOUT = 80 MHz
fDAC = 1.2288 GSPS, fOUT = 30.72 MHz
fDAC = 1.2288 GSPS, fOUT = 153.6 MHz
fDAC = 1.2288 GSPS, fOUT = 30.72 MHz
fDAC = 1.2288 GSPS, fOUT = 153.6 MHz
fDAC = 1.25 GSPS, fOUT = 10 MHz
73
70
Spurious free dynamic range
(0 to fDAC/2) Tone at 0 dBFS
SFDR
dBc
66
87
Third-order two-tone intermodulation
distortion
Each tone at –12 dBFS
IMD3
NSD
85
dBc
78
Noise Spectral Density(3)
Tone at 0dBFS
160
155
77
dBc/Hz
Adjacent channel leakage ratio, single
carrier
74
ACLR(3)
dBc
dBc
82
Alternate channel leakage ratio, single
carrier
80
Channel Isolation
95
(1) Measured single ended into 50 Ω load.
(2) 4:1 transformer output termination, 50 Ω doubly terminated load
(3) Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF, PAR = 12dB. TESTMODEL 1, 10 ms
12
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
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SLAS751A –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS
All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 2x interpolation, NCO enabled, Mixer Gain disabled, QMC
enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer
(unless otherwise noted)
6
5
5
4
4
3
3
2
2
1
1
0
0
−1
−2
−3
−4
−5
−6
−1
−2
−3
−4
−5
0
10k
20k
30k
Code
40k
50k
60k
0
10k
20k
30k
Code
40k
50k
60k
Figure 1. Integral Nonlinearity
Figure 2. Differential Nonlinearity
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
0 dBFS
−6 dBFS
−12 dBFS
0 dBFS
−6 dBFS
−12 dBFS
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Output Frequency (MHz)
Output Frequency (MHz)
Figure 3. SFDR vs Output Frequency Over Input Scale
Figure 4. Second Harmonic Distortion vs Output
Frequency Over Input Scale
100
100
90
80
70
60
50
40
30
fDATA = 625 MSPS, 1x Interpolation
fDATA = 625 MSPS, 2x Interpolation
fDATA = 312.5 MSPS, 4x Interpolation
fDATA = 156.25MSPS, 8x Interpolation
0 dBFS
−6 dBFS
−12 dBFS
90
80
fDATA = 78.125MSPS, 16x Interpolation
70
60
50
40
30
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Output Frequency (MHz)
Output Frequency (MHz)
Figure 5. Third Harmonic Distortion vs Output Frequency
Over Input Scale
Figure 6. SFDR vs Output Frequency Over Interpolation
Copyright © 2011, Texas Instruments Incorporated
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DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 2x interpolation, NCO enabled, Mixer Gain disabled, QMC
enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer
(unless otherwise noted)
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
fDAC = 600 MSPS
fDAC = 800 MSPS
fDAC = 1000 MSPS
fDAC = 1250 MSPS
IOUTFS = 10 mA w/ 4:1 Transformer
IOUTFS = 20 mA w/ 4:1 Transformer
IOUTFS = 30 mA w/ 2:1 Transformer
0
100
200
300
400
500
600
0
50
100
150
200
250
300
350
400
Output Frequency (MHz)
Output Frequency (MHz)
Figure 7. SFDR vs Output Frequency Over fDAC
Figure 8. SFDR vs Output Frequency Over IOUTFS
10
0
10
NCO Bypassed
QMC Bypassed
fDAC = 1250 MSPS
fOUT = 20 MHz
NCO Bypassed
QMC Bypassed
fDAC = 1250 MSPS
fOUT = 70 MHz
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−10
−20
−30
−40
−50
−60
−70
−80
−90
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Frequency (MHz)
Frequency (MHz)
Figure 9. Single Tone Spectral Plot
Figure 10. Single Tone Spectral Plot
10
0
10
0
fDAC = 1250 MSPS
fOUT = 150 MHz
fDAC = 1250 MSPS
fOUT = 200 MHz
−10
−20
−30
−40
−50
−60
−70
−80
−90
−10
−20
−30
−40
−50
−60
−70
−80
−90
0
100
200
300
400
500
600
10
110
210
310
410
510
610
Frequency (MHz)
Frequency (MHz)
Figure 11. Single Tone Spectral Plot
Figure 12. Single Tone Spectral Plot
14
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
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SLAS751A –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 2x interpolation, NCO enabled, Mixer Gain disabled, QMC
enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer
(unless otherwise noted)
10
0
100
90
80
70
60
50
40
30
PLL Enabled w/ PFD of 78.125 MHz
fDAC = 1250 MSPS
fOUT = 200 MHz
0 dBFS
−6 dBFS
−12 dBFS
−10
−20
−30
−40
−50
−60
−70
−80
−90
10
110
210
310
410
510
610
0
100
200
300
400
500
600
Frequency (MHz)
Output Frequency (MHz)
Figure 13. Single Tone Spectral Plot
Figure 14. IMD3 vs Output Frequency Over Input Scale
100
90
80
70
60
50
40
30
100
fDAC = 600 MSPS
fDAC = 800 MSPS
fDAC = 1000 MSPS
fDAC = 1250 MSPS
90
80
70
60
50
40
30
fDATA = 625 MSPS, 1x Interpolation
fDATA = 625 MSPS, 2x Interpolation
fDATA = 312.5 MSPS, 4x Interpolation
fDATA = 156.25 MSPS, 8x Interpolation
fDATA = 78.125 MSPS, 16x Interpolation
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Output Frequency (MHz)
Output Frequency (MHz)
Figure 15. IMD3 vs Output Frequency Over Interpolation
Figure 16. IMD3 vs Output Frequency Over fDAC
100
90
80
70
60
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
NCO Bypassed
QMC Bypassed
fDAC = 1250 MSPS
fOUT = 70 MHz
Tone Spacing = 1 MHz
50
IOUTFS = 10 mA w/ 4:1 Transformer
IOUTFS = 20 mA w/ 4:1 Transformer
IOUTFS = 30 mA w/ 2:1 Transformer
40
30
0
50
100
150
200
250
300
350
400
65
66
67
68
69
70
71
72
73
74
75
Output Frequency (MHz)
Frequency (MHz)
Figure 17. IMD3 vs Output Frequency Over IOUTFS
Figure 18. Two Tone Spectral Plot
Copyright © 2011, Texas Instruments Incorporated
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DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 2x interpolation, NCO enabled, Mixer Gain disabled, QMC
enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer
(unless otherwise noted)
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
170
165
160
155
150
145
140
135
130
fDAC = 1250 MSPS
fOUT = 200 MHz
Tone Spacing = 1 MHz
0 dBFS
−6 dBFS
−12 dBFS
195 196 197 198 199 200 201 202 203 204 205
Frequency (MHz)
0
100
200
300
400
500
600
Output Frequency (MHz)
Figure 19. Two Tone Spectral Plot
Figure 20. NSD vs Output Frequency Over Input Scale
170
170
fDATA = 625 MSPS, 1x Interpolation
fDATA = 625 MSPS, 2x Interpolation
fDATA = 312.5 MSPS, 4x Interpolation
fDATA = 156.25 MSPS, 8x Interpolation
fDATA = 78.125 MSPS, 16x Interpolation
fDAC = 600 MSPS
fDAC = 800 MSPS
fDAC = 1000 MSPS
fDAC = 1250 MSPS
165
160
155
150
145
140
135
130
165
160
155
150
145
140
135
130
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Output Frequency (MHz)
Output Frequency (MHz)
Figure 21. NSD vs Output Frequency Over Interpolation
Figure 22. NSD vs Output Frequency Over fDAC
170
170
165
160
155
150
145
140
135
130
IOUTFS = 10 mA w/ 4:1 Transformer
IOUTFS = 20 mA w/ 4:1 Transformer
IOUTFS = 30 mA w/ 2:1 Transformer
PLL Bypassed
PLL Enabled w/ PFD of 78.125 MHz
165
160
155
150
145
140
135
130
0
50
100
150
200
250
300
350
400
0
100
200
300
400
500
600
Output Frequency (MHz)
Output Frequency (MHz)
Figure 23. NSD vs Output Frequency Over IOUTFS
Figure 24. NSD vs Output Frequency Over Clocking
Options
16
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 2x interpolation, NCO enabled, Mixer Gain disabled, QMC
enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer
(unless otherwise noted)
85
80
75
70
65
60
55
85
80
75
70
65
60
55
PLL Disabled
PLL Enabled
PLL Disabled
PLL Enabled
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Output Frequency (MHz)
Output Frequency (MHz)
Figure 25. Single Carrier WCDMA ACLR (Adjacent) vs
Output Frequency Over Clocking Options
Figure 26. Single Carrier WCDMA ACLR (Alternate) vs
Output Frequency Over Clocking Options
2x Interpolation, 0 dBFS
fDAC = 1228.8 MSPS
2x Interpolation, 0 dBFS
fDAC = 1228.8 MSPS
fOUT = 70 MHz
fOUT = 120 MHz
Figure 27. Single Carrier W-CDMA Test Model 1
Figure 28. Single Carrier W-CDMA Test Model 1
2x Interpolation, 0 dBFS
fDAC = 1228.8 MSPS
2x Interpolation, 0 dBFS
fDAC = 1228.8 MSPS
fOUT = 70 MHz
fOUT = 200 MHz
Figure 29. Single Carrier W-CDMA Test Model 1
Figure 30. Four Carrier W-CDMA Test Model 1
Copyright © 2011, Texas Instruments Incorporated
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DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 2x interpolation, NCO enabled, Mixer Gain disabled, QMC
enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer
(unless otherwise noted)
2x Interpolation, 0 dBFS
fDAC = 1228.8 MSPS
2x Interpolation, 0 dBFS
fDAC = 1228.8 MSPS
fOUT = 200 MHz
fOUT = 120 MHz
Figure 31. Four Carrier W-CDMA Test Model 1
Figure 32. Four Carrier W-CDMA Test Model 1
2x Interpolation, 0 dBFS
fDAC = 1228.8 MSPS
2x Interpolation, 0 dBFS
fDAC = 1228.8 MSPS
fOUT = 140 MHz
fOUT = 240 MHz
Figure 33. 10 MHz Single Carrier LTE Test Model 3.1
Figure 34. 10 MHz Single Carrier LTE Test Model 3.1
2x Interpolation, 0 dBFS
fDAC = 1228.8 MSPS
2x Interpolation, 0 dBFS
fDAC = 1228.8 MSPS
fOUT = 140 MHz
fOUT = 240 MHz
Figure 35. 20 MHz Single Carrier LTE Test Model 3.1
Figure 36. 20 MHz Single Carrier LTE Test Model 3.1
18
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 2x interpolation, NCO enabled, Mixer Gain disabled, QMC
enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer
(unless otherwise noted)
1400
1200
1000
800
1400
1200
1000
800
1x Interpolation
2x Interpolation
4x Interpolation
8x Interpolation
16x Interpolation
1x Interpolation
2x Interpolation
4x Interpolation
8x Interpolation
16x Interpolation
600
600
Bandbase Input = 5 MHz
NCO Disabled
QMC Disabled
Bandbase Input = 0 MHz
NCO Enabled w/ 5 MHz Mixing
QMC Enabled
400
400
CMIX Disabled
200
200
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
fDAC (MSPS)
fDAC (MSPS)
Figure 37. Power Consumption vs fDAC Over Interpolation
Figure 38. Power Consumption vs fDAC Over Interpolation
160
700
NCO Enabled
QMC Enabled
1x Interpolation
2x Interpolation
4x Interpolation
8x Interpolation
16x Interpolation
Bandbase Input = 5 MHz
NCO Disabled
QMC Disabled
140
120
100
80
600
500
400
300
200
100
0
CMIX Disabled
60
40
20
0
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
fDAC (MSPS)
fDAC (MSPS)
Figure 39. Power Consumption vs fDAC Over Digital
Processing Functions
Figure 40. DIGVDD Current vs fDAC Over Interpolation
700
160
1x Interpolation
2x Interpolation
4x Interpolation
8x Interpolation
16x Interpolation
NCO Enabled
QMC Enabled
140
120
100
80
600
500
400
300
200
100
0
60
40
Bandbase Input = 0 MHz
NCO Enabled w/ 5 MHz Mixing
QMC Enabled
20
0
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
fDAC (MSPS)
fDAC (MSPS)
Figure 41. DIGVDD Current vs fDAC Over Interpolation
Figure 42. DIGVDD Current vs fDAC Over Digital
Processing Functions
Copyright © 2011, Texas Instruments Incorporated
19
DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltage, fDAC = 1250 MSPS, 2x interpolation, NCO enabled, Mixer Gain disabled, QMC
enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer
(unless otherwise noted)
40
35
30
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
0
0
0
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
fDAC (MSPS)
fDAC (MSPS)
Figure 43. DACVDD Current vs fDAC
Figure 44. CLKVDD Current vs fDAC
140
120
100
80
120
110
100
90
Channel A
Channel B
80
60
70
40
60
20
50
Channel A/B Off
Channel C/D Active
0
40
200
400
600
800
1000
1200
0
100
200
300
400
500
600
Output Frequency (MHz)
fDAC (MSPS)
Figure 45. AVDD Current vs fDAC
Figure 46. Channel Isolation vs Output Frequency
120
110
100
90
110
Channel C
Channel D
Channel A
Channel B
Channel C
Channel D
100
90
80
70
60
50
40
30
20
10
0
80
70
60
fDAC = 614.4 MSPS
fOUT = 138.4 MHz
50
Channel C/D Off
Channel A/B Active
40
100 200
300
400
500
600
0
32
64
96
128
160
192
224
256
Output Frequency (MHz)
Step Code
Figure 47. Channel Isolation vs Output Frequency
Figure 48. Group Delay vs Step Code
20
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
DEFINITION OF SPECIFICATIONS
Adjacent Carrier Leakage Ratio (ACLR): Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a
3.84MHz bandwidth at a 5MHz offset from the carrier with a 12dB peak-to-average ratio.
Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the
ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.
Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB
change in the digital input code.
Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the
value at ambient (25°C) to values over the full operating temperature range.
Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output
current and the ideal full-scale output current.
Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output,
determined by a straight line drawn from zero scale to full scale.
Intermodulation Distortion (IMD3): The two-tone IMD3 is defined as the ratio (in dBc) of the 3rd-order
intermodulation distortion product to either fundamental output tone.
Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C,
from the value at ambient (25°C) to values over the full operating temperature range.
Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output
current and the ideal mid-scale output current.
Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the
current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting
distortion performance.
Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius
from value at ambient (25°C) to values over the full operating temperature range.
Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the
output signal and the peak spurious signal within the first Nyquist zone.
Noise Spectral Density (NSD): Defined as the difference of power (in dBc) between the output tone signal
power and the noise floor of 1Hz bandwidth within the first Nyquist zone.
SERIAL INTERFACE
The serial port of the DAC34H84 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of DAC34H84. It is compatible with most synchronous transfer formats and can be configured
as a 3 or 4 pin interface by sif4_ena in register config2. In both configurations, SCLK is the serial interface input
clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in
and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input into the device
with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte
is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit
address to be accessed. Table 1 indicates the function of each bit in the instruction cycle and is followed by a
detailed description of each bit. The data transfer cycle consists of two bytes
Table 1. Instruction Byte of the Serial Interface
MSB
7
LSB
0
Bit
6
5
4
3
2
1
Description
R/W
A6
A5
A4
A3
A2
A1
A0
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DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
R/W
Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from DAC34H84 and a low indicates a write operation to DAC34H84.
[A6 : A0]
Identifies the address of the register to be accessed during the read or write operation.
22
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
Figure 49 shows the serial interface timing diagram for a DAC34H84 write operation. SCLK is the serial interface clock input to DAC34H84. Serial data
enable SDENB is an active low input to DAC34H84. SDIO is serial data in. Input data to DAC34H84 is clocked on the rising edges of SCLK.
Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
SDIO
rwb
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
tS(SDENB)
t(SCLK)
SDENB
SCLK
SDIO
tH(SDIO)
tS(SDIO)
T0521-01
Figure 49. Serial Interface Write Timing Diagram
Copyright © 2011, Texas Instruments Incorporated
23
DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
Figure 50 shows the serial interface timing diagram for a DAC34H84 read operation. SCLK is the serial interface clock input to DAC34H84. Serial data
enable SDENB is an active low input to DAC34H84. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO is data out from the
DAC34H84 during the data transfer cycle, while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from the DAC34H84 during the
data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the final falling edge of SCLK until the rising edge of SDENB when it
will 3-state.
Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
SDIO
SDO
rwb
A6
A5
A4
A3
A2
A1
A0
D15
D15
D14
D14
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SDENB
SCLK
SDIO
SDO
Data n
Data n – 1
td(Data)
T0522-01
Figure 50. Serial Interface Read Timing Diagram
24
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
Table 2. Register Map(1)
(MSB)
Bit 15
(LSB)
Bit 0
Name
Address
Default
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
fifo_ena
dacA_
Bit 6
reserved
dacB_
Bit 5
reserved
dacC_
Bit 4
Bit 3
Bit 2
Bit 1
qmc_
qmc_
qmc_
corrAB_
ena
qmc_
corrCD_
ena
alarm_out_ alarm_out clkdiv_sync_ invsincAB_
ena
invsincCD_
ena
config0
0x00
0x049C
offsetAB_ offsetCD_
ena
interp(3:0)
pol
ena
ena
ena
single_
parity_
ena
dual_
parity_
ena
alarm_
2away_
ena
alarm_
1away_
ena
alarm_
collision_
ena
64cnt_
ena
iotest_
ena
oddeven_
parity
rev_
interface
dacD_
config1
config2
0x01
0x02
0x040E
0x7000
reserved
reserved
reserved
complement complement complement complement
dacclk
dataclk
collision_
reserved
reserved
reserved
reserved
reserved
sif4_ena
mixer_ena
mixer_gain
nco_ena
reserved
revbus
reserved
twos
reserved
gone_ena gone_ena gone_ena
config3
config4
0x03
0x04
0xF000
NA
coarse_dac(3:0)
reserved
sif_txenable
iotest_results(15:0)
alarm_
from_
zerochk
alarm_
from_
iotest
alarm_
dacclk_
gone
alarm_
dataclk_
gone
alarm_
output_
gone
alarm_
Bparity
alarm_
from_pll
alarm_
Aparity
alarm_
Cparity
alarm_
Dparity
config5
0x05
NA
reserved
alarms_from_fifo(2:0)
reserved
reserved
reserved
config6
config7
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
NA
tempdata(7:0)
reserved
reserved
0xFFFF
0x0000
0x8000
0x0000
0x0000
0x0400
0x0400
0x0400
0x0400
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
alarms_mask(15:0)
config8
reserved
reserved
fifo_offset(2:0)
reserved
reserved
qmc_offsetA(12:0)
qmc_offsetB(12:0)
qmc_offsetC(12:0)
qmc_offsetD(12:0)
config9
config10
config11
config12
config13
config14
config15
config16
config17
config18
config19
config20
config21
config22
config23
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
qmc_gainA(10:0)
qmc_gainB(10:0)
qmc_gainC(10:0)
qmc_gainD(10:0)
cmix(3:0)
reserved
reserved
reserved
output_delayAB(1:0)
output_delayCD(1:0)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
qmc_phaseAB(11:0)
qmc_phaseCD(11:0)
phase_offsetAB(15:0)
phase_offsetCD(15:0)
phase_addAB(15:0)
phase_addAB(31:16)
phase_addCD(15:0)
phase_addCD(31:16)
pll_
config24
0x18
NA
reserved
reserved
pll_reset ndivsync_
ena
pll_ena
reserved
pll_cp(1:0)
pll_p(2:0)
pll_lfvolt(2:0)
sleepC
config25
config26
0x19
0x1A
0x0440
0x0020
pll_m(7:0)
pll_n(3:0)
pll_sleep
pll_vcoitune(2:0)
reserved
bias_
sleep
tsense_
sleep
clkrecv_
sleep
pll_vco(5:0)
reserved
reserved
reserved
reserved
sleepA
sleepB
sleepD
extref_
ena
fuse_
sleep
config27
0x1B
0x0000
reserved
reserved
reserved
reserved
reserved
reserved
config28
config29
config30
0x1C
0x1D
0x1E
0x0000
0x0000
0x1111
reserved
reserved
reserved
reserved
syncsel_qmoffsetAB(3:0)
syncsel_qmoffsetCD(3:0)
syncsel_qmcorrAB(3:0)
syncsel_qmcorrCD(3:0)
(1) Unless otherwise noted, all reserved registers should be programmed to default values.
Copyright © 2011, Texas Instruments Incorporated
25
DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
Table 2. Register Map(1) (continued)
(MSB)
Bit 15
(LSB)
Bit 0
Name
Address
0x1F
Default
0x1140
0x2400
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
config31
config32
syncsel_mixerAB(3:0)
syncsel_fifoin(3:0)
syncsel_mixerCD(3:0)
syncsel_fifoout(3:0)
syncsel_nco(3:0)
syncsel_fifo_input
sif_sync
reserved
clkdiv_
sync_sel
0x20
reserved
config33
config34
config35
config36
config37
config38
config39
config40
config41
config42
config43
config44
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x0000
0x1B1B
0xFFFF
0x0000
0x7A7A
0xB6B6
0xEAEA
0x4545
0x1A1A
0x1616
0xAAAA
0xC6C6
reserved
pathA_in_set(1:0)
pathB_in_set(1:0)
pathC_in_set(1:0)
clkdly(2:0)
pathD_in_set(1:0)
DACA_out_set(1:0)
sleep_cntl(15:0)
DACB_out_set(1:0)
reserved
DACC_out_set(1:0)
DACD_out_set(1:0)
datadly(2:0)
iotest_pattern0
iotest_pattern1
iotest_pattern2
iotest_pattern3
iotest_pattern4
iotest_pattern5
iotest_pattern6
iotest_pattern7
ostrtodig_
sel
config45
0x2D
0x0004
reserved
ramp_ena
reserved
sifdac_ena
config46
config47
config48
version
0x2E
0x2F
0x30
0x7F
0x0000
0x0000
0x0000
0x5408
grp_delayA(7:0)
grp_delayC(7:0)
grp_delayB(7:0)
grp_delayD(7:0)
sifdac(15:0)
reserved
reserved
reserved
reserved
deviceid(1:0)
versionid(2:0)
26
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
REGISTER DESCRIPTIONS
Register name: config0 – Address: 0x00, Default: 0x049C
Register
Name
Default
Value
Address
Bit
Name
Function
config0
0x00
15
qmc_offsetAB_ena When set, the digital Quadrature Modulator Correction (QMC) offset
correction for the AB data path is enabled.
0
14
13
12
qmc_offsetCD_ena When set, the digital Quadrature Modulator Correction (QMC) offset
correction for the CD data path is enabled.
0
qmc_corrAB_ena
When set, the QMC phase and gain correction circuitry for the AB
data path is enabled.
0
qmc_corrCD_ena
When set, the QMC phase and gain correction circuitry for the CD
data path is enabled.
0
11:8 interp(3:0)
These bits define the interpolation factor
0100
interp
0000
0001
0010
0100
1000
Interpolation Factor
1x
2x
4x
8x
16x
7
fifo_ena
When set, the FIFO is enabled. When the FIFO is disabled
DACCCLKP/N and DATACLKP/N must be aligned to within
t(align) (not recommended).
1
6
5
4
Reserved
Reserved for factory use.
Reserved for factory use.
0
0
1
Reserved
alarm_out_ena
When set, the ALARM pin becomes an output. When cleared, the
ALARM pin is 3-stated.
3
2
alarm_out_pol
This bit changes the polarity of the ALARM signal.
MM 0: Negative logic
MM 1: Positive logic
1
1
clkdiv_sync_ena
When set, enables the syncing of the clock divider and the FIFO
output pointer using the sync source selected by register config32.
The internal divided-down clocks will be phase aligned after syncing.
Refer to the Power-Up Sequence section for more detail.
1
0
invsincAB_ena
invsincCD_ena
When set, the inverse sinc filter for the AB data path is enabled.
When set, the inverse sinc filter for the CD data path is enabled.
0
0
Copyright © 2011, Texas Instruments Incorporated
27
DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
Register name: config1 – Address: 0x01, Default: 0x040E
Register
www.ti.com
Default
Value
Address
Bit
Name
Function
Name
config1
0x01
15
iotest_ena
When set, enables the data pattern checker test. The outputs are
0
deactivated regardless of the state of TXENA and sif_txenable.
14
13
12
Reserved
Reserved
64cnt_ena
Reserved for factory use.
Reserved for factory use.
0
0
0
When set, enables resetting of the alarms after 64 good samples
with the goal of removing unnecessary errors. For instance, when
checking setup/hold through the pattern checker test, there may
initially be errors. Setting this bit removes the need for a SIF write to
clear the alarm register.
11
oddeven_parity
Selects between odd and even parity check
MM 0: Even parity
0
MM 1: Odd parity
10
9
single_parity_ena
dual_parity_ena
rev_interface
When set, enables parity checking of each input word using the 1
PARITYP/N parity input. It should match the oddeven_parity
register setting.
1
0
0
When set, enables parity checking using the ISTR signal to 0 source
the parity bit. The parity bit should match the oddeven_parity
register setting.
8
When set, the PARITY, SYNC, and ISTR inputs are rotated to allow
complete reversal of the data interface when setting the
rev_interface bit.
When rev_interface = “1”, the following changes occurs
MM 1. SYNCP/N becomes ISTRP/N
MM 2. PARITYP/N becomes SYNCP/N
MM 3. ISTRP/N becomes PARITYP/N
7
6
5
4
3
2
1
0
dacA_complement
dacB_complement
dacC_complement
dacD_complement
alarm_2away_ena
alarm_1away_ena
alarm_collision_ena
Reserved
When set, the DACA output is complemented. This allows to
effectively change the + and – designations of the LVDS data lines.
0
0
0
0
1
1
1
0
When set, the DACB output is complemented. This allows to
effectively change the + and – designations of the LVDS data lines.
When set, the DACC output is complemented. This allows to
effectively change the + and – designations of the LVDS data lines.
When set, the DACD output is complemented. This allows to
effectively change the + and – designations of the LVDS data lines.
When set, the alarm from the FIFO indicating the write and read
pointers being 2 away is enabled.
When set, the alarm from the FIFO indicating the write and read
pointers being 1 away is enabled.
When set, the alarm from the FIFO indicating a collision between the
write and read pointers is enabled.
Reserved for factory use.
28
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DAC34H84
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SLAS751A –MARCH 2011–REVISED JUNE 2011
Register name: config2 – Address: 0x02, Default: 0x7000
Register
Name
Default
Value
Address
Bit
Name
Reserved
Function
config2
0x02
15
14
Reserved for factory use.
0
1
dacclkgone_ena
dataclkgone_ena
collisiongone_ena
When set, the DACCLK-gone signal from the clock monitor circuit can
be used to shut off the DAC outputs. The corresponding alarms,
alarm_dacclk_gone and alarm_output_gone, must not be masked
(i.e.Config7, bit <10> and bit <8> must set to "0").
13
12
When set, the DATACLK-gone signal from the clock monitor circuit
can be used to shut off the DAC outputs. The corresponding alarms,
alarm_dataclk_gone and alarm_output_gone, must not be masked
(i.e.Config7, bit <9> and bit <8> must set to "0").
1
1
When set, the FIFO collision alarms can be used to shut off the DAC
outputs. The corresponding alarms, alarm_fifo_collision and
alarm_output_gone, must not be masked (i.e.Config7, bit <13> and
bit <8> must set to "0").
11
10
9
Reserved
Reserved
Reserved
Reserved
sif4_ena
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
0
0
0
0
0
8
7
When set, the serial interface (SIF) is a 4 bit interface, otherwise it is
a 3 bit interface.
6
5
4
3
mixer_ena
mixer_gain
nco_ena
revbus
When set, the mixer block is enabled.
0
0
0
0
When set, a 6dB gain is added to the mixer output.
When set, the NCO is enabled. This is not required for coarse mixing.
When set, the input bits for the data bus are reversed. MSB becomes
LSB.
2
1
Reserved
twos
Reserved for factory use.
0
0
When set, the input data format is expected to be 2’s complement.
When cleared, the input is expected to be offset-binary.
0
Reserved
Reserved for factory use.
0
Register name: config3 – Address: 0x03, Default: 0xF000
Register
Name
Default
Value
Address
Bit
Name
Function
config3
0x03
15:12 coarse_dac(3:0)
Scales the output current in 16 equal steps.
1111
VEXTIO
IFS
=
´ 2´ coarse _ dac +1
(
)
RBIAS
11:8
7:1
0
Reserved
Reserved
sif_txenable
Reserved for factory use.
0000
0000000
0
Reserved for factory use.
When set, the internal value of TXENABLE is set to “1”.
To enable analog output data transmission, set sif_txenable to “1” or
pull CMOS TXENA pin (N9) to high. To disable analog output, set
sif_txenable to “0” and pull CMOS TXENA pin (N9) to low.
Copyright © 2011, Texas Instruments Incorporated
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DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
Register name: config4 – Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)
Register
Name
Default
Value
Address
Bit
Name
Function
config4
0x04
15:0
iotest_results(15:0)
Bits in iotest_results with logic value of “1” tell which bit in either DAB[15:0]
bus or DCD[15:0] bus failed during the pattern checker test.
No RESET
Value
iotest_results(15:8) correspond to the data bits on both DAB[15:8] and
DCD[15:8].
iotest_results(7:0) correspond to the data bits on both DAB[7:0] and DCD[7:0].
Register name: config5 – Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO
CLEAR)
Register Address
Name
Default
Value
Bit
Name
Function
config5
0x05
15
alarm_from_zerochk
This alarm indicates the 8-bit FIFO write pointer address has an all
zeros patterns. Due to pointer address being a shift register, this is
not a valid address and will cause the write pointer to be stuck until
the next sync. This error is typically caused by timing error or
improper power start-up sequence. If this alarm is asserted,
resynchronization of FIFO is necessary. Refer to the Power-Up
Sequence section for more detail.
NA
14
Reserved
Reserved for factory use.
NA
NA
13:11 alarms_from_fifo(2:0)
Alarm indicating FIFO pointer collisions and nearness:
MM 000: All fine
MM 001: Pointers are 2 away
MM 01x: Pointers are 1 away
MM 1xx: FIFO pointer collision
If the FIFO pointer collision alarm is set when collisiongone_ena is
enabled, the FIFO must be re-synchronized and the bits must be
cleared to resume normal operation.
10
9
alarm_dacclk_gone
alarm_dataclk_gone
Alarm indicating the DACCLK has been stopped.
If the bit is set when dacclkgone_ena is enabled, the DACCLK must
resume and the bit must be cleared to resume normal operation.
NA
NA
Alarm indicating the DATACLK has been stopped.
If the bit is set when dataclkgone_ena is enabled, the DATACLK
must resume and the bit must be cleared to resume normal
operation.
8
7
alarm_output_gone
alarm_from_iotest
Alarm indicating either alarm_dacclk_gone, alarm_dataclk_gone, or
alarm_fifo_collision are asserted. It controls the output. When high it
will output "0x8000" for each output connected to the DAC. If the bit
is set when dacclkgone_ena, dataclkgone_ena, or
collisiongone_ena are enabled, then the corresponding errors must
be fixed and the bits must be cleared to resume normal operation.
NA
NA
Alarm indicating the input data pattern does not match the pattern in
the iotest_pattern registers. When data pattern checker mode is
enabled, this alarm in register config5, bit7 is the only valid alarm.
Other alarms in register config5 are not valid and can be
disregarded.
6
5
Reserved
Reserved for factory use.
NA
NA
alarm_from_pll
Alarm indicating the PLL has lost lock. For version ID "001",
alarm_from_PLL may not indicate the correct status of the PLL.
Refer to pll_lfvolt(2:0) in register config24 for proper PLL lock
indication.
4
3
alarm_Aparity
alarm_Bparity
In dual parity mode, alarm indicating a parity error on the A word. In
single parity mode, alarm on the 32-bit data captured on the rising
edge of DATACLKP/N.
NA
NA
In dual parity mode, alarm indicating a parity error on the B word. In
single parity mode, alarm on the 32-bit data captured on the falling
edge of DATACLKP/N.
2
1
0
alarm_Cparity
alarm_Dparity
Reserved
In dual parity mode, alarm indicating a parity error on the C word.
In dual parity mode, alarm indicating a parity error on the D word.
Reserved for factory use.
NA
NA
NA
30
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DAC34H84
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SLAS751A –MARCH 2011–REVISED JUNE 2011
Register name: config6 – Address: 0x06, Default: No RESET Value (READ ONLY)
Register
Name
Default
Value
Address
Bit
Name
tempdata(7:0)
Function
config6
0x06
15:8
This is the output from the chip temperature sensor. The value of this register in
two’s complement format represents the temperature in degrees Celsius. This
register must be read with a minimum SCLK period of 1μs.
No
RESET
Value
7:2
1
Reserved
Reserved
Reserved
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
000000
0
0
0
Register name: config7 – Address: 0x07, Default: 0xFFFF
Register
Name
Default
Value
Address
Bit
Name
Function
config7
0x07
15:0 alarms_mask(15:0)
These bits control the masking of the alarms. (0=not masked, 1= masked)
0xFFFF
alarm_mask
Alarm that is Masked
alarm_from_zerochk
not used
15
14
13
12
11
10
9
alarm_fifo_collision
alarm_fifo_1away
alarm_fifo_2away
alarm_dacclk_gone
alarm_dataclk_gone
alarm_output_gone
alarm_from_iotest
not used
8
7
6
5
alarm_from_pll
alarm_Aparity
4
3
alarm_Bparity
2
alarm_Cparity
1
alarm_Dparity
0
not used
Register name: config8 – Address: 0x08, Default: 0x0000 (CAUSES AUTO-SYNC)
Register
Name
Default
Value
Address
Bit
Name
Reserved
Function
config8
0x08
15
14
13
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
0
Reserved
Reserved
0
0
12:0 qmc_offsetA(12:0)
DACA offset correction. The offset is measured in DAC LSBs. If enabled in config30
writing to this register causes an auto-sync to be generated. This loads the values of
the QMC offset registers (config8-config9) into the offset block at the same time.
When updating the offset values for the AB channel config8 should be written last.
Programming config9 will not affect the offset setting.
All zeros
Register name: config9 – Address: 0x09, Default: 0x8000
Register
Name
Default
Value
Address
Bit
Name
Function
config9
0x09
15:13 fifo_offset(2:0)
When the sync to the FIFO occurs, this is the value loaded into the FIFO read pointer. With
this value the initial difference between write and read pointers can be controlled. This may
be helpful in syncing multiple chips or controlling the delay through the device.
100
12:0 qmc_offsetB(12:0) DACB offset correction. The offset is measured in DAC LSBs.
All zeros
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Register name: config10 – Address: 0x0A, Default: 0x0000 (CAUSES AUTO-SYNC)
Register
Name
Default
Value
Address
Bit
Name
Reserved
Function
config10
0x0A
15
14
13
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
0
Reserved
Reserved
0
0
12:0 qmc_offsetC(12:0)
DACC offset correction. The offset is measured in DAC LSBs. If enabled in config30
writing to this register causes an auto-sync to be generated. This loads the values of
the CD-channel QMC offset registers (config10-config11) into the offset block at the
same time. When updating the offset values for the CD-channel config10 should be
written last. Programming config11 will not affect the offset setting.
All zeros
Register name: config11 – Address: 0x0B, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
Reserved
Function
config11
0x0B
15
14
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
0
Reserved
0
0
13
Reserved
12:0
qmc_offsetD(12:0)
DACD offset correction. The offset is measured in DAC LSBs.
All zeros
Register name: config12 – Address: 0x0C, Default: 0x0400
Register
Name
Default
Value
Address
Bit
Name
Reserved
Function
config12
0x0C
15
14
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
0
0
0
0
0
Reserved
13
Reserved
12
Reserved
11
Reserved
10:0
qmc_gainA(10:0)
QMC gain for DACA. The full 11-bit qmc_gainA(10:0) word is formatted as UNSIGNED
with a range of 0 to 1.9990. The implied decimal point for the multiplication is between bit
9 and bit 10.
10000000
000
Register name: config13 – Address: 0x0D, Default: 0x0400
Register
Name
Default
Value
Address
Bit
Name
Function
Sets the mixing function of the coarse mixer.
config13
0x0D
15
cmix_mode(3:0)
0000
MM Bit 15: Fs/8 mixer
MM Bit 14: Fs/4 mixer
MM Bit 13: Fs/2 mixer
MM Bit 12: -Fs/4 mixer
The various mixers can be combined together to obtain a ±n×Fs/8 total mixing factor.
11
Reserved
Reserved for factory use.
0
10:0
qmc_gainB(10:0)
QMC gain for DACB. The full 11-bit qmc_gainB(10:0) word is formatted as UNSIGNED
with a range of 0 to 1.9990. The implied decimal point for the multiplication is between
bit 9 and bit 10.
10000000
000
Register name: config14 – Address: 0x0E, Default: 0x0400
Register
Name
Default
Value
Address
Bit
Name
Reserved
Function
config14
0x0E
15
14
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
0
0
0
0
0
Reserved
13
Reserved
12
Reserved
11
Reserved
10:0
qmc_gainC(10:0)
QMC gain for DACC. The full 11-bit qmc_gainC(10:0) word is formatted as UNSIGNED 10000000
with a range of 0 to 1.9990. The implied decimal point for the multiplication is between
bit 9 and bit 10.
000
32
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SLAS751A –MARCH 2011–REVISED JUNE 2011
Register name: config15 – Address: 0x0F, Default: 0x0400
Register
Name
Default
Value
Address
Bit
Name
Function
config15
0x0F
15:14 output_
Delays the AB data path outputs from 0 to 3 DAC clock cycles.
Delays the CD data path outputs from 0 to 3 DAC clock cycles.
Reserved for factory use.
00
00
0
delayAB(1:0)
13:12 output_
delayCD(1:0)
Reserved
11
10:0
qmc_gainD(10:0)
QMC gain for DACD. The full 11-bit qmc_gainD(10:0) word is formatted as UNSIGNED
with a range of 0 to 1.9990. The implied decimal point for the multiplication is between
bit 9 and bit 10.
10000000
000
Register name: config16 – Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC)
Register
Name
Default
Value
Address
Bit
Name
Reserved
Function
config16
0x10
15
14
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
0
Reserved
0
13
Reserved
0
0
12
Reserved
11:0
qmc_phaseAB(11:0)
QMC correction phase for the AB data path. The 12-bit qmc_phaseAB(11:0) word is
formatted as two’s complement and scaled to occupy a range of -0.5 to 0.49975 and
a default phase correction of 0.00. To accomplish QMC phase correction, this value
is multiplied by the current B sample, then summed into the A sample. If enabled in
config30 writing to this register causes an auto-sync to be generated. This
loads the values of the QMC offset registers (config12, config13, and config16)
into the QMC block at the same time. When updating the QMC values for the
AB channel config16 should be written last. Programming config12 and
config13 will not affect the QMC settings.
All zeros
Register name: config17 – Address: 0x11, Default: 0x0000 (CAUSES AUTO-SYNC)
Register
Name
Default
Value
Address
Bit
Name
Reserved
Function
config17
0x11
15
14
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
0
Reserved
0
13
Reserved
0
0
12
Reserved
11:0
qmc_phaseCD(11:0)
QMC correction phase for the CD data path. The 12-bit qmc_gainCD(11:0) word is
formatted as two’s complement and scaled to occupy a range of -0.5 to 0.49975
and a default phase correction of 0.00. To accomplish QMC phase correction, this
value is multiplied by the current D sample, then summed into the C sample. If
enabled in config30 writing to this register causes an auto-sync to be
generated. This loads the values of the CD-channel QMC block registers
(config14, config15 and config17) into the QMC block at the same time. When
updating the QMC values for the CD-channel config17 should be written last.
Programming config14 and config15 will not affect the QMC settings.
All zeros
Register name: config18 – Address: 0x12, Default: 0x0000 (CAUSES AUTO-SYNC)
Register
Name
Default
Value
Address
Bit
Name
Function
config18
0x12
15:0
phase_offsetAB(15:0) Phase offset added to the AB data path NCO accumulator before the generation of
the SIN and COS values. The phase offset is added to the upper 16 bits of the NCO
accumulator results and these 16 bits are used in the sin/cos lookup tables. If
enabled in config31 writing to this register causes an auto-sync to be
generated. This loads the values of the fine mixer block registers (config18,
config20, and config21) at the same time. When updating the mixer values the
config18 should be written last. Programming config20 and config21 will not
affect the mixer settings.
0x0000
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Register name: config19 – Address: 0x13, Default: 0x0000 (CAUSES AUTO-SYNC)
Register
Name
Default
Value
Address
Bit
Name
Function
config19
0x13
15:0
phase_offsetCD(15:0)
Phase offset added to the CD data path NCO accumulator before the generation of
the SIN and COS values. The phase offset is added to the upper 16 bits of the NCO
accumulator results and these 16 bits are used in the sin/cos lookup tables. If
enabled in config31 writing to this register causes an auto-sync to be
generated. This loads the values of the CD-channel fine mixer block registers
(config19, config22, and config23) at the same time. When updating the mixer
values for the CD-channel config19 should be written last. Programming
config22 and config23 will not affect the mixer settings.
0x0000
Register name: config20 – Address: 0x14, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
Function
config20
0x14
15:0
phase_ addAB(15:0)
The phase_addAB(15:0) value is used to determine the NCO frequency. The two’s
complement formatted value can be positive or negative. Each LSB represents
Fs/(2^32) frequency step.
0x0000
Register name: config21 – Address: 0x15, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
Function
config21
0x15
15:0
phase_ addAB(31:16)
See config20 above.
0x0000
Register name: config22 – Address: 0x16, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
Function
config22
0x16
15:0
phase_ addCD(15:0)
The phase_addCD(15:0) value is used to determine the NCO frequency. The two’s
complement formatted value can be positive or negative. Each LSB represents
Fs/(2^32) frequency step.
0x0000
Register name: config23 – Address: 0x17, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
Function
config23
0x17
15:0
phase_ addCD(31:16)
See config22 above.
0x0000
34
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SLAS751A –MARCH 2011–REVISED JUNE 2011
Register name: config24 – Address: 0x18, Default: NA
Register
Name
Default
Address
Bit
Name
Function
Value
001
0
config24
0x18
15:13
12
Reserved
pll_reset
Reserved for factory use.
When set, the PLL loop filter (LPF) is pulled down to 0V. Toggle from ‘1’ to ‘0’ to
restart the PLL if an over-speed lock-up occurs. Over-speed can happen when the
process is fast, the supplies are higher than nominal, etc. resulting in the feedback
dividers missing a clock.
11
10
pll_ndivsync_ena
pll_ena
When set, the LVDS SYNC input is used to sync the PLL N dividers.
When set, the PLL is enabled. When cleared, the PLL is bypassed.
Reserved for factory use.
1
0
9:8
7:6
Reserved
00
00
pll_cp(1:0)
PLL pump charge select
MM 00: No charge pump
MM 01: Single pump charge
MM 10: Not used
MM 11: Dual pump charge
5:3
pll_p(2:0)
PLL pre-scaler dividing module control.
001
MM 010: 2
MM 011: 3
MM 100: 4
MM 101: 5
MM 110: 6
MM 111: 7
MM 000: 8
2:0
pll_lfvolt(2:0)
PLL loop filter voltage. This three bit read-only indicator has step size of 0.4125V.
The entire range covers from 0V to 3.3V. The optimal lock range of the PLL will be
from 010 to 101 (i.e. 0.825V to 2.063V). Adjust pll_vco(5:0) for optimal lock range.
NA
Register name: config25 – Address: 0x19, Default: 0x0440
Register
Name
Default
Value
Address
Bit
Name
pll_m(7:0)
Function
M portion of the M/N divider of the PLL.
config25
0x19
15:8
0x04
If pll_m<7> = 0, the M divider value has the range of pll_m<6:0>, spanning from
4 to 127. (i.e. 0, 1, 2, and 3 are not valid.)
If pll_m<7> = 1, the M divider value has the range of 2 × pll_m<6:0>, spanning
from 8 to 254. (i.e. 0, 2, 4, and 6 are not valid. M divider has even values only.)
7:4
pll_n(3:0)
N portion of the M/N divider of the PLL.
MM 0000: 1
0100
MM 0001: 2
MM 0010: 3
MM 0011: 4
MM 0100: 5
MM 0101: 6
MM 0110: 7
MM 0111: 8
MM 1000: 9
MM 1001: 10
MM 1010: 11
MM 1011: 12
MM 1100: 13
MM 1101: 14
MM 1110: 15
MM 1111: 16
3:2
1:0
pll_vcoitune(1:0)
Reserved
PLL VCO bias tuning bits. Set to "01" for normal PLL operation
Reserved for factory use.
00
00
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Register name: config26 – Address: 0x1A, Default: 0x0020
Register
Name
Default
Value
Address
Bit
Name
pll_vco(5:0)
Function
config26
0x1A
15:10
VCO frequency coarse tuning bits.
Reserved for factory use.
000000
9
8
7
6
5
4
Reserved
0
0
0
0
1
0
Reserved
Reserved for factory use.
bias_sleep
tsense_sleep
pll_sleep
When set, the bias amplifier is put into sleep mode.
Turns off the temperature sensor when asserted.
When set, the PLL is put into sleep mode.
clkrecv_sleep
When asserted the clock input receiver gets put into sleep mode. This affects the
OSTR receiver as well.
3
2
1
0
sleepA
sleepB
sleepC
sleepD
When set, the DACA is put into sleep mode.
When set, the DACB is put into sleep mode.
When set, the DACC is put into sleep mode.
When set, the DACD is put into sleep mode.
0
0
0
0
Register name: config27 – Address: 0x1B, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
extref_ena
Function
config27
0x1B
15
Allows the device to use an external reference or the internal reference.
0: Internal reference
0
1: External reference
14
13
12
11
Reserved
Reserved
Reserved
fuse_sleep
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
0
0
0
0
Put the fuses to sleep when set high.
Note: Default value is ‘0’. Must be set to ‘1’ for proper operation
10
9
Reserved
Reserved
Reserved
Reserved
Reserved
atest
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
0
0
8
0
7
0
0
6
5:0
ATEST mode allows the user to check for the internal die voltages to ensure the
supply voltages are within the range. When ATEST mode is programmed, the
internal die voltages can be measured at the TXENA pin. The TXENA pin (N9) must
be floating without any pull-up or pull-down resistors.
000000
In ATEST mode, the TXENA and sif_txenable logics are bypassed, and output will
be active at all time.
Config27, bit<5:0>
001110
Description
DACA AVSS
DACA DVDD
DACA AVDD
DACB AVSS
DACB DVDD
DACB AVDD
DACC AVSS
DACC DVDD
DACC AVDD
DACD AVSS
DACD DVDD
DACD AVDD
1.2VDIG
Expected Nominal Voltage
0V
001111
1.2V
3.3V
0V
010000
010110
010111
1.2V
3.3V
0V
011000
011110
011111
1.2V
3.3V
0V
100000
100110
100111
1.2V
3.3V
1.2V
1.2V
101000
110000
000101
1.2VCLK
36
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SLAS751A –MARCH 2011–REVISED JUNE 2011
Register name: config28 – Address: 0x1C, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
Function
config28
0x1C
15:8
7:0
Reserved
Reserved
Reserved for factory use.
Reserved for factory use.
0x00
0x00
Register name: config29 – Address: 0x1D, Default: 0x0000
Register
Name
Default
Address
Bit
Name
Function
Value
0x00
0x00
config29
0x1D
15:8
7:0
Reserved
Reserved
Reserved for factory use.
Reserved for factory use.
Register name: config30 – Address: 0x1E, Default: 0x1111
Register
Name
Default
Value
Address
Bit
Name
Function
config30
0x1E
15:12 syncsel_qmoffsetAB(3:0) Selects the syncing source(s) of the AB data path double buffered QMC offset
registers. A ‘1’ in the bit enables the signal as a sync source. More than one sync
source is permitted.
0001
0001
0001
0001
MM Bit 15: sif_sync (via config31)
MM Bit 14: SYNC
MM Bit 13: OSTR
MM Bit 12: Auto-sync from register write
11:8
syncsel_qmoffsetCD(3:0) Selects the syncing source(s) of the CD data path double buffered QMC offset
registers. A ‘1’ in the bit enables the signal as a sync source. More than one sync
source is permitted.
MM Bit 11: sif_sync (via config31)
MM Bit 10: SYNC
MM Bit 9: OSTR
MM Bit 8: Auto-sync from register write
7:4
syncsel_qmcorrAB(3:0)
syncsel_qmcorrCD(3:0)
Selects the syncing source(s) of the AB data path double buffered QMC offset
registers. A ‘1’ in the bit enables the signal as a sync source. More than one sync
source is permitted.
MM Bit 7: sif_sync (via config31)
MM Bit 6: SYNC
MM Bit 5: OSTR
MM Bit 4: Auto-sync from register write
3:0
Selects the syncing source(s) of the CD data path double buffered QMC offset
registers. A ‘1’ in the bit enables the signal as a sync source. More than one sync
source is permitted.
MM Bit 3: sif_sync (via config31)
MM Bit 2: SYNC
MM Bit 1: OSTR
MM Bit 0: Auto-sync from register write
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Register name: config31 – Address: 0x1F, Default: 0x1140
Register
Name
Default
Value
Address
Bit
Name
Function
config31
0x1F
15:12 syncsel_mixerAB(3:0)
Selects the syncing source(s) of the AB data path double buffered mixer
registers. A ‘1’ in the bit enables the signal as a sync source. More than one
sync source is permitted.
MM Bit 15: sif_sync (via config31)
MM Bit 14: SYNC
MM Bit 13: OSTR
MM Bit 12: Auto-sync from register write
0001
0001
11:8
syncsel_mixerCD(3:0)
Selects the syncing source(s) of the CD data path double buffered mixer
registers. A ‘1’ in the bit enables the signal as a sync source. More than one
sync source is permitted.
MM Bit 11: sif_sync (via config31)
MM Bit 10: SYNC
MM Bit 9: OSTR
MM Bit 8: Auto-sync from register write
7:4
3:2
syncsel_nco(3:0)
syncsel_fifo_input
Selects the syncing source(s) of the two NCO accumulators. A ‘1’ in the bit
enables the signal as a sync source. More than one sync source is permitted.
MM Bit 7: sif_sync (via config31)
MM Bit 6: SYNC
MM Bit 5: OSTR
0100
MM Bit 4: ISTR
Selects either ISTR or SYNC LVDS signal to be routed to the internal
FIFO_ISTR path if syncsel_fifoin(3:0) is set to be ISTR (i.e. syncsel_fifoin(3:0) =
“0010”). In conjunction with config1 register bit(8), this allows flexibility of
external LVDS signal routing to the internal FIFO. The syncsel_fifo_input(1:0)
can only have one bit active at a time.
00
MM 00: external LVDS ISTR signal to internal FIFO_ISTR path
MM 01: external LVDS SYNC signal to internal FIFO_ISTR path
MM 10: external LVDS ISTR signal to internal FIFO_ISTR path
MM 11: external LVDS SYNC signal to internal FIFO_ISTR path
1
0
sif_sync
SIF created sync signal. Set to ‘1’ to cause a sync and then clear to ‘0’ to
remove it.
0
0
Reserved
Reserved for factory use.
Register name: config32 – Address: 0x20, Default: 0x2400
Register
Name
Default
Value
Address
Bit
Name
Function
config32
0x20
15:12
syncsel_fifoin(3:0)
Selects the syncing source(s) of the FIFO input side. A ‘1’ in the bit enables the
0010
signal as a sync source. More than one sync source is permitted.
MM Bit 15: sif_sync (via config31)
MM Bit 14: Always zero
MM Bit 13: ISTR
MM Bit 12: SYNC
11:8
syncsel_fifoout(3:0)
Selects the syncing source(s) of the FIFO output side. A ‘1’ in the bit enables the
signal as a sync source. More than one sync source is permitted. clkdiv_sync_ena
must be set to "1" for the FIFO output pointer sync to occur.
0100
MM Bit 11: sif_sync (via config31)
MM Bit 10: OSTR – Dual Sync Sources Mode
MM Bit 9: ISTR – Single Sync Source mode
MM Bit 8: SYNC – Single Sync Source mode
7:1
0
Reserved
Reserved for factory use.
0000
0
clkdiv_sync_sel
Selects the signal source for clock divider synchronization.
clkdiv_sync_sel
Sync Source
0
1
OSTR
ISTR or SYNC, based on syncsel_fifoin source
selection
(config32, bit<15:12>)
Register name: config33 – Address: 0x21, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
Reserved
Function
config33
0x21
15:0
Reserved for factory use.
0x0000
38
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Register name: config34 – Address: 0x22, Default: 0x1B1B
Register
Name
Default
Value
Address
Bit
Name
Function
config34
0x22
15:14
13:12
11:10
9:8
pathA_in_sel(1:0)
pathB_in_sel(1:0)
pathC_in_sel(1:0)
pathD_in_sel(1:0)
DACA_out_sel(1:0)
DACB_out_sel(1:0)
DACC_out_sel(1:0)
DACD_out_sel(1:0)
Selects the word used for the A channel path.
Selects the word used for the B channel path.
Selects the word used for the C channel path.
Selects the word used for the D channel path.
Selects the word used for the DACA output.
Selects the word used for the DACB output.
Selects the word used for the DACC output.
Selects the word used for the DACD output.
00
01
10
11
00
01
10
11
7:6
5:4
3:2
1:0
Register name: config35 – Address: 0x23, Default: 0xFFFF
Register
Name
Default
Value
Address
Bit
Name
Function
config35
0x23
15:0
sleep_cntl(15:0)
Controls the routing of the CMOS SLEEP signal (pin B40) to different blocks. When a
bit in this register is set, the SLEEP signal will be sent to the corresponding block. The
block will only be disabled when the SLEEP is logic HIGH and the correspond bit is set
to “1”.
0xFFFF
These bits do not override SIF bits in config26 that control the same sleep function.
sleep_cntl(bit)
Function
DACA sleep
15
14
DACB sleep
13
DACC sleep
12
DACD sleep
11
Clock receiver sleep
PLL sleep
10
9
LVDS data sleep
LVDS control sleep
Temp sensor sleep
reserved
8
7
6
5
Bias amplifier sleep
not used
All others
Register name: config36 – Address: 0x24, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
Function
config36
0x24
15:13 datadly(2:0)
Controls the delay of the data inputs through the LVDS receivers. Each LSB adds
approximately 50 ps
000
0: Minimum
12:10 clkdly(2:0)
Controls the delay of the data clock through the LVDS receivers. Each LSB adds
approximately 50 ps
000
0: Minimum
9:0
Reserved
Reserved for factory use.
0x000
Register name: config37 – Address: 0x25, Default: 0x7A7A
Register
Name
Default
Value
Address
Bit
Name
Function
config37
0x25
15:0
iotest_pattern0
Dataword0 in the IO test pattern. It is used with the seven other words to test the input data.
0x7A7A
At the start of the IO test pattern, this word should be aligned with rising edge of ISTR or
SYNC signal to indicate sample 0.
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DAC34H84
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Register name: config38 – Address: 0x26, Default: 0xB6B6
Register
Name
Default
Value
Address
Bit
Name
Function
config38
0x26
15:0
iotest_pattern1
Dataword1 in the IO test pattern. It is used with the seven other words to test the input data.
0xB6B6
Register name: config39 – Address: 0x27, Default: 0xEAEA
Register
Name
Default
Value
Address
Bit
Name
Function
config39
0x27
15:0
iotest_pattern2
Dataword2 in the IO test pattern. It is used with the seven other words to test the input
data.
0xEAEA
Register name: config40 – Address: 0x28, Default: 0x4545
Register
Name
Default
Value
Address
Bit
Name
Function
Dataword3 in the IO test pattern. It is used with the seven other words to test the input data.
config40
0x28
15:0
iotest_pattern3
0x4545
Register name: config41 – Address: 0x29, Default: 0x1A1A
Register
Name
Default
Value
Address
Bit
Name
Function
config41
0x29
15:0
iotest_pattern4 Dataword4 in the IO test pattern. It is used with the seven other words to test the input data.
0x1A1A
Register name: config42 – Address: 0x2A, Default: 0x1616
Register
Name
Default
Value
Address
Bit
Name
Function
config42
0x2A
15:0
iotest_pattern5
Dataword5 in the IO test pattern. It is used with the seven other words to test the input
data.
0x1616
Register name: config43 – Address: 0x2B, Default: 0xAAAA
Register
Name
Default
Value
Address
Bit
Name
Function
config43
0x2B
15:0
iotest_pattern6
Dataword6 in the IO test pattern. It is used with the seven other words to test the input
data.
0xAAAA
Register name: config44 – Address: 0x2C, Default: 0xC6C6
Register
Name
Default
Value
Address
Bit
Name
Function
config44
0x2C
15:0
iotest_pattern7
Dataword7 in the IO test pattern. It is used with the seven other words to test the input
data.
0xC6C6
Register name: config45 – Address: 0x2D, Default: 0x0004
Register
Name
Default
Value
Address
Bit
Name
Reserved
Function
config45
0x2D
15
14
Reserved for factory use.
0
0
ostrtodig_sel
When set, the OSTR signal is passed directly to the digital block. This is the signal that
is used to clock the dividers.
13
ramp_ena
Reserved
When set, a ramp signal is inserted in the input data at the FIFO input.
Reserved for factory use.
0
12:1
0000
0000
0100
0
sifdac_ena
When set, the DAC output is set to the value in sifdac(15:0) in register config48.
0
40
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Register name: config46 – Address: 0x2E, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
Function
config46
0x2E
15:8
grp_delaya(7:0)
Sets the group delay function for DACA. The maximum delay ranges from 30ps to
100ps and is dependent on DAC sample clock. Contact TI for specific application
information.
0x00
7:0
grp_delayB(7:0)
Sets the group delay function for DACB. The maximum delay ranges from 30ps to
100ps and is dependent on DAC sample clock. Contact TI for specific application
information.
0x00
Register name: config47 – Address: 0x2F, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
Function
config47
0x2F
15:8
grp_delayC(7:0)
Sets the group delay function for DACC. The maximum delay ranges from 30ps to
100ps and is dependent on DAC sample clock. Contact TI for specific application
information.
0x00
7:0
grp_delayD(7:0)
Sets the group delay function for DACD. The maximum delay ranges from 30ps to
100ps and is dependent on DAC sample clock. Contact TI for specific application
information.
0x00
Register name: config48 – Address: 0x30, Default: 0x0000
Register
Name
Default
Value
Address
Bit
Name
sifdac(15:0)
Function
config48
0x30
15:0
Value sent to the DACs when sifdac_ena is asserted. DATACLK must be running to
latch this value into the DACs. The format would be based on twos in register config2.
0x0000
Register name: version– Address: 0x7F, Default: 0x5408 (READ ONLY)
Register
Name
Default
Value
Address
Bit
Name
Function
version
0x7F
15:10
9
Reserved
Reserved
Reserved
Reserved
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Returns ‘01’ for DAC34H84.
010101
0
8:7
6:5
4:3
2:0
00
00
deviceid(1:0)
versionid(2:0)
01
A hardwired register that contains the version of the chip.
001
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DAC34H84
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www.ti.com
DATA INTERFACE
The DAC34H84 has a 32-bit LVDS bus that accepts quad, 16-bit data in word-wide format. The quad-16-bit data
can be input to the device using a dual-bus, 16-bit interface. The bus accepts LVDS transfer rates up to
1.25GSPS which corresponds to a maximum data rate of 625MSPS per data channel. The default LVDS bus
input assignment is shown in Table 3.
Table 3. LVDS Bus Input Assignment
Data Paths
A and B
Pins
DAB[15..0]
DCD[15..0]
C and D
Data is sampled by the LVDS double data rate (DDR) clock DATACLK. Setup and hold requirements must be
met for proper sampling. A and C data are captured on the rising edge of DATACLK. B and D data are captured
on the falling edge of DATACLK.
For both input bus modes, a sync signal, either ISTR or SYNC, is required to sync the FIFO read and/or write
pointers.
The sync signal, either ISTR or SYNC, can be either a pulse or a periodic signal where the sync period
corresponds to multiples of 8 samples. ISTR or SYNC is sampled by a rising edge in DATACLK. The pulse-width
t(ISTR_SYNC) needs to be at least equal to 1/2 of the DATACLK period.
DATA FORMAT
The 16-bit data for channels A and B is interleaved in the form A0[15:0], B0[15:0], A1[15:0], B1[15:0], A2[15:0]…
into the DAB[15:0]P/N LVDS inputs. Similarly data for channels C and D is interleaved into the DCD[15:0]P/N
LVDS inputs. Data into the DAC34H84 is formatted according to the diagram shown in Figure 51 where index 0
is the data LSB and index 15 is the data MSB.
SAMPLE 0
SAMPLE 1
SAMPLE 2
SAMPLE 3
A0
B0
A1
B1
A2
B2
A3
B3
DAB[15:0]P/N
DCD[15:0]P/N
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
C0
D0
C1
D1
C2
D2
C3
D3
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
DATACLKP/N (DDR)
t(ISTR_SYNC)
Sync
Option #1
ISTRP/N
t(ISTR_SYNC)
Sync
SYNCP/N
Option #2
T0530-01
Figure 51. Data Transmission Format
The FIFO read and write pointer can also be synced by SIF SYNC as the third sync option if multi-device
synchronization is not needed. In this sync mode, the syncsel_fifoin(3:0) and syncsel_fifoout(3:0) in register
config32 need to be both set to "1000" for the SIF SYNC option.
42
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DAC34H84
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SLAS751A –MARCH 2011–REVISED JUNE 2011
INPUT FIFO
The DAC34H84 includes a 4-channel, 16-bits wide and 8-samples deep input FIFO which acts as an elastic
buffer. The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC
data rate clock such as the ones resulting from clock-to-data variations from the data source.
Figure 52 shows a simplified block diagram of the FIFO.
Clock Handoff
Input Side
Clocked by DATACLK
Output Side
Clocked by FIFO Out Clock
(DACCLK/Interpolation Factor)
FIFO:
4 x 16-Bits Wide
8-Samples deep
16-Bit
DAB[15:0]
Initial
Position
Sample 0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
A0[15:0], B0[15:0], C0[15:0], D0[15:0]
16-Bit
A-Data, 16-Bit
FIFO A Output
Sample 0
A1[15:0], B1[15:0], C1[15:0], D1[15:0]
16-Bit
16-Bit
16-Bit
B-Data, 16-Bit
C-Data, 16-Bit
D-Data, 16-Bit
64-Bit
FIFO B Output
FIFO C Output
FIFO D Output
64-Bit
16-Bit
16-Bit
Sample 0
A2[15:0], B2[15:0], C2[15:0], D2[15:0]
De-Interleave
DCD[15:0]
Sample 0
A3[15:0], B3[15:0], C3[15:0], D3[15:0]
Initial
Position
Sample 0
A4[15:0], B4[15:0], C4[15:0], D4[15:0]
Sample 0
A5[15:0], B5[15:0], C5[15:0], D5[15:0]
16-Bit
Sample 0
A6[15:0], B6[15:0], C6[15:0], D6[15:0]
Read Pointer Reset
Write Pointer Reset
ISTR/
SYNC
Sample 0
A7[15:0], B7[15:0], C7[15:0], D7[15:0]
FIFO Reset
fifo_offset(2:0)
syncsel_fifoout
S
M
OSTR
syncsel_fifoin
S (Single Sync Sources Mode): Reset handoff from
input side to output side
M (Dual Sync Source Mode): OSTR resets read
pointer. Allows Multi-DAC synchronization
B0461-01
Figure 52. DAC34H84 FIFO Block Diagram
Data is written to the device 32-bits at a time on the rising and falling edges of DATACLK. In order to form a
complete 64-bit wide sample (16-bit A-data, 16-bit B-data, 16-bit C-data, and 16-bit D-data) one DATACLK
period is required. Each 64-bit wide sample is written into the FIFO at the address indicated by the write pointer.
Similarly, data from the FIFO is read by the FIFO Out Clock 64-bits at a time from the address indicated by the
read pointer. The FIFO Out Clock is generated internally from the DACCLK signal and its rate is equal to
DACCLK/Interpolation. Each time a FIFO write or FIFO read is done the corresponding pointer moves to the next
address.
The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in
Figure 52. This offset gives optimal margin within the FIFO. The default read pointer location can be set to
another value using fifo_offset(2:0) in register config3 (address 4 by default). Under normal conditions data is
written-to and read-from the FIFO at the same rate and consequently the write and read pointer gap remains
constant. If the FIFO write and read rates are different, the corresponding pointers will be cycling at different
speeds which could result in pointer collision. Under this condition the FIFO attempts to read and write data from
the same address at the same time which will result in errors and thus must be avoided.
The write pointer sync source is selected by syncsel_fifoin(3:0) in register config32. In most applications either
ISTR or SYNC are used to reset the write pointer. Unlike DATA, the sync signal is latched only on the rising
edges of DATACLK. A rising edge on the sync signal source causes the pointer to return to its original position.
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DAC34H84
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Similarly, the read pointer sync source is selected by syncsel_fifoout(3:0). The write pointer sync source can be
set to reset the read pointer as well. In this case, the FIFO Out clock will recapture the write pointer sync signal
to reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock) results in phase ambiguity of
the sync signal. This limits the precise control of the output timing and makes full synchronization of multiple
devices difficult.
To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write
pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing
requirements in the specifications table. In order to minimize the skew it is recommended to use the same clock
distribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the
DAC34H84 devices in the system. Swapping the polarity of the DACCLK outputs with respect to the OSTR ones
establishes proper phase relationship.
The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointers
automatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, it is
necessary to have the ISTR, SYNC, and OSTR signals to repeat at multiples of 8 FIFO samples. To disable
FIFO reset, set syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to “0000”.
The frequency limitation for ISTR and SYNC signals are the following:
fsync = fDATACLK/(n x 8) where n = 1, 2, …
The frequency limitation for the OSTR signal is the following:
fOSTR = fDAC/(n x interpolation x 8) where n = 1, 2, …
The frequencies above are at maximum when n = 1. This is when the ISTR, SYNC, or OSTR have a rising edge
transition every 8 FIFO samples. The occurrence can be made less frequent by setting n > 1, for example, every
n × 8 FIFO samples.
D[15:0]P/N
tS(DATA)
tH(DATA)
tS(DATA)
tH(DATA)
DATACLKP/N
(DDR)
tH(DATA)
tS(DATA)
ISTRP/N
SYNCP/N
Resets Write Pointer to Position 0
DACCLKP/N
2x Interpolation
tS(OSTR)
tH(OSTR)
OSTRP/N
(optionally internal
sync from Write Reset)
Resets Read Pointer to Position
Set by fifo_offset (4 by Default)
T0531-01
Figure 53. FIFO Write and Read Descriptions
FIFO MODES OF OPERATION
The DAC34H84 input FIFO can be completely bypassed through registers config0 and config32. The register
configuration for each mode is described in Table 4.
44
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SLAS751A –MARCH 2011–REVISED JUNE 2011
Register
config0
Control Bits
fifo_ena
config32
syncsel_fifoout(3:0)
Table 4. FIFO Operation Modes
config0 and config32 FIFO Bits
FIFO Mode
syncsel_fifoout
fifo_ena
Bit 3: sif_sync
Bit 2: OSTR
Bit 1: ISTR
Bit 0: SYNC
Dual Sync Sources
1
1
0
0
0
X
1
0
0
Single Sync
Source
1 or 0 Depends on the sync
source
1 or 0 Depends on the
sync source
0
Bypass
X
X
X
DUAL SYNC SOURCES MODE
This is the recommended mode of operation for those applications that require precise control of the output
timing. In Dual Sync Sources mode, the FIFO write and read pointers are reset independently. The FIFO write
pointer is reset using the LVDS ISTR or SYNC signal, and the FIFO read pointer is reset using the LVPECL
OSTR signal. This allows LVPECL OSTR signal to control the phase of the output for either a single chip or
multiple chips. Multiple devices can be fully synchronized in this mode.
SINGLE SYNC SOURCE MODE
In Single Sync Source mode, the FIFO write and read pointers are reset from the same source, either LVDS
ISTR or LVDS SYNC signal. This mode has a possibility of up to 2 DAC clocks offset between the multiple DAC
outputs. Applications requiring exact output timing control will need Dual Sync Sources mode instead of Single
Sync Source Mode. A single rising edge for FIFO and clock divider sync is recommended. Periodic sync signal is
not recommended due to the non-deterministic latency of the sync signal through the clock domain transfer.
BYPASS MODE
In FIFO bypass mode, the FIFO block is not used. As a result the input data is handed off from the DATACLK to
the DACCLK domain without any compensation. In this mode the relationship between DATACLK and DACCLK
t(align) is critical and used as a synchronizing mechanism for the internal logic. Due to the t(align) constraint this
mode is not recommended. In bypass mode the pointers have no effect on the data path or handoff.
CLOCKING MODES
The DAC34H84 has a dual clock setup in which a DAC clock signal is used to clock the DAC cores and internal
digital logic and a separate DATA clock is used to clock the input LVDS receivers and FIFO input. The
DAC34H84 DAC clock signal can be sourced directly or generated through an on-chip low-jitter phase-locked
loop (PLL).
In those applications requiring extremely low noise it is recommended to bypass the PLL and source the DAC
clock directly from a high-quality external clock to the DACCLK input. In most applications system clocking can
be simplified by using the on-chip PLL to generate the DAC core clock while still satisfying performance
requirements. In this case the DACCLK pins are used as the reference frequency input to the PLL.
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DAC34H84
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16-Bit
DACI
PLL
DACCLK
Clock Distribution
to Digital
16-Bit
DACQ
VCO/
Dividers
pll_ena
B0452-01
Figure 54. Top Level Clock Diagram
PLL BYPASS MODE
In PLL bypass mode a very high quality clock is sourced to the DACCLK inputs. This clock is used to directly
source the DAC34H84 DAC sample rate clock. This mode gives the device best performance and is
recommended for extremely demanding applications.
The bypass mode is selected by setting the following:
1. pll_ena bit in register config24 to “0” to bypass the PLL circuitry.
2. pll_sleep bit in register config26 to “1” to put the PLL and VCO into sleep mode.
PLL MODE
In this mode the clock at the DACCLKP/N input functions as a reference clock source to the on-chip PLL. The
on-chip PLL will then multiply this reference clock to supply a higher frequency DAC sample rate clock. Figure 55
shows the block diagram of the PLL circuit.
OSTR (Internally Generated)
External Loop
Filter
DACCLKP
REFCLK
DACCLKN
PFD
and
CP
N
Divider
Prescaler
DACCLK
SYNCP
SYNCN
SYNC_PLL
VCO
Internal Loop
Filter
Note:
The PLL generates internal OSTR signal. In this mode
external LVPECL OSTR signal is not required.
M
Divider
If the DAC is configured with PLL enabled with Dual Sync
Sources mode, then the PFD frequency has to be the pre-
defined OSTR frequency.
B0453-01
Figure 55. PLL Block Diagram
The DAC34H84 PLL mode is selected by setting the following:
1. pll_ena bit in register config24 to “1” to route to the PLL clock path.
2. pll_sleep bit in register config26 to “0” to enable the PLL and VCO.
46
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SLAS751A –MARCH 2011–REVISED JUNE 2011
The output frequency of the VCO is designed to be the in the range from 3.3GHz to 4.0GHz. The prescaler
value, pll_p(2:0) in register config24, should be chosen such that the product of the prescaler value and DAC
sample rate clock is within the VCO range. To maintain optimal PLL loop, the coarse tune bits, pll_vco(5:0) in
register config26, can adjust the center frequency of the VCO towards the product of the prescaler value and
DAC sample rate clock. Figure 56 shows a typical relationship between coarse tune bits and VCO center
frequency.
4000
VCO Frequency MHz - 3253
)
(
Coarse Tune Bits @
3900
3800
3700
3600
3500
3400
3300
11.6
0
8
16
32
40
48
56
64
24
Coarse Tuning Bits
G047
Figure 56. Typical PLL/VCO Lock Range vs Coarse Tuning Bits
Common wireless infrastructure frequencies (614.4MHz, 737.28MHz, 1.2288GHz, etc.) are generated from this
VCO frequency in conjunction with the pre-scaler setting as shown in Table 5.
Table 5. VCO Operation
VCO Frequency (MHz)
3440.64
Pre-Scale Divider
Desired DACCLK (MHz)
pll_p(2:0)
111
7
6
5
3
491.52
614.4
3686.4
110
3686.4
737.28
1228.8
101
3686.4
011
The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency.
Table 6. PFD and CP Operation
DACCLK Frequency
M Divider
PDF Update Rate (MHz)
pll_m(7:0)
(MHz)
491.52
491.52
491.52
491.52
4
8
122.88
61.44
30.72
15.36
00000100
00001000
00010000
00100000
16
32
The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock. Both M and N
dividers can keep the PFD frequency below 155 MHz for peak operation.
The overall divide ratio inside the loop is the product of the Pre-Scale and M dividers (P × M) and the following
guidelines should be followed:
•
•
The overall divide ratio range is from 24 to 480
When the overall divide ratio is less than 120, the internal loop filter can assure a stable loop
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•
When the overall divide ratio is greater than 120, an external loop filter is required to ensure loop stability
The single charge pump current option is selected by setting pll_cp(1:0) in register config24 to “01”. If an external
filter is required, the following filter should be connected to the LPF pin (A1):
LPF
R = 1 kΩ
C2 = 1 nF
C1 = 100 nF
S0514-01
Figure 57. Recommended External Loop Filter
The PLL will generate an internal OSTR signal and does not require the external LVPECL OSTR signal. The
OSTR signal is buffered from the N-divider output in the PLL block, and the frequency of the signal is the same
as the PFD frequency. Therefore, using PLL with Dual Sync Sources mode would require the PFD frequency to
be the pre-defined OSTR frequency. This will allow the FIFO to be synced correctly by the internal OSTR.
MULTI-DEVICE SYNCHRONIZATION
In various applications, such as multi antenna systems where the various transmit channels information is
correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase
aligned. The DAC34H84 architecture supports this mode of operation.
MULTI-DEVICE SYNCHRONIZATION: PLL BYPASSED WITH DUAL SYNC SOURCES MODE
For single- or multi-device synchronization it is important that delay differences in the data are absorbed by the
device so that latency through the device remains the same. Furthermore, to ensure that the outputs from each
DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In the
DAC34H84 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode the
additional OSTR signal is required by each DAC34H84 to be synchronized.
Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into multiple
DAC devices can experience different delays due to variations in the digital source output paths or board level
wiring. These different delays can be effectively absorbed by the DAC34H84 FIFO so that all outputs are phase
aligned correctly.
48
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DACCLKP/N
OSTRP/N
DAB[15:0]P/N
DCD[15:0]P/N
FPGA
DAC34H84 DAC1
ISTRP/N
Delay 1
LVPECL Outputs
DATACLKP/N
Outputs are
Phase Aligned
Variable delays due to variations in the FPGA(s) output
paths or board level wiring or temperature/voltage deltas
PLL/
DLL
Clock Generator
LVPECL Outputs
DAB[15:0]P/N
DCD[15:0]P/N
ISTRP/N
DATACLKP/N
OSTRP/N
Delay 2
DAC34H84 DAC2
DACCLKP/N
B0454-02
Figure 58. SynchronizationSystem in Dual Sync Sources Mode with PLL Bypassed
For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTR
signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clock
generator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity of
the DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of the
DACCLK. This may help establish proper setup and hold time requirement of the OSTR signal.
Careful board layout planning must be done to ensure that the DACCLK and OSTR signals are distributed from
device to device with the lowest skew possible as this will affect the synchronization process. In order to
minimize the skew across devices it is recommended to use the same clock distribution device to provide the
DACCLK and OSTR signals to all the DAC devices in the system.
DACCLKP/N(1)
tS(OSTR)
tH(OSTR)
tSKEW ~ 0
OSTRP/N(1)
DACCLKP/N(2)
OSTRP/N(2)
tS(OSTR)
tH(OSTR)
•
•
•
•
T0526-02
Figure 59. Timing Diagram for LVPECL Synchronization Signals
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The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the
DAC34H84 devices have a DACCLK and OSTR signal and must be carried out on each device.
1. Start-up the device as described in the power-up sequence. Set the DAC34H84 in Dual Sync Sources mode
and select OSTR as the clock divider sync source (clkdiv_sync_sel in register config32).
2. Sync the clock divider and FIFO pointers.
3. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
4. Disable clock divider sync by setting clkdiv_sync_ena to “0” in register config0.
After these steps all the DAC34H84 outputs will be synchronized.
MULTI-DEVICE SYNCHRONIZATION: PLL ENABLED WITH DUAL SYNC SOURCES MODE
The DAC34H84 allows exact phase alignment between multiple devices even when operating with the internal
PLL clock multiplier. In PLL clock mode, the PLL generates the DAC clock and an internal OSTR signal from the
reference clock applied to the DACCLK inputs so there is no need to supply an additional LVPECL OSTR signal.
For this method to operate properly the SYNC signal should be set to reset the PLL N dividers to a known state
by setting pll_ndivsync_ena in register config24 to “1”. The SYNC signal resets the PLL N dividers with a rising
edge, and the timing relationship ts(SYNC_PLL) and th(SYNC_PLL) are relative to the reference clock presented on the
DACCLK pin.
Both SYNC and DACCLK can be set as low frequency signals to greatly simplifying trace routing (SYNC can be
just a pulse as a single rising edge is required, if using a periodic signal it is recommended to clear the
pll_ndivsync_ena bit after resetting the PLL dividers). Besides the ts(SYNC_PLL) and th(SYNC_PLL) requirement
between SYNC and DACCLK, there is no additional required timing relationship between the SYNC and ISTR
signals or between DACCLK and DATACLK. The only restriction as in the PLL disabled case is that the DACCLK
and SYNC signals are distributed from device to device with the lowest skew possible.
DACCLKP/N
SYNCP/N
DAB[15:0]P/N
DCD[15:0]P/N
FPGA
DAC34H84 DAC1
ISTRP/N
Delay 1
Outputs
DATACLKP/N
Outputs are
Phase Aligned
Variable delays due to variations in the FPGA(s) output
paths or board level wiring or temperature/voltage deltas
PLL/
DLL
Clock Generator
Outputs
DAB[15:0]P/N
DCD[15:0]P/N
ISTRP/N
DATACLKP/N
SYNCP/N
Delay 2
DAC34H84 DAC2
DACCLKP/N
B0455-02
Figure 60. Synchronization System in Dual Sync Sources Mode with PLL Enabled
The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the
DAC34H84 devices have a DACCLK and OSTR signal and must be carried out on each device.
1. Start-up the device as described in the power-up sequence. Set the DAC34H84 in Dual Sync Sources mode
and enable SYNC to reset the PLL dividers (set pll_ndivsync_ena in register config24 to "1").
2. Reset the PLL dividers with a rising edge on SYNC.
3. Disable PLL dividers resetting.
4. Sync the clock divider and FIFO pointers.
50
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5. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
6. Disable clock divider sync by setting clkdiv_sync_ena to “0” in register config0.
After these steps all the DAC34H84 outputs will be synchronized.
MULTI-DEVICE OPERATION: SINGLE SYNC SOURCE MODE
In Single Sync Source mode, the FIFO write and read pointers are reset from the same sync source, either ISTR
or SYNC. Although the FIFO in this mode can still absorb the data delay differences due to variations in the
digital source output paths or board level wiring it is impossible to guarantee data will be read from the FIFO of
different devices simultaneously thus preventing exact phase alignment.
In Single Sync Source mode the FIFO read pointer reset is handoff between the two clock domains (DATACLK
and FIFO OUT CLOCK) by simply re-sampling the write pointer reset. Since the two clocks are asynchronous
there is a small but distinct possibility of a meta-stablility during the pointer handoff. This meta-stability can cause
the outputs of the multiple devices to slip by up to 2 DAC clock cycles.
When the PLL is enabled with Single Sync Source mode, the FIFO read pointer is not synchronized by the
OSTR signal. Therefore, there is no restriction on the PLL PFD frequency as described in the previous section.
DACCLKP/N
DAB[15:0]P/N
DCD[15:0]P/N
FPGA
DAC34H84 DAC1
ISTRP/N
Delay 1
LVPECL Outputs
DATACLKP/N
Variable delays due to variations in the FPGA(s) output
paths or board level wiring or temperature/voltage deltas
PLL/
DLL
Clock Generator
LVPECL Outputs
0 to 2 DAC Clock Cycles
DAB[15:0]P/N
DCD[15:0]P/N
ISTRP/N
Delay 2
DATACLKP/N
DAC34H84 DAC2
DACCLKP/N
B0456-02
Figure 61. Multi-Device Operation in Single Sync Source Mode
FIR FILTERS
Figure 62 through Figure 65 show the magnitude spectrum response for the FIR0, FIR1, FIR2 and FIR3
interpolating filters where fIN is the input data rate to the FIR filter. Figure 66 to Figure 69 show the composite
filter response for 2x, 4x, 8x and 16x interpolation. The transition band for all interpolation settings is from 0.4 to
0.6 x fDATA (the input data rate to the device) with < 0.001dB of pass-band ripple and > 90 dB stop-band
attenuation.
The DAC34H84 also has a 9-tap inverse sinc filter (FIR4) that runs at the DAC update rate (fDAC) that can be
used to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the
output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well-known
sin(x)/x or sinc(x) frequency response (Figure 70, red line). The inverse sinc filter response (Figure 70, blue line)
has the opposite frequency response from 0 to 0.4 x Fdac, resulting in the combined response (Figure 70, green
line). Between 0 to 0.4 x fDAC, the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03
dB error.
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The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to FIR4 must be reduced from
full scale to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, and
is set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0
dB). For example, if the signal input to FIR4 is at 0.25 x fDAC, the response of FIR4 is 0.9 dB, and the signal must
be backed off from full scale by 0.9 dB to avoid saturation. The gain function in the QMC blocks can be used to
reduce the amplitude of the input signal. The advantage of FIR4 having a positive gain at all frequencies is that
the user is then able to optimize the back-off of the signal based on its frequency.
The filter taps for all digital filters are listed in Table 4. Note that the loss of signal amplitude may result in lower
SNR due to decrease in signal amplitude.
20
20
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
f/fIN
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
f/fIN
1
G048
G049
Figure 62. Magnitude Spectrum for FIR0
Figure 63. Magnitude Spectrum for FIR1
20
20
0
0
–20
–40
–60
–80
–20
–40
–60
–80
–100
–100
–120
–140
–160
–120
–140
–160
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
f/fIN
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
f/fIN
1
G050
G051
Figure 64. Magnitude Spectrum for FIR2
Figure 65. Magnitude Spectrum for FIR3
52
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20
0
20
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
f/fDATA
1
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
f/fDATA
G052
G053
Figure 66. 2x Interpolation Composite Response
Figure 67. 4x Interpolation Composite Response
20
20
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
0.5
1
1.5
2
2.5
3
3.5
4
0
1
2
3
4
5
6
7
8
f/fDATA
f/fDATA
G054
G055
Figure 68. 8x Interpolation Composite Response
Figure 69. 16x Interpolation Composite Response
4
3
2
FIR4
1
Corrected
0
–1
–2
–3
–4
sin(x)/x
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
f/fDAC
G056
Figure 70. Magnitude Spectrum for Inverse Sinc Filter
Table 7. FIR Filter Coefficients
Non-Interpolating
Inverse-SINC Filter
2x Interpolating Half-band Filters
FIR0
FIR1
FIR2
FIR3
FIR4
59 Taps
23 Taps
11 Taps
11 Taps
9 Taps
6
6
-12
-12
29
29
3
3
1
1
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Table 7. FIR Filter Coefficients (continued)
Non-Interpolating
Inverse-SINC Filter
2x Interpolating Half-band Filters
FIR0
FIR1
FIR2
FIR3
FIR4
59 Taps
23 Taps
11 Taps
11 Taps
9 Taps
0
-19
0
0
-19
0
0
84
0
84
0
0
0
-25
0
0
-25
0
-4
13
-4
13
-214
0
-214
0
0
0
-50
-50
47
47
-336
0
-336
0
1209
2048(1)
1209
150
256(1)
150
592(1)
0
0
-100
0
-100
0
1006
0
1006
0
192
0
192
0
-2691
0
-2691
0
-342
0
-342
0
10141
16384(1)
10141
572
0
572
0
-914
0
-914
0
1409
0
1409
0
-2119
0
-2119
0
3152
0
3152
0
-4729
0
-4729
0
7420
0
7420
0
-13334
0
-13334
0
41527
65536(2)
41527
(1) Center taps are highlighted in BOLD
(2) Center taps are highlighted in BOLD
54
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COMPLEX SIGNAL MIXER
The DAC34H84 has two paths of complex signal mixer blocks that contain two full complex mixer (FMIX) blocks
and power saving coarse mixer (CMIX) blocks. The signal path is shown in Figure 71.
16
16
16
16
I Data In
(A)
I Data Out
(A)
Complex
Signal
Multiplier
Fs/2
Mixer
Fs/4
Mixer
16
16
16
16
Q Data In
(B)
Q Data Out
(B)
sine
16
cosine
16
CMIX<1>
CMIX<2> CMIX<0>
CMIX<3>
sine
16
cosine sine
16 16
cosine
16
(AB)
Numerically
Controlled
Oscillator
Fixed Fs/8
Oscillator
NCO_ENA
B0471-02
Note: Channel CD data path not shown
Figure 71. Path of Complex Signal Mixer
FULL COMPLEX MIXER
The two FMIX blocks operate with independent Numerically Controlled Oscillators (NCOs) and enable flexible
frequency placement without imposing additional limitations in the signal bandwidth. The NCOs have 32-bit
frequency registers (phaseaddAB(31:0) and phaseaddCD(31:0)) and 16-bit phase registers (phaseoffsetAB(15:0)
and phaseoffsetCD(15:0)) that generate the sine and cosine terms for the complex mixing. The NCO block
diagram is shown in Figure 72.
32
16
sin
Accumulator
32
16
32
32
16
Look-Up
Table
Frequency
Register
Σ
Σ
16
cos
CLK
RESET
16
fDAC
Phase
Register
NCO SYNC
via
syncsel_NCO[3:0]
B0026-03
Figure 72. NCO Block Diagram
Synchronization of the NCOs occurs by resetting the NCO accumulators to zero. The synchronization source is
selected by syncsel_NCO(3:0) in config31. The frequency word in the phaseaddAB(31:0) and phaseaddCD(31:0)
registers is added to the accumulators every clock cycle, fDAC. The output frequency of the NCO is:
freq´ fNCO _ CLK
fNCO
=
232
(1)
55
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With the complex mixer enabled, the two channels in the mixer path are treated as complex vectors of the form
IIN(t) + j QIN(t). The complex signal multiplier (shown in Figure 73) will multiply the complex channels with the sine
and cosine terms generated by the NCO. The resulting output, IOUT(t) + j QOUT(t), of the complex signal multiplier
is:
IOUT(t) = (IIN(t)cos(2πfNCOt + δ) – QIN(t)sin(2πfNCOt + δ)) × 2(mixer_gain – 1)
QOUT(t) = (IIN(t)sin(2πfNCOt + δ) + QIN(t)cos(2πfNCOt + δ)) × 2(mixer_gain – 1)
where t is the time since the last resetting of the NCO accumulator, δ is the phase offset value and mixer_gain is
either 0 or 1. δ is given by:
δ = 2π × phase_offsetAB/CD(15:0)/216
The mixer_gain option allows the output signals of the multiplier to reduce by half (6dB). See Mixer Gain section
for details.
16
16
IOUT(t)
IIN(t)
16
QIN(t)
16
QOUT(t)
16
cosine
16
sine
B0472-01
Figure 73. Complex Signal Multiplier
COARSE COMPLEX MIXER
In addition to the full complex mixers, the DAC34H84 also has coarse mixer blocks capable of shifting the input
signal spectrum by the fixed mixing frequencies ±n×fS/8. Utilizing the coarse mixer instead of the full mixers
lowers power consumption.
The output of the fs/2, fs/4, and –fs/4 mixer block is:
IOUT(t) = I(t)cos(2πfCMIXt) – Q(t)sin(2πfCMIXt)
QOUT(t) = I(t)sin(2πfCMIXt) + Q(t)cos(2πfCMIXt)
Since the sine and the cosine terms are a function of fs/2, fs/4, or –fs/4 mixing frequencies, the possible resulting
value of the terms will only be 1, -1, or 0. The simplified mathematics allows the complex signal multiplier to be
bypassed in any one of the modes, thus mixer gain is not available. The fs/2, fs/4, and –fs/4 mixer blocks
performs mixing through negating and swapping of I/Q channel on certain sequence of samples. Table 8 shows
the algorithm used for those mixer blocks.
Table 8. Fs/2, Fs/4, and –Fs/4 Mixing Sequence
MODE
MIXING SEQUENCE
Iout = {+I1, +I2, +I3, +I4…}
Qout = {+Q1, +Q2, +Q3, +Q4…}
Normal (mixer bypassed)
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Table 8. Fs/2, Fs/4, and –Fs/4 Mixing Sequence (continued)
MODE
MIXING SEQUENCE
Iout = {+I1, -I2, +I3, -I4…}
Qout = {+Q1, -Q2, +Q3, -Q4…}
Iout = {+I1, -Q2, -I3, +Q4…}
Qout = {+Q1, +I2, -Q3, -I4…}
Iout = {+I1, +Q2, -I3, -Q4…}
Qout = {+Q1, -I2, -Q3, +I4…}
fs/2
fs/4
-fs/4
The fs/8 mixer can be enabled along with various combinations of fs/2, fs/4, and –fs/4 mixer. Since the fs/8 mixer
uses the complex signal multiplier block with fixed fs/8 sine and cosine term, the output of the multiplier is:
IOUT(t) = (IIN(t)cos(2πfNCOt + δ) – QIN(t)sin(2πfNCOt + δ)) × 2(mixer_gain – 1)
QOUT(t) = (IIN(t)sin(2πfNCOt + δ) + QIN(t)cos(2πfNCOt + δ)) × 2(mixer_gain – 1)
where fCMIX is the fixed mixing frequency selected by cmix(3:0). The mixing combinations are described in
Table 9. The mixer_gain option allows the output signals of the multiplier to reduce by half (6dB). See Mixer Gain
section for details.
Table 9. Coarse Mixer Combinations
Fs/8 Mixer
cmix(3)
Fs/4 Mixer
cmix(2)
Fs/2 Mixer
cmix(1)
–Fs/4 Mixer
cmix(0)
cmix(3:0)
Mixing Mode
0000
0001
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
–
Disabled
Disabled
Disabled
Enabled
Disabled
Disabled
Enabled
Enabled
–
Disabled
Disabled
Enabled
Disabled
Disabled
Enabled
Disabled
Enabled
–
Disabled
Enabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
–
No mixing
–Fs/4
0010
Fs/2
0100
+Fs/4
1000
+Fs/8
1010
–3Fs/8
1100
+3Fs/8
1110
–Fs/8
All others
Not recommended
MIXER GAIN
The maximum output amplitude out of the complex signal multiplier (i.e., FMIX mode or CMIX mode with fs/8
mixer enabled) occurs if IIN(t) and QIN(t) are simultaneously full scale amplitude and the sine and cosine
arguments are equal to 2π x fMIXt + δ (2N-1) x π/4, where N = 1, 2, 3, etc....
sine
cosine
Max output occurs when both
sine and cosine are 0.707
M0221-01
Figure 74. Maximum Output of the Complex Signal Multiplier
With mixer_gain = 1 and both IIN(t) and QIN(t) are simultaneously full scale amplitude, the maximum output
possible out of the complex signal multiplier is 0.707 + 0.707 = 1.414 (or 3dB). This configuration can cause
clipping of the signal and should therefore be used with caution.
With mixer_gain = 0 in config2, the maximum output possible out of the complex signal multiplier is 0.5 x (0.707
+ 0.707) = 0.707 (or -3dB). This loss in signal power is in most cases undesirable, and it is recommended that
the gain function of the QMC block be used to increase the signal by 3 dB to compensate.
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REAL CHANNEL UPCONVERSION
The mixer in the DAC34H84 treats the A, B, C, and D inputs are complex input data and produces a complex
output for most mixing frequencies. The real input data for each channel can be isolated only when the mixing
frequency is set to normal mode or fs/2 mode. Refer to Table 8 for details.
QUADRATURE MODULATION CORRECTION (QMC)
GAIN AND PHASE CORRECTION
The DAC34H84 includes a Quadrature Modulator Correction (QMC) block. The QMC blocks provide a mean for
changing the gain and phase of the complex signals to compensate for any I and Q imbalances present in an
analog quadrature modulator. The block diagram for the QMC block is shown in Figure 75. The QMC block
contains 3 programmable parameters.
Registers qmc_gainA/B(10:0) and qmc_gainC/D(10:0) controls the I and Q path gains and is an 11-bit unsigned
value with a range of 0 to 1.9990 and the default gain is 1.0000. The implied decimal point for the multiplication
is between bit 9 and bit 10.
Register qmc_phaseAB/CD(11:0) control the phase imbalance between I and Q and are a 12-bit values with a
range of –0.5 to approximately 0.49975. The QMC phase term is not a direct phase rotation but a constant that is
multiplied by each "Q" sample then summed into the "I" sample path. This is an approximation of a true phase
rotation in order to keep the implementation simple.
LO feed-through can be minimized by adjusting the DAC offset feature described below.
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qmc_gainA[10:0]
11
16
16
I Data In
(A)
I Data Out
(A)
Σ
12
qmc_phaseAB[11:0]
16
16
Q Data In
(B)
Q Data Out
(B)
11
qmc_gainB[10:0]
qmc_gainC[10:0]
11
16
16
I Data In
(C)
I Data Out
(C)
Σ
12
qmc_phaseCD[11:0]
16
16
Q Data In
(D)
Q Data Out
(D)
11
qmc_gainD[10:0]
B0164-03
Figure 75. QMC Block Diagram
OFFSET CORRECTION
Registers qmc_offsetA(12:0), qmc_offsetB(12:0), qmc_offsetC(12:0) and qmc_offsetD(12:0) can be used to
independently adjust the DC offsets of each channel. The offset values are in represented in 2s-complement
format with a range from –4096 to 4095.
The offset value adds a digital offset to the digital data before digital-to-analog conversion. Since the offset is
added directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offset
values are LSB aligned.
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qmc_offsetA
{–4096, –4095, ..., 4095}
13
16
16
16
16
A Data In
A Data Out
B Data Out
Σ
Σ
B Data In
13
qmc_offsetB
{–4096, –4095, ..., 4095}
qmc_offsetC
{–4096, –4095, ..., 4095}
13
16
16
16
16
C Data In
D Data In
C Data Out
D Data Out
Σ
Σ
13
qmc_offsetD
{–4096, –4095, ..., 4095}
B0165-03
Figure 76. Digital Offset Block Diagram
GROUP DELAY CORRECTION
A complex transmitter system typically is consisted of a DAC, reconstruction filter network, and I/Q modulator.
Besides the gain and phase mismatch contribution, there could also be timing mismatch contribution from each
components. For instance, the timing mismatch could come from the PCB trace length variation between the I
and Q channels and the group delay variation from the reconstruction filter.
This timing mismatch in the complex transmitter system creates phase mismatch that varies linearly with respect
to frequency. To compensate for the I/Q imbalances due to this mismatch, the DAC34H84 has group delay
correction block for each DAC channel. Each DAC channel can adjust its delay through grp_delayA(7:0)
grp_delayB(7:0) grp_delayC(7:0) and grp_delayD(7:0) in register config46 and config47. The maximum delay
ranges from 30ps to 100ps and is dependent on DAC sample clock. Contact TI for specific application
information. Refer to the Group Delay vs Step Code plots in the Typical Characteristics section. The group delay
correction, along with gain/phase correction, can be useful for correcting imbalances in wide-band transmitter
system.
TEMPERATURE SENSOR
The DAC34H84 incorporates a temperature sensor block which monitors the temperature by measuring the
voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation
(SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement
value representing the temperature in degrees Celsius.
The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled
(tsense_sleep = “0” in register config26) a conversion takes place each time the serial port is written or read. The
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data is only read and sent out by the digital block when the temperature sensor is read in tempdata(7:0) in
config6. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the
data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth
SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the
temperature sensor is enabled even when the device is in sleep mode.
In order for the process described above to operate properly, the serial port read from config6 must be done with
an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.
DATA PATTERN CHECKER
The DAC34H84 incorporates a simple pattern checker test in order to determine errors in the data interface. The
main cause of failures is setup/hold timing issues. The test mode is enabled by asserting iotest_ena in register
config1. In test mode the analog outputs are deactivated regardless of the state of TXENA or sif_texnable in
register config3.
The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in
registers config37 through config44. The data pattern key can be modified by changing the contents of these
registers.
The first word in the test frame is determined by a rising edge transition in ISTR or SYNC, depending on the
syncsel_fifoin(3:0) setting in config32. At this transition, the pattern0 word should be input to the data DAB[15:0]
pins, and pattern2 should be input to the data DCD[15:0] pins. Patterns 1, 4, and 5 of DAB[15:0] bus and pattern
3, 6, and 7 of DCD[15:0] bus should follow sequentially on each edge of DATACLK (rising and falling). The
sequence should be repeated until the pattern checker test is disabled by setting iotest_ena back to “0”. It is not
necessary to have a rising ISTR or SYNC edge aligned with every four DATACLK cycle, just the first one to mark
the beginning of the series.
Start cycle again with optional rising edge of ISTR or SYNC
Pattern 0 Pattern 1 Pattern 4 Pattern 5 Pattern 0 Pattern 1 Pattern 4 Pattern 5
DAB[15:0]P/N
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Pattern 2 Pattern 3 Pattern 6 Pattern 7 Pattern 2 Pattern 3 Pattern 6 Pattern 7
[15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0]
DCD[15:0]P/N
DATACLKP/N (DDR)
ISTRP/N
Sync
Option #1
Sync
Option #2
SYNCP/N
T0532-01
Figure 77. IO Pattern Checker Data Transmission Format
The test mode determines if the all the patterns on the two 16-bit LVDS data buses (DAB[15:0]P/N and
DCD[15:0]P/N) were received correctly by comparing the received data against the data pattern key. If any bits in
either of the two 16-bit data buses were received incorrectly, the corresponding bits in iotest_results(15:0) in
register config4 will be set to “1” to indicate bit error location. The user can check the corresponding bit location
on both 16-bit data buses and implement the fix accordingly. Furthermore, the error condition will trigger the
alarm_from_iotest bit in register config5 to indicate a general error in the data interface. When data pattern
checker mode is enabled, this alarm in register config5, bit7 is the only valid alarm. Other alarms in register
config5 are not valid and can be disregarded.
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For instance, pattern0 is programmed to the default of 0x7A7A. If the received Pattern 0 is 0x7A7B, then bit 0 in
iotest_results(15:0) will be set to “1” to indicate an error in bit 0 location. The alarm_from_iotest will also be set to
“1” to report the data transfer error. Note that iotest_results(15:0) does not indicate which of the 16-bit buses has
the error. The user needs to check both 16-bit buses and then narrow down the error from the bit location
information.
The alarms can be cleared by writing 0x0000 to iotest_results(15:0) and “0” to alarm_from_iotest through the
serial interface. The serial interface will read back 0s if there are no errors or if the errors are cleared. The
corresponding alarm bit will remain a “1” if the errors remain.
It is recommended to enable the pattern checker and then run the pattern sequence for 100 or more complete
cycles before clearing the iotest_results(15:0) and alarm_from_iotest. This will eliminate the possibility of false
alarms generated during the setup sequence.
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iotest_pattern0
iotest_pattern1
iotest_pattern2
iotest_pattern3
iotest_pattern4
iotest_pattern5
iotest_pattern6
iotest_pattern7
Pattern 0
Bit-by-Bit Compare
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Pattern 1
Bit-by-Bit Compare
32-Bit
8-Bit
Input
DAB[15:0]
DCD[15:0]
Pattern 2
Bit-by-Bit Compare
iotest_results[15]
16-Bit
Pattern 3
Bit-by-Bit Compare
32-Bit
16-Bit
Input
Bit 15
Results
ISTR
or
SYNC
LVDS
Drivers
Data
Format
Only one
edge needed
Pattern 4
Bit-by-Bit Compare
•
•
•
•
•
•
•
•
•
alarm_from
Pattern 5
Bit-by-Bit Compare
All Bits
Results
16-Bit
DATACLK
iotest_results[0]
Pattern 6
Bit-by-Bit Compare
8-Bit
Input
Bit 0
Results
Pattern 7
Bit-by-Bit Compare
Go back to 0 after cycle or new
rising edge on ISTR or SYNC
Figure 78. DAC34H84 Pattern Check Block Diagram
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PARITY CHECK TEST
The DAC34H84 has a parity check test that enables continuous validity monitoring of the data received by the
DAC. Parity check testing in combination with the data pattern checker offer an excellent solution for detecting
board assembly issues due to missing pad connections.
For the parity check test, an extra parity bit is added to the data bits to ensure that the total number of set bits
(bits with value 1) is even or odd. This simple scheme is used to detect single or any other odd number of data
transfer errors. Parity testing is implemented in the DAC34H84 in two ways: 32-bit parity and dual 16-bit parity.
32-BIT PARITY
In the 32-bit mode the additional parity bit is sourced to the parity input (PARITYP/N) for the 32-bit data transfer
into the DAB[15:0]P/N and DCD[15:0]P/N inputs. This mode is enabled by setting the single_parity_ena bit in
register config1. The input parity value is defined to be the total number of logic 1s on the 33-bit data bus – the
DAB[15:0]P/N inputs, the DCD[15:0]P/N inputs, and the PARITYP/N input. This value, the total number of logic
1s, must match the parity test selected in the oddeven_parity bit in register config1.
For example, if the oddeven_parity bit is set to “1” for odd parity, then the number of 1s on the 33-bit data bus
should be odd. The DAC will check the data transfer through the parity input. If the data received has odd
number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect.
The corresponding alarm for parity error will be set accordingly.
Figure 79 shows the simple XOR structure used to check word parity. Parity is tested independently for data
captured on both rising and falling edges of DATACLK (alarm_Aparity and alarm_Bparity, respectively). Testing
on both edges helps in determining a possible setup/hold issue. Both alarms are captured individually in register
config5.
PARITY
DAB[15:0]
DCD[15:0]
alarm_Aparity
oddeven_parity
alarm_Bparity
Parity Block
DATACLK
B0458-02
Figure 79. DAC34H84 32-Bit Parity Check
DUAL 16-BIT PARITY
In the dual 16-bit mode, each 16-bit LVDS data bus input will be accompanied by a parity bit for error checking.
The DAB[15:0]P/N and ISTRP/N are one 17-bit data path, and the DCD[15:0]P/N and PARITYP/N are another
path. This mode is enabled by setting the dual_parity_ena bit in register config1. The input parity value is defined
to be the total number of logic 1s on each 17-bit data bus. This value, the total number of logic 1s, must match
the parity test selected in the oddeven_parity bit in register config1.
For example, if the oddeven_parity bit is set to “1” for odd parity, then the number of 1s on each 17-bit data bus
should be odd. The DAC will check the data transfer through the parity input. If the data received has odd
number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect.
The corresponding alarm for parity error will be set accordingly.
Figure 80 shows the simple XOR structure used to check word parity. Parity is tested independently for data
captured on both rising and falling edges of DATACLK for each data path (alarm_Aparity, alarm_Bparity,
alarm_Cparity, and alarm_Dparity, respectively). Testing on both edges and both data buses helps in
determining a possible setup/hold issue. All of the alarms are captured individually in register config5.
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In this mode the ISTR signal functions as a parity signal and cannot be used to sync the FIFO pointer
simultaneously. It is recommended to use the SYNC to sync the FIFO pointer. If ISTR has to be used to sync the
FIFO pointer, the ISTR sync can only be possible upon start-up when dual 16-bit parity function is disabled.
Once the initialization is finished, disable the FIFO pointer sync through ISTR (by configuring syncsel_fifoin and
syncsel_fifoout in config32) and enable the dual 16-bit parity function afterwards.
alarm_Aparity
ISTR
oddeven_parity
DAB[15:0]
alarm_Bparity
Parity Block
DATACLK
alarm_Cparity
PARITY
oddeven_parity
DCD[15:0]
alarm_Dparity
Parity Block
DATACLK
B0463-01
Figure 80. DAC34H84 Dual 16-Bit Parity Check
DAC34H84 ALARM MONITORING
The DAC34H84 includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction
scenario. All the alarm events can be accessed either through the config5 register or through the ALARM pin.
Once an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface to
allow further testing. The set of alarms includes the following conditions:
Zero check alarm
•
Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a
shift register, all zeros will cause the input point to be stuck until the next sync event. When this happens a
sync to the FIFO block is required.
FIFO alarms
alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close.
•
–
–
–
alarm_fifo_2away. Pointers are within two addresses of each other.
alarm_fifo_1away. Pointers are within one address of each other.
alarm_fifo_collision. Pointers are equal to each other.
Clock alarms
clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped.
•
–
–
alarm_dacclk_gone. Occurs when the DACCLK has been stopped.
alarm_dataclk_gone. Occurs when the DATACLK has been stopped.
Pattern checker alarm
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•
alarm_from_iotest. Occurs when the input data pattern does not match the pattern key.
PLL alarm
•
alarm_from_pll. Occurs when the PLL is out of lock.
Parity alarms
•
alarm_Aparity: In dual parity mode, alarm indicating a parity error on the A word. In single parity mode, alarm
on the 32-bit data captured on the rising edge of DATACLKP/N.
•
alarm_Bparity: In dual parity mode, alarm indicating a parity error on the B word. In single parity mode, alarm
on the 32-bit data captured on the falling edge of DATACLKP/N.
•
•
alarm_Cparity: In dual parity mode, alarm indicating a parity error on the C word.
alarm_Dparity: In dual parity mode, alarm indicating a parity error on the D word.
To prevent unexpected DAC outputs from propagating into the transmit channel chain, the clock and alarm_
fifo_collision alarms can be set in config2 to shut-off the DAC output automatically regardless of the state of
TXENA or sif_txenable.
Alarm monitoring is implemented as follows:
•
•
•
•
•
Power up the device using the recommended power-up sequence.
Clear all the alarms in config5 by setting them to zeros.
Unmask those alarms that will generate a hardware interrupt through the ALARM pin in config7.
Enable automatic DAC shut-off in register config2 if required.
In the case of an alarm event, the ALARM pin will trigger. If automatic DAC shut-off has been enabled the
DAC outputs will be disabled.
•
•
•
•
•
Read registers config5 to determine which alarm triggered the ALARM pin.
Correct the error condition and re-synchronize the FIFO.
Clear the alarms in config5.
Re-read config5 to ensure the alarm event has been corrected.
Keep clearing and reading config5 until no error is reported.
POWER-UP SEQUENCE
The following startup sequence is recommended to power-up the DAC34H84:
1. Set TXENA low
2. Supply all 1.2V voltages (DACVDD, DIGVDD, CLKVDD and VFUSE) and all 3.3V voltages (AVDD, IOVDD,
and PLLAVDD). The 1.2V and 3.3V supplies can be powered up simultaneously or in any order. There are
no specific requirements on the ramp rate for the supplies.
3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after
the SIF register programming.
4. Toggle the RESETB pin for a minimum 25 ns active low pulse width.
5. Program the SIF registers.
6. Program fuse_sleep (config27, bit<11>) to put the internal fuses to sleep.
7. FIFO configuration needed for synchronization:
(a) Program syncsel_fifoin(3:0) (config32, bit<15:12>) to select the FIFO input pointer sync source.
(b) Program syncsel_fifoout(3:0) (config32, bit<11:8>) to select the FIFO output pointer sync source.
(c) Program syncsel_fifo_input(1:0) (config31, bit<3:2>) to select the FIFO input sync source.
8. Clock divider configuration needed for synchronization:
(a) Program clkdiv_sync_sel (config32, bit<0>) to select the clock divider sync source.
(b) Program clkdiv_sync_ena (config0, bit<2>) to "1" to enable clock divider sync.
(c) For multi-DAC synchronization in PLL mode, program pll_ndivsync_ena (config24, bit<11>) to “1” to
synchronize the PLL N-divider.
9. Provide all LVDS inputs (D[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N and PARITYP/N)
simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed.
(a) For Single Sync Source Mode where either ISTRP/N or SYNCP/N is used to sync the FIFO, a single
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rising edge for FIFO and clock divider sync is recommended. Periodic sync signal is not recommended
due to the non-deterministic latency of the sync signal through the clock domain transfer.
(b) For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used.
(c) For multi-DAC synchronization in PLL mode, the LVDS SYNCP/N signal is used to sync the PLL
N-divider and can be sourced from either the FPGA/ASIC pattern generator or clock distribution circuit as
long as the t(SYNC_PLL) setup and hold timing requirement is met with respect to the reference clock
source at DACCLKP/N pins. The LVDS SYNCP/N signal can be provided at this point.
10. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed
for synchronization:
(a) For Single Sync Source Mode where the clock divider sync source is either ISTRP/N or SYNCP/N, clock
divider syncing must be disabled after DAC34H84 initialization and before the data transmission by
setting clkdiv_sync_ena (config0, bit 2) to “0”.
(b) For Dual Sync Sources Mode, where the clock divider sync source is from the OSTR signal (either from
external OSTRP/N or internal PLL N divider output), the clock divider syncing may be enabled at all time.
(c) Optionally, to prevent accidental syncing of the FIFO when sending the ISTRP/N or SYNCP/N pulse to
other digital blocks such as NCO, QMC, etc, disable FIFO syncing by setting syncsel_fifoin(3:0) and
syncsel_fifoout(3:0) to “0000” after the FIFO input and output pointers are initialized. If the FIFO and
sync remain enabled after initialization, the ISTRP/N or SYNCP/N pulse must occur in ways to not
disturb the FIFO operation. Refer to the INPUT FIFO section for detail.
(d) Disable PLL N-divider syncing by setting pll_ndivsync_ena (config24, bit<11>) to "0".
11. Enable transmit of data by asserting the TXENA pin or set sif_txenable to “1”.
12. At any time, if any of the clocks (i.e DATACLK or DACCLK) is lost or a FIFO collision alarm is detected, a
complete resynchronization of the DAC is necessary. Set TXENABLE low and repeat steps 7 through 11.
Program the FIFO configuration and clock divider configuration per steps 7 and 8 appropriately to accept the
new sync pulse or pulses for the synchronization.
EXAMPLE START-UP ROUTINE
DEVICE CONFIGURATION
fDATA = 614.4MSPS
Interpolation = 2x
Input data = baseband data
fOUT = 122.88MHz
PLL = Enabled
Full Mixer = Enabled
Dual Sync Sources Mode
PLL CONFIGURATION
fREFCLK = 614.4MHz at the DACCLKP/N LVPECL pins
fDACCLK = fDATA x Interpolation = 1228.8MHz
fVCO = 3 x fDACCLK = 3686.4MHz (keep fVCO between 3.3GHz to 4GHz)
PFD = fOSTR = 38.4MHz
N = 16, M = 32, P = 3, single charge pump
pll_vco(5:0) = “100100” (36)
NCO CONFIGURATION
fNCO = 122.88MHz
fNCO_CLK = 1228.8MHz
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freq = fCNO x 2^32 / 1228.8 = 429496730 = 0x1999999A
phaseaddAB(31:0) or phaseaddCD(31:0) = 0x19999999A
NCO SYNC = sif_sync
EXAMPLE START-UP SEQUENCE
Table 10. Example Start-Up Sequence Description
STEP
READ/WRITE
ADDRESS
N/A
VALUE
N/A
DESCRIPTION
1
2
3
4
N/A
N/A
N/A
N/A
Set TXENA Low
N/A
N/A
N/A
N/A
N/A
N/A
Power-up the device
Apply LVPECL DACCLKP/N for PLL reference clock
Toggle RESETB pin
QMC offset and correction enabled, 2x int, FIFO enabled, Alarm enabled,
clock divider sync enabled, inverse sinc filter enabled.
5
6
7
Write
Write
Write
0x00
0x01
0x02
0xF19F
0x040E
0x7052
Single parity enabled, FIFO alarms enabled (2 away, 1 away, and collision).
Output shut-off when DACCLK gone, DATACLK gone, and FIFO collision.
Mixer block with NCO enabled, twos complement.
Output current set to 20mAFS with internal reference and 1.28kohm RBIAS
resistor.
8
9
Write
Write
0x03
0x07
0xA000
0xD8FF
Un-mask FIFO collision, DACCLK-gone, and DATACLK-gone alarms to the
Alarm output.
Program the desired channel A QMC offset value. (Causes Auto-Sync for
QMC AB-Channels Offset Block)
10
11
12
Write
Write
Write
0x08
0x09
0x0A
N/A
N/A
N/A
Program the desired FIFO offset value and channel B QMC offset value.
Program the desired channel C QMC offset value. (Causes Auto-Sync for
QMC CD-Channels Offset Block)
13
14
Write
Write
0x0B
0x0C
N/A
N/A
Program the desired channel D QMC offset value.
Program the desired channel A QMC gain value.
Coarse mixer mode not used. Program the desired channel B QMC gain
value.
15
Write
0x0D
N/A
16
17
Write
Write
0x0E
0x0F
N/A
N/A
Program the desired channel B QMC gain value.
Program the desired channel C QMC gain value.
Program the desired channel AB QMC phase value. (Causes Auto-Sync
QMC AB-Channels Correction Block)
18
19
20
21
Write
Write
Write
Write
0x10
0x11
0x12
0x13
N/A
N/A
N/A
N/A
Program the desired channel CD QMC phase value. (Causes Auto-Sync for
the QMC CD-Channels Correction Block)
Program the desired channel AB NCO phase offset value. (Causes
Auto-Sync for Channel AB NCO Mixer)
Program the desired channel CD NCO phase offset value. (Causes
Auto-Sync for Channel CD NCO Mixer)
22
23
24
25
Write
Write
Write
Write
0x14
0x15
0x16
0x17
0x999A
0x1999
0x999A
0x1999
Program the desired channel AB NCO frequency value
Program the desired channel AB NCO frequency value
Program the desired channel CD NCO frequency value
Program the desired channel CD NCO frequency value
PLL enabled, PLL N-dividers sync enabled, single charge pump, prescaler =
3.
26
Write
0x18
0x2C58
27
28
29
Write
Write
Write
0x19
0x1A
0x1B
0x20F4
0x9000
0x0800
M = 32, N = 16, PLL VCO bias tune = “01”
PLL VCO coarse tune = 36
Internal reference
QMC offset AB, QMC offset CD, QMC correction AB, and QMC correction
CD can be synced by sif_sync or auto-sync from register write
30
31
Write
Write
0x1E
0x1F
0x9999
0x4440
Mixer AB and CD values synced by SYNCP/N. NCO accumulator synced by
SYNCP/N.
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Table 10. Example Start-Up Sequence Description (continued)
STEP
READ/WRITE
ADDRESS
VALUE
DESCRIPTION
FIFO Input Pointer Sync Source = ISTR FIFO Output Pointer Sync Source =
OSTR (from PLL N-divider output) Clock Divider Sync Source = OSTR
32
Write
0x20
0x2400
Provide all the LVDS DATA and DATACLK Provide rising edge FRAMEP/N
and rising edge SYNCP/N to sync the FIFO input pointer and PLL
N-dividers.
33
N/A
N/A
N/A
Read back pll_lfvolt(2:0). If the value is not optimal, adjust pll_vco(5:0) in
0x1A.
34
35
Read
Write
0x18
0x05
N/A
0x0000
Clear all alarms in 0x05.
Read back all alarms in 0x05. Check for PLL lock, FIFO collision,
DACCLK-gone, DATACLK-gone, etc. Fix the error appropriately. Repeat
step 34 and 35 as necessary.
36
Read
0x05
N/A
Sync all the QMC blocks using sif_sync. These blocks can also be synced
via auto-sync through appropriate register writes.
37
Write
0x1F
0x4442
38
39
40
41
42
Write
Write
Write
Write
N/A
0x00
0x1F
0x20
0x18
N/A
0xF19B
0x4448
0x0000
0x2458
N/A
Disable clock divider sync.
Set sif_sync to “0” for the next sif_sync event.
Disable FIFO input and output pointer sync.
Disable PLL N-dividers sync.
Set TXENA high. Enable data transmission.
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LVPECL INPUTS
Figure 81 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the output strobe clock
(OSTRP/N).
CLKVDD
250 Ω
2 kΩ
2 kΩ
DACCLKP
OSTRP
DACCLKN
OSTRN
Internal
Digital In
250 Ω
SLEEP
GND
S0515-01
Figure 81. DACCLKP/N and OSTRP/N Equivalent Input Circuit
Figure 82 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential
ECL/PECL source.
CAC
0.1 μF
+
CLKIN
Differential
ECL
CAC
or
100 Ω
0.1 μF
(LV)PECL
Source
–
CLKINC
RT
RT
150 Ω
150 Ω
S0029-02
Figure 82. Preferred Clock Input Configuration with a Differential ECL/PECL Clock Source
70
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
LVDS INPUTS
The DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, SYNCP/N, PARITYP/N, and ISTRP/N LVDS pairs have the
input configuration shown in Figure 83. Figure 84 shows the typical input levels and common-move voltage used
to drive these inputs.
IOVDD
LVDS
Receiver
Internal Digital In
100 Ω
GND
S0516-01
Figure 83. DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N and PARITYP/N LVDS Input
Configuration
Example
VA
VB
1.4 V
1 V
DAC34H84
LVDS
Receiver
VA, B
100 Ω
400 mV
0 V
VA, B
VA
VCOM = (VA + VB)/2
–400 mV
VB
GND
1
0
Logical Bit
Equivalent
B0459-02
Figure 84. LVDS Data Input Levels
Table 11. Example LVDS Data Input Levels
Resulting Differential
Voltage
Resulting Common-Mode
Voltage
Applied Voltages
Logical Bit Binary
Equivalent
VA
VB
VA,B
VCOM
1.4 V
1.0 V
1.2 V
0.8 V
1.0 V
1.4 V
0.8 V
1.2 V
400 mV
-400 mV
400 mV
-400 mV
1
0
1
0
1.2 V
1.0 V
Copyright © 2011, Texas Instruments Incorporated
71
DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
CMOS DIGITAL INPUTS
Figure 85 shows a schematic of the equivalent CMOS digital inputs of the DAC34H84. SDIO, SCLK, SLEEP and
TXENA have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC34H84. All
the CMOS digital inputs and outputs are referred to the IOVDD2 supply, which can vary from 1.8V to 3.3V. This
facilitates the I/O interface and eliminates the need of level translation. See the specification table for logic
thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ.
IOVDD2
IOVDD2
100 kΩ
SDIO
SCLK
SLEEP
TXENA
400 Ω
400 Ω
Internal
Digital In
Internal
Digital In
SDENB
RESETB
100 kΩ
GND
GND
S0027-04
Figure 85. CMOS Digital Equivalent Input
REFERENCE OPERATION
The DAC34H84 uses a bandgap reference and control amplifier for biasing the full-scale output current. The
full-scale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS through
resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale
output current equals 64 times this bias current and can thus be expressed as:
IOUTFS = 64 x IBIAS = 64 x (VEXTIO / RBIAS ) / 2
The DAC34H84 has a 4-bit coarse gain control coarse_dac(3:0) in the config3 register. Using gain control, the
IOUTFS can be expressed as:
IOUTFS = (coarse_dac + 1)/16 x IBIAS x 64 = (coarse_dac + 1)/16 x (VEXTIO / RBIAS) / 2 x 64
where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of
1.2V. This reference is active when extref_ena = ‘0’ in config27. An external decoupling capacitor CEXT of 0.1 µF
should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be
used for external reference operation. In that case, an external buffer with high impedance input should be
applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be
disabled and overridden by an external reference by setting the extref_ena control bit. Capacitor CEXT may hence
be omitted. Terminal EXTIO thus serves as either input or output node.
The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor RBIAS, programming
coarse_dac(3:0), or changing the externally applied reference voltage.
NOTE
With internal reference, the minimum Rbias resistor value is 1.28kΩ. Resistor value below
1.28kΩ is not recommended sice it will program the full-scale current to go above 30mA
and potentially damages the device.
DAC TRANSFER FUNCTION
The CMOS DACs consist of a segmented array of PMOS current sources, capable of sourcing a full-scale output
current up to 30 mA. Differential current switches direct the current to either one of the complementary output
nodes IOUTP or IOUTN. Complementary output currents enable differential operation, thus canceling out
common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion
components, and increasing signal output power by a factor of two.
72
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage
reference source (+1.2 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to
provide a maximum full-scale output current equal to 64 times IBIAS
The relation between IOUTP and IOUTN can be expressed as:
IOUTFS = IOUTP + IOUTN
.
We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the
output stage is a current source the current flows from the IOUTP and IOUTN pins. The output current flow in
each pin driving a resistive load can be expressed as:
IOUTP = IOUTFS x CODE / 65536
IOUTN = IOUTFS x (65535 – CODE) / 65536
where CODE is the decimal representation of the DAC data input word
For the case where IOUTP and IOUTN drive resistor loads RL directly, this translates into single ended voltages
at IOUTP and IOUTN:
VOUTP = IOUT1 x RL
VOUTN = IOUT2 x RL
Assuming that the data is full scale (65535 in offset binary notation) and the RL is 25 Ω, the differential voltage
between pins IOUTP and IOUTN can be expressed as:
VOUTP = 20mA x 25 Ω = 0.5 V
VOUTN = 0mA x 25 Ω = 0 V
VDIFF = VOUTP – VOUTN = 0.5V
Note that care should be taken not to exceed the compliance voltages at node IOUTP and IOUTN, which would
lead to increased signal distortion.
ANALOG CURRENT OUTPUTS
The DAC34H84 can be easily configured to drive a doubly terminated 50 Ω cable using a properly selected RF
transformer. Figure 86 and Figure 87 show the 50 Ω doubly terminated transformer configuration with 1:1 and 4:1
impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be grounded
to enable a DC current flow. Applying a 20 mA full-scale output current would lead to a 0.5 Vpp for a 1:1
transformer and a 1 Vpp output for a 4:1 transformer. The low dc-impedance between IOUTP or IOUTN and the
transformer center tap sets the center of the ac-signal to GND, so the 1 Vpp output for the 4:1 transformer
results in an output between –0.5 V and +0.5 V.
50 Ω
1:1
IOUTP
RLOAD
50 Ω
100 Ω
AGND
IOUTN
50 Ω
S0517-01
Figure 86. Driving a Doubly Terminated 50 Ω Cable Using a 1:1 Impedance Ratio Transformer
Copyright © 2011, Texas Instruments Incorporated
73
DAC34H84
SLAS751A –MARCH 2011–REVISED JUNE 2011
www.ti.com
100 Ω
4:1
IOUTP
IOUTN
RLOAD
50 Ω
AGND
100 Ω
S0518-01
Figure 87. Driving a Doubly Terminated 50 Ω Cable Using a 4:1 Impedance Ratio Transformer
PACKAGE OPTION ADDENDUM
ORDERABLE
DEVICE
PACKAGE
TYPE
PACKAGE
QUANTITY
LEAD/BALL
FINISH
MSL PEAK
TEMPERATURE
STATUS
Active
PINS
196
ECO PLAN
Green (RoHS & no
DAC34H84IZAY
DAC34H84IZAYR
NFBGA
NFBGA
800
SNAGCU
SNAGCU
MSL3 260C
MSL3 260C
Sb/Br)
Green (RoHS & no
Active
196
1000
Sb/Br)
74
Copyright © 2011, Texas Instruments Incorporated
DAC34H84
www.ti.com
SLAS751A –MARCH 2011–REVISED JUNE 2011
REVISION HISTORY
Changes from Original (March 2011) to Revision A
Page
•
Changed from PRODUCT PREVIEW to PRODUCTION DATA ........................................................................................... 1
Copyright © 2011, Texas Instruments Incorporated
75
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DAC34H84IZAY
DAC34H84IZAYR
PDAC34H84IZAY
ACTIVE
ACTIVE
NFBGA
NFBGA
NFBGA
ZAY
ZAY
ZAY
196
196
196
160
Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
1000
Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
PREVIEW
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC34H84IZAYR
NFBGA
ZAY
196
1000
330.0
24.4
12.35 12.35
2.3
16.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA ZAY 196
SPQ
Length (mm) Width (mm) Height (mm)
341.0 345.9 41.3
DAC34H84IZAYR
1000
Pack Materials-Page 2
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相关型号:
DAC3560CXN
Consumer Circuit, PQCC40, 6 X 6 MM, 0.85 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-220, QFN-40
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