DAC43701DSGTQ1 [TI]
具有 GPIO 触发器的汽车类 8 位、单通道、电压输出、智能 DAC | DSG | 8 | -40 to 125;
| 型号： | DAC43701DSGTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 GPIO 触发器的汽车类 8 位、单通道、电压输出、智能 DAC | DSG | 8 | -40 to 125 触发器 |
| 文件： | 总46页 (文件大小：2426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC53701-Q1, DAC43701-Q1
ZHCSM85 –OCTOBER 2020
DACx3701-Q1 具有非易失性存储器和兼容PMBus™ 且具有GPI 控制功能的I2C
接口的汽车类10 位和8 位电压输出智能DAC
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
汽车级 10 位 DAC53701-Q1 和 8 位 DAC43701-Q1
(DACx3701-Q1) 是具有引脚兼容性的缓冲电压输出智
能数模转换器 (DAC) 系列产品。这些器件功耗极低且
均可采用微型 8 引脚 WSON 封装。DACx3701-Q1 的
功能集与微型封装和低功耗相结合，非常适合汽车尾灯
和制动灯、牌照灯的淡入淡出和适用于车内照明的
PWM 扩展等应用。
– 温度等级1：–40°C 至+125°C，TA
• 1 LSB INL 和DNL（10 位和8 位）
• 宽工作范围
– 电源：1.8V 至5.5V
• 基于通用输入(GPI) 的功能触发
• 兼容PMBus™ 的I2C 接口
– 标准模式、快速模式和快速+ 模式
– 使用广播地址配置的四个从器件地址选项
– 1.62V VIH (VDD = 5.5V)
这些器件具有非易失性存储器 (NVM)、一个内部基
准、一个兼容 PMBus 的 I2C 接口和一个通用输入。
DACx3701-Q1 使用内部基准或以电源作为基准运行，
并提供1.8V 至5.5V 的满量程输出。
• 用户可编程的非易失性存储器(NVM/EEPROM)
– 保存和撤销所有寄存器设置
• 可编程波形生成：方形、三角形和锯齿形
• 使用三角波形和FB 引脚的脉宽调制(PWM) 输出
• 数字压摆率控制
DACx3701-Q1 是智能 DAC 器件，因为它们具有高级
集成特性。凭借强制检测输出、基于 GPI 的功能触
发、PWM 输出和 NVM 功能，智能 DAC 无需使用软
件即可实现系统性能和控制。
• 内部基准
器件信息(1)
• 功耗极低：在1.8V 时为0.2 mA
• 灵活启动：高阻抗或10K-GND
• 微型封装：8 引脚WSON (2mm × 2mm)
封装尺寸（标称值）
器件型号
DAC53701-Q1
DAC43701-Q1
封装
WSON (8)
2.00mm × 2.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• 后灯
• 前灯
• 车内灯
功能方框图
采用DACx3701-Q1 的汽车制动灯
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEW8
DAC53701-Q1, DAC43701-Q1
ZHCSM85 –OCTOBER 2020
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................17
8.5 Programming............................................................ 19
8.6 Register Map.............................................................25
9 Application and Implementation..................................33
9.1 Application Information............................................. 33
9.2 Typical Applications.................................................. 33
10 Power Supply Recommendations..............................38
11 Layout...........................................................................38
11.1 Layout Guidelines................................................... 38
11.2 Layout Example...................................................... 38
12 Device and Documentation Support..........................39
12.1 Documentation Support.......................................... 39
12.2 接收文档更新通知................................................... 39
12.3 支持资源..................................................................39
12.4 Trademarks.............................................................39
12.5 静电放电警告.......................................................... 39
12.6 术语表..................................................................... 39
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 Recommended Operating Conditions ........................4
7.4 Thermal Information ...................................................4
7.5 Electrical Characteristics ............................................5
7.6 Timing Requirements: I2C Standard Mode ................ 7
7.7 Timing Requirements: I2C Fast Mode ........................7
7.8 Timing Requirements: I2C Fast Mode Plus ................8
7.9 Timing Requirements: GPI .........................................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description...................................................10
Information.................................................................... 39
4 Revision History
DATE
REVISION
NOTES
October 2020
*
Initial release.
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English Data Sheet: SLASEW8
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ZHCSM85 –OCTOBER 2020
5 Device Comparison Table
DEVICE
RESOLUTION
10-bit
DAC53701-Q1
DAC43701-Q1
8-bit
6 Pin Configuration and Functions
图6-1. DSG Package, 8-Pin WSON, Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
5
Ground
Input
Ground reference point for all circuitry on the device
External capacitor for the internal LDO. Connect a capacitor (approximately 1.5 µF) between CAP and
AGND.
CAP
4
FB
7
1
8
Input
Input
Voltage-feedback pin
GPI
OUT
General-purpose input
Output
Analog output voltage from DAC
Serial interface clock. This pin must be connected to the supply voltage with an external pullup
resistor.
SCL
2
Input
Data are clocked into or out of the input register. This pin is a bidirectional, and must be connected to
the supply voltage with an external pullup resistor.
SDA
VDD
3
6
Input/output
Power
Analog supply voltage: 1.8 V to 5.5 V
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English Data Sheet: SLASEW8
DAC53701-Q1, DAC43701-Q1
ZHCSM85 –OCTOBER 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–10
–40
–65
MAX
6
UNIT
V
VDD
Supply voltage, VDD to AGND
Digital input(s) to AGND
CAP to AGND
VDD + 0.3
1.65
V
V
VFB to AGND
VDD + 0.3
VDD + 0.3
10
V
VOUT to AGND
V
Current into any pin
Junction temperature
Storage temperature
mA
°C
°C
TJ
150
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
±2000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011
CDM ESD classification level C5
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
1.62
NOM
MAX UNIT
VDD
VIH
VIL
TA
Positive supply voltage to ground (AGND
)
5.5
V
V
V
Digital input high voltage, 1.7 V < VDD ≤5.5 V
Digital input low voltage
0.4
Ambient temperature
125 °C
–40
7.4 Thermal Information
DACx3701-Q1
THERMAL METRIC(1)
DSG (WSON)
UNIT
8 PINS
49
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
50
24.1
1.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
24.1
8.7
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
DAC53701-Q1
DAC43701-Q1
10
8
Resolution
Bits
INL Relative accuracy(1)
1
1
LSB
LSB
–1
–1
DNL Differential nonlinearity(1)
Code 0d into DAC
6
6
12
15
Zero code error
mV
Internal VREF, gain = 4x, VDD = 5.5 V
Zero code error temperature
coefficient
±10
0.25
µV/°C
%FSR
Offset error(2)
0.5
0.5
–0.5
–0.5
Offset error temperature
coefficient(2)
±0.0003
0.25
%FSR/°C
%FSR
Gain error(2)
Gain error temperature
coefficient(2)
±0.0008
%FSR/°C
1.8 V ≤VDD ≺ 2.7 V, code 1023d into DAC,
0.5
0.25
1
–1
no headroom
Full scale error
%FSR
2.7 V ≤VDD ≤5.5 V, code 1023d into DAC,
no headroom
0.5
–0.5
Full scale error temperature
coefficient
±0.0008
%FSR/°C
OUTPUT CHARACTERISTICS
Output voltage
Reference tied to VDD
0
5.5
1
V
RL = Infinite, phase margin = 30°
RL = 5 kΩ, phase margin = 30°
CL
Capacitive load(3)
Load regulation
nF
2
DAC at midscale, –10 mA ≤IOUT ≤10 mA,
VDD = 5.5 V
0.4
10
25
50
mV/mA
VDD = 1.8 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
Short circuit current
mA
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
To VDD (DAC output unloaded, internal reference =
1.21 V), VDD ≥1.21 ☓ gain + 0.2 V
0.2
0.8
V
To VDD (DAC output unloaded, reference tied to VDD
)
Output voltage headroom(1)
To VDD (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at
VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), DAC code
= full scale
%FSR
10
DAC output enabled and DAC code = midscale
DAC output enabled and DAC code = 4d
DAC output enabled and DAC code = 1016d
0.25
0.25
0.26
VOUT dc output impedance
VFB dc output impedance(4)
Ω
DAC output enabled, DAC reference tied to VDD (gain
= 1x) or internal reference (gain = 1.5x or 2x)
160
192
200
240
240
288
ZO
kΩ
DAC output enabled, internal VREF, gain = 3x or 4x
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English Data Sheet: SLASEW8
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ZHCSM85 –OCTOBER 2020
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7.5 Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT + VFB dc output
leakage(3)
At start up, measured when DAC output is disabled
and held at VDD / 2 for VDD = 5.5 V
5
nA
Power supply rejection ratio
(dc)
Internal VREF, gain = 2x, DAC at midscale;
VDD = 5 V ±10%
0.25
8
mV/V
µs
DYNAMIC PERFORMANCE
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V
tsett Output voltage settling time
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V, internal VREF, gain = 4x
12
1
Slew rate
VDD = 5.5 V
V/µs
mV
At startup (DAC output disabled), RL = 5 kΩ,
CL = 200 pF
75
Power-on glitch magnitude
200
250
34
At startup (DAC output disabled), RL = 100 kΩ
DAC output disabled to enabled (DAC registers at zero
scale, RL = 100 kΩ
Output enable glitch
magnitude
mV
0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V
Output noise voltage (peak to
peak)
Vn
µVPP
Internal VREF, gain = 4x, 0.1 Hz to 10 Hz, DAC at
midscale, VDD = 5.5 V
70
Measured at 1 kHz, DAC at midscale, VDD = 5.5 V
0.2
0.7
Output noise density
µV/√Hz
Internal VREF, gain = 4x,, measured at 1 kHz, DAC at
midscale, VDD = 5.5 V
Internal VREF, gain = 4x, 200-mV 50 or 60 Hz sine
wave superimposed on power supply voltage, DAC at
midscale
Power supply rejection ratio
(ac)(4)
dB
–71
±1 LSB change around mid code (including
feedthrough)
Code change glitch impulse
10
15
nV-s
mV
Code change glitch impulse
magnitude
±1 LSB change around mid code (including
feedthrough)
VOLTAGE REFERENCE
Initial accuracy
TA = 25°C
1.212
V
Reference output temperature
coefficient(2)
50 ppm/°C
EEPROM
20000
1000
50
–40°C ≤TA ≤+85°C
TA > 85°C
Endurance(3)
Cycles
Years
TA = 25°C
Data retention
TA = 125°C
20
EEPROM programming write
cycle time(3)
10
20
ms
DIGITAL INPUTS
Digital feedthrough
Pin capacitance
DAC output static at midscale, fast mode plus, SCL
toggling
20
10
nV-s
pF
Per pin
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English Data Sheet: SLASEW8
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7.5 Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
Load capacitor - CAP pin(3)
0.5
15
µF
mA
µA
Normal mode, DACs at full scale, digital pins static
DAC power-down, internal reference power down
0.5
80
0.8
IDD
Current flowing into VDD
(1) Measured with DAC output unloaded. For external reference between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for
8-bit resolution. For internal reference VDD ≥1.21 x gain + 0.2 V, between end-point codes: 8d to 1016d for 10-bit resolution, 2d to
254d for 8-bit resolution.
(2) Measured with DAC output unloaded. For 10-bit resolution, between end-point codes: 8d to 1016d and for 8-bit resolution, between
end-point codes: 2d to 254d.
(3) Specified by design and characterization, not production tested.
(4) Specified with 200-mV headroom with respect to reference value when internal reference is used.
7.6 Timing Requirements: I2C Standard Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and
1.8 V ≤Vpull-up ≤VDD V (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
0.1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
4.7
4
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
4.7
4
µs
µs
0
ns
Data setup time
250
4700
4000
ns
SCL clock low period
ns
SCL clock high period
Clock and data fall time
Clock and data rise time
ns
300
ns
tR
1000
ns
7.7 Timing Requirements: I2C Fast Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and
1.8 V ≤Vpull-up ≤VDD V (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
0.4
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
1.3
0.6
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
0.6
µs
0.6
µs
0
ns
Data setup time
100
1300
600
ns
SCL clock low period
ns
SCL clock high period
Clock and data fall time
Clock and data rise time
ns
300
300
ns
tR
ns
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ZHCSM85 –OCTOBER 2020
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7.8 Timing Requirements: I2C Fast Mode Plus
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and
1.8 V ≤Vpull-up ≤VDD V (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
0.5
0.26
0.26
0.26
0
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
µs
µs
ns
Data setup time
50
ns
SCL clock low period
0.5
µs
SCL clock high period
Clock and data fall time
Clock and data rise time
0.26
µs
120
120
ns
tR
ns
7.9 Timing Requirements: GPI
all input signals are timed from VIL to 70% of VDD. VDD = 1.8 V to 5.5 V and TA = –40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
tGPIOS
2
µs
GPI high time, 1.7 V ≤VDD ≤5.5 V
GPI low time, 1.7 V ≤VDD ≤5.5 V
GPI latency, 1.7 V ≤VDD ≤5.5 V(1)
tGPIOH
2
µs
tGPIDELAY
2
µs
(1) The maximum value specified for GPI latency in the timing table is in addition to 2x SLEW_RATE for margin-high or low operation. The
maximum value for the total latency is (2xSLEW_RATE + GPI Latency).
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8 Detailed Description
8.1 Overview
The 10-bit DAC53701-Q1 and 8-bit DAC43701-Q1 (DACx3701-Q1) are a pin-compatible family of automotive,
buffered voltage-output, smart digital-to-analog converters (DACs). These smart DACs contain nonvolatile
memory (NVM), an internal reference, a PMBus-compatible I2C interface, force-sense output, and a general-
purpose input. The DACx3701-Q1 operate with either an internal reference or with a power supply as the
reference, and provide a full-scale output of 1.8 V to 5.5 V.
These devices communicate through an I2C interface, and support I2C standard mode (100 kbps), fast mode
(400 kbps), and fast mode plus (1 Mbps). These devices also support specific PMBus commands such as turn
on/off, margin high or low, and more. The GPI input can be configured as a power-down trigger, margin-high-low,
and function trigger. The DACx3701-Q1 also include digital slew rate control, and support basic signal
generation such as square, ramp, and sawtooth waveforms. These devices can generate pulse-width modulation
(PWM) output with the combination of the triangular or sawtooth waveform and the FB pin. These features
enable DACx3701-Q1 to go beyond the limitations of a conventional DAC that depends on a processor to
function. Because of processor-less operation and the smart feature set, the DACx3701-Q1 are called smart
DACs.
The DACx3701-Q1have a power-on-reset (POR) circuit that makes sure all the registers start with default or
user-programmed settings using NVM. The DAC output powers on in high-impedance mode (default); this
setting can be programmed to 10kΩ-GND using NVM.
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC) Architecture
The DACx3701-Q1 family of devices consists of string architecture with an output buffer amplifier. 节 8.2 shows
the DAC architecture within the block diagram. This DAC architecture operates from a 1.8-V to 5.5-V power
supply. These devices consume only 0.2 mA of current when using a 1.8-V power supply. The DAC output pin
starts up in high-impedance mode, making these devices an excellent choice for power-supply control
applications. To change the power-up mode to 10kΩ-GND, program the DAC_PDN bit (address: D1h), and load
these bits in the device NVM. The DACx3701-Q1 devices include a smart feature set to enable processor-less
operation and high-integration. The NVM enables a predictable startup. The GPI triggers the DAC output without
the I2C interface in the absence of a processor or when the processor or software fails. The integrated functions
and the FB pin enable PWM output for control applications. The FB pin enables this device to be used as a
programmable comparator. The digital slew rate control and the Hi-Z power-down modes enable a hassle-free
voltage margining and function.
8.3.1.1 Reference Selection and DAC Transfer Function
The device writes the input data to the DAC data registers in straight-binary format. After a power-on or a reset
event, the device sets all DAC registers to the values set in the NVM.
8.3.1.1.1 Power Supply as Reference
By default, the DACx3701-Q1 operate with the power-supply pin (VDD) as a reference. 方程式 1 shows DAC
transfer function when the power-supply pin is used as reference.
DAC _DATA
2N
VOUT
=
ì VDD
(1)
where:
• N is the resolution in bits, either 8 (DAC43701-Q1) or 10 (DAC53701-Q1).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC register.
• DAC_DATA ranges from 0 to 2N –1.
• VDD is used as the DAC reference voltage.
8.3.1.1.2 Internal Reference
The DACx3701-Q1 also contain an internal reference that is disabled by default. Enable the internal reference
by writing 1 to REF_EN (address D1h). The internal reference generates a fixed 1.21-V voltage (typical). Using
DAC_SPAN (address D1h) bits, gain of 1.5x, 2x, 3x, 4x can be achieved for the DAC output voltage (VOUT) 方程
式2 shows DAC transfer function when the internal reference is used.
DAC_DATA
2N
VOUT
=
ì VREF ìGAIN
(2)
where:
• N is the resolution in bits, either 8 (DAC43701-Q1) or 10 (DAC53701-Q1).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC register
• DAC_DATA ranges from 0 to 2N –1.
• VREF is the internal reference voltage = 1.21 V.
• GAIN = 1.5x, 2x, 3x, 4x, based on DAC_SPAN (address D1h) bits.
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8.3.2 General-Purpose Input (GPI)
The GPI pin of DACx3701-Q1 enables processorless operation. The GPI pin can be configured to trigger various
functions as shown in 表 8-1. The GPI_EN bit in the TRIGGER (节 8.6.4) register enables or disables the GPI
input. The GPI_CONFIG field in the CONFIG2 (节8.6.3) register maps the GPI pin to various functions. The GPI
pin is edge-triggered. By default, the GPI pin is not mapped to any operation. When the GPI pin is mapped to a
specific function, the corresponding software bit functionality is disabled to avoid a race condition. When the GPI
is mapped to margin-high or low trigger function, the output changes dynamically, unlike the behavior with I2C-
based programming. All other constraints of the functions are applied to the GPI-based trigger. At power-on, the
device registers the GPI level and executes the associated command. When the GPI toggles after power-on, the
commands are edge-triggered.
表8-1. GPI Configuration
REGISTER NAME
GPI_EN
GPI_CONFIG
PIN EDGE
COMMAND
No Operation (Default)
0
X
X
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Rising
Falling
Power-Up
1
1
1
1
1
1
1
1
000
001
010
011
100
101
110
111
Hi-Z Power-Down
Power-Up
10kΩPower-Down
Margin High Trigger
Margin Low Trigger
Start Function Generation
Stop Function Generation
Start High-Priority Medical Alarm
Stop High-Priority Medical Alarm
Start Medium-Priority Medical Alarm
Stop Medium-Priority Medical Alarm
Start Low-Priority Medical Alarm
Stop Low-Priority Medical Alarm
Enable I2C Slave Address Update
Disable I2C Slave Address Update
D2h, CONFIG2 and
D3h, TRIGGER
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8.3.3 DAC Update
The DAC output pin (OUT) is updated at the end of I2C DAC write frame.
8.3.3.1 DAC Update Busy
The DAC_UPDATE_BUSY bit (address D0h) is set to 1 by the device when certain DAC update operations,
such as function generation, transition to margin high or low, or any of the medical alarms are in progress. When
the DAC_UPDATE_BUSY bit is set to 1, do not write to any of the DAC registers. After the DAC update
operation is completed (DAC_UPDATE_BUSY = 0), any of the DAC registers can be written.
8.3.4 Nonvolatile Memory (EEPROM or NVM)
The DACx3701-Q1 contain nonvolatile memory (NVM) bits. These memory bits are user programmable and
erasable, and retain the set values in the absence of a power supply. All the register bits, as shown in 表 8-2,
can be stored in the device NVM by setting NVM_PROG = 1 (address D3h). The NVM_BUSY bit (address D0h)
is set to 1 by device when a NVM write or reload operation is ongoing. During this time, the device blocks all
write operations to the device. The NVM_BUSY bit is set to 0 after the write or reload operation is complete; at
this point, all write operations to the device are allowed. The default value for all the registers in the DACx3701-
Q1 is loaded from NVM as soon as a POR event is issued. Do not perform a read operation from the DAC
register while NVM_BUSY = 1.
The DACx3701-Q1 also implement NVM_RELOAD bit (address D3h). Set this bit to 1 for the device to start an
NVM reload operation. After the operation is complete, the device autoresets this bit to 0. During the
NVM_RELOAD operation, the NVM_BUSY bit is set to 1.
表8-2. NVM Programmable Registers
REGISTER ADDRESS
REGISTER NAME
BIT ADDRESS
BIT NAME
DEVICE_LOCK
13
11:9
8:5
CODE_STEP
SLEW_RATE
D1h
GENERAL_CONFIG
4:3
DAC_PDN
2
REF_EN
1:0
DAC_SPAN
15:14
13:11
5:4
SLAVE_ADDRESS
GPI_CONFIG
D2h
CONFIG2
INTERBURST_TIME
PULSE_OFF_TIME
PULSE_ON_TIME
GPI_EN
3:2
1:0
D3h
10h
25h
26h
TRIGGER
10
DAC_DATA
11:2
11:4
11:4
DAC_DATA
DAC_MARGIN_HIGH
DAC_MARGIN_LOW
MARGIN_HIGH (8 most significant bits)
MARGIN_LOW (8 most significant bits)
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8.3.4.1 NVM Cyclic Redundancy Check
The DACx3701-Q1 implement a cyclic redundancy check (CRC) feature for the device NVM to make sure that
the data stored in the device NVM is uncorrupted. There are two types of CRC alarm bits implemented in
DACx3701-Q1:
• NVM_CRC_ALARM_USER
• NVM_CRC_ALARM_INTERNAL
The NVM_CRC_ALARM_USER bit indicates the status of user-programmable NVM bits, and the
NVM_CRC_ALARM_INTERNAL bit indicates the status of internal NVM bits The CRC feature is implemented by
storing a 10-Bit CRC (CRC-10-ATM) along with the NVM data each time NVM program operation (write or
reload) is performed and during the device start up. The device reads the NVM data and validates the data with
the stored CRC. The CRC alarm bits (NVM_CRC_ALARM_USER and NVM_CRC_ALARM_INTERNAL address
D0h) report any errors after the data are read from the device NVM.
8.3.4.2 NVM_CRC_ALARM_USER Bit
A logic 1 on NVM_CRC_ALARM_USER bit indicates that the user-programmable NVM data are corrupt. During
this condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be
written to or read from. To reset the alarm bits to 0, issue a software reset (see 节 8.3.7) command, or cycle
power to the DAC. A power cycle also reloads the user-programmable NVM bits.
8.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
A logic 1 on NVM_CRC_ALARM_INTERNAL bit indicates that the internal NVM data are corrupt. During this
condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be written
to or read from. In case of a temporary failure, to reset the alarm bits to 0, issue a software reset (see 节 8.3.7)
command or cycle power to the DAC.
8.3.5 Programmable Slew Rate
When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new
code following the slew rate and settling time specified in 节 7.5. The slew rate control feature allows the user to
control the rate at which the output voltage (VOUT) changes. When this feature is enabled (using
SLEW_RATE[3:0] bits), the DAC output changes from the current code to the code in MARGIN_HIGH (address
25h) or MARGIN_LOW (address 26h) registers (when margin high or low commands are issued to the DAC)
using the step and rate set in CODE_STEP and SLEW_RATE bits. With the default slew rate control setting
(CODE_STEP and SLEW_RATE bits, address D1h), the output changes smoothly at a rate limited by the output
drive circuitry and the attached load. Using this feature, the output steps digitally at a rate defined by bits
CODE_STEP and SLEW_RATE on address D1h. SLEW_RATE defines the rate at which the digital slew
updates; CODE_STEP defines the amount by which the output value changes at each update. 表8-3 and 表8-4
show different settings for CODE_STEP and SLEW_RATE.
When the slew rate control feature is used, the output changes happen at the programmed slew rate. This
configuration results in a staircase formation at the output. Do not write to CODE_STEP, SLEW_RATE, or
DAC_DATA during the output slew.
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表8-3. Code Step
REGISTER ADDRESS
AND NAME
CODE_STEP[2]
CODE_STEP[1]
CODE_STEP[0]
COMMENT
Code step size = 1 LSB
(default)
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Code step size = 2 LSB
Code step size = 3 LSB
Code step size = 4 LSB
Code step size = 6 LSB
Code step size = 8 LSB
Code step size = 16 LSB
Code step size = 32 LSB
D1h, GENERAL_CONFIG
表8-4. Slew Rate
REGISTER ADDRESS
SLEW_RATE[3]
SLEW_RATE[2]
SLEW_RATE[1]
SLEW_RATE[0]
COMMENT
AND NAME
25.6 µs
(per step)
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
25.6 µs × 1.25
(per step)
0
0
0
1
1
1
0
1
1
0
0
1
25.6 µs × 1.50
(per step)
25.6 µs × 1.75
(per step)
204.8 µs
(per step)
204.8 µs × 1.25
(per step)
204.8 µs × 1.50
(per step)
D1h, GENERAL_CONFIG
819.2 µs
(per step)
0
1
1
1
0
0
1
0
0
1
0
1
1638.4 µs (per step)
2457.6 µs
(per step)
3276.8 µs
(per step)
1
1
0
0
1
1
0
1
4915.2 µs
(per step)
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
12 µs (per step)
8 µs (per step)
4 µs (per step)
No slew (default)
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8.3.6 Power-on-Reset (POR)
The DACx3701-Q1 family of devices includes a power-on reset (POR) function that controls the output voltage at
power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to
initialize to default values, and communication with the device is valid only after a 30-ms, POR delay. The default
value for all the registers in the DACx3701-Q1 is loaded from NVM as soon as the POR event is issued.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in 图 8-1, in order to make sure that the internal capacitors discharge and reset the
device on power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD
drops to less than 1.65 V, but remains greater than 0.7 V (shown as the undefined region), the device may or
may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When
VDD remains greater than 1.65 V, a POR does not occur.
VDD (V)
5.5 V
Specified supply
voltage range
No power-on reset
1.71 V
1.65 V
Undefined
0.7 V
Power-on reset
0 V
图8-1. Threshold Levels for VDD POR Circuit
8.3.7 Software Reset
To initiate a device software reset event, write the reserved code 1010 to the SW_RESET (address D3h). A
software reset initiates a POR event.
8.3.8 Device Lock Feature
The DACx3701-Q1 implement a device lock feature that prevents an accidental or unintended write to the DAC
registers. The device locks all the registers when the DEVICE_LOCK bit (address D1h) is set to 1. To bypass the
DEVICE_LOCK setting, write 0101 to the DEVICE_UNLOCK_CODE bits (address D3h).
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8.3.9 PMBus Compatibility
The PMBus protocol is an I2C-based communication standard for power-supply management. PMBus contains
standard command codes tailored to power supply applications. TheDACx3701-Q1 implement some PMBus
commands such as Turn Off, Turn On, Margin Low, Margin High, Communication Failure Alert Bit (CML), as well
as PMBUS revision. 图8-2 shows typical PMBus connections. The EN_PMBus bit (Bit 12, address D1h) must be
set to 1 to enable the PMBus protocol.
PMBus-compatible device #1
ALERT
CONTROL
DATA
CLOCK
Alert signal
PMBus-compatible device #2
ALERT
Control signal
CONTROL
Data
DATA
Clock
CLOCK
Optional
Required
PMBus-compatible device #3
ALERT
CONTROL
DATA
CLOCK
图8-2. PMBus Connections
Similar to I2C, PMBus is a variable length packet of 8-bit data bytes, each with a receiver acknowledge, wrapped
between a start and stop bit. The first byte is always a 7-bit slave address followed by a write bit, sometimes
called the even address that identifies the intended receiver of the packet. The second byte is an 8-bit command
byte, identifying the PMBus command being transmitted using the respective command code. After the
command byte, the transmitter either sends data associated with the command to write to the receiver command
register (from most significant byte to least significant byte), or sends a new start bit indicating the desire to read
the data associated with the command register from the receiver. Then the receiver transmits the data following
the same most significant byte first format (see 表8-8).
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8.4 Device Functional Modes
8.4.1 Power Down Mode
The DACx3701-Q1 output amplifier and internal reference can be independently powered down through the
DAC_PDN bits (address D1h). At power up, the DAC output and the internal reference are disabled by default.
In power-down mode, the DAC output (OUT pin) is in a high-impedance state. To change this state to 10kΩ-
AGND (at power up), use the DAC_PDN bits (address D1h).
The DAC power-up state can be programmed to any state (power-down or normal mode) using the NVM. 表 8-5
shows the DAC power-down bits.
表8-5. DAC Power-Down Bits
REGISTER ADDRESS AND NAME
DAC_PDN[1]
DAC_PDN[0]
DESCRIPTION
Power up
0
0
0
1
Power down to 10 kΩ
D1h, GENERAL_CONFIG
Power down to high impedance (HiZ)
(default)
1
1
0
1
Power down to 10 kΩ
8.4.2 Continuous Waveform Generation (CWG) Mode
The DACx3701-Q1 implement a continuous waveform generation feature. To set the device to this mode, set the
START_FUNC_GEN (address D3h) to 1. In this mode, the DAC output pin (OUT) generates a continuous
waveform based on the FUNC_CONFIG bits (address D1h). 表8-6 shows the continuous waveforms that can be
generated in this mode. The frequency of the waveform depends on the resistive and capacitive load on the
OUT pin, high and low codes, and slew rate settings as shown in the following equations.
1
fSQUARE-WAVE
=
2ìSLEW _RATE
(3)
(4)
(5)
1
fTRIANGLE-WAVE
=
≈ MARGIN_HIGH -MARGIN_LOW +1’
CODE _STEP
2ìSLEW _RATEì
∆
÷
«
◊
1
fSAWTOOTH-WAVE
=
≈MARGIN_HIGH-MARGIN_LOW +1’
CODE_STEP
SLEW _RATEì
∆
÷
«
◊
where:
• SLEW_RATE is the programmable DAC slew rate specified in 表8-4.
• MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes.
• CODE_STEP is the programmable DAC step code in 表8-3.
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表8-6. FUNC_CONFIG bits
REGISTER ADDRESS AND NAME
FUNC_CONFIG[1]
FUNC_CONFIG[0]
DESCRIPTION
Generates a triangle wave between
MARGIN_HIGH (address 25h) code to
MARGIN_LOW (address 26h) code with slope
defined by SLEW_RATE (address D1h) bits
0
0
0
Generates Saw-Tooth wave between
MARGIN_HIGH (address 25h) code to
MARGIN_LOW (address 26h) code, with rising
slope defined by SLEW_RATE (address D1h)
bits and immediate falling edge
1
0
1
D1h, GENERAL_CONFIG
Generates Saw-Tooth wave between
MARGIN_HIGH (address 25h) code to
MARGIN_LOW (address 26h) code, with falling
slope defined by SLEW_RATE (address D1h)
bits and immediate rising edge
1
1
Generates a square wave between
MARGIN_HIGH (address 25h) code to
MARGIN_LOW (address 26h) code with pulse
high and low period defined by SLEW_RATE
(address D1h) bits
8.4.3 PMBus Compatibility Mode
The DACx3701-Q1 I2C interface implements some of the PMBus commands. 表 8-7 shows the supported
PMBus commands that are implemented in DACx3701-Q1.The DAC uses MARGIN_LOW (address 26h),
MARGIN_HIGH (address 25h) bits, SLEW_RATE, and CODE_STEP bits (address D1h) for
PMBUS_OPERATION_CMD. The EN_PMBus bit (Bit 12, address D1h) must be set to 1 to enable the PMBus
protocol.
表8-7. PMBus Operation Commands
REGISTER ADDRESS AND NAME
PMBUS_OPERATION_CMD[15:8]
DESCRIPTION
Turn off
00h
80h
94h
A4h
Turn on
01h, PMBUS_OPERATION
Margin low
Margin high
The DACx3701-Q1 also implement PMBus features such as group command protocol and communication time-
out failure. The CML bit (address 78h) indicates a communication fault in the PMBus. This bit is reset by writing
1.
To get the PMBus version, read the PMBUS_VERSION bits (address 98h).
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8.5 Programming
The DACx3701-Q1 devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0), as shown
in the pin diagram of 节 6. The I2C bus consists of a data line (SDA) and a clock line (SCL) with pullup
structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect
to the I2C bus through the open drain I/O pins, SDA and SCL.
The I2C specification states that the device that controls communication is called a master, and the devices that
are controlled by the master are called slaves. The master device generates the SCL signal. The master device
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device
on an I2C bus is typically a microcontroller or digital signal processor (DSP). The DACx3701-Q1 family operates
as a slave device on the I2C bus. A slave device acknowledges master commands, and upon master control,
receives or transmits data.
Typically, theDACx3701-Q1 family operates as a slave receiver. A master device writes to the DACx3701-Q1, a
slave receiver. However, if a master device requires the DACx3701-Q1 internal register data, the DACx3701-Q1
operate as a slave transmitter. In this case, the master device reads from the DACx3701-Q1. According to I2C
terminology, read and write refer to the master device.
The DACx3701-Q1 family is a slave and supports the following data transfer modes:
• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast mode plus (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred
to as F/S-mode in this document. The fast mode plus protocol is supported in terms of data transfer speed, but
not output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes.
The DACx3701-Q1 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device
supports the general call reset function. Sending the following sequence initiates a software reset within the
device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the
ACK bit, following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. An acknowledge is when the SDA line is pulled low during
the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high
period of the ninth clock cycle, as shown in 图8-3.
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Data output
by transmitter
Not acknowledge
Data output
by receiver
Acknowledge
2
9
1
8
SCL from
master
S
Clock pulse for
acknowledgement
Start
condition
图8-3. Acknowledge and Not Acknowledge on the I2C Bus
8.5.1 F/S Mode Protocol
The following steps explain a complete transaction in F/S mode.
1. The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图8-4. All I2C-compatible devices
recognize a start condition.
2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in 图
8-5. All devices recognize the address sent by the master and compare the address to the respective
internal fixed address. Only the slave device with a matching address generates an acknowledge by pulling
the SDA line low during the entire high period of the 9th SCL cycle, as shown in Figure 8-3. When the
master detects this acknowledge, the communication link with a slave has been established.
3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
either case, the receiver must acknowledge the data sent by the transmitter. The acknowledge signal can be
generated by the master or by the slave, depending on which is the receiver. The 9-bit valid data sequences
consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.
4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from
low-to-high while the SCL line is high, as shown in 图8-4. This action releases the bus and stops the
communication link with the addressed slave. All I2C-compatible devices recognize the stop condition. Upon
receipt of a stop condition, the bus is released, and all slave devices then wait for a start condition followed
by a matching address.
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SDA
SDA
SCL
SCL
S
P
Start
condition
Stop
condition
Change of data
allowed
Data line stable
Data valid
图8-4. Start and Stop Conditions
图8-5. Bit Transfer on the I2C Bus
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8.5.2 I2C Update Sequence
For a single update, the DACx3701-Q1 require a start condition, a valid I2C address byte, a command byte, and
two data bytes, as listed in 表8-8.
表8-8. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
Address (A) byte
Command byte
节8.5.2.2
Data byte - MSDB
DB [15:8]
Data byte - LSDB
DB [7:0]
节8.5.2.1
DB [31:24]
DB [23:16]
After each byte is received, the DACx3701-Q1 family acknowledges the byte by pulling the SDA line low during
the high period of a single clock pulse, as shown in 图 8-6. These four bytes and acknowledge cycles make up
the 36 clock cycles required for a single update to occur. A valid I2C address byte selects the DACx3701-Q1
devices.
Recognize
START or
REPEATED
Recognize
STOP or
REPEATED
Generate ACKNOWLEDGE
START
START
signal
condition
condition
P
SDA
Sr
MSB
Acknowledgement
signal from Slave
Address
R/W
1
SCL
1
7
8
9
2 - 8
9
Sr
or
P
S
or
Sr
ACK
ACK
START or
REPEATED
START or
STOP
REPEATED
START
condition
Clock line held low while
interrupts are serviced
condition
图8-6. I2C Bus Protocol
The command byte sets the operating mode of the selected DACx3701-Q1 device. For a data update to occur
when the operating mode is selected by this byte, the DACx3701-Q1 device must receive two data bytes: the
most significant data byte (MSDB) and least significant data byte (LSDB). The DACx3701-Q1 device performs
an update on the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 10 kSPS. Using the fast
mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is
received, the DACx3701-Q1 device releases the I2C bus and awaits a new start condition.
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8.5.2.1 Address Byte
The address byte, as shown in 表 8-9, is the first byte received following the start condition from the master
device. The first five bits (MSBs) of the address are factory preset to 10010. The next two bits of the address are
controlled by the SLAVE_ADDRESS field in the CONFIG2 register. Follow the procedure described in the next
section, Slave Address Configuration, to configure the slave address. The possible slave addresses using these
bits are shown in 表8-10.
The DACx3701-Q1 family supports broadcast addressing, which can be used for synchronously updating or
powering down multiple DACx3701-Q1 devices. The DACx3701-Q1 family is designed to work with other
members of the family to support multichip synchronous updates. Using the broadcast address, the DACx3701-
Q1 devices respond regardless of the states of the address pins. Broadcast is supported only in write mode.
表8-9. Address Byte
COMMENT
MSB
LSB
AD6
1
AD5
0
AD4
0
AD3
AD2
0
AD1
AD0
R/ W
—
See TBD Address
Format (slave address
column)
General address
1
0
0 or 1
0
Broadcast address
1
0
0
1
1
1
8.5.2.1.1 Slave Address Configuration
This section provides the step by step procedure to configure the I2C slave addresses for up to four DACs. Use
the broadcast address for all the steps.
1. Set GPI pin to 0b for all devices.
2. Set GPI_CONFIG in the CONFIG2 register to 111b.
3. Set GPI_EN in the TRIGGER register to 1b.
4. Set the GPI pin to logic HIGH for the device that needs to be configured.
5. Write data to SLAVE_ADDRESS bit field in the CONFIG2 register. Only the device with GPI pin logic HIGH
updates the SLAVE_ADDRESS setting passed in the command. Make sure that the rest of the devices on
the same I2C bus have their respective GPI pins set to logic LOW during this process.
6. Toggle the GPI pin of the device bring programmed to logic LOW.
7. Repeat steps (1) through (6) above to program the I2C slave addresses to all the devices on the bus.
8. Set GPI_EN to 0b.
9. Change GPI_CONFIG to 000b.
10. Trigger NVM write operation.
The devices are now ready for use.
表8-10. Address Format
SLAVE_ADDRESS[15:14] in
SLAVE ADDRESS
CONFIG2 Register
1001000
1001001
1001010
1001011
00 (Default)
01
10
11
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8.5.2.2 Command Byte
表8-11 lists the command byte addresses.
表8-11. Command Byte (Register Names)
ADDRESS
REGISTER NAME
D0h
STATUS
D1h
GENERAL_CONFIG
CONFIG2
D2h
D3h
TRIGGER
21h
DAC_DATA
25h
DAC_MARGIN_HIGH
DAC_MARGIN_LOW
PMBUS_OP
26h
01h
78h
PMBUS_STATUS_BYTE
PMBUS_VERSION
98h
8.5.3 I2C Read Sequence
To read any register the following command sequence must be used:
1. Send a start or repeated start command with a slave address and the R/ W bit set to 0 for writing. The device
acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the slave address and the R/ W bit set to 1 for reading. The device acknowledges
this event.
4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register.
An alternative reading method allows for reading back the value of the last register written. The sequence is a
start or repeated start with the slave address and the R/ W bit set to 1, and the two bytes of the last register are
read out.
The broadcast address cannot be used for reading.
表8-12. Read Sequence
R/ W
(0)
R/ W
(1)
S
MSB
ACK MSB
LSB ACK Sr MSB
ACK MSB
LSB
ACK
MSB
LSB
ACK
…
…
…
…
…
ADDRESS
BYTE
节8.5.2.1
COMMAND
BYTE
节8.5.2.2
ADDRESS
BYTE
节8.5.2.1
Sr
MSDB
From Slave
LSDB
From Master
Slave
From Master
Slave
From Master
Slave
Master
From Slave
Master
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8.6 Register Map
表8-13. Register Map
MOST SIGNIFICANT DATA BYTE (MSDB)
LEAST SIGNIFICANT DATA BYTE (LSDB)
ADDRESS
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
NVM_CRC_ NVM_CRC_
DAC_
UPDATE_
BUSY
D0h
ALARM_
USER
ALARM_
INTERNAL
NVM_BUSY
X(1)
DEVICE_ID
VERSION_ID
DEVICE_
LOCK
D1h
D2h
FUNC_CONFIG
SLAVE_ADDRESS
EN_PMBUS
CODE_STEP
GPI_EN
SLEW_RATE
DAC_PDN
REF_EN
DAC_SPAN
GPI_CONFIG
RESERVED
DEVICE_
CONFIG_
RESET
START_
FUNC_
GEN
PMBUS_
MARGIN_
HIGH
PMBUS_
MARGIN_
LOW
NVM_
RELOAD
NVM_
PROG
D3h
DEVICE_UNLOCK_CODE
X
SW_RESET
21h
25h
26h
01h
78h
98h
X
X
X
DAC_DATA[9:0] (10-Bit) or DAC_DATA[7:0] (8-Bit)
X
X
X
MARGIN_HIGH[9:0] (10-Bit) or MARGIN_HIGH[7:0] (8-Bit)
MARGIN_LOW[9:0] (10-Bit) or MARGIN_LOW[7:0] (8-Bit)
PMBUS_OPERATION_CMD
N/A
N/A
X
CML
N/A
PMBUS_VERSION
(1) X = Don't care.
表8-14. Register Names
ADDRESS
D0h
REGISTER NAME
SECTION
节8.6.1
节8.6.2
节8.6.3
节8.6.4
节8.6.5
节8.6.6
节8.6.7
节8.6.8
节8.6.9
节8.6.10
STATUS
GENERAL_CONFIG
CONFIG2
D1h
D2h
D3h
TRIGGER
21h
DAC_DATA
25h
DAC_MARGIN_HIGH
DAC_MARGIN_LOW
PMBUS_OPERATION
PMBUS_STATUS_BYTE
PMBUS_VERSION
26h
01h
78h
98h
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表8-15. Access Type Codes
Access Type
Code
Description
X
X
Don't care
Read Type
R
R
W
Read
Write Type
W
Write
Reset or Default Value
-n
Value after reset or the default value
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8.6.1 STATUS Register (address = D0h) [reset = 000Ch or 0014h]
图8-7. STATUS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NVM_CRC_
ALARM_
USER
NVM_CRC_
ALARM_
INTERNAL
NVM_
BUSY
DAC_
UPDATE_
BUSY
X
DEVICE_ID
VERSION_ID
R-0h
R-0h
R-0h
R-0h
X-00h
10-bit: R-0Ch
8-bit: R-14h
表8-16. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
NVM_CRC_ALARM_USER
NVM_CRC_ALARM_INTERNAL
NVM_BUSY
R
0
0 : No CRC error in user NVM bits
1: CRC error in user NVM bits
14
13
R
R
0
0
0 : No CRC error in internal NVM
1: CRC error in internal NVM bits
0 : NVM write or load completed, Write to DAC registers
allowed
1 : NVM write or load in progress, Write to DAC registers
not allowed
12
DAC_UPDATE_BUSY
R
0
0 : DAC outputs updated, Write to DAC registers allowed
1 : DAC outputs update in progress, Write to DAC
registers not allowed
11 - 6
5 - 2
1 - 0
X
X
R
00h
Don't care
DEVICE_ID
VERSION_ID
DAC53701-Q1:
0Ch
DAC43701-Q1:
14h
DAC53701-Q1: 0Ch
DAC43701-Q1: 14h
8.6.2 GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
图8-8. GENERAL_CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FUNC_
DEVICE_
LOCK
EN_
PMBUS
CODE_STEP
SLEW_RATE
R/W-Fh
DAC_PDN
REF_EN DAC_SPAN
CONFIG
R/ W-0h
W-0h
R/W-0h
R/W-0h
R/W-2h
R/W-0h R/W-0h
表8-17. GENERAL_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 14 FUNC_CONFIG
R/W
00
00 : Generates a triangle wave between MARGIN_HIGH
(address 25h) code to MARGIN_LOW (address 26h) code with
slope defined by SLEW_RATE (address D1h) bits.
01: Generates Saw-Tooth wave between MARGIN_HIGH
(address 25h) code to MARGIN_LOW (address 26h) code, with
rising slope defined by SLEW_RATE (address D1h) bits and
immediate falling edge.
10: Generates Saw-Tooth wave between MARGIN_HIGH
(address 25h) code to MARGIN_LOW (address 26h) code, with
falling slope defined by SLEW_RATE (address D1h) bits and
immediate rising edge.
11: Generates a square wave between MARGIN_HIGH (address
25h) code to MARGIN_LOW (address 26h) code with pulse high
and low period defined by SLEW_RATE (address D1h) bits.
13
12
DEVICE_LOCK
EN_PMBUS
W
0
0
0 : Device not locked
1: Device locked, the device locks all the registers. This bit can be
reset (unlock device) by writing 0101 to the
DEVICE_UNLOCK_CODE bits (address D3h)
R/W
0: PMBus mode disabled
1: PMBus mode enabled
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表8-17. GENERAL_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
11 - 9
CODE_STEP
R/W
000
Code step for programmable slew rate control.
000: Code step size = 1 LSB (default)
001: Code step size = 2 LSB
010: Code step size = 3 LSB
011: Code step size = 4 LSB
100: Code step size = 6 LSB
101: Code step size = 8 LSB
110: Code step size = 16 LSB
111: Code step size = 32 LSB
8 - 5
SLEW_RATE
R/W
1111
Slew rate for programmable slew rate control.
0000: 25.6 µs (per step)
0001: 25.6 µs × 1.25 (per step)
0010: 25.6 µs × 1.50 (per step)
0011: 25.6 µs × 1.75 (per step)
0100: 204.8 µs (per step)
0101: 204.8 µs × 1.25 (per step)
0110: 204.8 µs × 1.50 (per step)
0111: 819.2 µs (per step)
1000: 1.6384 ms (per step)
1001: 2.4576 ms (per step)
1010: 3.2768 ms (per step)
1011: 4.9152 ms (per step)
1100: 12 µs (per step)
1101: 8 µs (per step)
1110: 4 µs (per step)
1111: No slew (default)
4 - 3
DAC_PDN
R/W
10
00: Power up
01: Power down to 10K
10: Power down to high impedance (default)
11: Power down to 10K
2
REF_EN
R/W
R/W
0
0: Internal reference disabled, VDD is DAC reference voltage,
DAC output range from 0 to VDD
1: Internal reference enabled, DAC reference = 1.21 V
.
1 - 0
DAC_SPAN
00
Only applicable when internal reference is enabled.
00: Reference to VOUT gain 1.5x
01: Reference to VOUT gain 2x
10: Reference to VOUT gain 3x
11: Reference to VOUT gain 4x
8.6.3 CONFIG2 Register (address = D2h) [reset = 0000h]
图8-9. CONFIG2 Register
15
14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
SLAVE_
ADDRESS
GPI_
CONFIG
RESERVED
RESERVED
R/W-0h
R/W-0h
表8-18. CONFIG2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15 - 14 SLAVE_ADDRESS
0h
AD1-AD0 of device address as per 表8-10
Refer to 表8-1 for the GPI configuration
Always write 0h
13-11
10-0
GPI_CONFIG
RESERVED
0h
RESERV 0h
ED
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8.6.4 TRIGGER Register (address = D3h) [reset = 0008h]
图8-10. TRIGGER Register
15
14
13
12
11
X
10
9
8
7
6
5
4
3
2
1
0
DEVICE_UNLOCK_CODE
GPI_ DEVICE_ START_
PMBUS_
PMBUS_
NVM_
NVM_
SW_RESET
EN
CONFIG_
RESET
FUNC_
GEN
MARGIN_ MARGIN_ RELOAD PROG
HIGH
LOW
W-0h
X-0
h
R/
W-0h
W-0h
W-0h
R/W-0h
R/W-0h
W-0h
W-0h
W-8h
表8-19. TRIGGER Register Field Descriptions
Bit
Field
Type
Reset
0000
0h
Description
15 - 12 DEVICE_UNLOCK_CODE
W
Write 0101 to unlock the device to bypass DEVICE_LOCK bit.
Don't care
11
10
X
X
GPI_EN
R/W
0
0: GPI disabled
1: GPI enabled
9
8
DEVICE_CONFIG_RESET
START_FUNC_GEN
W
W
0
0
0: Device configuration reset not initiated
1: Device configuration reset initiated. All registers loaded with
factory reset values.
0: Continuous waveform generation mode disabled
1: Continuous waveform generation mode enabled, device
generates continuous waveform based on FUNC_CONFIG (D1h),
MARGIN_LOW (address 18h), and SLEW_RATE (address D1h)
bits.
7
6
5
4
PMBUS_MARGIN_HIGH
PMBUS_MARGIN_LOW
NVM_RELOAD
R/ W
R/W
W
0
0
0
0
0: PMBus margin high command not initiated
1: PMBus margin high command initiated, DAC output margins
high to MARGIN_HIGH code (address 25h). This bit automatically
resets to 0 after the DAC code reaches MARGIN_HIGH value.
0: PMBus margin low command not initiated
1: PMBus margin low command initiated, DAC output margins
low to MARGIN_LOW code (address 26h). This bit automatically
resets to 0 after the DAC code reaches MARGIN_LOW value.
0: NVM reload not initiated
1: NVM reload initiated, applicable DAC registers loaded with
corresponding NVM. NVM_BUSY bit set to 1 which this operation
is in progress.. This bit is self-resetting.
NVM_PROG
W
0: NVM write not initiated
1: NVM write initiated, NVM corresponding to applicable DAC
registers loaded with existing register settings. NVM_BUSY bit
set to 1 which this operation is in progress. This bit is self-
resetting.
3 - 0
SW_RESET
W
1000
1000: Software reset not initiated
1010: Software reset initiated, DAC registers loaded with
corresponding NVMs, all other registers loaded with default
settings.
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8.6.5 DAC_DATA Register (address = 21h) [reset = 0000h]
图8-11. DAC_DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
DAC_DATA[9:0] / DAC_DATA[7:0] –MSB Left aligned
X-0h
W-000h
X-0h
表8-20. DAC_DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-2
X
X
0h
Don't care
DAC_DATA[9:0] / DAC_DATA[7:0]
W
000h
Writing to the DAC_DATA register forces the respective DAC
channel to update the active register data to the DAC_DATA.
Data are in straight binary format and use the following format:
DACx3701-Q1: { DATA[9:0] }
DACx3701-Q1: { DATA[7:0], X, X }
X = Don’t care bits
1-0
X
X
0h
Don't care
8.6.6 DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]
图8-12. DAC_MARGIN_HIGH Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
MARGIN_HIGH[9:0] / MARGIN_HIGH[7:0] –MSB Left aligned
X-0h
W-000h
X-0h
表8-21. DAC_MARGIN_HIGH Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-2
X
X
0h
Don't care
MARGIN_HIGH[9:0] /
MARGIN_HIGH[7:0] –MSB Left
aligned
W
000h
Margin high code for DAC output.
Data are in straight binary format and use the following format:
DACx3701-Q1: { MARGIN_HIGH[[9:0] }
DACx3701-Q1: { MARGIN_HIGH[[7:0], X, X }
X = Don’t care bits
1-0
X
X
0h
Don't care
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8.6.7 DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]
图8-13. DAC_MARGIN_LOW Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
MARGIN_LOW[9:0] / MARGIN_LOW[7:0] –MSB Left aligned
X-0h
W-000h
X-0h
表8-22. DAC_MARGIN_LOW Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-2
X
X
0h
Don't care
MARGIN_LOW[9:0] /
MARGIN_LOW[7:0] –MSB Left
aligned
W
000h
Margin low code for DAC output.
Data are in straight binary format and follows the format below:
DACx3701-Q1: { MARGIN_LOW[[9:0] }
DACx3701-Q1: { MARGIN_LOW[[7:0], X, X }
X = Don’t care bits
1-0
X
X
0h
Don't care
8.6.8 PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
图8-14. PMBUS_OPERATION Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PMBUS_OPERATION_CMD
R/ W-00h
X
X-00h
表8-23. PMBUS_OPERATION Register Field Descriptions
Bit
15 - 8
Field
Type
Reset
Description
PMBUS_OPERATION_CMD
R/W
00h
PMBus operation commands
00h: Turn off
80h: Turn on
A4h: Margin high, DAC output margins high to MARGIN_HIGH
code (address 25h)
94h: Margin low, DAC output margins low to MARGIN_LOW code
(address 26h)
7 - 0
X
X
00h
Not applicable
8.6.9 PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
图8-15. PMBUS_STATUS_BYTE Register
15
14
13
12
11
10
9
8
7
6
5
4
X
3
2
1
0
X
CML
X-00h
R/W-0h
X-000h
表8-24. PMBUS_STATUS_BYTE Register Field Descriptions
Bit
Field
Type
Reset
00h
0
Description
15 - 10
9
X
X
Don't care
CML
R/W
0: No communication Fault
1: PMBus communication fault for timeout, write with incorrect
number of clocks, read before write command, and so more;
reset this bit by writing 1.
8 - 0
X
X
000h
Not applicable
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8.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
图8-16. PMBUS_VERSION Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PMBUS_VERSION
R-22h
X
X-00h
表8-25. PMBUS_VERSION Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 8
7 - 0
PMBUS_VERSION
X
R
22h
PMBus version
Not applicable
X
00h
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9 Application and Implementation
备注
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The DACx3701 are buffered, force-sense output, single-channel, DACs that include an NVM and internal
reference and are available in a tiny 3-mm × 3-mm package . These DACs are designed for general-purpose
applications in a wide range of end equipment. Some of the most common applications for these devices are
power-supply margining and control, adaptive voltage scaling (AVS), set-and-forget LED biasing in automotive
applications and mobile projectors, general-purpose function generation, medical alarm generation, and
programmable comparator applications (such as smoke detectors, standalone PWM control loops, and offset
and gain trimming in precision circuits).
9.2 Typical Applications
This section explains the design details of three primary applications of DACx3701-Q1: programmable LED
biasing, power-supply margining. and medical alarm generation.
9.2.1 Power-Supply Margining
A power-supply margining or scaling circuit is used to test and trim the output of a power converter. This
example circuit is used to test a system by margining the power supplies, for adaptive voltage scaling, or to
program a desired value at the output. Adjustable power supplies, such as LDOs and DC/DC converters provide
a feedback or adjust input that is used to set the desired output. A precision voltage-output DAC is the best
choice for controlling the power-supply output linearly. 图 9-1 shows a control circuit for a switch-mode power
supply (SMPS) using the DACx3701-Q1. Typical applications of power-supply margining are communications
equipment, enterprise servers, test and measurement, automotive processor modules, and general-purpose
power-supply modules.
图9-1. Power-Supply Margining
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English Data Sheet: SLASEW8
DAC53701-Q1, DAC43701-Q1
ZHCSM85 –OCTOBER 2020
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9.2.1.1 Design Requirements
• Power-supply nominal output: 3.3 V
• Reference voltage of the converter (VFB): 0.6 V
• Margin: ±10% (that is, 2.97 V to 3.63 V)
• DAC output range: 1.8 V
• Nominal current through R1 and R2: 100 µA
9.2.1.2 Detailed Design Procedure
The DACx3701-Q1 features a Hi-Z power-down mode that is set by default at power-up, unless the device is
programmed otherwise using the NVM. When the DAC output is at Hi-Z, the current through R3 is zero and the
SMPS is set at the nominal output voltage of 3.3 V. To have the same nominal condition when the DAC powers
up, bring up the device at the same output as VFB (that is 0.6 V). This configuration makes sure there is no
current through R3 even at power-up. Calculate R1 as (VOUT –VFB) / 100 µA = 27 kΩ.
To achieve ±10% margin-high and margin-low conditions, the DAC must sink or source additional current
through R1. Calculate the current from the DAC (IMARGIN) using 方程式6 as 12 µA.
(6)
where
• IMARGIN is the margin current sourced or sinked from the DAC.
• MARGIN is the percentage margin value divided by 100.
• INOMINAL is the nominal current through R1 and R2.
To calculate the value of R3, first decide the DAC output range, and make sure to avoid the codes near zero-
scale and full-scale for safe operation in the linear region. A DAC output of 20 mV is a safe consideration as the
minimum output, and (1.8 V – 0.6 V –20 mV = 1.18 V) as the maximum output. When the DAC output is at 20
mV, the power supply goes to margin high, and when the DAC output is at 1.18 V, the power supply goes to
margin low. Calculate the value of R3 using 方程式 7 as 48.3 kΩ. Choose a standard resistor value and adjust
the DAC outputs. Choosing R3 = 47 kΩ makes the DAC margin high code as 1.164 V and the DAC margin low
code as 36 mV.
(7)
The DACx3701-Q1 have a slew rate feature that is used to toggle between margin high, margin low, and
nominal outputs with a defined slew rate. See the GENERAL_CONFIG Register Field Descriptions for the slew
rate setting details.
备注
The MARGIN HIGH register value in DACx3701-Q1 results in the MARGIN LOW value at the power
supply output. Similarly, the MARGIN LOW register value in DACx3701-Q1 results in the MARGIN
HIGH value at the power-supply output.
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The pseudocode for getting started with a power-supply control application is as follows:
//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Write DAC code (12-bit aligned) for nominal output
//For a 1.8-V output range, the 10-bit hex code for 0.6 V is 0x0155. With 12-bit alignment, it
becomes 0x0554
WRITE DAC_DATA(0x21), 0x05, 0x54
//Write DAC code (12-bit aligned) for margin-low output at the power supply
//For a 1.8-V output range, the 10-bit hex code for 1.164 V is 0x0296. With 12-bit alignment, it
becomes 0x0A58
WRITE DAC_MARGIN_HIGH(0x25), 0x0A, 0x58
//Write DAC code (12-bit aligned) for margin-high output at the power supply
//For a 1.8-V output range, the 10-bit hex code for 36 mV is 0x14. With 12-bit alignment, it
becomes 0x50
WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x50
//Power-up the device with enable internal reference with 1.5x output span. This will output the
nominal voltage (0.6 V)
//CODE_STEP: 2 LSB, SLEW_RATE: 25.6 µs
WRITE GENERAL_CONFIG(0xD1), 0x12, 0x14
//Trigger margin-low output at the power supply
WRITE TRIGGER(0xD3), 0x00, 0x80
//Trigger margin-high output at the power supply
WRITE TRIGGER(0xD3), 0x00, 0x40
//Write back DAC code (12-bit aligned) for nominal output
WRITE DAC_DATA(0x21), 0x05, 0x54
9.2.2 LED Thermal Foldback
The reliability of LED lights is inversely proportional to the operating temperature. Most LED lighting designs
implement heatsinking for thermal management. However, to improve the life of the LEDs, an active thermal-
foldback loop is needed to avoid over-design of the thermal management components. The daytime running light
(DRL) in automotive lighting remains always on and is exposed to sunlight during daytime. Thermal foldback is a
necessity in DRLs to maximize the LED life. DACx3701-Q1 provides a thermal-foldback loop using the force-
sense output of the DAC. 图9-2 shows a simplified circuit diagram of the LED thermal foldback.
图9-2. LED Thermal Foldback
9.2.2.1 Design Requirements
• LED supply voltage: 12 V
• DAC supply voltage: 5 V
• Temperature range: –20°C to +105°C
• Foldback point: 30°C
• Cut-off temperature: 105°C
• Output type: PWM
• PWM frequency: ~ 200 Hz
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DAC53701-Q1, DAC43701-Q1
ZHCSM85 –OCTOBER 2020
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9.2.2.2 Detailed Design Procedure
Choose a 5-V Zener diode of less than 50 μA of reverse current. The DACx3701-Q1consumes a quiescent
current of around 200 μA. Assume the load current of the DAC to be maximum 500 μA. Thus, the total current
needed for the DAC and the Zener diode is 750 μA. Considering a 2x derating factor, design the circuit for 1.5
mA. Hence, the value of the current limiting resistor RZ is (12 V –5 V) / 1.5 mA = 4.7 kΩ. The worst-case
power dissipation across the Zener diode is (5 V × 1.5 mA) = 7.5 mW. Any standard Zener diode can be used
with this power rating.
Choose a negative temperature coefficient (NTC) thermistor with nominal resistance of 10 kΩ at 25°C. At the
foldback point of 30°C, the resistance of the NTC, RNTC is approximately 7 kΩ. At 105°C, the resistance of the
NTC is approximately 800 Ω. Choose the value of R after simulating the linearity plot along with the correct NTC
part number. For the sake of calculation, take R as 5 kΩ. In this case, VFB is 2.08 V at 25 °C (RNTC = 7 kΩ). For
10-bit resolution and a full-scale output of 5 V, 2.08 V corresponds to the DAC code (2.08 × 1024 / 5) = 426.
Similarly, the LED must be cut off at 105°C that refers to an RNTC of 800 Ω and a corresponding VFB of 4.31 V,
or the DAC code 883. Thus, the margin-high value is 883, or 0x373, and the margin-low value is 426, or 0x1AA.
Configure the FUNC_CONFIG bits to 00b in the GENERAL_CONFIG register to select triangular waveform. Use
方程式4 for calculating the frequency of the triangular waveform. By choosing a CODE_STEP of 6 LSB and
SLEW_RATE of (25.6 μs × 1.25), the frequency of the triangular waveform is 205 Hz.
For voltage output, use an RC filter as shown in 图 9-2. The resistor divider comprised of R1, R2, and R3 define
the voltage below the foldback temperature. This voltage divider is useful in case the maximum LED current is
set below the 100% value.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEW8
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9.2.3 Automotive Brake Light
Automotive brake and tail lights that are not on a local interconnect network (LIN) or controller area network
(CAN) are driven by general-purpose input/output (GPIO) from the body control module. The LEDs are driven by
LED drivers and the dimming is typically controlled by PWM. The DACx3701-Q1 generates PWM output by
appropritely configuring the DAC in triangular function generation mode and applying a voltage to the FB pin. 图
9-3 shows the simplified circuit diagram of an automotive brake light.
图9-3. Automotive Brake Light
9.2.3.1 Design Requirements
• LED supply voltage: 12 V
• DAC supply voltage: 5 V
• PWM frequency: ~ 200 Hz
表9-1. GPI to PWM Mapping
GPI0
GPI1
GPI2
PWM
OFF
70%
60%
40%
30%
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
9.2.3.2 Detailed Design Procedure
节9.2.2.2 explains how to design the VDD circuit and how to configure the PWM frequency. GPI0 is connected
to the GPI pin. Configure the GPI_CONFIG bits to 011b in the CONFIG2 register and GPI_EN bit to 1 in the
TRIGGER register. We can achieve 4 distinct PWM duty cycles as shown in 表9-1 by keeping all the
resistances on the FB pin, i.e. R1, R2, R3, and R4 equal. Choose standard value for R1 = R2 = R3 = R4 = 10 kΩ.
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SLASEW8
DAC53701-Q1, DAC43701-Q1
ZHCSM85 –OCTOBER 2020
www.ti.com.cn
10 Power Supply Recommendations
The DACx3701-Q1 family of devices does not require specific supply sequencing. These devices require a
single power supply, VDD. Use a 0.1-µF decoupling capacitor for the VDD pin. Use a bypass capacitor with a
value approximately 1.5 µF for the CAP pin.
11 Layout
11.1 Layout Guidelines
The DACx3701-Q1 pin configuration separates the analog, digital, and power pins for an optimized layout. For
signal integrity, separate the digital and analog traces, and place decoupling capacitors close to the device pins.
11.2 Layout Example
图11-1 shows an example layout drawing with decoupling capacitors and pullup resistors.
图11-1. Layout Example
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ZHCSM85 –OCTOBER 2020
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Texas, Instruments DAC53701EVM user's guide
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
PMBus™ is a trademark of SMIF, Inc.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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English Data Sheet: SLASEW8
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC43701DSGRQ1
DAC43701DSGTQ1
PDAC53701DSGT
PREVIEW
PREVIEW
ACTIVE
WSON
WSON
WSON
DSG
DSG
DSG
8
8
8
3000 RoHS & Green
NIPDAU
NIPDAU
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
47Q1
47Q1
250
250
RoHS & Green
TBD
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2023
OTHER QUALIFIED VERSIONS OF DAC43701-Q1, DAC53701-Q1 :
Catalog : DAC43701, DAC53701
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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