DAC53204W [TI]
采用 Wafer Chip Scale Package 且具有 I²C、SPI 和高阻态输出的四通道、10 位、VOUT 和 IOUT 智能 DAC;
| 型号： | DAC53204W |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 Wafer Chip Scale Package 且具有 I²C、SPI 和高阻态输出的四通道、10 位、VOUT 和 IOUT 智能 DAC |
| 文件： | 总83页 (文件大小：2978K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC53204W, DAC63204W
ZHCSRA2 –DECEMBER 2022
DACx3204W 采用DSBGA 封装、带自动检测型I2C、SPI 或PMBus® 接口的12 位
和10 位四路电压和电流输出智能DAC
1 特性
2 应用
• 具有灵活配置的可编程电压或电流输出：
– 电压输出：
• 光学模块
• 标准笔记本电脑
• 1LSB DNL
• 1x、1.5x、2x、3x 和4x 增益
– 电流输出：
3 说明
12 位 DAC63204W 和 10 位 DAC53204W
(DACx3204W) 是引脚兼容系列四通道、缓冲型、电压
输出和电流输出智能数模转换器 (DAC)。这些器件支
持高阻态断电模式，并在断电情况下支持高阻态输出。
DAC 输出提供强制检测选项，可用作可编程比较器和
拉电流或灌电流。多功能 GPIO、函数生成和 NVM 使
这些智能 DAC 适用于无处理器的应用和设计重复使
用。这些器件自动检测 I2C、SPI 和 PMBus 接口，并
包含内部基准。
• 1LSB INL 和DNL（8 位）
• ±25μA、±50μA、±125μA、±250μA 输出
范围选项
• 适合所有通道的可编程比较器模式
• 当VDD 关闭时提供高阻抗输出
• 高阻抗和电阻下拉断电模式
• 50MHz SPI 兼容型接口
• 自动检测I2C、SPI 或PMBus® 接口
这些功能集与微型封装和低功耗相结合，使这些智能
DAC 成为电压裕量和调节、偏置和校准用直流设定点
以及波形生成等应用的理想选择。
– 1.62V VIH (VDD = 5.5V)
• 可配置为多种功能的通用输入/输出(GPIO)
• 生成预定义的波形：正弦波、三角形波、锯齿波
• 用户可编程的非易失性存储器(NVM)
• 内部、外部或电源作为基准
器件信息
器件型号
分辨率
12 位
10 位
封装(1)
• 宽工作电压范围：
DAC63204W
DAC53204W
YBH（DSBGA，16）
YBH（DSBGA，16）
– 电源：1.8V 至5.5V
– 温度范围：-40˚C 至+125˚C
• 微型封装：16 引脚DSBGA（1.75mm × 1.75mm）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
CAP
VREF
VDD
LDO
Internal
Reference
Nonvolatile
Memory
MUX
A0/SDI
SCL/SYNC
DAC
Register
DAC
Buffer
DAC
R2
+
OUT0-3
FB0-3
SDA/SCLK
GPIO/SDO
BUF
-
Function Generation
Channel 0-3
R1
AGND
简化版方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASF71
DAC53204W, DAC63204W
ZHCSRA2 –DECEMBER 2022
www.ti.com.cn
内容
6.18 Typical Characteristics: Current Output.................. 21
6.19 Typical Characteristics: Comparator.......................25
6.20 Typical Characteristics: General............................. 26
7 详细说明.......................................................................... 27
7.1 Overview...................................................................27
7.2 Functional Block Diagram.........................................27
7.3 特性说明....................................................................28
7.4 器件功能模式............................................................ 30
7.5 编程...........................................................................47
7.6 Register Map.............................................................55
8 应用和实现.......................................................................74
8.1 Application Information............................................. 74
8.2 Typical Application.................................................... 74
8.3 Power Supply Recommendations.............................77
8.4 布局...........................................................................77
9 器件和文档支持............................................................... 78
9.1 Documentation Support............................................ 78
9.2 接收文档更新通知..................................................... 78
9.3 支持资源....................................................................78
9.4 商标...........................................................................78
9.5 Electrostatic Discharge Caution................................78
9.6 术语表....................................................................... 78
10 机械、封装和可订购信息...............................................78
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 规格................................................................................... 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics: Voltage Output...................5
6.6 Electrical Characteristics: Current Output...................7
6.7 Electrical Characteristics: Comparator Mode..............9
6.8 Electrical Characteristics: General............................10
6.9 Timing Requirements: I2C Standard Mode............... 11
6.10 Timing Requirements: I2C Fast Mode..................... 11
6.11 Timing Requirements: I2C Fast Mode Plus............. 11
6.12 Timing Requirements: SPI Write Operation............12
6.13 Timing Requirements: SPI Read and Daisy
Chain Operation (FSDO = 0).......................................12
6.14 Timing Requirements: SPI Read and Daisy
Chain Operation (FSDO = 1).......................................12
6.15 Timing Requirements: GPIO...................................14
6.16 Timing Diagrams.....................................................14
6.17 Typical Characteristics: Voltage Output.................. 16
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 Pin Configuration and Functions
1
2
3
4
A
B
C
D
VREF
OUT3
OUT2
GPIO/SDO
VDD
AGND
CAP
FB3
FB0
FB2
FB1
SCL/SYNC
A0/SDI
OUT0
OUT1
SDA/SCLK
Not to scale
图5-1. YBH Package, 16-pin DSBGA (Top View)
表5-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
External reference input. Connect a capacitor (approximately 0.1 μF) between VREF and AGND.
Use a pullup resistor to VDD when the external reference is not used. Do not ramp up this pin before
VDD. In case an external reference is used, make sure the reference ramps up after VDD.
A1
VREF
Power
A2
A3
OUT3
OUT2
Output
Output
Analog output voltage from DAC channel 3.
Analog output voltage from DAC channel 2.
General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS.
A4
GPIO/SDO Input/Output For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor. If unused,
connect the GPIO pin to VDD or AGND using an external resistor. This pin can ramp up before VDD.
B1
B2
VDD
FB3
Power
Input
Supply voltage.
Voltage feedback pin for channel 3. In voltage-output mode, connect to OUT3 for closed-loop amplifier
output. In current-output mode, keep the FB3 pin unconnected to minimize leakage current.
Voltage feedback pin for channel 2. In voltage-output mode, connect to OUT2 for closed-loop amplifier
output. In current-output mode, keep the FB2 pin unconnected to minimize leakage current.
B3
FB2
Input
I2C serial interface clock or SPI chip select input. Connect this to the IO voltage using an external
pullup resistor. This pin can ramp up before VDD.
B4
C1
C2
SCL/SYNC
AGND
Output
Ground
Input
Ground reference point for all circuitry on the device.
Voltage feedback pin for channel 0. In voltage-output mode, connect to OUT0 for closed-loop amplifier
output. In current-output mode, keep the FB0 pin unconnected to minimize leakage current.
FB0
Voltage feedback pin for channel 1. In voltage-output mode, connect to OUT1 for closed-loop amplifier
output. In current-output mode, keep the FB1 pin unconnected to minimize leakage current.
C3
C4
D1
FB1
A0/SDI
CAP
Input
Input
Address configuration pin for I2C or serial data input for SPI.
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (节7.5.2.2.1).
For SDI, this pin need not be pulled up or pulled down. This pin can ramp up before VDD.
External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between
CAP and AGND.
Power
D2
D3
OUT0
OUT1
Output
Output
Analog output voltage from DAC channel 0.
Analog output voltage from DAC channel 1.
Bidirectional I2C serial data bus or SPI clock input. Connect this pinto the IO voltage using an external
pullup resistor in I2C mode. This pin can ramp up before VDD.
D4
SDA/SCLK Input/Output
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6 规格
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–10
–40
–65
MAX
6
UNIT
V
VDD
Supply voltage, VDD to AGND
Digital inputs to AGND
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
10
V
VFBX to AGND
V
VOUTX to AGND
V
VREF
External reference, VREF to AGND
Current into any pin except the OUTx, VDD, and AGND pins
Junction temperature
V
mA
°C
°C
TJ
150
Tstg
Storage temperature
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.7
NOM
MAX UNIT
VDD
VREF
VIH
Positive supply voltage to ground (AGND)
External reference to ground (AGND)
Digital input high voltage, 1.7 V < VDD ≤5.5 V
Digital input low voltage
5.5
V
V
1.7
VDD
1.62
V
VIL
0.4
15
V
CCAP
TA
External capacitor on CAP pin
0.5
μF
°C
Ambient temperature
125
–40
6.4 Thermal Information
DACx3204W
YBH (DSBGA)
16 PINS
81.2
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
0.3
20.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
20.3
ΨJB
(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
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6.5 Electrical Characteristics: Voltage Output
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1 ×, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
DAC63204W
DAC53204W
DAC63204W
DAC53204W
12
10
Resolution
Bits
5
1.25
1
–5
INL Integral nonlinearity(1)
LSB
LSB
–1.25
–1
DNL Differential nonlinearity(1)
Code 0d into DAC, external reference, VDD = 5.5 V
6
6
12
Zero-code error(4)
mV
Code 0d into DAC, internal VREF, gain = 4 ×,
VDD = 5.5 V
15
Zero-code error temperature
coefficient(4)
±10
0.3
µV/°C
1.7 V ≤VDD < 2.7 V, VFB pin shorted to VOUT, DAC
code: 32d for 12-bit resolution
0.75
0.5
–0.75
–0.5
Offset error(4) (6)
%FSR
2.7 V ≤VDD ≤5.5 V, VFB pin shorted to VOUT
,
0.25
DAC code: 32d for 12-bit resolution
Offset-error temperature
coefficient(4)
VFB pin shorted to VOUT, DAC code: 32d for 12-bit
resolution, 8d for 10-bit resolution
±0.0003
0.25
%FSR/°C
%FSR
Between end-point codes: 32d to 4064d for 12-bit
resolution, 8d to 1016d for 10-bit resolution
Gain error(4)
0.5
–0.5
Gain-error temperature
coefficient(4)
Between end-point codes: 32d to 4064d for 12-bit
resolution, 8d to 1016d for 10-bit resolution
±0.0008
%FSR/°C
1
1.7 V ≤VDD < 2.7 V, DAC at full-scale
2.7 V ≤VDD ≤5.5 V, DAC at full-scale
–1
Full-scale error(4) (6)
%FSR
0.5
–0.5
Full-scale-error temperature
coefficient(4)
DAC at full-scale
±0.0008
%FSR/°C
OUTPUT
Output voltage
Reference tied to VDD
0
VDD
200
V
RL = infinite, phase margin = 30°
Phase margin = 30°
CL
Capacitive load(2)
pF
1000
VDD = 1.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
15
50
60
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
Short-circuit current
mA
V
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
To VDD (DAC output unloaded, internal reference =
1.21 V), VDD ≥1.21 V ☓ gain + 0.2 V
0.2
0.8
To VDD and to AGND
(DAC output unloaded, external reference at VDD (gain
Output-voltage headroom(2)
= 1 ×), the VREF pin is not shorted to VDD
To VDD and to AGND (ILOAD = 10 mA at VDD = 5.5 V,
ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD
1.8 V), external reference at VDD (gain = 1 ×), the VREF
pin is not shorted to VDD
)
%FSR
=
10
)
DAC output enabled, internal reference (gain = 1.5 ×
or 2 ×) or external reference at VDD (gain = 1 ×), the
VREF pin is not shorted to VDD
400
325
500
400
600
485
ZO
VFB dc output impedance(3)
kΩ
DAC output enabled, internal VREF, gain = 3 × or 4 ×
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6.5 Electrical Characteristics: Voltage Output (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1 ×, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power supply rejection ratio
(dc)
Internal VREF, gain = 2 ×, DAC at midscale,
VDD = 5 V ±10%
0.25
mV/V
DYNAMIC PERFORMANCE
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V
20
25
tsett Output voltage settling time
µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V, internal VREF, gain = 4 ×
Slew rate
VDD = 5.5 V
0.3
75
V/µs
mV
At startup (DAC output disabled)
At startup (DAC output disabled), RL = 100 kΩ
Power-on glitch magnitude
200
DAC output disabled to enabled (DAC registers at zero
scale), RL = 100 kΩ
Output-enable glitch
magnitude
250
50
mV
f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V
Output noise voltage (peak to
peak)
Vn
µVPP
Internal VREF, gain = 4 ×, f = 0.1 Hz to 10 Hz,
DAC at midscale, VDD = 5.5 V
90
f = 1 kHz, DAC at midscale, VDD = 5.5 V
0.35
0.9
Output noise density
µV/√Hz
Internal VREF, gain = 4 ×, f = 1 kHz, DAC at midscale,
VDD = 5.5 V
Internal VREF, gain = 4 ×, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power supply voltage, DAC at
midscale
Power supply rejection ratio
(ac)(3)
-68
dB
±1 LSB change around midscale (including
feedthrough)
Code change glitch impulse
10
15
nV-s
mV
Code change glitch impulse
magnitude
±1 LSB change around midscale (including
feedthrough)
POWER
Normal operation, DACs at full scale, digital pins static,
IDD
Current flowing into VDD(4) (5) external reference at VDD but the VREF pin is not
150
µA/ch
shorted to VDD
(1) Measured with DAC output unloaded. For external reference and internal reference VDD ≥1.21 × gain + 0.2 V, between end-point
codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution.
(2) Specified by design and characterization, not production tested.
(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.
(4) Measured with DAC output unloaded.
(5) The total power consumption is calculated by IDD × (total number of channels powered on) + (sleep-mode current).
(6) When a DAC channel is configured in IOUT mode for long term and then switched to VOUT mode, the VOUT mode can show
parametric drift.
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6.6 Electrical Characteristics: Current Output
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤VDD ≤5.5 V,
±250µA output range, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
8
–1
–1
Bits
LSB
LSB
INL Integral nonlinearity
DNL Differential nonlinearity
DAC codes between 0d and 255d
DAC codes between 0d and 255d
1
1
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and
±250 µA; DAC at midscale
Offset error
±1
%FSR
%FSR
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and
±250 µA; DAC codes between 0d and 255d
Gain error
OUTPUT
±1.3
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and
±250 µA; to VDD and to AGND
Output compliance voltage(1)
400
60
mV
MΩ
ZO
IOUT dc output impedance(2)
DAC at midscale, DAC output kept at VDD/2
Power supply rejection ratio
(dc)
DAC at midscale, all bipolar ranges, VDD changed from
4.5V to 5.5V
0.23
60
LSB/V
DYNAMIC PERFORMANCE
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 1 LSB
at 8-bit resolution, VDD = 5.5 V, common-mode voltage
at OUTx pin is VDD/2
tsett Output current settling time
µs
Output noise current (peak to 0.1 Hz to 10 Hz, DAC at midscale,
Vn
150
1
nAPP
peak)
VDD = 5.5 V, ±250-µA output range
f = 1 kHz, DAC at midscale,
VDD = 5.5 V, ±250-µA output range
Output noise density
nA/√Hz
±250 µA output range, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power-supply voltage, DAC at
midscale
Power supply rejection ratio
(ac)(3)
0.65
LSB/V
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6.6 Electrical Characteristics: Current Output (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤VDD ≤5.5 V,
±250µA output range, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
Normal operation, DACs at full scale, ±25-µA output
range, digital pins static
42
56
50
70
Normal operation, DACs at full scale, ±50-µA output
range, digital pins static
IDD
Current flowing into VDD(3) (4)
µA/ch
Normal operation, DACs at full scale, ±125-µA output
range, digital pins static
98
120
200
Normal operation, DACs at full scale, ±250-µA output
range, digital pins static
167
(1) Measured between DAC codes 0d and 255d.
(2) Specified by design and characterization, not production tested.
(3) The current flowing into VDD does not account for the load current sourced or sinked on the OUTx pins. The VREF pin is connected to
VDD
(4) The total power consumption is calculated by IDD × (total number of channels powered on) + (sleep-mode current).
.
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6.7 Electrical Characteristics: Comparator Mode
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1 × in voltage output mode, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ
to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC PERFORMANCE
1.7 V ≤VDD ≤5.5 V; DAC at midscale,
comparator input at Hi-Z, and DAC operating
with external reference.
Offset error(1) (2)
0
6
mV
mV
–6
VDD = 5.5 V, external reference, TA = 125°C, FB
in Hi-Z mode, DAC at full scale and VFB at 0 V
or DAC at zero scale and VFB at 1.84 V, drift
specified for 10 years of continuous operation
Offset error time drift(1)
4
OUTPUT
VREF connected to VDD, VFB resistor network
connected to ground
0
0
VDD
Input voltage
V
V
VREF connected to VDD, VFB resistor network
disconnected from ground
VDD × (1/3 –1/100)
VOL Logic low output voltage
0.1
10
ILOAD = 100 μA, output in open-drain mode
DYNAMIC PERFORMANCE
DAC at midscale with 10-bit resolution, FB input
at Hi-Z, and transition step at FB node is (VDAC
–2 LSB) to (VDAC + 2 LSB), transition time
measured between 10% and 90% of
tresp Output response time
µs
output, output current of 100 µA, comparator
output configured in push-pull mode, load
capacitor at DAC output is 25 pF
(1) Specified by design and characterization, not production tested.
(2) This specification does not include the total unadjusted error (TUE) of the DAC.
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6.8 Electrical Characteristics: General
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1 × in voltage output mode or ±250µA output range in current output mode, DAC output
pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) in voltage-output mode and capacitive load (CL = 200 pF to
AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
INTERNAL REFERENCE
Initial accuracy
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
1.1979
1.212
1.224
V
Reference output temperature
50 ppm/°C
coefficient(1) (2)
EXTERNAL REFERENCE
VREF input impedance(1) (3)
EEPROM
192
kΩ-ch
20000
1000
50
–40°C ≤TA ≤+85°C
TA = 125°C
Endurance(1)
Cycles
Years
Data retention(1)
TA = 25°C
EEPROM programming write
cycle time(1)
200
ms
Time taken from power valid (VDD ≥1.7 V) to output
valid state (output state as programmed in EEPROM),
0.5-µF capacitor on the CAP pin
Device boot-up time(1)
5
ms
DIGITAL INPUTS
Voltage output mode, DAC output static at midscale,
fast mode plus, SCL toggling
Digital feedthrough
20
10
nV-s
pF
Pin capacitance
Per pin
POWER-DOWN MODE
DAC in sleep mode, internal reference powered down,
external reference at 5.5 V
IDD
IDD
Current flowing into VDD
Current flowing into VDD(1)
28
µA
µA
DAC in sleep mode, internal reference
enabled, additional current through internal reference
10
DAC channels enabled, internal reference enabled,
additional current through internal reference per DAC
channel in voltage-output mode
IDD
Current flowing into VDD(1)
12.5
µA
HIGH-IMPEDANCE OUTPUT
10
nA
nA
DAC in Hi-Z output mode, 1.7 V ≤VDD ≤5.5 V
VDD = 0 V, VOUT ≤1.5 V, decoupling capacitor
between VDD and AGND = 0.1 μF
200
Current flowing into VOUTX and
VFBX
ILEAK
VDD = 0 V, 1.5 V < VOUT ≤5.5 V, decoupling capacitor
between VDD and AGND = 0.1 μF
500
±2
nA
µA
100 kΩbetween VDD and AGND, VOUT ≤1.25 V,
series resistance of 10 kΩat OUT pin
(1) Specified by design and characterization, not production tested.
(2) Measured at –40°C and +125°C and calculated the slope.
(3) Impedances for the DAC channels are connected in parallel.
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6.9 Timing Requirements: I2C Standard Mode
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.7 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
kHz
µs
fSCL
SCL frequency
100
tBUF
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
4.7
4
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
4.7
4
µs
Stop condition setup time
µs
Data hold time
0
ns
Data setup time
250
4700
4000
ns
SCL clock low period
ns
tHIGH
tF
SCL clock high period
ns
Clock and data fall time
300
1000
3.45
3.45
ns
tR
Clock and data rise time
ns
tVDDAT
tVDACK
µs
Data valid time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF
Data valid acknowledge time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF
µs
6.10 Timing Requirements: I2C Fast Mode
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.7 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
kHz
µs
fSCL
SCL frequency
400
tBUF
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
1.3
0.6
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
0.6
µs
Stop condition setup time
0.6
µs
Data hold time
0
ns
Data setup time
100
1300
600
ns
SCL clock low period
ns
tHIGH
tF
SCL clock high period
ns
Clock and data fall time
300
300
0.9
0.9
ns
tR
Clock and data rise time
ns
tVDDAT
tVDACK
µs
Data valid time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF
Data valid acknowledge time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF
µs
6.11 Timing Requirements: I2C Fast Mode Plus
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.7 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
MHz
µs
fSCL
SCL frequency
1
tBUF
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
0.5
0.26
0.26
0.26
0
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
µs
µs
ns
Data setup time
50
ns
SCL clock low period
0.5
µs
SCL clock high period
0.26
µs
Clock and data fall time
120
120
ns
tR
Clock and data rise time
ns
tVDDAT
0.45
µs
Data valid time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF
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all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.7 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
tVDACK
0.45
µs
Data valid acknowledge time, R = 360 Ω, Ctrace = 23 pF, Cprobe = 10 pF
6.12 Timing Requirements: SPI Write Operation
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤VIO ≤5.5 V, 1.7 V ≤VDD ≤5.5 V, and –40°C ≤TA ≤+125°C
MIN
NOM
MAX
UNIT
MHz
ns
fSCLK
Serial clock frequency
SCLK high time
50
tSCLKHIGH
tSCLKLOW
tSDIS
9
9
SCLK low time
ns
SDI setup time
8
ns
tSDIH
SDI hold time
8
ns
tCSS
CS to SCLK falling edge setup time
SCLK falling edge to CS rising edge
CS high time
18
10
50
ns
tCSH
ns
tCSHIGH
ns
Sequential DAC update wait time (time between subsequenct LDAC falling
edges) for same channel
tDACWAIT
2
2
µs
µs
Broadcast DAC update wait time (time between subsequent LDAC falling
edges)
tBCASTWAIT
6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤VIO ≤5.5 V, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and FSDO = 0
MIN
NOM
MAX
UNIT
MHz
ns
fSCLK
Serial clock frequency
1.25
tSCLKHIGH
tSCLKLOW
tSDIS
SCLK high time
350
350
8
SCLK low time
ns
SDI setup time
ns
tSDIH
SDI hold time
8
ns
tCSS
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
SYNC high time
400
400
1
ns
tCSH
ns
tCSHIGH
tSDODLY
µs
300
ns
SCLK rising edge to SDO falling edge, IOL ≤5 mA, CL = 20 pF.
6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤VIO ≤5.5 V, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and FSDO = 1
MIN
NOM
MAX
UNIT
MHz
ns
fSCLK
Serial clock frequency
SCLK high time
2.5
tSCLKHIGH
tSCLKLOW
tSDIS
175
175
8
SCLK low time
ns
SDI setup time
ns
tSDIH
SDI hold time
8
ns
tCSS
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
SYNC high time
300
300
1
ns
tCSH
ns
tCSHIGH
µs
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all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤VIO ≤5.5 V, 1.7 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and FSDO = 1
MIN
NOM
MAX
UNIT
tSDODLY
300
ns
SCLK rising edge to SDO falling edge, IOL ≤5 mA, CL = 20 pF.
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6.15 Timing Requirements: GPIO
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤VIO ≤5.5 V, 1.7 V ≤VDD ≤5.5 V, and –40°C ≤TA ≤+125°C
MIN
2
NOM
MAX
UNIT
µs
tGPIHIGH
tGPILOW
tGPAWGD
tCS2LDAC
tSTP2LDAC
tLDACW
GPI high time
GPI low time
2
µs
LDAC falling edge to DAC update delay(1)
SYNC rising edge to LDAC falling edge
I2C stop bit rising edge to LDAC falling edge
LDAC low time
2
µs
1
1
2
µs
µs
µs
(1) The GPIOs can be configured as a channel-specific or global LDAC function.
6.16 Timing Diagrams
tF
tR
tSUDAT
VIH
VIL
SDA
SCL
...
...
tR
tHDDAT
tF
tHIGH
tVDDAT
VIH
VIL
tHDSTA
S
9th clock pulse
1 / fSCL
1st clock cycle
tLOW
tBUF
... SDA
tSUSTA
tHDSTA
tVDACK
tSUSTO
... SCL
9th clock pulse
Sr
P
S
GPIO/
LDAC
tSTP2LDAC
tLDACW
S: Start bit, Sr: Repeated start bit, P: Stop bit
图6-1. I2C Timing Diagram
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tCSS
tCSH
tCSHIGH
SYNC
SCLK
SDI
tSCLKLOW
tSCLKHIGH
tSDIH
tSDIS
Bit 23
Bit 1
Bit 0
GPIO/
LDAC
tCS2LDAC
tLDACW
图6-2. SPI Write Timing Diagram
tCSHIGH
tCSS
tCSH
SYNC
SCLK
tSCLKLOW tSCLKHIGH
FIRST READ COMMAND
Bit 23
ANY COMMAND
Bit 1
SDI
Bit 22
Bit 0
Bit 23
Bit 23
Bit 0
Bit 0
tSDIS tSDIH
SDO
Bit 1
FSDO = 0
tSDODLY
tSDODZ
DATA FROM FIRST READ COMMAND
SDO
Bit 23
Bit 1 Bit 0
FSDO = 1
tSDODLY
DATA FROM FIRST READ COMMAND
图6-3. SPI Read Timing Diagram
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6.17 Typical Characteristics: Voltage Output
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1 ×, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
5
4
5
4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
Channel 0
Channel 1
Channel 2
Channel 3
Channel 0
Channel 1
Channel 2
Channel 3
32
544
1056 1568 2080 2592 3104 3616 4064
Code
32
544
1056 1568 2080 2592 3104 3616 4064
Code
Internal reference, gain = 4 ×
图6-4. Voltage Output INL vs Digital Input Code
图6-5. Voltage Output INL vs Digital Input Code
5
4
5
4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
CH0 MAX
CH1 MAX
CH2 MAX
CH3 MAX
CH0 MIN
CH0 MAX
CH1 MAX
CH2 MAX
CH3 MAX
CH0 MIN
CH1 MIN
CH2 MIN
CH3 MIN
CH1 MIN
CH2 MIN
CH3 MIN
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
1.8
2.725
3.65
Supply Voltage (V)
4.575
5.5
图6-6. Voltage Output INL vs Temperature
Channel 0
图6-7. Voltage Output INL vs Supply Voltage
1
1
0.8
0.6
0.4
0.2
0
Channel 0
0.8
0.6
0.4
0.2
0
Channel 1
Channel 2
Channel 3
Channel 1
Channel 2
Channel 3
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
32
544
1056 1568 2080 2592 3104 3616 4064
Code
32
544
1056 1568 2080 2592 3104 3616 4064
Code
Internal reference, gain = 4 ×
图6-8. Voltage Output DNL vs Digital Input Code
图6-9. Voltage Output DNL vs Digital Input Code
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1 ×, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
CH0 MAX
CH1 MAX
CH2 MAX
CH3 MAX
CH0 MIN
CH1 MIN
CH2 MIN
CH3 MIN
CH0 MAX
CH1 MAX
CH2 MAX
CH3 MAX
CH0 MIN
CH1 MIN
CH2 MIN
CH3 MIN
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
1.8
2.725
3.65
Supply Voltage (V)
4.575
5.5
图6-10. Voltage Output DNL vs Temperature
图6-11. Voltage Output DNL vs Supply Voltage
1.5
1.2
0.9
0.6
0.3
0
1.5
1.2
0.9
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
-1.5
-0.3
-0.6
-0.9
-1.2
-1.5
Channel 0
Channel 0
Channel 1
Channel 2
Channel 3
Channel 1
Channel 2
Channel 3
0
512 1024 1536 2048 2560 3072 3584 4095
Code
0
512 1024 1536 2048 2560 3072 3584 4095
Code
Internal reference, gain = 4 ×
图6-12. Voltage Output TUE vs Digital Input Code
1.5
图6-13. Voltage Output TUE vs Digital Input Code
1.5
1.2
0.9
0.6
0.3
0
1.2
0.9
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
-1.5
-0.3
-0.6
-0.9
-1.2
-1.5
Channel 0
Channel 1
Channel 2
Channel 3
Channel 0
Channel 1
Channel 2
Channel 3
-40 -25 -10
5
20 35 50 65 80 95 110 125
1.8
2.725
3.65
4.575
5.5
Temperature (C)
Supply Voltage (V)
DAC channels at midscale
图6-14. Voltage Output TUE vs Temperature
DAC channels at midscale
图6-15. Voltage Output TUE vs Supply Voltage
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1 ×, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Channel 0
Channel 1
Channel 2
Channel 3
Channel 0
Channel 1
Channel 2
Channel 3
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
图6-16. Voltage Output Offset Error vs Temperature
图6-17. Voltage Output Gain Error vs Temperature
2.76
2.758
2.756
2.754
2.752
2.75
LDAC (1 V/div)
VOUT (1 LSB/div)
2.748
2.746
2.744
Channel 0
Channel 1
Channel 2
Channel 3
2.742
2.74
-5
-3.75 -2.5 -1.25
0
1.25
2.5
3.75 5
Load Current (mA)
0
10
20
30
40
50
Time (s)
DAC channels at midscale
图6-19. Voltage Output Code-to-Code Glitch - Rising Edge
图6-18. Voltage Output vs Load Current
LDAC (1 V/div)
VOUT (1 LSB/div)
Trigger (1 V/div)
VOUT (1 V/div)
Settling Band (+10% FSR)
Settling Band (-10% FSR)
0
10
20
30
40
50
0
10
20
30
40
50
Time (s)
Time (s)
Zero scale to full scale swing
图6-21. Voltage Output Setting Time: Rising Edge
图6-20. Voltage Output Code-to-Code Glitch: Falling Edge
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1 ×, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
Trigger (1 V/div)
VOUT (1 V/div)
Settling Band (+10% FSR)
Settling Band (-10% FSR)
VDD (1 V/div)
VOUT (15 mV/div)
0
200
400
600
800 1000 1200 1400 1600
Time (s)
0
10
20
30
40
50
Time (s)
DAC in Hi-Z power-down mode
图6-23. Voltage Output Power-On Glitch
Full scale to zero scale swing
图6-22. Voltage Output Setting Time: Falling Edge
CH0 (1 V/div)
CH1 (1 V/div)
CH2 (1 mV/div)
CH3 (1 V/div)
VDD (1 V/div)
VOUT (1 mV/div)
0
5
10
15
20
Time (s)
25
30
35
40
0
200
400
600
800 1000 1200 1400 1600
Time (s)
Channel 2 is resident, all other channels are interferers
DAC at zero scale
图6-24. Voltage Output Power-Off Glitch
图6-25. Voltage Output Channel-to-Channel Crosstalk
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
Internal reference, gain = 4 ×
图6-26. Voltage Output Noise Density
图6-27. Voltage Output Noise Density
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1 ×, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
35
30
25
20
15
10
5
25
20
15
10
5
0
0
-5
-5
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Time (s)
Time (s)
Internal reference, gain = 4 ×, f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
图6-29. Voltage Output Flicker Noise
图6-28. Voltage Output Flicker Noise
10
0
-10
-20
-30
-40
-50
-60
-70
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
图6-30. Voltage Output AC PSRR vs Frequency
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6.18 Typical Characteristics: Current Output
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
Channel 0
Channel 1
Channel 2
Channel 3
CH0 MAX
CH1 MAX
CH2 MAX
CH3 MAX
CH0 MIN
CH1 MIN
CH2 MIN
CH3 MIN
0
32
64
96
128
160
192
224
255
-40 -25 -10
5
20 35 50 65 80 95 110 125
Code
Temperature (C)
图6-31. Current Output INL vs Digital Input Code
图6-32. Current Output INL vs Temperature
1
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
Channel 0
CH0 MAX
CH1 MAX
CH2 MAX
CH3 MAX
CH0 MIN
CH1 MIN
CH2 MIN
CH3 MIN
Channel 1
Channel 2
Channel 3
0
32
64
96
128
Code
160
192
224
255
1.8
2.725
3.65
Supply Voltage (V)
4.575
5.5
图6-34. Current Output DNL vs Digital Input Code
图6-33. Current Output INL vs Supply Voltage
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
CH0 MAX
CH1 MAX
CH2 MAX
CH3 MAX
CH0 MIN
CH0 MAX
CH1 MAX
CH2 MAX
CH3 MAX
CH0 MIN
CH1 MIN
CH2 MIN
CH3 MIN
CH1 MIN
CH2 MIN
CH3 MIN
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
1.8
2.725
3.65
Supply Voltage (V)
4.575
5.5
图6-35. Current Output DNL vs Temperature
图6-36. Current Output DNL vs Supply Voltage
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6.18 Typical Characteristics: Current Output (continued)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
2
1.6
1.2
0.8
0.4
0
2
1.6
1.2
0.8
0.4
0
-0.4
-0.8
-1.2
-1.6
-2
-0.4
-0.8
-1.2
-1.6
-2
Channel 0
Channel 1
Channel 2
Channel 3
Channel 0
Channel 1
Channel 2
Channel 3
0
32
64
96
128
160
192
224
255
-40 -25 -10
5
20 35 50 65 80 95 110 125
Code
Temperature (C)
DAC channels at midscale
图6-38. Current Output TUE vs Temperature
图6-37. Current Output TUE vs Digital Input Code
2
1.5
1.2
0.9
0.6
0.3
0
1.6
1.2
0.8
0.4
0
-0.3
-0.6
-0.9
-1.2
-1.5
-0.4
-0.8
-1.2
-1.6
-2
Channel 0
Channel 0
Channel 1
Channel 2
Channel 3
Channel 1
Channel 2
Channel 3
-40 -25 -10
5
20 35 50 65 80 95 110 125
1.8
2.725
3.65
4.575
5.5
Temperature (C)
Supply Voltage (V)
DAC channels at midscale
图6-39. Current Output TUE vs Supply Voltage
图6-40. Current Output Offset Error vs Temperature
1000
800
600
400
200
0
1.5
1.2
0.9
0.6
0.3
0
-200
-400
-0.3
-0.6
-0.9
-1.2
-1.5
CH0, DAC Code = 0
CH1, DAC Code = 0
CH2, DAC Code = 0
CH3, DAC Code = 0
CH0, DAC Code = 255
CH1, DAC Code = 255
CH2, DAC Code = 255
CH3, DAC Code = 255
-600
-800
Channel 0
Channel 1
Channel 2
Channel 3
-1000
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Load Voltage (V)
Temperature (C)
图6-42. Current Output vs Load Voltage
图6-41. Current Output Gain Error vs Temperature
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6.18 Typical Characteristics: Current Output (continued)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
Trigger (1 V/div)
IOUT (Zoomed, 10A/div)
Settling Band (−1 LSB)
Settling Band (+1 LSB)
Trigger (1 V/div)
IOUT (Zoomed, 10 A/div)
Settling Band (−1 LSB)
Settling Band (+1 LSB)
0
10
20
30
40
50
0
10
20
30
40
50
Time (s)
Time (s)
图6-43. Current Output Settling Time:
图6-44. Current Output Settling Time:
Rising Edge (¼ to ¾ scale)
Falling Edge (¾ to ¼ scale)
VDD ( 1 V/div)
IOUT (40 A/div)
VDD (1 V/div)
IOUT (20 A/div)
0
500
1000
1500
2000
2500 3000
0
500
1000
1500
2000
2500
3000
Time (s)
Time (s)
DAC at mid scale (0 μA) stored in EEPROM
图6-45. Current Output Power-On Glitch
DAC at mid scale (0 μA)
图6-46. Current Output Power-Off Glitch
500
200
100
50
20
10
5
2
1
Channel 1 (100 A/div)
Channel 2 (100 A/div)
Channel 3 (100 A/div)
Channel 4 (0.4 A/div)
0.5
0.2
10 20 30 50 100 200 500 10002000
Frequency (Hz)
10000 30000
0
100 200 300 400 500 600 700 800 900 1000
Time (S)
Channel 4 is resident, all other channels are interferers
图6-48. Current Output AC PSRR vs Frequency
图6-47. Current Output Channel-to-Channel Crosstalk
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6.18 Typical Characteristics: Current Output (continued)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
2
1.8
1.6
1.4
1.2
1
30
25
20
15
10
5
0
0.8
0.6
0.4
0.2
0
-5
-10
-15
-20
-25
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
0
1
2
3
4
5
6
7
8
9
10
Time (s)
f = 0.1 Hz to 10 Hz
图6-50. Current Output Flicker Noise
图6-49. Current Output Noise Density
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6.19 Typical Characteristics: Comparator
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, FBx pin in Hi-Z mode, and DAC outputs
unloaded (unless otherwise noted)
VOUT (1 V/div)
VFB (1 LSB/div)
VOUT (1 V/div)
VFB (1 LSB/div)
0
2
4
6
8
10
0
2
4
6
8
10
Time (s)
Time (s)
Comparator output in push-pull mode
Comparator output in push-pull mode
图6-51. Comparator Response Time: Low‑to‑High Transition
图6-52. Comparator Response Time: High‑to‑Low Transition
6
Channel 0
Channel 1
Channel 2
Channel 3
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
图6-53. Comparator Offset Error vs Temperature
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6.20 Typical Characteristics: General
at TA = 25°C, VDD = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
1.2102
1.210175
1.21015
1.210125
1.2101
1.217
1.216
1.215
1.214
1.213
1.212
1.211
1.21
1.210075
1.21005
1.210025
1.21
1.209
1.208
1.207
1.209975
1.20995
1.8
2.725
3.65
4.575
5.5
Supply Voltage (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
Internal reference
Internal reference
图6-55. Internal Reference vs Supply Voltage
图6-54. Internal Reference vs Temperature
5
4
3
2
1
0
30
27
24
21
18
15
12
9
6
VDD = 1.8 V
VDD = 3.3 V
VDD = 5.5 V
3
0
0.5
3.5
6.5
9.5
12.5
15
-40 -25 -10
5
20 35 50 65 80 95 110 125
External Capacitance on CAP Pin (F)
Temperature (C)
Sleep mode, internal reference disabled
图6-57. Boot-up Time vs Capacitance on CAP pin
图6-56. Power-Down Current vs Temperature
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7 详细说明
7.1 Overview
The 12-bit DAC63204W and 10-bit DAC53204W (DACx3204W) are a pin-compatible family of quad-channel,
buffered, voltage-output and current-output, smart digital-to-analog converters (DACs). The DAC channels are
independently configurable as voltage or current output. The DAC outputs change to Hi-Z when VDD is off. This
feature is useful in voltage-margining applications. These smart DACs contain nonvolatile memory (NVM), an
internal reference, automatically detectable SPI or I2C interface, PMBus-compatibility in I2C mode, force-sense
output, and a general-purpose input. These devices support Hi-Z power-down modes by default, which can be
configured to 10 kΩ-GND or 100 kΩ-GND using the NVM. The DACx3204W have a power-on-reset (POR)
circuit that makes sure all the registers start with default or user-programmed settings using NVM. The
DACx3204W operate with either an internal reference, external reference, or with a power supply as the
reference, and provide a full-scale output of 1.8 V to 5.5 V.
The DACx3204W devices support I2C standard mode (100Kbps), fast mode (400Kbps), and fast mode plus
(1Mbps). The I2C interface can be configured with four target addresses using the A0 pin. These devices also
support specific PMBus commands such as turn on/off, margin high or low, and more. The SPI mode supports a
three-wire interface by default with up to a 50-MHz SCLK input. The GPIO input can be configured as SDO in
the NVM for SPI read capability. The GPIO input can alternatively be configured as the LDAC, PD, STATUS,
FAULT-DUMP, RESET, or PROTECT function.
The DACx3204W also include digital slew rate control, and support standard waveform generation such as sine
and cosine, triangular, and sawtooth waveforms. These devices can generate pulse-width modulation (PWM)
output with the combination of the triangular or sawtooth waveform and the FB pin. The force-sense outputs of
the DAC channels can be used as programmable comparators. The comparator mode allows programmable
hysteresis, latching comparator, window comparator, and fault-dump to the NVM. These features enable the
DACx3204W to go beyond the limitations of a conventional DAC that depends on a processor to function. As a
result of processor-less operation and the smart feature set, the DACx3204W are called smart DACs.
7.2 Functional Block Diagram
图7-1. Functional Block Diagram
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7.3 特性说明
7.3.1 智能数模转换器(DAC) 架构
DACx3204W 器件采用串式架构,每个通道均具有一个电压输出放大器,一个外部 FB 引脚和电压电流转换器。节
7.2 显示了方框图中的DAC 架构，该架构采用1.8V 至5.5V 电源供电。DAC 的内部电压基准为1.21V。有一个选
项可以选择 VREF 引脚上的外部基准或以电源作为基准。电压输出模式使用这三个基准选项之一。电流输出模式
使用内部带隙来生成电流输出。电压和电流输出模式均支持多个可编程输出范围。
DACx3204W 器件在 VDD 关闭时支持高阻态输出，能够在强制电压高达 1.25V 的条件下在输出引脚上保持极低
的泄漏电流。默认情况下，DAC 输出引脚也以高阻抗模式启动，这使得这些器件非常适合电压裕量和调节应用。
要将加电模式更改为10kΩGND 或100kΩGND，需对COMMON-CONFIG 寄存器中相应的VOUT-PDN-X 字段
进行编程，并将这些位加载到器件NVM 中。
DACx3204W 器件支持每个通道的独立比较器模式。相应的FBx 引脚充当比较器的输入。DAC 架构支持使用寄存
器设置反转比较器输出。比较器输出可以是推挽式或开漏式。比较器模式支持使用裕度高 和裕度低 寄存器字段的
可编程迟滞、锁存比较器和窗口比较器。比较器输出可由器件在内部访问。
DACx3204W 器件包括一个智能功能集，可实现无处理器运行和高度集成。NVM 支持可预测的启动。在没有处理
器时，或者处理器或软件出现故障时，GPIO 在没有I2C 接口的情况下触发DAC 输出。集成功能和FBx 引脚可为
控制应用启用 PWM 输出。FBx 引脚使该器件能够用作可编程比较器。数字转换率控制和高阻态断电模式可实现
轻松的电压裕量和调节功能。
7.3.2 数字输入/输出
DACx3204W 有四个数字 IO 引脚，其中包括 I2C、SPI、PMBus 和GPIO 接口。这些器件会在加电后首次成功通
信时自动检测 I2C 和SPI 协议，然后连接到检测到的接口。连接接口协议后，协议中的任何更改都将被忽略。I2C
接口使用 A0 引脚从四个地址选项中进行选择。SPI 接口默认为 3 线接口。此模式下没有回读功能。GPIO 引脚可
在寄存器映射中配置，然后编程到NVM 中作为SDO 引脚。SPI 回读模式比写入模式慢。编程接口引脚为：
• I2C：SCL、SDA、A0
• SPI：SCLK、SDI、SYNC、SDO/GPIO
GPIO 可配置为 SDO 以外的多种功能。这些是 LDAC、PD、STATUS、PROTECT、FAULT-DUMP 和 RESET。
当用作输出时，所有数字引脚都是开漏。因此，必须使用外部电阻器将所有输出引脚上拉至所需的IO 电压。
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7.3.3 Nonvolatile Memory (NVM)
The DACx3204W contain nonvolatile memory (NVM) bits. These memory bits are user programmable and
erasable, and retain the set values in the absence of a power supply. All the register bits, as shown in the
highlighted gray cells in the Register Map section, can be stored in the NVM by setting NVM-PROG = 1 in the
COMMON-TRIGGER register. The NVM-PROG is an autoresetting bit. The default values for all the registers in
the DACx3204W are loaded from NVM as soon as a POR event is issued.
The DACx3204W also implement NVM-RELOAD bit in the COMMON-TRIGGER register. Set this bit to 1 for the
device to start an NVM-reload operation. After completion, the device autoresets the NVM-RELOAD bit to 0.
During the NVM write or reload operation, all read/write operations to the device are blocked. The Electrical
Characteristics: General section provides the timing specification for the NVM write cycle. The processor must
wait for the specified duration before resuming any read or write operation on the SPI or I2C interface.
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7.4 器件功能模式
7.4.1 电压输出模式
通过在 COMMON-CONFIG 寄存器的 VOUT-PDN-X 字段中选择加电选项，并使用同一寄存器中的 IOUT-PDN-X
位同时为各个通道的电流输出选项断电，可以进入每个 DAC 通道的电压输出模式。将相应通道的 OUTx 和 FBx
引脚从外部短接可以实现闭环放大器输出。FBx 引脚开路会使放大器输出饱和。要获得所需的电压输出，请选择
正确的基准选项，为所需的输出范围选择放大器增益，并在相应通道的 DAC-X-DATA 寄存器中对 DAC 代码进行
编程。
7.4.1.1 电压基准和DAC 传递函数
DACx3204W 可以支持以下三种电压基准选项：内部基准、外部基准，以及以电源作为基准，如图 7-2 所示。电
压输出和比较器模式下的DAC 传递函数会根据电压基准选择而变化。
VDD
VREF
Digital
IO
EN-INT-REF
Internal
DIS-MODE-IN
Reference
IOUT-RANGE-X
MUX
VOUT-GAIN-X
VOUT-PDN-X
IOUT-PDN-X
VOUT-PDN-X
+
–
DAC Ladder
OUTx
FBx
IOUT-PDN-X
10k /100k
Internal
Bandgap
R1
R2
CMP-X-HIZ-IN-DIS or
VOUT-PDN-X (Hi-Z)
AGND
图7-2. 电压基准选择与断电逻辑
7.4.1.1.1 Internal Reference
The DACx3204W contain an internal reference that is disabled by default. To enable the internal reference, write
1 to bit EN-INT-REF in the COMMON-CONFIG register. The internal reference generates a fixed 1.21-V voltage
(typical). Use the VOUT-GAIN-X bit in the DAC-X-VOUT-CMP-CONFIG register to achieve gains of 1.5 ×, 2 ×, 3
×, or 4 × for the DAC output voltage (VOUT). 方程式1 shows DAC transfer function using the internal reference.
DAC_DATA
V
=
× V
× GAIN
REF
(1)
OUT
N
2
where:
• N is the resolution in bits, 10 (DAC53204W) or 12 (DAC63204W).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA bit in the DAC-X-
DATA register. DAC_DATA ranges from 0 to 2N –1.
• VREF is the internal reference voltage = 1.21 V (typical).
• GAIN = 1.5 ×, 2 ×, 3 ×, or 4 ×, based on VOUT-GAIN-X bits.
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7.4.1.1.2 External Reference
By default, the DACx3204W operate from an external reference input. The external reference option can also be
selected by configuring the VOUT-GAIN-X field in the DAC-X-VOUT-CMP-CONFIG register appropriately. Write
1 to the DIS-MODE-IN bit in the DEVICE-MODE-CONFIG register to minimize IDD. The external reference can
be between 1.7 V and VDD. 方程式 2 shows DAC transfer function when the external reference is used. The
gain at the output stage of the DAC is always 1 × in the external reference mode.
备注
The external reference must be less than VDD in both transient and steady-state conditions.
Therefore, the external reference must ramp up after VDD and ramp down before VDD.
DAC_DATA
V
=
× V
(2)
OUT
REF
N
2
where:
• N is the resolution in bits, 10 (DAC53204W) or 12 (DAC63204W).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA field in the DAC-
X-DATA register. DAC_DATA ranges from 0 to 2N –1.
• VREF is the external reference voltage.
7.4.1.1.3 Power-Supply as Reference
The DACx3204W can operate with the power-supply pin (VDD) as a reference. 方程式 3 shows DAC transfer
function when the power-supply pin is used as reference. The gain at the output stage is always 1x.
DAC_DATA
V
=
× V
(3)
OUT
DD
N
2
where:
• N is the resolution in bits, 10 (DAC53204W) or 12 (DAC63204W).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA bit in the DAC-X-
DATA register.
• DAC_DATA ranges from 0 to 2N –1.
• VDD is used as the DAC reference voltage.
7.4.2 Current-Output Mode
To enter current-output mode for each DAC channel, disable the respective IOUT-PDN-X bits in the COMMON-
CONFIG register, and set the respective VOUT-PDN-X bits in the same register to Hi-Z power-down mode.
Select the desired current-output range by writing to the IOUT-RANGE-X bit in the DAC-X-IOUT-MISC-CONFIG
register. To minimize leakage in current-output mode, disconnect the FBx pin. For the best power-on glitch
performance, program the NVM with IOUT mode using the smallest output range before powering on the output
channel, and then immediately program the DAC code and desired output range. The transfer function of the
output current is shown in the following equation:
DAC_DATA × I
− I
MIN
MAX
I
=
+ I
(4)
OUT
MIN
8
2
where:
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA bits specified in 节
7.6.8 or the DAC-X-DATA-8BIT bits specified in 节7.6.19. DAC_DATA ranges from 0 to 255.
• IMAX is the signed maximum current in the IOUT-RANGE-X setting specified in 节7.6.5.
• IMIN is the signed minimum current in the IOUT-RANGE-X setting specified in 节7.6.5.
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7.4.3 比较器模式
在电压输出模式下，所有 DAC 通道均可配置为可编程比较器。要进入某个通道的比较器模式，需向相应 DAC-X-
VOUT-CMP-CONFIG 寄存器的 CMP-X-EN 位中写入 1。比较器输出可使用 CMP-X-OD-EN 位配置为推挽或开漏
输出。要启用输出引脚上的比较器输出，需向 CMP-X-OUT-EN 位写入 1。要反转比较器输出，需向 CMP-X-INV-
EN 位写入 1。FBx 引脚具有有限阻抗。默认情况下，FBx 引脚处于高阻抗模式。要禁用 FBx 引脚上的高阻抗，
需向CMP-X-HIZ-IN-DIS 位写入1。表7-1 显示了不同位设置条件下该引脚上的比较器输出。
备注
在高阻态输入模式下，比较器输入范围限制为：
• 对于GAIN = 1x、1.5x 或2x：VFB ≤(VREF × GAIN) / 3
• 对于GAIN = 3x 或4x：VFB ≤(VREF × GAIN) / 6
任何较高的输入电压都会被削波。
表7-1. 比较器输出配置
CMP-X-EN
CMP-X-OUT-EN
CMP-X-OD-EN
CMP-X-INV-EN
CMPX-OUT PIN
比较器未启用
0
1
1
1
1
1
X
0
1
1
1
1
X
X
0
0
1
1
X
X
0
1
0
1
无输出
推挽式输出
推挽和反相输出
开漏输出
开漏和反相输出
图7-3 显示了所有 DAC 通道均配置为比较器时的接口电路。可编程比较器操作如图7-4 所示。在无迟滞、带迟滞
和窗口比较器模式下，可以使用相应 DAC-X-CMP-MODE-CONFIG 寄存器中的 CMP-X-MODE 位来配置各个比
较器通道，如表7-2 所示。
VDD
10 k
0.1 μF
1.5 μF
VDD
CAP
VREF
+
-
+
-
CMP3
CMP2
CMP0
CMP0-OUT
CMP3-OUT
FB3/AIN3
FB0/AIN0
(0 V to VFS/3 or 0 V to VFS
(0 V to VFS/3 or 0 V to VFS
)
)
+
-
+
-
CMP1
CMP1-OUT
CMP2-OUT
FB2/AIN2
FB1/AIN1
(0 V to VFS/3 or 0 V to VFS
)
(0 V to VFS/3 or 0 V to VFS
)
AGND
VIO
10 k
图7-3. 比较器接口
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DAC-X-DATA
FBx/AINx
OUT-X
CMP-X-INV-EN = 0
OUT-X
CMP-X-INV-EN = 1
图7-4. 可编程比较器操作
表7-2. 比较器模式选择
CMP-X-MODE 位字段
比较器配置
00
01
10
11
正常比较器模式。无迟滞或窗口操作。
迟滞比较器模式。DAC-X-MARGIN-HIGH 和DAC-X-MARGIN-LOW 寄存器设置迟滞。
窗口比较器模式。DAC-X-MARGIN-HIGH 和DAC-X-MARGIN-LOW 寄存器设置窗口边界。
无效设置
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7.4.3.1 可编程迟滞比较器
当 CMP-X-MODE 位设置为 01b 时，比较器模式提供迟滞，如表 7-2 所示。迟滞由 DAC-X-MARGIN-HIGH 和
DAC-X-MARGIN-LOW 寄存器提供，如图7-5 所示。
当 DAC-X-MARGIN-HIGH 设置为全代码或 DAC-X-MARGIN-LOW 设置为零代码时，比较器用作锁存比较器，即
在超过阈值后锁存输出。通过写入 COMMON DAC-TRIG 寄存器中相应的 RST-CMP-FLAG-X 位，可以复位锁存
输出。图 7-6 显示了具有低电平有效输出的闭锁比较器的行为，而图 7-7 显示了具有高电平有效输出的闭锁比较
器的行为。
备注
DAC-X-MARGIN-HIGH 寄存器的值必须大于 DAC-X-MARGIN-LOW 寄存器的值。迟滞模式下的比较器
输出只能是同相的，即 DAC-X-VOUT-CMP-CONFIG 寄存器中的 CMP-X-INV-EN 位必须设置为 0。在
锁存模式下，为了使复位生效，输入电压必须在 DAC-X-MARGIN-HIGH 和 DAC-X-MARGIN-LOW 范
围内。
DAC-X-MARGIN-HIGH
Hysteresis
FBx/AINx
DAC-X-MARGIN-LOW
OUT-X
CMP-X-INV-EN = 0
图7-5. 不带锁存输出的可编程迟滞
DAC-X-MARGIN-HIGH
FBx/AINx
DAC-X-MARGIN-LOW
(ZERO-CODE)
OUT-X
CMP-X-INV-EN = 0
RST-CMP-FLAG-X
图7-6. 具有低电平有效输出的闭锁比较器
DAC-X-MARGIN-HIGH
(FULL-CODE)
FBx/AINx
DAC-X-MARGIN-LOW
OUT-X
CMP-X-INV-EN = 0
RST-CMP-FLAG-X
图7-7. 具有高电平有效输出的锁存比较器
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7.4.3.2 Programmable Window Comparator
Window comparator mode is enabled by setting the CMP-X-MODE bit to 10b, as shown in 表 7-2. The window
bounds are set by the DAC-X-MARGIN-HIGH and the DAC-X-MARGIN-LOW registers, as shown in 图 7-8. The
output of the window comparator for a given channel is indicated by the respective WIN-CMP-X bit in the CMP-
STATUS register. The comparator output (WIN-CMP-X) can be latched by writing 1 to the WIN-LATCH-EN bit in
the COMMON-CONFIG register. After being latched, the comparator output can be reset using the
corresponding RST-CMP-FLAG-X bit in the COMMON-DAC-TRIG register. For the reset to take effect, the input
must be within the window bounds.
DAC-X-MARGIN-HIGH
FBx/AINx
DAC-X-MARGIN-LOW
WIN-CMP-X
WIN-LATCH-EN = 0
WIN-CMP-X
WIN-LATCH-EN = 1
RST-CMP-FLAG-X
图7-8. Window Comparator Operation
A single comparator is used per channel to check both the margin-high and margin-low limits of the window.
Therefore, the window comparator function has a finite response time as specified in the Electrical
Characteristics: Comparator Mode section. Also, the static behavior of the WIN-CMP-X bit is not reflected at the
output pins. Set the CMP-X-OUT-EN bit to 0. The WIN-CMP-X bit must be read digitally using the
communication interface. This bit can also be mapped to the GPIO pin, as shown in 表7-19.
备注
• The value of the DAC-X-MARGIN-HIGH register must be greater than that of the DAC-X-MARGIN-
LOW register.
• Set the SLEW-RATE-X bit to 0000b (no-slew) and LOG-SLEW-EN-X bit to 0b in the DAC-X-FUNC-
CONFIG register to get the best response time from the window comparator.
• The CMP-X-OUT-EN bit in the DAC-X-VOUT-CMP-CONFIG register can be set to 0b to eliminate
undesired toggling of the OUT pin.
7.4.4 故障转储模式
DACx3204W 提供了一项功能，可在 FAULT-DUMP 位触发时或映射到故障转储的 GPIO（如表 7-18 所示）时将
几个寄存器内容保存到NVM 中。此功能在系统级故障管理中非常有用，可用于捕获就在故障触发之前的器件或系
统状态，以便在故障发生后进行诊断。故障转储触发时保存的寄存器为：
• CMP-STATUS[7:0]
• DAC-0-DATA[15:8]
• DAC-1-DATA[15:8]
• DAC-2-DATA[15:8]
• DAC-3-DATA[15:8]
备注
在故障转储期间，数据中的任何更改都会破坏最终结果。确保比较器和 DAC 代码在 NVM 写入周期期
间保持稳定。
表7-3 显示了NVM 中寄存器的存储格式。
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表7-3. 故障转储NVM 存储格式
B31-B24
B23-B16
B15-B8
B7-B0
NVM 行
行1
CMP-STATUS[7:0]
DAC-0-DATA[15:8]
不用考虑
DAC-1-DATA[15:8]
DAC-2-DATA[15:8]
DAC-3-DATA[15:8]
行2
故障转储后在NVM 中捕获的数据可按特定顺序读取：
1. 将COMMON-CONFIG 寄存器中的EE-READ-ADDR 位设置为0b，以选择NVM 的行1。
2. 通过向COMMON-TRIGGER 寄存器中的READ-ONE-TRIG 写入1 来触发所选NVM 行的读取；该位会自动
复位。此操作会将数据从选定的NVM 行复制到SRAM 地址0x9D（LSB 16 位来自NVM）和0x9E（MSB 16
位来自NVM）。
3. 要读取SRAM 数据，需按照以下步骤操作：
a. 将0x009D 写入SRAM-CONFIG 寄存器。
b. 从SRAM-DATA 寄存器中读取数据以获得LSB 16 位。
c. 将0x009E 写入SRAM-CONFIG 寄存器。
d. 再次从SRAM-DATA 寄存器读取数据以获得MSB 位。
4. 将COMMON-CONFIG 寄存器中的EE-READ-ADDR 位设置为1b，以选择NVM 的行2。重复步骤2 和3。
7.4.5 应用特定模式
本节详细介绍了DACx3204W 中提供的各个应用特定功能模式。
7.4.5.1 电压裕量和调节
电压裕量和调节是 DACx3204W 的一种主要应用。本节介绍了可用于此类应用的具体功能，例如高阻态输出、转
换率控制、PROTECT 输入和PMBus 兼容性。
7.4.5.1.1 高阻抗输出和PROTECT 输入
当 VDD 关闭时，所有 DAC 输出通道都保持高阻抗状态（高阻态）。图 7-9 显示了在电压裕量调节应用中使用
DACx3204W 的简化原理图。串联电阻器RS 在电压输出模式下是必需的，但在电流输出模式下是可选的。几乎所
有线性稳压器和直流/直流转换器都具有 ≤ 1.25V 的反馈电压。对于 VFB ≤ 1.25V，输出端保持低泄漏电流。因
此，对于所有实际用途，当DAC 的VDD 在电压裕量和调节应用中处于关闭时，DAC 输出显示为高阻态。此功能
允许将DACx3204W 无缝集成到系统中，而无需为DAC 进行额外的电源时序控制。
VIN
VREG
VDD
DAC
R1
Linear
Regulator
or
DC/DC
Converter
ILEAK
RS
VFB
PROTECT
1.25 V
R2
ZOUT
图7-9. 高阻抗（高阻态）输出和PROTECT 输入
DAC 通道在启动时断电至高阻态。输出可以使用与直流/直流转换器或线性稳压器的标称输出相对应的预编程代码
加电。此功能可实现DAC 的平稳加电和断电，而不影响直流/直流转换器或线性稳压器的反馈环路。
DACx3204W 的 GPIO 引脚可配置为 PROTECT 功能，如表 7-18 所示。PROTECT 通过转换或直接转换将 DAC
输出变为可预测状态。在故障条件（如欠压）、子系统故障或软件崩溃要求DAC 输出达到预定义状态而不涉及处
理器的系统中，此功能非常有用。检测到的事件可以馈送到配置为 PROTECT 输入的 GPIO 引脚。PROTECT 功
能可以使用 COMMON-TRIGGER 寄存器中的 PROTECT 位来触发。PROTECT 功能的行为可以使用 DEVICE-
MODE-CONFIG 寄存器的PROTECT-CONFIG 字段配置，如表7-4 所示。
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备注
• 在PROTECT 功能触发后，通信接口上的写入功能会被禁用，直到该功能完成。
• 当PROTECT 功能触发时，CMP-STATUS 寄存器中的PROTECT-FLAG 位会设置为1。该位可以
通过读取CMP-STATUS 寄存器来轮询。在PROTECT 功能完成后，CMP-STATUS 寄存器上的读
取命令会将PROTECT-FLAG 位复位。
表7-4. PROTECT 功能配置
PROTECT-CONFIG 字段
功能
00
01
10
11
切换至高阻态断电模式（无转换）。
切换到存储在NVM 中的DAC 代码（无转换），然后切换到高阻态断电模式。
转换为裕度低代码，然后切换到高阻态断电模式。
转换为裕度高代码，然后切换到高阻态断电模式。
7.4.5.1.2 Programmable Slew-Rate Control
When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new
code following the slew rate and settling time specified in the Electrical Characteristics.
The slew rate control feature allows the user to control the rate at which the output voltage (VOUT) changes.
When this feature is enabled (using the SLEW-RATE-X[3:0] bits), the DAC output changes from the current code
to the code in the DAC-X-MARGIN-HIGH or DAC-X-MARGIN-LOW registers (when margin high or low
commands are issued to the DAC) using the step size and time-period per step set in CODE-STEP-X and
SLEW-RATE-X bits in the DAC-X-FUNC-CONFIG register:
• SLEW-RATE-X defines the time-period per step at which the digital slew updates.
• CODE-STEP-X defines the number of LSBs by which the output value changes at each update, for the
corresponding channels.
表 7-5 and 表 7-6 show different settings available for CODE-STEP-X and SLEW-RATE-X. With the default slew
rate control setting of no-slew, the output changes immediately at a rate limited by the output drive circuitry and
the attached load.
When the slew rate control feature is used, the output changes happen at the programmed slew rate. This
configuration results in a staircase formation at the output as shown in 图 7-10. Do not write to CODE-STEP-X,
SLEW-RATE-X, or DAC-X-DATA during the output slew operation. 方程式 5 provides the equation for the
calculating the slew time (tSLEW).
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MARGIN-HIGH
CODE-STEP
MARGIN-LOW
TIME PERIOD
tSLEW
图7-10. Programmable Slew-Rate Control
MARGIN_HIGH − MARGIN_LOW
t
= SLEW_RATE × CEILING
+ 1
(5)
SLEW
CODE_STEP
where:
• SLEW_RATE is the SLEW-RATE-X setting as specified in 表7-6.
• CODE_STEP is the CODE-STEP-X setting as specified in 表7-5.
• MARGIN_HIGH is the decimal value of the DAC-X-MAGIN-HIGH bits specified in the DAC-X-MARGIN-HIGH
register.
• MARGIN_LOW is the decimal value of the DAC-X-MAGIN-LOW bits specified in the DAC-X-MARGIN-LOW
register.
表7-5. Code Step
REGISTER
CODE-STEP-X[2]
CODE-STEP-X[1]
CODE-STEP-X[0]
CODE STEP SIZE
1 LSB (default)
2 LSB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3 LSB
4 LSB
DAC-X-FUNC-CONFIG
6 LSB
8 LSB
16 LSB
32 LSB
表7-6. Slew Rate
TIME PERIOD
(PER STEP)
REGISTER
SLEW-RATE-X[3]
SLEW-RATE-X[2]
SLEW-RATE-X[1]
SLEW-RATE-X[0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No slew (default)
4 µs
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
8 µs
12 µs
18 µs
27.04 µs
40.48 µs
60.72 µs
91.12 µs
136.72 µs
239.2 µs
418.64 µs
732.56 µs
1282 µs
2563.96 µs
5127.92 µs
DAC-X-FUNC-CONFIG
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7.4.5.1.3 PMBus Compatibility Mode
The PMBus protocol is an I2C-based communication standard for power-supply management. PMBus contains
standard command codes tailored to power supply applications. The DACx3204W implement some PMBus
commands such as Turn Off, Turn On, Margin Low, Margin High, Communication Failure Alert Bit (CML), as well
as PMBUS revision. 图7-11 shows typical PMBus connections. The EN-PMBUS bit in the INTERFACE-CONFIG
register must be set to 1 to enable the PMBus protocol.
PMBus-compatible device #1
ALERT
CONTROL
DATA
CLOCK
Alert signal
PMBus-compatible device #2
ALERT
Control signal
CONTROL
Data
DATA
Clock
CLOCK
Optional
Required
PMBus-compatible device #3
ALERT
CONTROL
DATA
CLOCK
图7-11. PMBus Connections
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Similar to I2C, PMBus is a variable length packet of 8-bit data bytes, each with a receiver acknowledge, wrapped
between a start and stop bit. The first byte is always a 7-bit target address followed by a write bit, sometimes
called the even address that identifies the intended receiver of the packet. The second byte is an 8-bit command
byte, identifying the PMBus command being transmitted using the respective command code. After the
command byte, the transmitter either sends data associated with the command to write to the receiver command
register (from least significant byte to most significant byte, as shown in 表 7-7), or sends a new start bit
indicating the desire to read the data associated with the command register from the receiver. Then the receiver
transmits the data following the same least significant byte first format (see 表7-8).
表7-7. PMBus Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
Address (A) byte
节7.5.2.2.1
Command byte
节7.5.2.2.2
Data byte - MSDB
(Optional)
Data byte - LSDB
DB [15:8]
DB [31:24]
DB [23:16]
DB [7:0]
表7-8. PMBus Read Sequence
R/W
(0)
R/W
(1)
S
MSB
ACK
MSB
LSB
ACK Sr MSB
ACK
MSB
LSB
ACK
MSB
LSB
ACK
…
…
…
…
…
ADDRESS BYTE
节7.5.2.2.1
COMMAND BYTE
ADDRESS BYTE
节7.5.2.2.1
Sr
LSDB
MSDB (Optional)
From Target
节7.5.2.2.2
From Controller
Target
From Controller
Target
From Controller
Target
From Target
Controller
Controller
The DACx3204W I2C interface implements some of the PMBus commands. 表 7-9 shows the supported PMBus
commands that are implemented in DACx3204W. The DAC uses DAC-X-MARGIN-LOW, DAC-X-MARGIN-HIGH
bits, SLEW-RATE-X, and CODE-STEP-X bits for PMBUS-OPERATION-CMD-X. To access multiple channels,
write the PMBus page address as specified in the Register Names table in the Register Map section to the
PMBUS-PAGE register first, followed by a write to the channel-specific register.
表7-9. PMBus Operation Commands
REGISTER
PMBUS-OPERATION-CMD-X[15:8]
DESCRIPTION
Turn off
00h
80h
94h
A4h
Turn on
PMBUS-OP-CMD-X
Margin low
Margin high
The DACx3204W also implement PMBus features such as group command protocol and communication time-
out failure. The CML bit in the PMBUS-CML register indicates a communication fault in the PMBus. This bit is
reset by writing 1.
To get the PMBus version, read the PMBUS-VERSION register.
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7.4.5.2 函数生成
DACx3204W 实施了连续函数或波形生成功能。这些器件可以为每个通道独立生成三角波、锯齿波和正弦波。
7.4.5.2.1 Triangular Waveform Generation
图 7-12 shows that the triangular waveform uses the DAC-X-MARGIN-LOW (FUNCTION-MIN) and DAC-X-
MARGIN-HIGH (FUNCTION-MAX) registers for minimum and maximum levels, respectively. The frequency of
the waveform depends on the min and max levels, CODE-STEP and SLEW-RATE settings as shown in 方程式
6. An external RC load with a time-constant larger than the slew-rate settings can be dominant over the internal
frequency calculation. The CODE-STEP-X and SLEW-RATE-X settings are available in the DAC-X-FUNC-
CONFIG register. Writing 0b000 to the FUNC-CONFIG-X bit field in the DAC-X-FUNC-CONFIG register selects
triangular waveform.
1
f
=
(6)
TRIANGLE
FUNCTION_MAX − FUNCTION_MIN
CODE_STEP
2 × TIME_STEP × CEILING
where:
• TIME_STEP is the SLEW-RATE-X setting as specified in 表7-6.
• CODE_STEP is the CODE-STEP-X setting as specified in 表7-5.
• FUNCTION_MAX is the decimal value of DAC-X-MAGIN-HIGH bits specified in the DAC-X-MARGIN-HIGH
register.
• FUNCTION_MIN is the decimal value of the DAC-X-MAGIN-LOW bits specified in the DAC-X-MARGIN-LOW
register.
FUNCTION-MAX
TIME-STEP
CODE-STEP
FUNCTION-MIN
图7-12. Triangle Waveform
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7.4.5.2.2 Sawtooth Waveform Generation
图 7-13 shows the sawtooth and the inverse sawtooth waveforms use the DAC-X-MARGIN-LOW (FUNCTION-
MIN) and DAC-X-MARGIN-HIGH (FUNCTION-MAX) registers for minimum and maximum levels, respectively.
The frequency of the waveform depends on the min and max levels, CODE-STEP and SLEW-RATE settings as
shown in 方程式 7. An external RC load with a time constant larger than the slew-rate settings can be dominant
over the internal frequency calculation. The CODE-STEP-X and SLEW-RATE-X settings are available in the
DAC-X-FUNC-CONFIG register. Write 0b001 to the FUNC-CONFIG-X bit field in the DAC-X-FUNC-CONFIG
register to select sawtooth waveform, and write 0b010 to select inverse sawtooth waveform.
1
f
=
(7)
SAWTOOTH
FUNCTION_MAX − FUNCTION_MIN
CODE_STEP
TIME_STEP × CEILING
+ 1
where:
• TIME_STEP is the SLEW-RATE-X setting as specified in 表7-6.
• CODE_STEP is the CODE-STEP-X setting as specified in 表7-5.
• FUNCTION_MAX is the decimal value of the DAC-X-MAGIN-HIGH bits specified in the DAC-X-MARGIN-
HIGH register.
• FUNCTION_MIN is the decimal value of the DAC-X-MAGIN-LOW bits specified in the DAC-X-MARGIN-LOW.
FUNCTION-MAX
TIME-STEP
CODE-STEP
FUNCTION-MIN
图7-13. Sawtooth Waveform
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7.4.5.2.3 Sine Waveform Generation
The sine wave function uses 24 preprogrammed points per cycle. The frequency of the sine wave depends on
the SLEW-RATE settings as shown in 方程式8:
1
f
=
(8)
SINE_WAVE
24 × SLEW_RATE
where SLEW_RATE is the SLEW-RATE-X setting as specified in 表7-6.
An external RC load with a time constant larger than the slew-rate settings can be dominant over the internal
frequency calculation. The SLEW-RATE-X setting is available in the DAC-X-FUNC-CONFIG register. Writing
0b100 to the FUNC-CONFIG-X bit field in the DAC-X-FUNC-CONFIG register selects sine wave. The codes for
the sine wave are fixed. Use the gain settings at the output amplifier for changing the full-scale output using the
internal reference option. The gain settings are accessible through the VOUT-GAIN-X bits in the DAC-X-VOUT-
CMP-CONFIG register. 表 7-10 shows the list of hard-coded discrete points for the sine wave with 12-bit
resolution and 图 7-14 shows the pictorial representation of the sine wave. There are four phase settings
available for the sine wave that are selected using the PHASE-SEL-X bit in the DAC-X-FUNC-CONFIG register.
表7-10. Sine Wave Data Points
SEQUENCE
0 (0° phase start)
12-BIT VALUE
SEQUENCE
12-BIT VALUE
0x800
0x800
12
13
14
15
1
0x9A8
0x658
2
0xB33
0x4CD
0x379
3
0xC87
0xD8B
0xE2F
0xE66
4
16 (240° phase start)
0x275
5
17
18
19
20
21
22
23
0x1D1
0x19A
0x1D1
0x275
6 (90° phase start)
7
0xE2F
0xD8B
0xC87
0xB33
8 (120° phase start)
9
0x379
10
11
0x4CD
0x658
0x9A8
6
5
7
4
8
3
9
2
10
1
11
TIME PERIOD
0
12
0
13
23
14
22
15
21
16
20
17
19
18
图7-14. Sine Wave Generation
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7.4.6 器件复位和故障管理
本节详细介绍了DACx3204W 的上电复位(POR)、软件复位以及其他诊断和故障管理功能。
7.4.6.1 上电复位(POR)
DACx3204W 系列器件包含上电复位 (POR) 功能，可在加电时控制输出电压。在建立 VDD 电源后，便会发出
POR 事件。POR 使所有寄存器初始化为默认值，只有在 POR（启动）延迟之后，与该器件的通信才有效。一旦
发生POR 事件，DACx3204W 中所有寄存器的默认值都将立即从NVM 加载。
该器件加电时，POR 电路将器件设置为默认模式。POR 电路需要特定的VDD 电平（如图7-15 所示）才能确保内
部电容器在加电时放电并使器件复位。为了确保发生 POR，VDD 小于 0.7V 的时间必须至少为1ms。当VDD 降至
低于 1.65V 但仍高于 0.7V（显示为未定义区域）时，该器件在所有指定的温度和电源条件下可能会也可能不会复
位。在这种情况下，需启动POR。当VDD 保持为大于1.65V 时，不会发生POR。
VDD (V)
5.5 V
Specified supply
voltage range
No power-on reset
1.71 V
1.65 V
Undefined
0.7 V
Power-on reset
0 V
图7-15. VDD POR 电路的阈值电平
7.4.6.2 External Reset
An external reset to the device can be triggered through the GPIO pin or through the register map. To initiate a
device software reset event, write the reserved code 1010b to the RESET field in the COMMON-TRIGGER
register. A software reset initiates a POR event. The GPIO pin can be configured as a RESET pin as shown in 表
7-18. This configuration must be programmed into the NVM so that the setting is not cleared after the device
reset. The RESET input must be a low pulse. The device starts the boot-up sequence after the falling edge of
the RESET input. The rising edge of the RESET input does not have any effect.
7.4.6.3 Register-Map Lock
The DACx3204W implement a register-map lock feature that prevents an accidental or unintended write to the
DAC registers. The device locks all the registers when the DEV-LOCK bit in the COMMON-CONFIG register is
set to 1. However, the software reset function through the COMMON-TRIGGER register is not blocked when
using I2C interface. To bypass the DEV-LOCK setting, write 0101b to the DEV-UNLOCK bits in the COMMON-
TRIGGER register.
7.4.6.4 NVM 循环冗余校验(CRC)
DACx3204W 为 NVM 实施循环冗余校验 (CRC) 功能，以确保存储在 NVM 中的数据不被损坏。DACx3204W 中
实现了两种类型的CRC 报警位：
• NVM-CRC-FAIL-USER
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• NVM-CRC-FAIL-INT
NVM-CRC-FAIL-USER 位指示用户可编程 NVM 位的状态，而NVM-CRC-FAIL-INT 位指示内部 NVM 位的状态。
CRC 功能通过在每次执行 NVM 程序操作（写入或重新加载）时以及在器件启动期间，存储 16 位 CRC
(CRC-16-CCITT) 以及 NVM 数据来实现。器件会读取 NVM 数据并使用存储的 CRC 来验证数据。CRC 报警位
（GENERAL-STATUS 寄存器中的 NVM-CRC-FAIL-USER 和 NVM-CRC-FAIL-INT）报告从器件 NVM 读取数据
后的任何错误。报警位仅在启动时设置。
7.4.6.4.1 NVM-CRC-FAIL-USER 位
NVM-CRC-FAIL-USER 位为逻辑1 表示用户可编程的NVM 上数据已损坏。在这种情况下，DAC 中的所有寄存器
都会使用出厂复位值进行初始化，并且任何 DAC 寄存器都可以写入或读取。要将报警位复位为 0，需发出软件复
位（请参阅节 7.4.6.2）命令或对 DAC 执行循环通电。软件复位或执行循环通电也会重新加载用户可编程的 NVM
位。如果故障仍然存在，需重新对NVM 进行编程。
7.4.6.4.2 NVM-CRC-FAIL-INT 位
NVM-CRC-FAIL-INT 位为逻辑 1 表示内部 NVM 数据已损坏。在这种情况下，DAC 中的所有寄存器都会使用出厂
复位值进行初始化，并且任何 DAC 寄存器都可以写入或读取。在发生临时故障时，要将报警位复位为 0，需发出
软件复位（请参阅节7.4.6.2）命令或对DAC 执行循环通电。NVM 中的永久故障会导致器件无法使用。
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7.4.7 Power-Down Mode
The DACx3204W output amplifier and internal reference can be independently powered down through the EN-
INT-REF, VOUT-PDN-X, and IOUT-PDN-X bits in the COMMON-CONFIG register, as shown in 图 7-2. At power
up, the DAC output and the internal reference are disabled by default. In power-down mode, the DAC outputs
(OUTx pins) are in a high-impedance state. To change this state to 10 kΩ-AGND or 100 kΩ-AGND in the
voltage-output mode (at power up), use the VOUT-PDN-X bits. The power-down state for current-output mode is
always high-impedance.
The DAC power-up state can be programmed to any state (power-down or normal mode) using the NVM. 表
7-11 shows the DAC power-down bits. The individual channel power-down bits or the global device power-down
function can be mapped to the GPIO pin using the GPIO-CONFIG register.
表7-11. DAC Power-Down Bits
REGISTER
VOUT-PDN-X[1]
VOUT-PDN-X[0]
IOUT-PDN-X
DESCRIPTION
Power up VOUT-X.
0
0
1
Power down VOUT-X with 10 kΩ to AGND.
0
1
1
1
1
0
1
1
1
1
1
0
Power down IOUT-X to Hi-Z.
Power down VOUT-X with 100 kΩ to AGND.
Power down IOUT-X to Hi-Z.
COMMON-CONFIG
Power down VOUT-X to Hi-Z.
Power down IOUT-X to Hi-Z (default).
Power down VOUT-X to Hi-Z.
Power up IOUT-X.
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7.5 编程
DACx3204W 通过3 线SPI 或2 线I2C 接口进行编程。4 线SPI 模式通过将GPIO 引脚映射为SDO 来启用。SPI
回读操作的 SCLK 低于标准 SPI 写入操作。接口类型根据器件加电后的第一个通信协议来确定。在确定接口类型
后，器件会在器件开启时忽略类型的任何更改。接口类型可以在下电上电后更改。
7.5.1 SPI 编程模式
通过将 SYNC 引脚置于低电平，可以启动 DACx3204W 的 SPI 访问周期。串行时钟 SCLK 可以是连续时钟或选
通时钟。SDI 数据在 SCLK 下降沿上传输。DACx3204W 的 SPI 帧长度为 24 位。因此，SYNC 引脚必须保持低
电平至少 24 个 SCLK 下降沿。当 SYNC 引脚取消置位为高电平时，访问周期结束。如果访问周期包含的时钟边
沿小于最小值，则通信将被忽略。默认情况下，SDO 引脚未启用（三线 SPI）。在三线 SPI 模式下，如果访问周
期包含的时钟边沿大于最小值，则器件仅使用前 24 位。当 SYNC 为高电平时，SCLK 和 SDI 信号会被阻止，同
时SDO 变为高阻态，以允许从总线上连接的其他器件回读数据。
表 7-12 和图 7-16 介绍了 24 位 SPI 访问周期的格式。SDI 的第一个字节输入是指令周期。指令周期将请求标识
为读或写命令以及要访问的7 位地址。周期中的最后16 位构成数据周期。
表7-12. SPI 读/写访问周期
位
字段
说明
23
R/W
将通信标识为地址寄存器的读或写命令：R/W = 0 设置写入操作。R/W = 1 设置读取操作
寄存器地址：指定在读取或写入操作期间要访问的寄存器
22-16
15-0
A[6:0]
DI[15:0]
数据周期位：如果是写入命令，则数据周期位是要写入地址为A[6:0] 的寄存器的值。如果是读取命令，则
数据周期位为不用考虑值。
SYNC
1
8
9
24
1
8
9
24
SCLK
Write command
D16
Any command
D16
D23
D15
D0
D23
D23
D15
D0
D0
SDI
Write command echo
D16 D15
HiZ
HiZ
HiZ
SDO
图7-16. SPI 写入周期
读取操作要求首先通过设置 INTERFACE-CONFIG 寄存器中的 SDO-EN 位来启用 SDO 引脚。此配置称为四线
SPI。读取操作通过发出读取命令访问周期来启动。读取命令后，必须发出第二个访问周期来获取请求的数据。表
7-13 和图 7-17 显示了输出数据格式。根据 FSDO 位，数据通过 SDO 引脚在 SCLK 的下降沿或上升沿输出，如
图6-3 所示。
表7-13. SDO 输出访问周期
位
字段
说明
23
R/W
来自上一访问周期的回波R/W
来自上一访问周期的回波寄存器地址
上一访问周期中请求的回读数据
22-16
15-0
A[6:0]
DI[15:0]
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SYNC
1
8
9
24
1
8
9
24
SCLK
Read command
D16
Any command
D16
D23
D15
D0
D23
D23
D15
D15
D0
SDI
Read Data
HiZ
HiZ
HiZ
SDO
D16
D0
图7-17. SPI 读取周期
菊花链操作也通过 SDO 引脚启用。在菊花链模式下，多个器件采用链式连接，其中一个器件的 SDO 引脚连接到
以下器件的 SDI 引脚，如图7-18 所示。SPI 主机驱动链中第一个器件的SDI 引脚。链中最后一个器件的 SDO 引
脚连接到 SPI 主机的 POCI 引脚。在四线 SPI 模式下，如果访问周期包含 24 个时钟边沿的倍数，则链中的第一
个器件仅使用最后 24 个位。如果访问周期包含的时钟边沿不是 24 的倍数，则器件会忽略 SPI 数据包。图 7-19
介绍了菊花链写入周期的数据包格式。
VIO
VIO
VIO
C
B
A
RPULL-UP
RPULL-UP
RPULL-UP
TI SPI Device
TI SPI Device
TI SPI Device
SDO
SDO
SDO
SDI
SDI
SDI
SCLK
SYNC
SCLK
SCLK
SYNC
SYNC
图7-18. SPI 菊花链连接
SYNC
SCLK
1
8
9
24
25
48
49
72
Device A command
D16 D15
Device B command
D23 – D1
Device C command
D23 – D1
D23
D0
SDI-C
D0
D0
SDO-C
Device A command
Device B command
图7-19. SPI 菊花链写入周期
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7.5.2 I2C Programming Mode
The DACx3204W devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0), as shown in
the pin diagram in the Pin Configuration and Functions section. The I2C bus consists of a data line (SDA) and a
clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-
compatible devices connect to the I2C bus through the open drain I/O pins, SDA and SCL.
The I2C specification states that the device that controls communication is called a controller, and the devices
that are controlled by the controller are called targets. The controller generates the SCL signal. The controller
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the controller. The controller on
an I2C bus is typically a microcontroller or digital signal processor (DSP). The DACx3204W family operates as a
target on the I2C bus. A target acknowledges controller commands, and upon controller control, receives or
transmits data.
Typically, the DACx3204W family operates as a target receiver. A controller writes to the DACx3204W, a target
receiver. However, if a controller requires the DACx3204W internal register data, the DACx3204W operate as a
target transmitter. In this case, the controller reads from the DACx3204W. According to I2C terminology, read
and write refer to the controller.
The DACx3204W family supports the following data transfer modes:
• Standard mode (100Kbps)
• Fast mode (400Kbps)
• Fast mode plus (1.0Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred
to as F/S-mode in this document. The fast mode plus protocol is supported in terms of data transfer speed, but
not output current. The low-level output current is 3 mA; similar to the case of standard and fast modes. The
DACx3204W family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device
supports the general call reset function. Sending the following sequence initiates a software reset within the
device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the
ACK bit, following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. An acknowledge is when the SDA line is pulled low during
the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high
period of the ninth clock cycle, as shown in 图7-20.
Data output
by transmitter
Not acknowledge
Data output
by receiver
Acknowledge
2
9
1
8
SCL from
controller
S
Clock pulse for
acknowledgement
Start
condition
图7-20. Acknowledge and Not Acknowledge on the I2C Bus
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7.5.2.1 F/S 模式协议
以下步骤说明了F/S 模式下的完整事务。
1. 控制器通过产生启动条件来启动数据传输。启动条件是当SCL 为高电平时在SDA 线上发生从高到低的转
换，如图7-21 所示。所有与I2C 兼容的器件都会识别启动条件。
2. 控制器随后产生SCL 脉冲，并在SDA 线上发送7 位地址和读取/写入方向位(R/W)。在所有传输期间，控制
器确保数据有效。有效数据条件要求SDA 线在时钟脉冲的整个高电平期间保持稳定，如图7-22 所示。所有
器件都识别控制器发送的地址，并将其与相应内部固定地址进行比较。只有具有匹配地址的目标器件才会通过
在第9 个SCL 周期的整个高电平期间拉低SDA 线来生成确认，如图7-20 所示。当控制器检测到此确认时，
则表示与目标的通信链路已建立。
3. 控制器产生更多的SCL 周期，以便向目标器件发送（R/W 位为0）数据或接收（R/W 位为1）数据。在任一
种情况下，接收器都必须确认发送器发送的数据。因此，确认信号可由控制器或目标器件生成，具体取决于哪
一方是接收器。9 位有效数据序列包含8 个数据位和1 个确认位，并可根据需要继续。
4. 为了用信号指示数据传输结束，控制器通过在SCL 线处于高电平期间将SDA 线从高电平拉低来产生停止条
件，如图7-21 所示。此操作将释放总线并停止与寻址的目标器件之间的通信链路。所有与I2C 兼容的器件都
会识别停止条件。在收到停止条件后，将释放总线，然后所有目标器件等待启动条件，接着是匹配的地址。
SDA
SDA
SCL
SCL
S
P
Start
condition
Stop
condition
Change of data
allowed
Data line stable
Data valid
图7-21. 启动和停止条件
图7-22. 在I2C 总线上的位传输
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7.5.2.2 I2C 更新序列
对于单次更新，DACx3204W 需要一个开始条件、一个有效的I2C 地址字节、一个命令字节以及两个数据字节，
如表7-14 中所列。
表7-14. 更新序列
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
地址(A) 字节
节7.5.2.2.1
命令字节
节7.5.2.2.2
数据字节- MSDB
数据字节- LSDB
DB [31:24]
DB [23:16]
DB [15:8]
DB [7:0]
收到每个字节后，DACx3204W 系列通过在单个时钟脉冲的高电平期间拉低 SDA 线来确认该字节，如图 7-23 所
示。这四个字节和确认周期构成了单次更新所需的36 个时钟周期。一个有效的I2C 地址字节选择DACx3204W。
Recognize
START or
REPEATED
START
condition
Recognize
STOP or
REPEATED
START
Generate ACKNOWLEDGE
signal
condition
P
SDA
Sr
MSB
Acknowledgement
signal from target
Address
R/W
1
SCL
1
7
8
9
2 - 8
9
Sr
or
P
S
or
Sr
ACK
ACK
START or
REPEATED
START
REPEATED
START or
STOP
condition
condition
图7-23. I2C 总线协议
命令字节设置所选 DACx3204W 器件的工作模式。如果要在通过该字节选择工作模式时进行数据更新，
DACx3204W 器件必须接收两个数据字节：最高有效数据字节 (MSDB) 和最低有效数据字节 (LSDB)。
DACx3204W 器件在LSDB 之后的确认信号下降沿执行更新。
使用快速模式（时钟= 400kHz）时，最大DAC 更新速率限制为10kSPS。使用超快速模式（时钟= 1MHz）时，
最大DAC 更新速率限制为25kSPS。收到停止条件后，DACx3204W 器件将释放I2C 总线并等待新的启动条件。
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7.5.2.2.1 地址字节
地址字节（如表 7-15 所示）是在启动条件之后从控制器器件接收的第一个字节。地址的前四位 (MSB) 出厂预设
为 1001b。地址的接下来三位由 A0 引脚控制。A0 引脚输入可以连接到 VDD、AGND、SCL 或 SDA。在每个数
据帧的第一个字节期间对 A0 引脚进行采样以确定地址。该器件会锁存地址引脚的值，因此会根据表 7-16 响应该
特定地址。
表7-15. 地址字节
MSB
LSB
注释
—
AD6
1
AD5
0
AD4
0
AD3
AD2
1
AD1
AD0
1
R/W
请参阅表7-16
（目标地址列）
1
0
0 或1
一般地址
广播地址
1
0
0
1
0
表7-16. 地址格式
A0 引脚
AGND
VDD
目标地址
000
001
010
SDA
011
SCL
DACx3204W 支持使用广播地址来同步更新或关闭多个 DACx3204W 器件。使用广播地址时，无论地址引脚状态
如何，DACx3204W 都会进行响应。仅在写入模式下支持广播。
7.5.2.2.2 Command Byte
The Register Names table in the Register Map section lists the command byte in the ADDRESS column.
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7.5.2.3 I2C 读取序列
要读取任何寄存器，必须使用以下命令序列：
1. 发送启动或重复启动命令（使用目标器件地址并将R/W 位设置为0 以进行写入）。该器件将确认此事件。
2. 针对要读取的寄存器发送一个命令字节。该器件将再次确认此事件。
3. 发送重复启动命令（使用目标器件地址并将R/W 位设置为1 以进行读取）。该器件将确认此事件。
4. 该器件将写入寻址到的寄存器的MSDB 字节。控制器必须确认此字节。
5. 最后，该器件将写出寄存器的LSDB。
广播地址不能用于读取。
表7-17. 读取序列
R/W
(0)
R/W
(1)
S
MSB
ACK
MSB
LSB
ACK Sr MSB
ACK
MSB
LSB
ACK
MSB
LSB
ACK
…
…
…
…
…
地址字节
节7.5.2.2.1
命令字节
节7.5.2.2.2
地址字节
节7.5.2.2.1
Sr
MSDB
LSDB
来自控制器
目标
来自控制器
目标
来自控制器
目标
来自目标器件
控制器
来自目标器件
控制器
7.5.3 通用输入/输出(GPIO) 模式
借助 I2C 和 SPI，DACx3204W 还支持一个可在 NVM 中配置来提供多种功能的 GPIO。此引脚允许在不使用编程
接口的情况下更新 DAC 输出通道和读取状态位，从而实现无处理器运行。在 GPIO-CONFIG 寄存器中，向 GPI-
EN 位写入 1 以将 GPIO 引脚设置为输入，或向 GPO-EN 位写入 1 以将该引脚设置为输出。GPIO 引脚上映射了
全局功能和特定于通道的功能。对于特定于通道的功能，需使用 GPIO-CONFIG 寄存器中的 GPI-CH-SEL 字段选
择通道。表 7-18 列出了 GPIO 作为输入的可用功能选项，而 表 7-19 列出了 GPIO 作为输出的功能选项。一些
GP 输入操作在器件启动后由边沿触发。电源上升后，器件会寄存 GPI 电平并执行相关命令。此功能让用户可以
配置加电时的初始输出状态。默认情况下，GPIO 引脚不映射到任何操作。当 GPIO 引脚映射到特定的输入功能
时，相应的软件位功能会被禁用，以避免出现竞态条件。当用作RESET 输入时，GPIO 引脚必须发送低电平有效
脉冲来触发器件复位。这些功能的所有其他限制都应用于基于GPIO 的触发器。
备注
未使用时，将 GPIO 引脚拉至高电平或低电平。当 GPIO 引脚用作 RESET 时，必须将配置编程到
NVM 中。否则，该设置会在器件复位后被清除。
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表7-18. 通用输入功能映射
GPIO 边沿/电平
寄存器
位字段
值
通道
功能
触发FAULT-DUMP
下降沿
上升沿
下降沿
上升沿
0010
全部
没有影响
IOUT 断电
IOUT 加电
0011
0100
依据GPI-CH-SEL 标准
依据GPI-CH-SEL 标准
VOUT 断电。根据VOUT-PDN-X 设
置的下拉电阻器
下降沿
VOUT 加电
上升沿
下降沿
上升沿
下降沿
上升沿
下降沿
触发PROTECT 功能
没有影响
0101
0111
全部
全部
触发CLR 功能
没有影响
依据GPI-CH-SEL 标准。必须
为每个通道配置SYNC-
CONFIG-X 和GPI-CH-SEL。
触发LDAC 功能
1000
上升沿
没有影响
GPIO-CONFIG
GPI-CONFIG
下降沿
上升沿
下降沿
上升沿
停止函数生成
开始函数生成
触发裕度低
触发裕度高
1001
1010
依据GPI-CH-SEL 标准
依据GPI-CH-SEL 标准
触发器件RESET。RESET 配置必须
编程到NVM 中。
低电平脉冲
1011
1100
全部
全部
上升沿
下降沿
上升沿
下降沿
没有影响
允许NVM 编程
阻止NVM 编程
允许更新寄存器映射
阻止寄存器映射写入，但通过I2C 或
SPI 写入DEV-UNLOCK 字段和通过
I2C 写入RESET 字段除外
1101
全部
上升沿
不适用
其他
不适用
不可用
表7-19. 通用输出(STATUS) 功能映射
寄存器
位字段
值
功能
0001
0100
0101
0110
0111
1000
1001
1010
1011
NVM-BUSY
DAC-0-BUSY
DAC-1-BUSY
DAC-2-BUSY
DAC-3-BUSY
WIN-CMP-0
WIN-CMP-1
WIN-CMP-2
WIN-CMP-3
GPIO-CONFIG
GPO-CONFIG
其他
不可用
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7.6 Register Map
表7-20. Register Map
MOST SIGNIFICANT DATA BYTE (MSDB)
LEAST SIGNIFICANT DATA BYTE (LSDB)
REGISTER(1) (2)
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
NOP
NOP
DAC-X-MARGIN-
HIGH
DAC-X-MARGIN-HIGH
DAC-X-MARGIN-LOW
X
X
DAC-X-MARGIN-
LOW
DAC-X-VOUT-
CMP-CONFIG
CMP-X-OD-
EN
CMP-X-
OUT-EN
CMP-X-HIZ- CMP-X-INV-
IN-DIS EN
X
X
VOUT-GAIN-X
X
CMP-X-EN
DAC-X-IOUT-MISC-
CONFIG
IOUT-X-RANGE
X
DAC-X-CMP-
MODE-CONFIG
X
CMP-X-MODE
VOUT-PDN-3
X
DAC-X-FUNC-
CLR-SEL-X
CONFIG
SYNC-
CONFIG-X
BRD-
CONFIG-X
FUNC-GEN-CONFIG-BLOCK-X
DAC-X-DATA
DAC-X-DATA
IOUT-PDN-3
X
COMMON-CONFIG
WIN-
LATCH-EN
DEV-LOCK
EE-READ- EN-INT-REF
ADDR
VOUT-PDN-2
IOUT-PDN-2
CLR
VOUT-PDN-1
IOUT-PDN-1
VOUT-PDN-0
IOUT-PDN-0
COMMON-
TRIGGER
DEV-UNLOCK
RESET
LDAC
X
FAULT-
DUMP
PROTECT READ-ONE- NVM-PROG
TRIG
NVM-
RELOAD
COMMON-DAC-
TRIG
RST-CMP- TRIG-MAR- TRIG-MAR-
START-
FUNC-0
RST-CMP- TRIG-MAR- TRIG-MAR-
START-
FUNC-1
RST-CMP- TRIG-MAR- TRIG-MAR-
FLAG-2 LO-2 HI-2
START-
FUNC-2
RST-CMP- TRIG-MAR- TRIG-MAR-
START-
FUNC-3
FLAG-0
LO-0
HI-0
FLAG-1
LO-1
HI-1
FLAG-3
LO-3
HI-3
GENERAL-STATUS NVM-CRC- NVM-CRC-
X
DAC-
DAC-
DAC-
DAC-
NVM-BUSY
DEVICE-ID
FAIL-INT
FAIL-USER
BUSY-3
BUSY-2
BUSY-1
BUSY-0
CMP-STATUS
X
PROTECT- WIN-CMP-3 WIN-CMP-2 WIN-CMP-1 WIN-CMP-0
FLAG
CMP-
FLAG-3
CMP-
FLAG-2
CMP-
FLAG-1
CMP-
FLAG-0
GPIO-CONFIG
GF-EN
X
GPO-EN
GPO-CONFIG
RESERVED
GPI-CH-SEL
GPI-CONFIG
GPI-EN
DEVICE-MODE-
CONFIG
RESERVED
DIS-MODE-
IN
PROTECT-CONFIG
RESERVED
X
INTERFACE-
CONFIG
X
TIMEOUT-
EN
X
EN-PMBUS
X
FSDO-EN
X
SDO-EN
SRAM-CONFIG
SRAM-DATA
X
SRAM-ADDR
SRAM-DATA
DAC-X-DATA-8BIT
BRDCAST-DATA
PMBUS-PAGE
DAC-X-DATA-8BIT
X
BRDCAST-DATA
X
PMBUS-PAGE
PMBUS-OPERATION-CMD-X
X
NA
NA
NA
NA
PMBUS-OP-CMD
PMBUS-CML
CML
X
PMBUS-VERSION
PMBUS-VERSON
(1) The highlighted gray cells indicate the register bits or fields that are stored in the NVM.
(2) X = Don't care.
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表7-21. Register Names
PMBUS REGISTER
ADDR
I2C/SPI ADDRESS PMBUS PAGE ADDR
REGISTER NAME
SECTION
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Fh
FFh
00h
00h
FFh
FFh
FFh
FFh
01h
01h
FFh
FFh
FFh
FFh
02h
02h
FFh
FFh
FFh
FFh
03h
03h
FFh
FFh
FFh
FFh
00h
01h
02h
03h
FFh
D0h
25h
26h
D1h
D2h
D3h
D4h
25h
26h
D5h
D6h
D7h
D8h
25h
26h
D9h
DAh
DBh
DCh
25h
26h
DDh
DEh
DFh
E0h
21h
21h
21h
21h
E3h
NOP
节7.6.1
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
节7.6.7
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
节7.6.7
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
节7.6.7
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
节7.6.7
节7.6.8
节7.6.8
节7.6.8
节7.6.8
节7.6.9
DAC-0-MARGIN-HIGH
DAC-0-MARGIN-LOW
DAC-0-VOUT-CMP-CONFIG
DAC-0-IOUT-MISC-CONFIG
DAC-0-CMP-MODE-CONFIG
DAC-0-FUNC-CONFIG
DAC-1-MARGIN-HIGH
DAC-1-MARGIN-LOW
DAC-1-VOUT-CMP-CONFIG
DAC-1-IOUT-MISC-CONFIG
DAC-1-CMP-MODE-CONFIG
DAC-1-FUNC-CONFIG
DAC-2-MARGIN-HIGH
DAC-2-MARGIN-LOW
DAC-2-VOUT-CMP-CONFIG
DAC-2-IOUT-MISC-CONFIG
DAC-2-CMP-MODE-CONFIG
DAC-2-FUNC-CONFIG
DAC-3-MARGIN-HIGH
DAC-3-MARGIN-LOW
DAC-3-VOUT-CMP-CONFIG
DAC-3-IOUT-MISC-CONFIG
DAC-3-CMP-MODE-CONFIG
DAC-3-FUNC-CONFIG
DAC-0-DATA
DAC-1-DATA
DAC-2-DATA
DAC-3-DATA
COMMON-CONFIG
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表7-21. Register Names (continued)
PMBUS REGISTER
ADDR
I2C/SPI ADDRESS PMBUS PAGE ADDR
REGISTER NAME
SECTION
20h
21h
22h
23h
24h
25h
26h
2Bh
2Ch
40h
41h
42h
43h
50h
NA
FFh
FFh
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EFh
F0h
NA
COMMON-TRIGGER
COMMON-DAC-TRIG
GENERAL-STATUS
CMP-STATUS
节7.6.10
节7.6.11
节7.6.12
节7.6.13
节7.6.14
节7.6.15
节7.6.16
节7.6.17
节7.6.18
节7.6.19
节7.6.19
节7.6.19
节7.6.19
节7.6.20
节7.6.21
节7.6.22
节7.6.22
节7.6.22
节7.6.22
节7.6.23
节7.6.24
FFh
FFh
FFh
GPIO-CONFIG
FFh
DEVICE-MODE-CONFIG
INTERFACE-CONFIG
SRAM-CONFIG
FFh
FFh
FFh
SRAM-DATA
NA
DAC-0-DATA-8BIT
DAC-1-DATA-8BIT
DAC-2-DATA-8BIT
DAC-3-DATA-8BIT
BRDCAST-DATA
PMBUS-PAGE
NA
NA
NA
NA
NA
NA
FFh
F1h
00h
01h
01h
01h
01h
78h
98h
All pages
00h
NA
PMBIS-OP-CMD-0
PMBUS-OP-CMD-1
PMBUS-OP-CMD-2
PMBUS-OP-CMD-3
PMBUS-CML
NA
01h
NA
02h
NA
03h
NA
All pages
All pages
NA
PMBUS-VERSION
表7-22. Access Type Codes
Access Type
Code
Description
X
X
Don't care
Read Type
R
R
Read
Write
Write Type
W
W
Reset or Default Value
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表7-22. Access Type Codes (continued)
Access Type
Code
Description
-n
Value after reset or the default value
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7.6.1 NOP Register (address = 00h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D0h
图7-24. NOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOP
R-0h
表7-23. NOP Register Field Descriptions
Bit
15-0
Field
NOP
Type
Reset
Description
R
0000h
No operation
7.6.2 DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
PMBus page address = 00h, 01h, 02h, 03h, PMBus register address = 25h
图7-25. DAC-X-MARGIN-HIGH Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-X-MARGIN-HIGH[11:0]
DAC-X-MARGIN-HIGH[9:0]
DAC-X-MARGIN-HIGH[7:0]
X
R/W-000h
X-0h
表7-24. DAC-X-MARGIN-HIGH Register Field Descriptions
Bit
15-4
Field
Type
Reset
Description
DAC-X-MARGIN-HIGH[11:0]
DAC-X-MARGIN-HIGH[9:0]
DAC-X-MARGIN-HIGH[7:0]
R/W
000h
Margin-high code for DAC output
Data are in straight-binary format. MSB left-aligned.
Use the following bit-alignment:
DAC63204W VOUT: {DAC-X-MARGIN-HIGH[11:0]}
DAC53204W VOUT: {DAC-X-MARGIN-HIGH[9:0], X, X}
IOUT: {DAC-X-MARGIN-HIGH[7:0], X, X, X, X}
X = Don't care bits.
Don't care
3-0
X
X
0
7.6.3 DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
PMBus page address = 00h, 01h, 02h, 03h, PMBus register address = 26h
图7-26. DAC-X-MARGIN-LOW Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-X-MARGIN-LOW[11:0]
DAC-X-MARGIN-LOW[9:0]
DAC-X-MARGIN-LOW[7:0]
X
R/W-000h
X-0h
表7-25. DAC-X-MARGIN-LOW Register Field Descriptions
Bit
15-4
Field
Type
Reset
Description
DAC-X-MARGIN-LOW[11:0]
DAC-X-MARGIN-LOW[9:0]
DAC-X-MARGIN-LOW[7:0]
R/W
000h
Margin-low code for DAC output
Data are in straight-binary format. MSB left-aligned.
Use the following bit-alignment:
DAC63204W VOUT: {DAC-X-MARGIN-LOW[11:0]}
DAC53204W VOUT: {DAC-X-MARGIN-LOW[9:0], X, X}
IOUT: {DAC-X-MARGIN-LOW[7:0], X, X, X, X}
X = Don't care bits.
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表7-25. DAC-X-MARGIN-LOW Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
X
X
0
Don't care
7.6.4 DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D1h, D5h, D9h, DDh
图7-27. DAC-X-VOUT-CMP-CONFIG Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
VOUT-GAIN-X
X
CMP- CMP- CMP-X- CMP- CMP-
X-OD- X-OUT- HIZ-IN- X-INV- X-EN
EN
EN
DIS
EN
X-0h
R/W-0h
X-0h
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
表7-26. DAC-X-VOUT-CMP-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
12-10
X
X
0h
Don't care
VOUT-GAIN-X
R/W
0h
000: Gain = 1x, external reference on VREF pin
001: Gain = 1x, VDD as reference
010: Gain = 1.5x, internal reference
011: Gain = 2x, internal reference
100: Gain = 3x, internal reference
101: Gain = 4x, internal reference
Others: Invalid
9-5
4
X
X
0h
0
Don't care
CMP-X-OD-EN
R/W
0: Set OUTx pin as push-pull
1: Set OUTx pin as open-drain in comparator mode (CMP-X-EN =
1 and CMP-X-OUT-EN = 1)
3
2
CMP-X-OUT-EN
R/W
R/W
0
0
0: Generate comparator output but consume internally
1: Bring comparator output to the respective OUTx pin
CMP-X-HIZ-IN-DIS
0: FBx input has high-impedance. Input voltage range is limited.
1: FBx input is connected to resistor divider and has finite
impedance. Input voltage range is same as full-scale.
1
0
CMP-X-INV-EN
CMP-X-EN
R/W
R/W
0
0
0: Don't invert the comparator output
1: Invert the comparator output
0: Disable comparator mode
1: Enable comparator mode. Current-output must be in power-
down. Voltage-output mode must be enabled.
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7.6.5 DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D2h, D6h, DAh, DEh
图7-28. DAC-X-IOUT-MISC-CONFIG Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
IOUT-RANGE-X
R/W-0h
X
X-0h
X-0h
表7-27. DAC-X-IOUT-MISC-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
12-9
X
X
0h
Don't care
IOUT-RANGE-X
R/W
0000
1000: ‒25 μA to +25 μA
1001: ‒50 μA to +50 μA
1010: ‒125 μA to +125 μA
1011: ‒250 μA to +250 μA
Others: Invalid
8-0
X
X
000h
Don't care
7.6.6 DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D3h, D7h, DBh, DFh
图7-29. DAC-X-CMP-MODE-CONFIG Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
CMP-X-MODE
R/W-0h
X
X-0h
X-0h
表7-28. DAC-X-CMP-MODE-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
00h
00
Description
15-12
11-10
X
X
Don't care
CMP-X-MODE
R/W
00: No hysteresis or window function
01: Hysteresis provided using DAC-X-MARGIN-HIGH and DAC-
X-MARGIN-LOW registers
10: Window comparator mode with DAC-X-MARGIN-HIGH and
DAC-X-MARGIN-LOW registers setting window bounds
11: Invalid
9-0
X
X
000h
Don't care
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7.6.7 DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D4h, D8h, DCh, E0h
图7-30. DAC-X-FUNC-CONFIG Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR-SEL-X
SYNC-
BRD-
FUNC-GEN-CONFIG-BLOCK
CONFIG-X CONFIG-X
R/W-0h
R/W-0h R/W-0h
R/W-000h
表7-29. DAC-X-FUNC-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
CLR-SEL-X
R/W
0
0: Clear DAC-X to zero-scale
1: Clear DAC-X to mid-scale
14
13
SYNC-CONFIG-X
R/W
R/W
0
0
0: DAC-X output updates immediately after a write command
1: DAC-X output updates with LDAC pin falling-edge or when the
LDAC bit in the COMMON-TRIGGER register is set to 1
BRD-CONFIG-X
0: Don't update DAC-X with broadcast command
1: Update DAC-X with broadcast command
表7-30. Linear-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
Field
Type
Reset
Description
12-11
PHASE-SEL-X
R/W
0
00: 0°
01: 120°
10: 240°
11: 90°
10-8
FUNC-CONFIG-X
R/W
0
000: Triangular wave
001: Sawtooth wave
010: Inverse sawtooth wave
100: Sine wave
111: Disable function generation
Others: Invalid
7
LOG-SLEW-EN-X
CODE-STEP-X
R/W
R/W
0
0
0: Enable linear slew
6-4
CODE-STEP for linear slew mode:
000: 1-LSB
001: 2-LSB
010: 3-LSB
011: 4-LSB
100: 6-LSB
101: 8-LSB
110: 16-LSB
111: 32-LSB
3-0
SLEW-RATE-X
R/W
0
SLEW-RATE for linear slew mode:
0000: No slew for margin-high and margin-low. Invalid for
waveform generation.
0001: 4 µs/step
0010: 8 µs/step
0011: 12 µs/step
0100: 18 µs/step
0101: 27.04 µs/step
0110: 40.48 µs/step
0111: 60.72 µs/step
1000: 91.12 µs/step
1001: 136.72 µs/step
1010: 239.2 µs/step
1011: 418.64 µs/step
1100: 732.56 µs/step
1101: 1282 µs/step
1110: 2563.96 µs/step
1111: 5127.92 µs/step
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表7-31. Logarithmic-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
Field
Type
Reset
Description
12-11
PHASE-SEL-X
R/W
0
00: 0°
01: 120°
10: 240°
11: 90°
10 - 8
FUNC-CONFIG-X
R/W
R/W
0
0
000: Triangular wave
001: Sawtooth wave
010: Inverse sawtooth wave
100: Sine wave
111: Disable function generation
Others: Invalid
7
LOG-SLEW-EN-X
1: Enable logarithmic slew.
In logarithmic slew mode, the DAC output moves from the DAC-
X-MARGIN-LOW code to the DAC-X-MARGIN-HIGH code, or
vice versa, in 3.125% steps.
When slewing in the positive direction, the next step is (1 +
0.03125) times the current step.
When slewing in the negative direction, the next step is (1 ‒
0.03125) times the current step.
When DAC-X-MARGIN-LOW is 0, the slew starts from code 1.
The time interval for each step is defined by RISE-SLEW-X and
FALL-SLEW-X.
6-4
3-1
0
RISE-SLEW-X
FALL-SLEW-X
X
R/W
R/W
X
0
0
0
SLEW-RATE for logarithmic slew mode (DAC-X-MARGIN-LOW to
DAC-X-MARGIN-HIGH):
000: 4 µs/step
001: 12 µs/step
010: 27.04 µs/step
011: 60.72 µs/step
100: 136.72 µs/step
101: 418.64 µs/step
110: 1282 µs/step
111: 5127.92 µs/step
SLEW-RATE for logarithmic slew mode (DAC-X-MARGIN-HIGH
to DAC-X-MARGIN-LOW):
000: 4 µs/step
001: 12 µs/step
010: 27.04 µs/step
011: 60.72 µs/step
100: 136.72 µs/step
101: 418.64 µs/step
110: 1282 µs/step
111: 5127.92 µs/step
Don't care
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7.6.8 DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
PMBus page address = 00h, 01h, 02h, 03h, PMBus register address = 21h
图7-31. DAC-X-DATA Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-X-DATA[11:0]
DAC-X-DATA[9:0]
DAC-X-DATA[7:0]
X
R/W-000h
X-0h
表7-32. DAC-X-DATA Register Field Descriptions
Bit
15-4
Field
Type
Reset
Description
DAC-X-DATA[11:0]
DAC-X-DATA[9:0]
DAC-X-DATA[7:0]
R/W
000h
Data for DAC output
Data are in straight-binary format. MSB left-aligned.
Use the following bit-alignment:
DAC63204W VOUT: {DAC-X-DATA[11:0]}
DAC53204W VOUT: {DAC-X-DATA[9:0], X, X}
IOUT: {DAC-X-DATA[7:0], X, X, X, X}
X = Don't care bits.
3-0
X
X
0h
Don't care
7.6.9 COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
PMBus page address = FFh, PMBus register address = E3h
图7-32. COMMON-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WIN-
LATCH- LOCK
EN
DEV-
EE-READ-
ADDR
EN-INT-
REF
VOUT-PDN-3
IOUT-
PDN-3
VOUT-PDN-2
IOUT-
PDN-2
VOUT-PDN-1
IOUT-
PDN-1
VOUT-PDN-0
IOUT-
PDN-0
R/W-0h R/W-0h
R/W-0h
R/W-0h
R/W-11b
R/W-1b
R/W-11b
R/W-1b
R/W-11b
R/W-1b
R/W-11b
R/W-1b
表7-33. COMMON-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
WIN-LATCH-EN
R/W
0
0: Non-latching window-comparator output
1: Latching window-comparator output
14
DEV-LOCK
R/W
0
0: Device not locked.
1: Device locked, the device locks all the registers. To set this bit
back to 0 (unlock device), write to the unlock code to the DEV-
UNLOCK field in the COMMON-TRIGGER register first, followed
by a write to the DEV-LOCK bit as 0.
13
12
EE-READ-ADDR
EN-INT-REF
R/W
R/W
0
0
0: Fault-dump read enable at address 0x00
1: Fault-dump read enable at address 0x01
0: Disable internal reference.
1: Enable internal reference. This bit must be set before using
internal reference gain settings.
11-10, 8-7, VOUT-PDN-X
5-4, 2-1
R/W
R/W
11
1
00: Power-up VOUT-X
01: Power-down VOUT-X with 10 KΩto AGND
10: Power-down VOUT-X with 100 KΩto AGND
11: Power-down VOUT-X with Hi-Z to AGND
9, 6, 3, 0 IOUT-PDN-X
0: Power-up IOUT-X
1: Power-down IOUT-X
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7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E4h
图7-33. COMMON-TRIGGER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEV-UNLOCK
RESET
LDAC
CLR
X
FAULT- PROTECT
DUMP
READ-
ONE-
TRIG
NVM-
PROG RELOAD
NVM-
R/W-0h
R/W-0h
R/W-0h R/W-0h X-0h R/W-0h
R/W-0h
R/W-0h R/W-0h R/W-0h
表7-34. COMMON-TRIGGER Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
DEV-UNLOCK
R/W
0000
0101: Device unlocking password. To unlock device, write this
unlock password first, followed by a write 0 to the DEV-LOCK bit
in the COMMON-CONFIG register.
Others: Don't care
11 - 8
7
RESET
LDAC
W
0000
0
1010: POR reset triggered. This bit self-resets.
Others: Don't care
R/W
0: LDAC operation not triggered
1: LDAC operation triggered if the respective SYNC-CONFIG-X
bit in the DAC-X-FUNC-CONFIG register is 1. This bit self-resets.
6
CLR
R/W
0
0: DAC registers and outputs unaffected
1: DAC registers and outputs set to zero-code or mid-code based
on the respective CLR-SEL-X bit in the DAC-X-FUNC-CONFIG
register. This bit self-resets.
5
4
X
X
0
0
Don't care
FAULT-DUMP
R/W
0: Fault-dump is not triggered
1: Triggers fault-dump sequence. This bit self-resets.
3
2
1
0
PROTECT
R/W
R/W
R/W
R/W
0
0
0
0
0: PROTECT function not triggered
1: Trigger PROTECT function. This bit is self-resetting.
READ-ONE-TRIG
NVM-PROG
0: Fault-dump read not triggered
1: Read one row of NVM for fault-dump. This bit self-resets.
0: NVM write not triggered
1: NVM write triggered. This bit self-resets.
NVM-RELOAD
0: NVM reload not triggered
1: Reload data from NVM to register map. This bit self-resets.
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7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E5h
图7-34. COMMON-DAC-TRIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET-
CMP-
FLAG-0
TRIG-
MAR-
LO-0
TRIG-
MAR-
HI-0
START- RESET- TRIG-
TRIG- START- RESET- TRIG-
TRIG- START- RESET- TRIG-
TRIG- START-
MAR- FUNC-3
HI-3
FUNC-0 CMP-
FLAG-1
MAR-
LO-1
MAR- FUNC-1 CMP-
MAR-
LO-2
MAR- FUNC-2 CMP-
MAR-
LO-3
HI-1
FLAG-2
HI-2
FLAG-2
W-0h
W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h R/W-0h
表7-35. COMMON-DAC-TRIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15, 11, 7, RESET-CMP-FLAG-X
3
W
0
0: Latching-comparator output unaffected
1: Reset latching-comparator and window-comparator output.
This bit self-resets.
14, 10, 6, TRIG-MAR-LO-X
2
W
0
0
0
0: Don't care
1: Trigger margin-low command. This bit self-resets.
13, 9, 5, 1 TRIG-MAR-HI-X
W
0: Don't care
1: Trigger margin-high command. This bit self-resets.
12, 8, 4, 0 START-FUNC-X
R/W
0: Stop function generation
1: Start function generation as per FUNC-GEN-CONFIG-X in the
DAC-X-FUNC-CONFIG register.
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7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
PMBus page address = FFh, PMBus register address = E6h
图7-35. GENERAL-STATUS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NVM-
CRC-
FAIL-INT
NVM-
CRC-
FAIL-
USER
X
DAC-3- DAC-2- DAC-1- DAC-0-
X
DEVICE-ID
VERSION-ID
BUSY
R-0h
BUSY
R-0h
BUSY
R-0h
BUSY
R-0h
R-0h
R-0h
R-0h
X-0h
R
R-0h
表7-36. GENERAL-STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
NVM-CRC-FAIL-INT
R
0
0: No CRC error in OTP
1: Indicates a failure in OTP loading. A software
reset or power-cycle can bring the device out of
this condition in case of temporary failure.
14
NVM-CRC-FAIL-USER
R
0
0: No CRC error in NVM loading
1: Indicates a failure in NVM loading. The register
settings are corrupted. The device allows all
operations during this error condition. Reprogram
the NVM to get original state. A software reset
brings the device out of this temporary error
condition.
13
12
X
R
R
0
0
Don't care
DAC-3-BUSY
0: DAC-3 channel can accept commands
1: DAC-3 channel does not accept commands
11
10
9
DAC-2-BUSY
DAC-1-BUSY
DAC-0-BUSY
R
R
R
0
0
0
0
0: DAC-2 channel can accept commands
1: DAC-2 channel does not accept commands
0: DAC-1 channel can accept commands
1: DAC-1 channel does not accept commands
0: DAC-0 channel can accept commands
1: DAC-0 channel does not accept commands
8
X
R
R
Don't care
7-2
DEVICE-ID
DAC53204W: 02h
DAC63204W: 01h
Device identifier.
1-0
VERSION-ID
R
00
Version identifier.
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7.6.13 CMP-STATUS 寄存器（地址= 23h）[复位= 0000h]
PMBus 页面地址= FFh，PMBus 寄存器地址= E7h
图7-36. CMP-STATUS 寄存器
15
14
13
12
X
11
10
9
8
7
6
5
4
3
2
1
0
PROTECT- WIN- WIN- WIN- WIN- CMP- CMP- CMP- CMP-
FLAG
CMP-3 CMP-2 CMP-1 CMP-0 FLAG- FLAG- FLAG- FLAG-
3
2
1
0
X-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表7-37. CMP-STATUS 寄存器字段说明
位
字段
类型
复位
说明
15-9
8
X
X
0
0
不用考虑
PROTECT-FLAG
R
0：PROTECT 操作不会触发。
1：PROTECT 功能已完成或正在进行中。读取时该位复位为0。
WIN-CMP-X
R
R
0
0
7、6、5、
来自相应通道的窗口比较器输出。输出根据COMMON-CONFIG
寄存器中的WINDOW-LATCH-EN 设置来锁存或取消锁存。
4
CMP-FLAG-X
3、2、1、
来自相应通道的同步比较器输出。
0
7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E8h
图7-37. GPIO-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GF-EN
R/W-0h
X
GPO-EN
R/W-0h
GPO-CONFIG
R/W-0h
GPI-CH-SEL
R/W-0h
GPI-CONFIG
R/W-0h
GPI-EN
R/W-0h
X-0h
表7-38. GPIO-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
GF-EN
R/W
0
0: Glitch filter disabled for GP input. This setting provides faster
response.
1: Glitch filter enabled for GPI. This setting introduces additional
propagation delay but provides robustness.
14
13
X
X
0
0
Don't care.
GPO-EN
R/W
0: Disable output mode for GPIO pin.
1: Enable output mode for GPIO pin.
12 - 9
GPO-CONFIG
R/W
0000
STATUS function setting. The GPIO pin is mapped to the
following register bits as output:
0001: NVM-BUSY
0100: DAC-0-BUSY
0101: DAC-1-BUSY
0110: DAC-2-BUSY
0111: DAC-3-BUSY
1000: WIN-CMP-0
1001: WIN-CMP-1
1010: WIN-CMP-2
1011:WIN-CMP-3
Others: NA
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表7-38. GPIO-CONFIG Register Field Descriptions (continued)
Bit
Field
GPI-CH-SEL
Type
Reset
Description
8 - 5
R/W
0000
Each bit corresponds to a DAC channel. 0b is disabled and 1b is
enabled.
GPI-CH-SEL[0]: Channel 0
GPI-CH-SEL[1]: Channel 1
GPI-CH-SEL[2]: Channel 2
GPI-CH-SEL[3]: Channel 3
Example: when GPI-CH-SEL is 0101, both channel-0 and
channel-2 are enabled and both channel-1 and channel-3 are
disabled.
4 - 1
GPI-CONFIG
R/W
0000
GPIO pin input configuration. Global settings act on the entire
device. Channel-specific settings are dependent on the channel
selection by the GPI-CH-SEL bits:
0010: FAULT-DUMP (global). GPIO falling edge triggers fault
dump, GPIO = 1 has no effect.
0011: IOUT power up-down (channel-specific). GPIO falling edge
triggers power down, GPIO rising edge triggers power up.
0100: VOUT power up-down (channel-specific). The output load
is as per the VOUT-PDN-X setting. GPIO falling edge triggers
ECT input (global). GPIO falling edge asserts PROTECT function,
GPIO = 1 has no effect.
0111: CLR input (global). GPIO = 0 asserts CLR function, GPIO =
1 has no effect.
1000: LDAC input (channel-specific). GPIO falling edge asserts
LDAC function, GPIO = 1 has no effect. Both the SYNC-CONFIG-
X and the GPI-CH-SEL must be configured for every channel.
1001: Start and stop function generation (channel-specific). GPIO
falling edge stops function generation. GPIO rising edge starts
function generation.
1010: Trigger margin high-low (channel-specific). GPIO falling
edge triggers margin low. GPIO rising edge triggers margin high.
1011: RESET input (global). The falling edge of the GPIO pin
asserts the RESET function. The RESET input must be a pulse.
The GPIO rising edge brings the device out of reset. The RESET
configuration must be programmed into the NVM. Otherwise the
setting is cleared after the device reset.
1100: NVM write protection (global). GPIO falling edge allows
NVM programming. GPIO rising edge blocks NVM programming.
1101: Register-map lock (global). GPIO falling edge allows
update to the register map. GPIO rising edge blocks any register
map update except a write to the DEV-UNLOCK field through I2C
or SPI and to the RESET field through I2C.
Others: Invalid
0
GPI-EN
R/W
0
0: Disable input mode for GPIO pin.
1: Enable input mode for GPIO pin.
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7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E9h
图7-38. DEVICE-MODE-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
DIS-
MODE-IN
RESERVED
PROTECT-
CONFIG
RESERVED
X
R/W-0h
R/W-0h
R/W-0h
R/W-0h
X-0h
表7-39. DEVICE-MODE-CONFIG Register Field Descriptions
Bit
15-14
13
Field
RESERVED
Type
R/W
R/W
R/W
R/W
Reset
Description
00
0
Always write 0b00
DIS-MODE-IN
RESERVED
Write 1 to this bit for low-power consumption.
Always write 0b000
12-10
9-8
0
PROTECT-CONFIG
00
00: Switch to Hi-Z power-down (no slew)
01: Switch to DAC code stored in NVM (no slew) and then switch
to Hi-Z power-down
10: Slew to margin-low code and then switch to Hi-Z power-down
11: Slew to margin-high code and then switch to Hi-Z power-down
7-5
4-0
RESERVED
X
R/W
R/W
0
Always write 0b000
Don't care
00h
7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
图7-39. INTERFACE-CONFIG Register
15
14
X
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMEOUT-
EN
X
EN-PMBUS
X
FSDO-
EN
X
SDO-
EN
X-0h
R/W-0h
X-0h
R/W-0h
X-0h
R/W-0h X-0h R/W-0h
表7-40. INTERFACE-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
12
X
X
0h
Don't care
TIMEOUT-EN
R/W
0
0: I2C timeout disabled
1: I2C timeout enabled
11-9
8
X
X
0h
0
Don't care
EN-PMBUS
R/W
0: PMBus disabled
1: Enable PMBus
7-3
2
X
X
00h
0
Don't care
FSDO-EN
R/W
0: Fast SDO (FSDO) disabled
1: Fast SDO enabled
1
0
X
X
0
0
Don't care
SDO-EN
R/W
0: SDO disabled
1: SDO enabled on GPIO pin
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7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
PMBus page address = FFh, PMBus register address = EFh
图7-40. SRAM-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
SRAM-ADDR
R/W-00h
X-00h
表7-41. SRAM-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
7-0
X
X
00h
Don't care
SRAM-ADDR
R/W
00h
8-bit SRAM address. Writing to this register field configures the
SRAM address to be accessed next. This address automatically
increments after a write to the SRAM.
7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
PMBus page address = FFh, PMBus register address = F0h
图7-41. SRAM-DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRAM-DATA
R/W-0000h
表7-42. SRAM-DATA Register Field Descriptions
Bit
15-0
Field
SRAM-DATA
Type
Reset
Description
R/W
0000h
16-bit SRAM data. Data are written to or read from the address
configured in the SRAM-CONFIG register.
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7.6.19 DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
PMBus page address = Not applicable, PMBus register address = Not applicable
图7-42. DAC-X-DATA-8BIT Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-X-DATA-8BIT[7:0]
R/W-00h
X
X-00h
表7-43. DAC-X-DATA-8BIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
DAC-X-DATA-8BIT[7:0]
X
R/W
00h
8-bit data for current output. This register provides faster update
rate in the I2C mode. Data are in straight-binary format.
7-0
X
00h
Not applicable
7.6.20 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = F1h
图7-43. BRDCAST-DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BRDCAST-DATA[11:0]
BRDCAST-DATA[9:0]
BRDCAST-DATA[7:0]
X
R/W-000h
X-0h
表7-44. BRDCAST-DATA Register Field Descriptions
Bit
15-4
Field
Type
Reset
Description
BRDCAST-DATA[11:0]
BRDCAST-DATA[9:0]
BRDCAST-DATA[7:0]
R/W
000h
Broadcast code for all DAC channels
Data are in straight-binary format. MSB left-aligned.
Use the following bit-alignment:
DAC63204W VOUT: {BRDCAST-DATA[11:0]}
DAC53204W VOUT: {BRDCAST-DATA[9:0], X, X}
IOUT: {BRDCAST-DATA[7:0], X, X, X, X}
X = Don't care bits.
The BRD-CONFIG-X bit in the DAC-X-FUNC-CONFIG register
must be enabled for the respective channels.
3-0
X
X
0h
Don't care.
7.6.21 PMBUS-PAGE Register [reset = 0300h]
PMBus page address = X, PMBus register address = 00h
图7-44. PMBUS-PAGE Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PMBUS-PAGE
R/W-03h
X
X-00h
表7-45. PMBUS-PAGE Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
PMBUS-PAGE
R/W
03h
8-bit PMBus page address as specified in the Register Names
table in the Register Map section.
7-0
X
X
00h
Not applicable
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7.6.22 PMBUS-OP-CMD-X Register [reset = 0000h]
PMBus page address = 00h, 01h, 02h, 03h, PMBus register address = 01h
图7-45. PMBUS-OP-CMD-X Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PMBUS-OPERATION-CMD-X
R/W-00h
X
X-00h
表7-46. PMBUS-OP-CMD-X Register Field Descriptions
Bit
15-8
Field
Type
Reset
Description
PMBUS-OPERATION-CMD-X
R/W
00h
PMBus operation commands:
00h: Turn off
80h: Turn on
A4h: Margin high, DAC output margins high to DAC-X-MARGIN-
HIGH code
94h: Margin low, DAC output margins low to DAC-X-MARGIN-
LOW code
7-0
X
X
00h
Not applicable
7.6.23 PMBUS-CML Register [reset = 0000h]
PMBus page address = X, PMBus register address = 78h
图7-46. PMBUS-CML Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
CML
R/W-0h
X
N/A
X-00h
X-0h
X-00h
表7-47. PMBUS-CML Register Field Descriptions
Bit
Field
Type
Reset
00h
0
Description
15-10
9
X
X
Don't care
CML
R/W
0: No communication fault
1: PMBus communication fault for write with incorrect number of
clocks, read before write command, invalid command address,
and invalid or unsupported data value; reset this bit by writing 1.
8
X
X
X
X
0h
Don't care
7-0
00h
Not applicable
7.6.24 PMBUS-VERSION 寄存器[复位= 2200h]
PMBus 页面地址= X，PMBus 寄存器地址= 98h
图7-47. PMBUS-VERSION 寄存器
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PMBUS-VERSION
R-22h
X
X-00h
表7-48. PMBUS-VERSION 寄存器字段说明
位
字段
类型
复位
说明
15-8
7-0
PMBUS-VERSION
X
R
22h
PMBus 版本
不可用
X
00h
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8 应用和实现
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The DACx3204W are quad-channel buffered, force-sense output, voltage-output and current-output smart DACs
that include an NVM and internal reference, and are available in a tiny 1.75-mm × 1.75-mm DSBGA package.
The external reference must not exceed VDD, either during transient or steady-state conditions. For the best Hi-Z
output performance, use a pullup resistor on the VREF pin to VDD. In case the VDD pin remains floating during
the off condition, place a 100-kΩ resistor to AGND for proper detection of the VDD pin off condition. All the
digital outputs are open drain; use external pullup resistors on these pins. The interface protocol is detected at
power-on, and the device locks to the protocol as long as VDD is on. In I2C mode, when allocating the I2C
addresses in the system, also consider the broadcast address. I2C timeout can be enabled for robustness. SPI
mode is three-wire by default. Configure the GPIO pin as SDO in the NVM for SPI readback capability. The SPI
clock speed in readback mode is slower than in write mode. Power-down mode sets the DAC outputs in Hi-Z by
default. Change the configuration appropriately for different power-down settings. The DAC channels can also
power-up with a programmed DAC code in the NVM.
8.2 Typical Application
The DACx3204W can be used as a programmable current source using an external MOSFET for current values
greater than 250 µA. The force-sense outputs of DACx3204W can be used to compensate for the gate-source
voltage drop caused by temperature, drain current, and aging of the MOSFET. The GPIO pin can be used to
switch the output current on or off without the need for run-time software. The slew between the on and off
values can be programmed. 图 8-1 shows how the DACx3204W is used as a programmable current source. A
resistor, RSET, connected to the source of the MOSFET sets the output current range. This circuit can be used in
optical modules that require a high current output with a small size.
1.5 F
100nF
VDD
VDD
10k
15 VDD 16 VREF
13 CAP
IOUTx
LDO
Internal
Reference
NVM
DAC
BUF
DAC
REG
11
12
OUT0
FB0
VSET
8 SDA/SCLK
7 A0/SDI
DAC
BUF
DAC
REG
10
9
OUT1
FB1
RSET
6 SCL/SYNC
5 GPIO/SDO
DAC
BUF
DAC
REG
3
4
OUT2
FB2
HIGH
DAC
BUF
DAC
REG
LOW
2
1
OUT3
FB3
Output Configuration
Logic
14 AGND
图8-1. Current Source
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8.2.1 Design Requirements
表8-1. Design Parameters
PARAMETER
VALUE
0 mA to 200 mA
0 V to 0.6 V
3 Ω
Current output range
DAC range
RSET
8.2.2 Detailed Design Procedure
VSET is controlled by the DACx3204W to adjust the current output. RSET sets the output range of the current
source. Choose a small VSET so that the power dissipation across RSET is minimum. 方程式9 calculates RSET
.
V
SET
R
=
(9)
SET
I
OUT
A 0.6-V max VSET is used in this example. 方程式 10 shows that RSET is calculated to be 3 Ω. Choose an RSET
with a power rating of at least 120 mW.
0.6 V
200 mA
R
=
= 3 Ω
(10)
SET
方程式11 shows how to calculate the DAC code for a given output voltage, reference, and gain setting.
N
V
× 2
OUT
DAC_DATA =
(11)
V
× GAIN
REF
方程式 12 calculates the DAC code for an output voltage, VSET, of 0.6V, the internal 1.21-V reference, and the
1.5 × gain setting.
12
0.6 V × 2
DAC_DATA =
= 1354d
(12)
1.21 V × 1.5
The GPIO pin can be configured as an input to trigger the DACx3x04W output to turn on and off, which turns the
current source on and off. Configure the GPIO in the GPIO-CONFIG register. The GPI-EN bit enables the GPIO
pin as an input. The GPI-CH-SEL field selects which channels are controlled by the GPI. The GPI-CONFIG field
selects the GPI function. 表7-18 defines the functions for the GPI-CONFIG field. Choose the trigger margin-high
or margin-low function if programmable slew is needed, or VOUT power up or down if programmable slew is not
needed.
The programmable slew is configured by the CODE-STEP and SLEW-RATE fields in the DAC-X-FUNC-CONFIG
Register. The programmable slew is only available when toggling between two values stored in the DAC-X-
MARGIN-HIGH and DAC-X-MARGIN-LOW Registers. 节7.4.5.1.2 discusses how to set the programmable slew.
This application example uses a SLEW-RATE of 8 µV/s and a CODE-STEP of 8-LSB to achieve a 1.36-ms slew
time.
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The pseudo code for this application example is as follows:
//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Set gain setting to 1.5x internal reference (1.8 V) (repeat for all channels)
WRITE DAC-0-VOUT-CMP-CONFIG(0x3), 0x08, 0x00
//Power-up voltage output on all channels and enable the internal reference
WRITE COMMON-CONFIG(0x1F),0x12, 0x49
//Configure GPI for Margin-High, Low trigger for all channels
WRITE GPIO-CONFIG(0x24), 0x01, 0xF5
//Set slew rate and code step (repeat for all channels)
//CODE_STEP: 8 LSB, SLEW_RATE: 8 µs/step
WRITE DAC-0-FUNC-CONFIG(0x06), 0x00, 0x52
//Write DAC margin high code (repeat for all channels)
//For a 1.8-V output range, the 12-bit hex code for 0.6 V is 0x54A. With 16-bit left alignment,
this becomes 0x54A0
WRITE DAC-0-MARGIN-HIGH(0x01), 0x54, 0xA0
//Write DAC margin low code (repeat for all channels)
//The 12-bit hex code for 0 V is 0x000. With 16-bit left alignment, this
becomes 0x0000
WRITE DAC-0-MARGIN-LOW(0x02), 0x00, 0x00
//Save settings to NVM
WRITE COMMON-TRIGGER(0x20), 0x00, 0x02
8.2.3 Application Curve
1
0.8
0.6
0.4
0.2
0
250
200
150
100
50
VFB (V)
IOUT (mA)
0
0
1
2
3
4
5
6
7
8
Time (ms)
图8-2. IOUT and VFB On-to-Off Transition
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8.3 Power Supply Recommendations
The DACx3204W family of devices does not require specific power-supply sequencing. These devices require a
single power supply, VDD. However, make sure the external voltage reference is applied after VDD. Use a 0.1-µF
decoupling capacitor for the VDD pin. Use a bypass capacitor with a value approximately 1.5 µF for the CAP pin.
8.4 布局
8.4.1 布局指南
DACx3204W 引脚配置将模拟、数字和电源引脚分开以实现优化布局。为了保证信号完整性，需将数字和模拟走
线分开，并将去耦电容器放置在器件引脚附近。
8.4.2 Layout Example
VREF Pullup
Resistor
VDD
OUT2
OUT3
GPIO/SDO
VIO
GND
VREF Bypass
Capacitor
GND
VDD
A2
B2
C2
D2
A3
B3
C3
D3
A1
B1
C1
A4
B4
C4
D4
SCL/SYNC
VIO
Decoupling
Capacitor
GND
VIO
A0/SDI
LDO Bypass
Capacitor
D1
VIO
DACx3204W
SDA/SCLK
OUT0
OUT1
图8-3. Layout Example
Note: The ground and power planes have been omitted for clarity.
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9 器件和文档支持
TI 提供大量的开发工具。下面列出了用于评估器件性能、生成代码和开发解决方案的工具和软件。
9.1 Documentation Support
备注
TI is transitioning to use more inclusive terminology. Some language can be different than what is
expected for certain technology areas.
9.1.1 Related Documentation
The following EVM user's guide is available: DAC63004 Evaluation Module user's guide
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 商标
TI E2E™ is a trademark of Texas Instruments.
PMBus® is a registered trademark of SMIF, Inc.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，
且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
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23-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC53204YBHR
ACTIVE
DSBGA
YBH
16
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
DAC
53204
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
YBH0016
DSBGA - 0.4 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.4 MAX
SEATING PLANE
0.05 C
BALL TYP
0.16
0.10
1.2 TYP
SYMM
D
C
1.2
TYP
SYMM
D: Max = 1.748 mm, Min =1.687 mm
E: Max = 1.748 mm, Min =1.687 mm
B
A
0.4
TYP
2
1
3
4
0.225
0.185
16X
0.015
0.4 TYP
C A B
4225022/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YBH0016
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
16X ( 0.2)
2
1
4
A
(0.4) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.2)
METAL
(
0.2)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225022/A 06/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YBH0016
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
(R0.05) TYP
4
16X ( 0.21)
1
2
A
(0.4) TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4225022/A 06/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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