DAC5674IPHP [TI]
14-BIT, 40 MSPS, 2x/4x INTERPOLATING CommsDAC DIGITAL-TO-ANALOG CONVERTER; 14位， 40 MSPS ， 2倍/ 4倍插值CommsDAC数位类比转换器
| 型号： | DAC5674IPHP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-BIT, 40 MSPS, 2x/4x INTERPOLATING CommsDAC DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总39页 (文件大小：1314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
8
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D
Differential Scalable Current Outputs: 2 mA to
20 mA
FEATURES
D
D
D
200-MSPS Maximum Input Data Rate
400-MSPS Maximum Update Rate DAC
D
On-Chip 1.2-V Reference
D
1.8-V Digital and 3.3-V Analog Supply
Operation
76-dBc SFDR Over Full First Nyquist Zone
With Single Tone Input Signal (F = 21 MHz)
D
D
D
1.8/3.3-V CMOS Compatible Interface
Power Dissipation: 435 mW at 400 MSPS
Package: 48-Pin TQFP
out
D
D
D
74-dBc ACPR W-CDMA at 15.36 MHz IF
69-dBc ACPR W-CDMA at 30.72 MHz IF
Selectable 2y or 4y Interpolation Filter
− Linear Phase
− 0.05-dB Pass-Band Ripple
− 80-dB Stop-Band Attenuation
APPLICATIONS
D
Cellular Base Transceiver Station Transmit
Channel
− CDMA: W-CDMA, CDMA2000, IS-95
− TDMA: GSM, IS-136, EDGE/UWC-136
− Stop-Band Transition 0.4−0.6 F
data
− Interpolation Filters Configurable in Either
Low-Pass or High-Pass Mode, Allows For
Selection High-Order Images
D
Test and Measurement: Arbitrary Waveform
Generation
D
D
Direct Digital Synthesis (DDS)
D
On-Chip 2y /4y PLL Clock Multiplier, PLL
Bypass Mode
Cable Modem Termination System
DESCRIPTION
The DAC5674 is a 14-bit resolution, high-speed, digital-to-analog converter (DAC) with integrated
4× interpolation filter, onboard clock multiplier, and on-chip voltage reference. The device has been designed
for high-speed digital data transmission in wired and wireless communication systems, high-frequency
direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.
The 4× interpolation filter is implemented as a cascade of two 2× interpolation filters, each of which can be
configured for either low-pass or high-pass response. This enables the user to select one of the higher order
images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting
high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter
architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and
costs.
In 4× interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at
intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission
in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter
requirements by filtering out the images in the adjacent Nyquist zones.
The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential
clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is
supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock
divider of the PLL ensures that the digital filters operate at the correct clock frequencies.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Excel is a trademark of Microsoft Corporation.
CommsDAC and PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
ꢐꢕ ꢖ ꢀꢝ ꢂ ꢋꢊ ꢖꢓ ꢀ ꢁꢋꢁ ꢞꢟ ꢠꢙ ꢡ ꢚꢢ ꢣꢞꢙꢟ ꢞꢛ ꢤꢥ ꢡ ꢡ ꢦꢟꢣ ꢢꢛ ꢙꢠ ꢧꢥꢨ ꢩꢞꢤ ꢢꢣꢞ ꢙꢟ ꢪꢢ ꢣꢦꢫ ꢐꢡ ꢙꢪꢥ ꢤꢣꢛ
ꢤ ꢙꢟ ꢠꢙꢡ ꢚ ꢣꢙ ꢛ ꢧꢦ ꢤ ꢞ ꢠꢞ ꢤ ꢢ ꢣꢞ ꢙꢟꢛ ꢧ ꢦꢡ ꢣꢬꢦ ꢣꢦ ꢡ ꢚꢛ ꢙꢠ ꢋꢦꢭ ꢢꢛ ꢊꢟꢛ ꢣꢡ ꢥꢚ ꢦꢟꢣ ꢛ ꢛꢣ ꢢꢟꢪ ꢢꢡ ꢪ ꢮ ꢢꢡ ꢡ ꢢ ꢟꢣꢯꢫ
ꢐꢡ ꢙ ꢪꢥꢤ ꢣ ꢞꢙ ꢟ ꢧꢡ ꢙ ꢤ ꢦ ꢛ ꢛ ꢞꢟ ꢰ ꢪꢙ ꢦ ꢛ ꢟꢙꢣ ꢟꢦ ꢤꢦ ꢛꢛ ꢢꢡ ꢞꢩ ꢯ ꢞꢟꢤ ꢩꢥꢪ ꢦ ꢣꢦ ꢛꢣꢞ ꢟꢰ ꢙꢠ ꢢꢩ ꢩ ꢧꢢ ꢡ ꢢꢚ ꢦꢣꢦ ꢡ ꢛꢫ
Copyright 2005, Texas Instruments Incorporated
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
The DAC5674 operates from an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. The digital
I/Os are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 500 mW at maximum operating conditions.
The DAC5674 provides a nominal full-scale differential current-output of 20 mA, supporting both single-ended
and differential applications. The output current can be directly fed to the load with no additional external output
buffer required. The device has been specifically designed for a differential transformer coupled output with a
50-Ω doubly terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an
output power of 4 dBm) and 1:1 impedance ratio transformer (−2-dBm output power) are supported. The latter
configuration is preferred for optimum performance at high output frequencies and update rates.
An accurate on-chip 1.2-V temperature compensated band-gap reference and control amplifier allows the user
to adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control
capabilities. Alternatively, an external reference voltage may be applied for maximum flexibility. The device
features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby optimizing the
power consumption for the system’s need.
The DAC5674 is available in a 48-pin HTQFP PowerPAD plastic quad flatpack package. The device is
characterized for operation over the industrial temperature range of −40°C to 85°C.
AVAILABLE OPTIONS
T
PACKAGED DEVICES
48-HTQFP PowerPAD Plastic Quad Flatpack
DAC5674IPHP
A
−40°C to 85°C
DAC5674IPHPR
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNIT
−0.5 V to 4 V
(2) (2)
(2)
(2)
AVDD , CLKVDD , IOVDD , PLLVDD
Supply voltage range
(3)
DVDD
−0.5 V to 2.3 V
−0.5 V to 0.5 V
−0.5 V to IOVDD + 0.5 V
−1 V to AVDD + 0.5 V
−0.5 V to AVDD + 0.5 V
20 mA
Voltage between AGND, DGND, CLKGND, PLLGND, and IOGND
(3) (3) (3)
(3)
(3)
(3)
D[13..0] , HP1, HP2, DIV0 , DIV1 , PLLLOCK , RESET , X4
(2)
IOUT1, IOUT2
(2)
Supply voltage range
(2) (2)
(2)
(2)
(2)
(2)
EXTIO , EXTLO , BIASJ , SLEEP , CLK , CLKC , LPF
Peak input current (any input)
Peak total input current (all inputs)
−30 mA
Operating free-air temperature range, T : DAC5674I
A
−40°C to 85°C
−65°C to 150°C
260°C
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured with respect to AGND.
(2)
(3)
Measured with respect to DGND.
2
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
DC ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, R = 1.91 kΩ, internal reference, unless otherwise noted
set
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
14
Bits
(1)
DC ACCURACY
−3.5
−2.14e−4
−2
3.5
LSB
14
1 LSB = IOUT /2 , T
FS MIN
INL
Integral nonlinearity
to T
MAX
2.14e−4 IOUT
FS
LSB
2
DNL
Differential nonlinearity
−1.22e−4
1.22e−4 IOUT
FS
Monotonicity
Montonic to 12 bits
ANALOG OUTPUT
Offset error
0.02
2.3
FSR
Without internal reference
With internal reference
Gain error
%FSR
1.3
Minimum full-scale output
current
2
mA
mA
(2)
Maximum full-scale output
(2)
20
current
(3)
Output compliance range
Output resistance
IOUT
FS
= 20 mA
−1
300
5
1.25
V
kΩ
pF
Output capacitance
REFERENCE OUTPUT
Reference voltage
1.14
1.2
1.26
1.25
V
(4)
Reference output current
100
nA
REFERENCE INPUT
V
Input voltage range
Input resistance
0.1
V
EXTIO
1
1.4
MΩ
MHz
pF
Small signal bandwidth
Input capacitance
100
TEMPERATURE COEFFICIENTS
ppm of
FSR/°C
Offset drift
0
ppm of
FSR/°C
Without internal reference
With internal reference
50
Gain drift
ppm of
FSR/°C
100
50
Reference voltage drift
ppm/°C
POWER SUPPLY
AVDD
Analog supply voltage
Digital supply voltage
Clock supply voltage
I/O supply voltage
3
1.65
3
3.3
1.8
3.3
3.6
1.95
3.6
V
V
V
V
V
DVDD
CLKVDD
IOVDD
PLLVDD
1.65
3
3.6
PLL supply voltage
3.3
41
3.6
Including output current through the load
resistor, AVDD = 3.3 V, DVDD = 1.8 V, 4×
interpolation, PLL on, 9-MHz IF, 400 MSPS
I
Analog supply current
55
mA
AVDD
Specifications subject to change without notice.
(1)
Measured differentially across IOUT1 and IOUT2 into 50 Ω.
Nominal full-scale current, IOUTFS, equals 32× the IBIAS current.
The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting
in reduced reliability of the DAC5674 device. The upper limit of the output compliance is determined by the load resistors and full-scale output
current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(2)
(3)
(4)
Use an external buffer amplifier with high impedance input to drive any external load.
3
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, R = 1.91 kΩ, internal reference, unless otherwise noted
set
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY (CONTINUED)
AVDD = 3.3 V, DVDD = 1.8 V, 4× interpolation,
PLL on, 9-MHz IF, 400 MSPS
I
Digital supply current
107
140
mA
DVDD
I
I
Sleep mode
Sleep mode
Sleep mode, supply current 3.3 V
Sleep mode, supply current 1.8 V
6
12
3
mA
mA
SLEEP3.3
SLEEP1.8
0.5
F
= 100 MSPS, F = 400 MSPS,
update
data
(1)
I
PLL supply current
DIV[1:0] = ’00’, AVDD = 3.3 V, DVDD = 1.8 V, 4×
interpolation, PLL on, 9-MHz IF, 400 MSPS
23
35
mA
PLLVDD
AVDD = 3.3 V, DVDD = 1.8 V, 4× interpolation,
PLL on, 9-MHz IF, 400 MSPS
I
I
Buffer supply current
4
6
10
10
mA
mA
mW
IOVDD
AVDD = 3.3 V, DVDD = 1.8 V, 4× interpolation,
PLL on, 9-MHz IF, 400 MSPS
(1)
Clock supply current
CLKVDD
AVDD = 3.3 V, DVDD = 1.8 V, 4× interpolation,
PLL on, 9-MHz IF, 400 MSPS
P
Power dissipation
435
550
D
APSRR
DPSRR
Power supply rejection ratio
−0.2
0.2
0.2
85
%FSR/V
−0.2
−40
Operating range
°C
Specifications subject to change without notice.
(1)
PLL enabled
AC ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 1.8 V, DVDD = 1.8 V,
IOUTFS = 20 mA, differential transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted)
PARAMETER
ANALOG OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
t
t
t
Maximum output update rate
Output settling time to 0.1%
Output rise time 10% to 90%
400
MSPS
ns
CLK
Midscale transition
20
1.4
1.5
55
s(DAC)
r(IOUT)
f(IOUT)
(1)
(1)
ns
Output fall time 90% to 10%
ns
IOUT
IOUT
= 20 mA
FS
Output noise
pA/√HZ
= 2 mA
30
FS
AC LINEARITY 1:1 IMPEDANCE RATIO TRANSFORMER (ALL AC MEASUREMENTS PLLVDD = 0 V)
f
f
f
f
f
= 52 MSPS, f
OUT
= 14 MHz, T = 25_C
85
76
71
71
70
DATA
DATA
DATA
DATA
DATA
A
Spurious free dynamic range (First
Nyquist zone < f /2) X4 LL-mode
= 100 MSPS, f
= 21 MHz, T
to T
SFDR
dBc
OUT
OUT
MIN
MIN
MAX
MAX
DATA
= 100 MSPS, f
= 41 MHz, T
to T
= 78 MSPS, f
OUT
= 20 MHz, T
MIN
to T
MAX
Signal-to-noise ratio (First Nyquist
zone < f /2) X4 LL-mode
SNR
dB
dB
= 100 MSPS, f
OUT
= 20 MHz, T to T
MIN MAX
DATA
Adjacent channel power ratio
W-CDMA signal with 3.84-MHz BW
5-MHz channel spacing
f
= 61.44 MSPS, IF = 15.360 MHz, X4 LL-mode
= 122.88 MSPS, IF = 30.72 MHz, X2 L-mode
74
69
DATA
ACPR
f
f
DATA
= 61.44 MSPS, f
= 45.4 and 46.4 MHz,
DATA
OUT
68
82
76
64
X4 HL-mode
Third-order, two-tone intermodulation
(each tone at −6 dBFS)
IMD3
IMD
dBc
dBc
f
= 61.44 MSPS, f
= 15.1 and 16.1 MHz,
DATA
OUT
X4 LL-mode
f
= 78 MSPS f = 15.6 MHz, 15.8 MHz,
OUT
DATA
16.2 MHz, 16.4 MHz, X4 LL-mode
Four-tone Intermodulation to Nyquist
(each tone at –12 dBFS)
f
= 52 MSPS f = 68.8 MHz, 69.6 MHz,
DATA
OUT
71.2 MHz, 72 MHz, X4 HH-mode
(1)
Measured single-ended into 50-Ω load.
4
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, differential transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted)
DIGITAL SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CMOS INTERFACE
V
V
V
V
High-level input voltage for SLEEP and EXTLO
Low-level input voltage for SLEEP and EXTLO
High-level input voltage other digital inputs
Low-level input voltage other digital inputs
High-level input current
0.7 AV
V
V
IH
DD
0
0.3 AV
IL
DD
0.7 IOV
V
IH
IL
DD
0
0.3 IOV
V
DD
30
I
10
−1
1
µA
µA
pF
IH
IL
I
Low-level input current
10
5
Input capacitance
TIMING INTERNAL CLOCK MODE
t
t
t
t
t
Input setup time
0.6
0.6
ns
ns
ns
clk
clk
SU
Input hold time
H
Input latch pulse high time
2
26
35
LPH
lat_2x
lat_4x
Data in to DAC out latency − 2× interpolation
Data in to DAC out latency − 4× interpolation
TIMING − EXTERNAL CLOCK MODE
t
t
t
t
t
t
Input setup time
5
ns
ns
ns
ns
clk
clk
su
Input hold time
−1.75
h
Input latch pulse high time
Clock delay time
2
3.6
26
lph
d_clk
lat_2x
lat_4x
Data in to DAC out latency − 2× interpolation
Data in to DAC out latency − 4× interpolation
35
PLL
Input data rate supported
Phase noise
5
200 MSPS
dBc/Hz
At 600-kHz offset
At 6-MHz offset
−124
−134
DIGITAL FILTER SPECIFICATIONS
f
Input data rate
200 MSPS
DATA
FIR1 and FIR2 DIGITAL FILTER CHARACTERISTICS
0.005 db
0.01 dB
0.1 dB
3 dB
0.407
0.41
f
f
/
OUT
Pass-band width
0.427
0.481
DATA
5
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
PINOUT DIAGRAM
PHP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
DGND
DGND
D13
D12
D11
D10
D9
SLEEP
LPF
2
3
PLLVDD
PLLGND
CLKVDD
CLKGND
CLKC
4
5
6
7
8
D8
D7
D6
D5
CLK
DIV0
DIV1
RESET
PLLLOCK
9
10
11
12
D4
13 14 15 16 17 18 19 20 21 22 23 24
6
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
AVDD
37, 41, 44
45, 46
40
I
I
Analog ground return
Analog supply voltage
BIASJ
O
I
Full-scale output current bias
External clock input
CLK
29
CLKC
30
I
Complementary external clock input
Ground return for internal clock buffer
Internal clock buffer supply voltage
CLKGND
CLKVDD
D[13..0]
31
I
32
I
3−16
I
Data bits 0 through 13
D13 is most significant data bit (MSB)
D0 is least significant data bit (MSB)
DIV[1..0]
DGND
DVDD
27,28
1, 2, 19, 24
21, 47, 48
39
I
I
I
PLL prescaler divide ratio settings
Digital ground return
Digital supply voltage
EXTIO
I/O Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
Used as internal reference output when EXTLO = AGND, requires a 0.1-µF decoupling capacitor to AGND
when used as reference output
EXTLO
HP1
38
17
18
20
22
43
42
35
33
25
I
I
For internal reference connect to AGND. Connect to AVDD to disable the internal reference
Filter 1 high-pass setting. Active high
HP2
I
Filter 2 high-pass setting. Active high
IOGND
IODVDD
IOUT1
IOUT2
LPF
I
Input digital ground return
I
Input digital supply voltage
O
O
I
DAC current output. Full scale when all input bits are set 1
DAC complementary current output. Full scale when all input bits are 0
PLL loop filter connection
PLLGND
PLLLOCK
I
Ground return for internal PLL
O
PLL lock status bit. PLL is locked to input clock when high. Provides output clock equal to the data rate
when the PLL is disabled.
PLLVDD
RESET
SLEEP
X4
34
26
36
23
I
I
I
I
Internal PLL supply voltage. Connect to PLLGND to disable PLL clock multiplier.
Reset internal registers. Active high
Asynchronous hardware power-down input. Active high. Internally pull down.
4× interpolation mode. Active high. Filter 1 is bypassed when connected to DGND
7
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FUNCTIONAL BLOCK DIAGRAM
CLKVDD
CLKGND PLLLOCK
LPF
PLLGND
PLLVDD
DIV[1:0]
HP1
HP2
X4
CLK
SLEEP
PLL Clock
Multiplier
48-Pin TQFP
CLKC
AVDD (2y )
AGND (3y )
Clock Generation / Mode Select
HP1
X4
HP2
IODVDD
IOGND
BIASJ
..., 1, −1,...
..., 1, −1,...
D[13:0]
IOUT1
IOUT2
1
0
1
0
y 2
FIR1
y 2
FIR2
14-BIt DAC
1
0
Edge-
Triggered
Input
EXTIO
1.2-V
Reference
EXTLO
Latches
DVDD (3y )
DGND (4y )
Figure 1. Block Diagram
8
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TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
INPUT CODE
1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
V
= 3.3 V
f = 20 mA
CC
I
OUT S
0
2000
4000
6000
8000
10000
12000
14000
16000
Input Code
Figure 2
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
1.0
0.8
V
= 3.3 V
f = 20 mA
CC
I
OUT S
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
2000
4000
6000
8000
10000
12000
14000
16000
Input Code
Figure 3
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SPURIOUS-FREE DYNAMIC RANGE
SPURIOUS-FREE DYNAMIC RANGE
vs
vs
OUTPUT FREQUENCY
OUTPUT FREQUENCY
90
85
80
75
70
65
60
55
50
90
V
= 3.3 V
CC
= 100 MSPS
V
f
= 3.3 V
CC
= 50 MSPS
f
I
S
S
85
80
75
70
65
60
55
50
f = 20 mA
OUT S
4y LL-Mode
I
f = 20 mA
OUT S
4y LL-Mode
−3 dBf
S
0 dBf
S
0 dBf
S
−6 dBf
S
−6 dBf
S
−3 dBf
S
0
5
10
15
20
25
30
35
0
3
6
9
12
15
18
f
O
− Output Frequency − MHz
f
O
− Output Frequency − MHz
Figure 4
Figure 5
IN-BAND
POWER
vs
SPURIOUS-FREE DYNAMIC RANGE
vs
FREQUENCY
OUTPUT FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
90
V
= 3.3 V
V
= 3.3 V
CC
= 100 MSPS
CC
f = 100 MSPS
S
f
I
S
85
80
75
70
65
60
55
50
f
= 20 mA
I
f = 20 mA
OUT S
4y LL-Mode
= 10 MHz
OUT S
4y LL-Mode
0 dBf
S
F
out
In Band = 0 − 50 MHz
−6 dBf
S
−12 dBf
S
0
25
50
75
100 125 150 175 200
0
5
10
15 20
25 30
35 40 45
f − Frequency − MHz
f
O
− Output Frequency − MHz
Figure 6
Figure 7
NOTE: All measurements made with PLL off.
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OUT-OF-BAND
SPURIOUS-FREE DYNAMIC RANGE
vs
POWER
vs
FREQUENCY
OUTPUT FREQUENCY
−20
−40
80
V
= 3.3 V
CC
= 61.44 MSPS
V
= 3.3 V
CC
= 100 MSPS
f
f
S
75
70
65
60
55
50
45
40
35
30
f
S
= 15.36 MHz
f = 20 mA
carrier
I
f = 20 mA
OUT S
I
OUT S
4y LL-Mode
ACPR = 73.25 dB
4y LL-Mode
Out-of-Band = 50 − 100 MHz
−60
−6 dBf
S
−80
−12 dBf
S
0 dBf
S
−100
−120
6
9
12
15
18
21
24
0
5
10
15 20
25 30
35 40 45
f − Frequency − MHz
f
O
− Output Frequency − MHz
Figure 8
Figure 9
POWER
vs
FREQUENCY
POWER
vs
FREQUENCY
−20
−40
−20
−40
V
f
= 3.3 V
=76.80 MSPS
I
f = 20 mA
V
f
= 3.3 V
= 122.88 MSPS
= 30.72 MHz
CC
S
OUT S
CC
S
ACPR = 70.22 dB
4y LL-Mode
f
= 19.20 MHz
f
I
carrier
carrier
OUT S
f
= 20 mA
ACPR = 70.23 dB
2y L-Mode
−60
−60
−80
−80
−100
−120
−100
−120
8
12
16
20
24
28
17
21
25
29
33
37
41
45
f − Frequency − MHz
f − Frequency − MHz
Figure 10
Figure 11
NOTE: All measurements made with PLL off.
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POWER
vs
TWO-TONE IMD3
vs
FREQUENCY
OUTPUT FREQUENCY
−20
90
85
80
75
70
65
60
55
50
V
= 3.3 V
CC
= 61.44 MSPS
f
f
S
= 15.36 MHz
f = 20 mA
carrier
I
OUT S
−40
−60
ACPR = 69.73 dB
4y LH-Mode
−80
V
= 3.3 V
CC
= 78 MSPS
f
f
f
S
−100
−120
= f
out1 out
out2 out
= f + 1 MHz
f = 20 mA
I
OUT S
4y LL-Mode
32
36
40
44
48
52
56
60
0
5
10
15
20
25
30
35
f − Frequency − MHz
f
O
− Output Frequency − MHz
Figure 12
Figure 13
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
90
85
80
75
70
65
60
55
V
= 3.3 V
CC
= 78 MSPS
f
f
f
S
= f
out1 out
out2 out
= f + 4 MHz
f = 20 mA
I
OUT S
4y LL-Mode
50
0
5
10
15
20
25
30
35
f
O
− Output Frequency − MHz
Figure 14
NOTE: All measurements made with PLL off.
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DETAILED DESCRIPTION
Figure 1 shows a simplified block diagram of the DAC5674. The CMOS device consists of a segmented array
of PMOS current sources, capable of delivering a full-scale output current up to 20 mA. Differential current
switches direct the current of each current source to either one of the complementary output nodes IOUT1 or
IOUT2. The complementary output currents thus enable differential operation, canceling out common mode
noise sources (digital feedthrough, on-chip, and PCB noise), dc offsets, even-order distortion components, and
increase signal output power by a factor of two.
The full-scale output current is set using an external resistor R
in combination with an on-chip band-gap
BIAS
voltage reference source (1.2 V) and control amplifier. The current I
through resistor R
. The full-scale current can be adjusted
is mirrored
BIAS
BIAS
internally to provide a full-scale output current equal to 32 times I
from 20 mA down to 2 mA.
BIAS
Interpolation Filter
The interpolation filters FIR1 and FIR2 can be configured for either low-pass or high-pass response. In this way,
higher order images can be selected. Table 1 shows the DAC IF output range for the different filter response
combinations, for both the first and second Nyquist zone (after interpolation). Table 2 lists the DAC IF output
ranges for two popular GSM data rates. Table 3 shows the W-CDMA IF carrier center frequency for an input
data rate of 61.44 MSPS and a fundamental input IF of 15.36 MHz. Figure 15 shows the spectral response;
the corresponding nonzero tap weights are:
D
[5, −20, 50, −108, 206, −361, 597, −947, 1467, −2267, 3633, −6617, 20746, 32768]
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0.005
0
−50
0.000
−100
−150
−0.005
0.0
0.2
0.4
0.6
0.8
1.0
0.0
0.2
0.4
0.6
0.8
1.0
f / f
in
f / f
in
Figure 15. FIR1 and FIR2 Magnitude Spectrum
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Table 1. Interpolation Filters Configuration
IF OUTPUT RANGE 1
(FIRST NYQUIST ZONE)
IF OUTPUT RANGE 2
(SECOND NYQUIST ZONE)
FILTER 1
FILTER 2
CONFIGURATION CONFIGURATION
FREQUENCY
SINX/X ATT. [dB]
0…0.14
FREQUENCY SINX/X ATT. [dB]
Low pass
Low pass
High pass
High pass
Low pass
High pass
Low pass
High pass
0…0.4F
1.6…2F
3.6…4F
2…2.4F
19.2…∞
data
data
2.42…3.92
0.32…0.58
1.33…1.83
3.92…5.94
12.6…15.4
7.20…8.69
data
data
0.6…0.8F
1.2…1.4F
3.2…3.4F
2.6…2.8F
data
data
data
data
Table 2. Interpolation Filters Configuration: Example Frequencies GSM
IF OUTPUT RANGE 1
IF OUTPUT RANGE 2
(FIRST NYQUIST ZONE)
(SECOND NYQUIST ZONE)
FILTER 1
FILTER 2
IF FREQUENCY [MHz]
IF FREQUENCY [MHz]
CONFIGURATION CONFIGURATION
F
data
= 52 MSPS
F
data
= 78 MSPS
F
= 52 MSPS
data
187.2…208
F
= 78 MSPS
data
280.8…312
Low pass
Low pass
High pass
High pass
Low pass
High pass
Low pass
High pass
0…20.8
0…31.2
83.2…108
31.2…41.6
62.4…72.8
124.8…156
46.8…62.4
93.6…109.2
104…124.8
166.4…176.8
135.2…145.6
156…187.2
249.6…265.2
202.8…218.4
Table 3. Interpolation Filters Configuration: Example Frequencies W-CDMA, IF = F
/4, F
= 61.44
DATA
data
MSPS: F
= 245.76 MSPS
update
IF FREQUENCY [MHZ]
(FIRST NYQUIST ZONE)
IF FREQUENCY [MHZ]
(SECOND NYQUIST ZONE)
FILTER 1
FILTER 2
CONFIGURATION CONFIGURATION
IF CENTER [MHz]
SINX/X ATT. [dB]
IF CENTER [MHz]
230.4
SINX/X ATT. [dB]
23.6
Low pass
Low pass
High pass
High pass
Low pass
High pass
Low pass
High pass
15.36
107.52
46.08
76.8
0.05
2.93
0.51
1.44
138.24
199.68
168.96
5.11
13.2
8.29
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Low-Pass/Low-Pass 4y Interpolation Filter Operation
Figure 16 shows the low-pass/low-pass interpolation operation where the 4× FIR filter is implemented as a
cascade of two 2× interpolation filters with the input signal coming from a digital signal source such as an FPGA
or digital upconverter (DUC). Users can place their IF signal at a maximum of 0.4 times the FIR filter input (i.e.,
DAC5674 input) data rate. For a 100-MSPS data rate, this would translate into a pass band extending to 40
MHz.
Input Spectrum
Output of DUC
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
80 dB of
attenuation
st
1
2x
interpolation
filter
Fdata
Spectrum after
2
x interpolation
nd
2
LPF removes
nd
2
2x
interpolation images
interpolation
filter
Fdata
Fdata
Fdata
Fdata
Spectrum after
4
x interpolation
Fdata
Fdata
Fdata
Fdata
=
Fdac
Figure 16. Low-Pass/Low-Pass 4y Interpolation Filter Operation
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Low-Pass/High-Pass 4y Interpolation Filter Operation
By configuring the low-pass filters as high-pass filters, the user can select one of the images present at multiples
of the clock. Figure 17 shows the low-pass/high-pass filter response. After digital filtering, the DAC transmits
at 2F
− IF and 2F
+ IF. This configuration is equivalent to sub-sampling receiver systems where a
data
data
high-speed analog-to-digital converter samples high IF frequencies with relatively low sample rates, resulting
in low (output) data rates.
The placement of the IF in the first Nyquist zone combined with the DAC5674 input data determines the final
output signal frequency. For F
= 100 MSPS and a fundamental IF of 0.4 × F
= 40 MHz, this would translate
data
data
into images located at 160 MHz and 240 MHz. Note that this is the equivalent of mixing a 40-MHz analog IF
signal with a 200-MHz sine wave. By doing this, the first mixer in the total transmission chain is eliminated.
Input Spectrum
Output of DUC
Fdata
Fdata
Fdata
Fdata
st
80 dB of
Attenuation
1
interpolation
filter
2x
Spectrum after
2
x interpolation
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
HPF filters out
unwanted
image
HPF filters out
unwanted
image
nd
2
2x
interpolation
filter
Fdata
Spectrum after
x interpolation
4
Fdata
=
Fdac
Figure 17. Low-Pass/High-Pass 4y Interpolation Filter Operation
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High-Pass/Low-Pass 4y Interpolation Filter Operation
Figure 18 shows the high-pass/low-pass filter configuration. Images at F
− IF and 3F
+ IF can be
data
data
selected. Note that the latter image severely attenuates by the sinx/x response. The transition bandwidths of
filter 1 and filter 2 occupy 0.2Fdata. The combination of these transition bands results in an output IF between
0.6…0.8F
.
data
Input Spectrum
Output of DUC
Fdata
Fdata
Fdata
Fdata
80 dB of
attenuation
80 dB of
attenuation
80 dB of
attenuation
st
1
2x
interpolation
filter
Fdata
Fdata
Fdata
Fdata
Fdata
Spectrum after
2
x interpolation
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Unwanted images
removed by LPF
nd
2
interpolation
filter
2x
Fdata
Fdata
Spectrum after
4
x interpolation
Fdata
=
Fdac
Figure 18. High-Pass/Low-Pass 4y Interpolation Filter Operation
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High-Pass/High-Pass 4y Interpolation Filter Operation
Figure 19 shows the high-pass/high-pass filter configuration. The transition bands of filter 1 and filter 2 allow
for the placement of the fundamental IF between 0.2…0.4F . In this configuration, the user can select the
data
images at F
+ IF and 3F
– IF. For F
= 100 MSPS and a fundamental IF of 0.4 × F
= 40 MHz, this
data
data
data
data
would translate into images located at 140 MHz and 260 MHz. Note that this is the equivalent of mixing a 60-MHz
analog IF signal with a 200-MHz sine wave.
Input Spectrum
Output of DUC
Fdata
Fdata
Fdata
Fdata
80 dB of
attenuation
80 dB of
attenuation
80 dB of
attenuation
st
1
2x
interpolation
filter
Fdata
Fdata
Fdata
Fdata
Spectrum after
2
x interpolation
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Unwanted images
removed by HPF
Unwanted images
removed by HPF
nd
2
interpolation
filter
2x
Fdata
Spectrum after
x interpolation
4
Fdata
=
Fdac
Figure 19. High-Pass/High-Pass 4y Interpolation Filter Operation
DAC Sinx/x Output Attenuation
The output frequency spectrum of the DACs shows some inherent attenuation due to their sample-and-hold
nature. The output of the DAC is normally seen as the signal sample held over the sampling time in a stair-step
manner. In the time domain, this step-like output can be thought of as an impulse sample of some value
convolved with a unit-square pulse with a duration of the sampling time. In the frequency domain, this translates
to the frequency response of the discretely sampled signal multiplied by the sinx/x frequency response function
of the square pulse. The sinx/x function has a null at every integer multiple of the sampling rate.
This is shown in Figure 20 for various data rates at 4× interpolation.
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*1.83 dB
”Sinx/x”
Attenuation
*7.2 dB
F
+65 MSPS
+80 MSPS
update
0
0
0
IF=26
IF=32
IF=40
65
80
91
130
160
200
169
195
240
300
260
320
400
*1.83 dB
”Sinx/x”
Attenuation
*7.2 dB
F
update
112
208
*1.83 dB
”Sinx/x”
Attenuation
*7.2 dB
F +100 MSPS
update
100
140
260
Figure 20. High-Pass 4y Interpolation Filter Operation: Example Frequencies
Clock Generation Function
An internal phase-locked loop (PLL) or external clock can be used to derive the internal clocks (1×, 2×, and 4×)
for the logic, FIR interpolation filters, and DAC. Basic functionality is depicted in Figure 21. Power for the internal
PLL blocks (PLLVDD and PLLGND) is separate from the other clock generation blocks power (CLKVDD and
CLKGND), thus minimizing phase noise within the PLL. The PLLVDD pin establishes internal/external clock
mode: when PLLVDD is grounded, external clock mode is active and when PLLVDD is 3.3 V, internal clock mode
is active.
In external clock mode, the user provides a differential external clock on pins CLK/CLKC. This clock becomes
the 4× clock and is twice divided down to generate the 2× and 1× clocks. The 2× or 1× clock is multiplexed out
on the PLLLOCK pin to allow for external clock synchronization.
In internal clock mode, the user provides a differential external reference clock on CLK/CLKC. A type four
phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback clock and
drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated by dividing
the VCO output by 1×, 2×, 4×, or 8×, as selected by the prescaler (DIV[1:0]). The output of the prescaler is the
4× clock, and is divided down twice to generate the 2× and 1× clocks. Pin X4 selects the 1× or 2× clock to clock
in the input data; the selected clock is also fed back to the PFD for synchronization. The PLLLOCK pin is an
output indicating when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user
at pin LPF. See the Low-Pass Filter section for filter setting calculations. Table 4 provides a summary of the
clock configurations with corresponding data rate ranges.
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LPF
DIV[1:0] PLLVDD
DAC5674
/1
/2
/4
/8
Charge
Pump
CLK
PFD
VCO
Clk_4y
CLKC
Clk
Buffer
Clk_2y
Clk_1y
/2
/2
0
PLLVDD
PLLGND
1
s
0
CLKVDD
CLKGND
1
s
Data
PLLLOCK
PLLVDD
D[13:0]
X4
Figure 21. Clock Generation Functional Diagram
Table 4. Clock Mode Configuration
CLOCK MODE
PLLVDD
0 V
DIV[1:0]
XX
XX
00
X4
0
DATA RANGE (MHz)
DC to 200
DC to 100
100 to 200
50 to 100
25 to 50
PLLLOCK PIN FUNCTION
External clock/2
External 2×
External 4×
Internal 2×
Internal 2×
Internal 2×
Internal 2×
Internal 4×
Internal 4×
Internal 4×
Internal 4×
0 V
1
External clock/4
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
0
Internal PLL lock indicator
Internal PLL lock indicator
Internal PLL lock indicator
Internal PLL lock indicator
Internal PLL lock indicator
Internal PLL lock indicator
Internal PLL lock indicator
Internal PLL lock indicator
01
0
10
0
11
0
12 to 25
00
1
50 to 100
25 to 50
01
1
10
1
12 to 25
11
1
5 to 12
Low-Pass Filter
The PLL consists of a type four phase-frequency detector (PFD), charge pump, external low-pass loop filter,
voltage to current converter, and current controlled oscillator (ICO) as shown in Figure 22. The DAC5674
evaluation board comes with component values R = 200, C1 = 0.01 µF, and C2 = 100 pF. These values have
been designed to give the phase margins and loop bandwidths listed in Table 5 for the five divide down factors
of prescaling and interpolation. Note that the values derived were based on a charge pump current output of
1 mA and a VCO gain of 300 MHz/V (nominal at Fvco = 400 MHz). With this filter, the settling time from a phase
or frequency disturbance is about 2.5 µs. If different PLL dynamics are required, DAC5674 users can design
a second order filter for their application; see the Designing the PLL Loop Filter section of this data sheet.
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DAC5674
LPF
Fref
Fvco
PFD
R
C2
PN
C1
ICO
ref
External Loop Filter
Figure 22. PLL Functional Block Diagram
Table 5. DAC5674 Evaluation Board PLL Loop Filter Parameters
(1)
N
PHASE MARGIN (DEGREES)
BANDWIDTH (MHZ)
2
4
8
60
71
77
78
74
1.6
1.4
1
16
32
0.7
0.4
(1)
N is the VCO divide-down factor from prescale and interpolation.
Non-Harmonic Clock-Related Spurious Signals
In interpolating DACs, imperfect isolation between the digital and DAC clock circuits generates spurious signals
at frequencies related to the DAC clock rate. The digital interpolation filters in these DACs run at subharmonic
frequencies of the output rate clock, where these frequencies are f
/2 , N = 1,2. For example, for 2×
DAC
interpolation only one interpolation filter runs at f
/2; for 4× interpolation, on the other hand, two interpolation
DAC
filters run at f
/2 and f
/4. These lower-speed clocks for the interpolation filter mix with the DAC clock
DAC
DAC
N
circuit and create spurious images of the wanted signal and second Nyquist-zone image at offsets of f
/2 .
DAC
Figure 23 shows the location of the largest spurious signals for 4× interpolation for a real signal. With a real
output signal, there is no distinction between negative and positive frequencies, and therefore the signals that
appear at negative frequencies wrap and potentially fall near the wanted signal. In particular, at IFs near f
/8,
DAC
f
/4, and f
× 3/4 (50 MHz, 100 MHz, and 150 MHz in this example), the mixing effect results in spurious
DAC
DAC
signals falling near the wanted signal, which may present a problem depending on the system application. For
a frequency-symmetric signal (such as a single WCDMA or CDMA carrier), operating at exactly f /8, f /4
DAC
DAC
and f
× 3/4, the spurious signal falls completely inside the wanted signal, which produces a clean spectrum
DAC
but may result in degradation of the signal quality.
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0.500
Output IF
0.375
IF − 3f /4
DAC
IF + f /4
DAC
0.250
0.125
0.000
IF − f /4
DAC
IF − f /2
DAC
0.000
0.125
0.250
0.375
0.500
Output Frequency / DAC Frequency
Figure 23. Location of Clock Mixing Spurs vs IF for 4y Mode
The offset between wanted and spurious signals is maximized at low IFs (< f
/8) and at f
× 3/16,
DAC
DAC
fDAC × 5/16, and fDAC × 7/16. For example, with f
= 100 MSPS and 4× interpolation, operating with
DATA
IF = f
× 5/16 = 125 MHz results in spurious signals at offsets of 50 MHz from the wanted signal.
DAC
Figure 24a shows the amplitude of each spurious signal as a function of IF in external-clock mode. The
dominant spurious signal is IF − f /2. The amplitudes of the IF + f /4 and IF − f /4 are the next-highest
DAC
DAC
DAC
spurious signals and are approximately at the same amplitude. Finally, at IF frequencies greater than 100 MHz,
small spurious signals at IF − f × 3/4 are measurable.
DAC
Figure 24b shows the amplitude of each spurious signal as a function of IF in PLL clock mode. Generating the
DAC clock with the onboard PLL/VCO increases the IF − f /2 by 3 dB. The amplitude of the IF /4 and
f
DAC
DAC
IF − f
× 3/4 remain at about the same level as in the external-clock mode.
DAC
0
0
−10
−20
−30
−40
−50
−60
−10
−20
−30
−40
−50
−60
−70
IF − F
/2
DAC
IF−F
/2
DAC
IF − F
/4
DAC
IF − F
/4
DAC
IF − 3F
/4
DAC
IF − 3F
/4
DAC
IF + F
/4
DAC
IF + F
/4
DAC
−70
0
50
100
150
200
0
50
100
150
200
f
− Output Frequency − MHz
f
− Output Frequency − MHz
sig
sig
a. External Clock Mode
Figure 24. External Clock Mode and PLL Mode
b. PLL Mode
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The amplitudes in Figure 24 are typical values and vary by a few dB across different parts, supply voltages,
and temperatures. Figure 23 and Figure 24 can be used to estimate the non-harmonic clock-related spurious
signals. Take the example for using the DAC5674 in external-clock mode, f
= 400 MHz, 4× interpolation,
DAC
and IF = 30 MHz. Figure 23 and Figure 24a predict the spurious signals shown in Table 6. The resulting spurs
are at 170 MHz at −38 dBc, 130 MHz at −45 dBc, and 70 MHz at −43 dBc.
Table 6. Predicted Frequency and Amplitude for F
− 400 MHz, 4y Interpolation
DAC
SPURIOUS COMPONENT
SPURIOUS FREQUENCY
AMPLITUDE dBc
IF – f
IF + f
IF – f
/2
/4
/4
170 MHz
130 MHz
70 MHz
–38
–45
–43
N/A
DAC
DAC
DAC
IF – 3f
/4
DAC
>200 MHz
Figure 25 shows the DAC5674 output spectrum for the preceding example. The amplitudes of the clock-related
spurs agree quite well with the predicted amplitudes in Table 6.
10
IF
0
−10
−20
−30
IF − 3f
/4
DAC
IF − f /4
DAC
−40
−50
−60
−70
−80
IF + f
/4
DAC
0
25
50
75
100 125 150 175 200
Frequency− MHz
Figure 25. DAC Output Spectrum With F
Digital Inputs
= 400 MSPS, 4y Interpolation, IF=30 MHz, External Clock
DAC
Figure 26 shows a schematic of the equivalent CMOS digital inputs of the DAC5674. The CMOS-compatible
inputs have logic thresholds of IOVDD/2 20%. The 14-bit digital data input follows the offset positive binary
coding scheme.
IOVDD (AVDD for SLEEP and EXTLO)
D[13:0]
SLEEP
EXTLO
Internal
DIV[1:0]
Digital In
RESET
HP1, HP2
X4
IOGND
Figure 26. CMOS/TTL Digital Equivalent Input
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Clock Input and Timing
Figure 27 shows the clock and data input timing diagram for internal and external clock modes, respectively.
Note that a negative value indicates a reversal of the edge positions as shown in the timing diagram. Figure 27
also shows the delay (t ) of the 1×/2× data clock (PLLLOCK) from CLK in external clock mode (typical t = 4.1
d
d
ns). The latency from data to DAC is defined by Figure 28. The DAC5674 features a differential clock input.
In internal clock mode, the internal data clock is a divided down version of the PLL clock (/2 or /4), depending
on the level of interpolation (2× or 4×). In external mode, the internal data clock is a divided down version of
the input CLK (/2 or /4), depending on the level of interpolation (2× or 4×). Internal edge-triggered flip-flops latch
the input word on the rising edge of the positive data clock.
D[13:0]
Valid Data
t
su
t
h
D[13:0]
Valid Data
t
su
PLLLOCK
t
h
t
t
d_clk
lph
CLK
CLK
CLKC
CLKC
Figure 27. Internal (Left) and External (Right) Clock Mode Timing
t
lat_nx
2x Interpolation
DAC
D[13:0]
2000
0
2000 3FFF
0
0
0
4x Interpolation
DAC
Typical t = 0.5 ns, t = 0.1 ns
su
Typical t = 2.9 ns, t = −2.3 ns, t = 3.6 ns
su
h
h
d
Figure 28. Data to DAC Latency
24
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Figure 29 shows an equivalent circuit for the clock input.
AVDD
CLKVDD
AVDD
R1
10 kΩ
R1
10 kΩ
Internal
Digital In
CLK
CLKC
R2
R2
10 kΩ
10 kΩ
CLKGND
Figure 29. Clock Input Equivalent Circuit
Figure 30, Figure 31, Figure 32, and Figure 33 show various input configurations for driving the differential
clock input (CLK/CLKC).
Optional, May Be Bypassed
for Sine Wave Input
Swing Limitation
C
AC
0.1 µF
1:4
CLK
R
T
200 Ω
CLKC
Termination Resistor
Figure 30. Preferred Clock Input Configuration
C
R
opt
22 Ω
R
opt
22 Ω
AC
0.01 µF
1:1
TTL/CMOS
Source
TTL/CMOS
Source
CLK
CLK
Optional, Reduces
Clock Feedthrough
CLKC
CLKC
0.01 µF
Node CLKC
Internally Biased
to IVDDń2
Figure 31. Driving the DAC5674 With a Single-Ended TTL/CMOS Clock Source
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
C
AC
0.01 µF
+
CLK
Differential
ECL
or
(LV)PECL
C
AC
0.01 µF
Source
−
CLKC
R
50 Ω
R
T
50 Ω
T
V
TT
Figure 32. Driving the DAC5674 With Differential ECL/PECL Clock Source
ECL/PECL
Gate
C
AC
0.01 µF
Single-Ended
ECL
CLK
or
(LV)PECL
Source
C
AC
0.01 µF
CLKC
R
50 Ω
R
T
50 Ω
T
V
TT
Figure 33. Driving the DAC5674 With a Single-Ended ECL/PECL Clock Source
Supply Inputs
The DAC5674 comprises separate analog and digital supplies at AVDD, DVDD, and IOVDD. These supplies
can range from 3 V to 3.6 V for AVDD, 1.65 to 1.95 V for DVDD, and 1.65 to 3.6 for IOVDD.
DAC Transfer Function
The DAC5674 delivers complementary output currents IOUT1 and IOUT2. The DAC supports straight binary
coding, with D13 being the MSB and D0 the LSB. Output current IOUT1 equals the approximate full-scale output
current when all input bits are set high, i.e., the binary input word has the decimal representation 16383.
Full-scale output current flows through terminal IOUT2 when all input bits are set low (mode 0, straight binary
input). The relation between IOUT1 and IOUT2 can thus be expressed as:
N
2
* 1
IOUT1 +
IOUT * IOUT2
FS
N
2
Where IOUT is the full-scale output current, N = 14 bits. The output currents can be expressed as:
FS
CODE
16384
IOUT1 + IOUT
IOUT2 + IOUT
FS
16383 * CODE
FS
16384
Where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2
drive resistor loads (R ) or a transformer with equivalent input load resistance (R ). This would translate into
L
L
single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of:
26
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CODE
16384
VOUT1 + IOUT1 R + IOUT
R
L
FS
FS
L
16383 * CODE
VOUT2 + IOUT2 R + IOUT
R
L
L
16384
The differential output voltage VOUT
can thus be expressed as:
DIFF
2CODE * 16383
VOUT
+ VOUT1 * VOUT2 + IOUT
R
DIFF
FS
L
16384
The latter equation shows that applying the differential output results in doubling of the signal power delivered
to the load. Because the output currents IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Note that care should be taken not to exceed the compliance voltages at node IOUT1
and IOUT2, which would lead to increased signal distortion.
Reference Operation
The DAC5674 comprises a band-gap reference and control amplifier for biasing the full-scale output current.
The full-scale output current is set by applying an external resistor R
. The bias current I
through resistor
BIAS
BIAS
R
is defined by the on-chip band-gap reference voltage and control amplifier. The full-scale output current
BIAS
equals 32 times this bias current. The full-scale output current IOUT can thus be expressed as:
FS
32 V
EXTIO
IOUT
+ 32 I
+
FS
BIAS
R
BIAS
where V
is the voltage at terminal EXTIO. The band-gap reference voltage delivers an accurate voltage
EXTIO
of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor
C
of 0.1 µF should be connected externally to terminal EXTIO for compensation. The band-gap reference
EXT
can additionally be used for external reference operation. In that case, an external buffer with high impedance
input should be applied in order to limit the band-gap load current to a maximum of 100 nA. The internal
reference can be disabled and overridden by an external reference by connecting EXTLO to AVDD. In this case,
capacitor C
can be omitted. Terminal EXTIO serves as either input or output node.
EXT
The full-scale output current can be adjusted from 20 mA to 2 mA by varying resistor R
or changing the
BIAS
externally applied reference voltage. The internal control amplifier has a wide input range, supporting the
full-scale output current range of 20 mA.
Analog Current Outputs
Figure 34 shows a simplified schematic of the current source array output with corresponding switches.
Differential switches direct the current of each individual PMOS current source to either the positive output node
IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack
of the current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance
of 5 pF.
The external output resistors are referred to an external ground. The minimum output compliance at nodes
IOUT1 and IOUT2 is limited to −1 V, determined by the CMOS process. Beyond this value, transistor breakdown
may occur resulting in reduced reliability of the DAC5674 device. The maximum output compliance voltage at
nodes IOUT1 and IOUT2 equals 1.25 V. Exceeding the maximum output compliance voltage adversely affects
distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5 V.
27
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AVDD
S(1)
S(1)C
S(2)
S(2)C
S(N)
S(N)C
Current Source Array
IOUT1
IOUT2
R
LOAD
R
LOAD
Figure 34. Equivalent Analog Current Output
The DAC5674 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF
transformer. Figure 35 and Figure 36 show the 50-Ω doubly terminated transformer configuration with 1:1 and
4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be
grounded to enable a dc current flow. Applying a 20-mA full-scale output current would lead to a 0.5 V for
PP
a 1:1 transformer and a 1 V output for a 4:1 transformer.
PP
Figure 37 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent
load resistance of 25 Ω. Node IOUT2 should be connected to AGND or terminated with a resistor of 25 Ω to
AGND. The nominal resistor load of 25 Ω gives a differential output swing of 1 V when applying a 20-mA
PP
full-scale output current.
50 Ω
1:1
IOUT1
R
LOAD
50 Ω
100 Ω
AGND
IOUT2
50 Ω
Figure 35. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer
28
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100 Ω
4:1
IOUT1
IOUT2
R
LOAD
50 Ω
AGND
100 Ω
Figure 36. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer
IOUT1
R
LOAD
50 Ω
IOUT2
25 Ω
50 Ω
AGND
Figure 37. Driving a Doubly Terminated 50-Ω Cable Using Single-Ended Output
Sleep Mode
The DAC5674 features a power-down mode that turns off the output current and reduces the supply current
to less than 5 mA over the supply range of 3 V to 3.6 V and temperature range. The power-down mode is
activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal
pulldown circuit at node SLEEP ensures that the DAC5674 is enabled if the input is left disconnected. Power-up
and power-down activation times depend on the value of external capacitor at node EXTIO. For a nominal
capacitor value of 0.1-µF power-down takes less than 5 µs, and power-up takes approximately 3 ms. With
external reference, power up takes 10 µs; power down remains the same.
DAC5674 Evaluation Board
A combo EVM board is available for the DAC5674 digital-to-analog converter for evaluation. This board allows
the user the flexibility to operate the DAC5674 in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. The digital
inputs are designed to interface with a TMS320 DSP SDK or to be driven directly from various pattern
generators with the onboard option to add a resistor network for proper load termination. See the DAC5674 EVM
User’s Guide (SWRU007) for more information.
29
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DESIGNING THE PLL LOOP FILTER
The DAC5674 contains an external loop filter to set the bandwidth and phase margin of the PLL. For the external
second-order filter shown in Figure 38, the components R1, C1, and C2 are set by the user to optimize the PLL
for the application. The resistance R3 = 200 Ω. and the capacitance C3 = 8 pF are internal to the DAC5674.
Note that R1 and C1 can be reversed.
External
Internal
R3
C1
C2
C3
R1
Figure 38. DAC5674 Loop Filter
Typical DAC5674 Gvco at 255 C
500
450
400
350
300
250
200
150
100
50
0
0
100
200
300
400
500
600
Frequency− MHz
Figure 39. Typical VCO Gain vs VCO Frequency at 25°C
The typical VCO gain (Gvco) (the slope of VCO frequency vs voltage) as a function of VCO frequency for the
DAC5674 is shown in Figure 39. For the lowest possible phase noise, the VCO frequency should be chosen
so Gvco is minimized, where
Fvco = Fdata × Interpolation × PLL Divider:
For example, if Fdata = 100 MSPS and 2× interpolation is used, the PLL divider should be set to 2 to lock the
VCO at 400 MHz for a typical Gvco of 210 MHz/V. Note that the maximum specified VCO frequency range is
160 MHz to 400 MHz.
30
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The external loop filter components C1, C2, and R1 are given by choosing Gvco, N = Fvco/Fdata, the loop
phase margin φ and the loop bandwidth ω . Except for applications where abrupt clock frequency changes
d
d
require a fast PLL lock time, it is suggested that φ be set to at least 80 degrees for stable locking and
d
suppression of the phase noise side lobes. Phase margins of 60 degrees or less have occasionally been
sensitive to board layout and decoupling details.
The optimum loop bandwidth ω depends on both the VCO phase noise, which is largely a function of Gvco,
d
and the application. For the foregoing example with Gvco = 210 MHz/V, an ω = 1 MHz would be typical, but
d
lower and higher loop bandwidths may provide better phase-noise characteristics. For a higher Gvco, for
example Gvco = 400 MHz/V, a ω ≈ 7 MHz would be typical. However, it is suggested that the customer
d
experiment with varying the loop bandwidth by at least 1/2× through 2× to verify the optimum setting.
C1, C2, and R1 are then calculated by the following equations:
2
t2
t3
t3
t1–t2
t3
C1 + t1ǒ1– Ǔ
R1 +
C2 +
t1(t3 * t2)
where
K K
tan f ) secf
vco
d
1
d
d
ǒtan f ) secf
Ǔ
t1 +
t2 +
t3 +
d
d
w
2
w
d
ǒtan f ) secf
Ǔ
w
d
d
d
d
and
charge pump current:
vco gain:
iqp = 1 mA
Kvco = 2π × Gvco rad/V
Fvco/Fdata:
N = {2, 4, 8, 16, 32}
−1
phase detector gain:
Kd = iqp × (2πN) A/rad
An Excel spreadsheet is provided by TI for automatically calculating the values for C1, C2, and R.
Completing the preceding example with
PARAMETER
VALUE
2.10E+02
1.00E+00
4
UNIT
MHz/V
MHz
Gvco
ω
d
N
φ
80
degrees
d
the component values are
C1 (F)
C2 (F)
1.16E−10
R (W)
1.51E−08
1.21E+02
As the PLL characteristics are not sensitive to these components, the closest 20% tolerance capacitor and 1%
tolerance resistor values can be used. If the calculation results in a negative value for C2 or an unrealistically
large value for C1, then the phase margin may need to be reduced slightly.
USING PowerPAD DEVICES
A thermal land should be placed on the top and bottom layers of the circuit board. The recommended thermal
land size for this package is 5 mm × 5 mm, with top and bottom layers connected by 9 vias. A thermal land size
of 3,8 mm × 3,8 mm (as used on the DAC5674 EVM) is adequate for this device.
31
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REVISION HISTORY
DATE
REV
PAGE
10–12
15
SECTION
DESCRIPTION
Aug. 2005
A
Typical Characteristics
Added a note that ac measurements are taken with the PLL off
Low-Pass/Low-Pass 4× Interpolation
Filter Operation
16
17
18
Low-Pass/High-Pass 4× Interpolation
Filter Operation
Updated the filter mode diagrams with more-realistic response
High-Pass/Low-Pass 4× Interpolation
Filter Operation
High-Pass/High-Pass 4× Interpolation
Filter Operation
18
26
29
30
DAC Sinx/x Output Attenuation
DAC Transfer Function
Sleep Mode
Added this new section
Updated DAC transfer equation with a more-accurate model
Corrected a word and added a sentence
PLL Loop Filter Components
Replaced with a new section, Designing the PLL Loop Filter
32
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
DAC5674IPHP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PHP
48
48
48
48
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
DAC5674IPHPG4
DAC5674IPHPR
DAC5674IPHPRG4
HTQFP
HTQFP
HTQFP
PHP
PHP
PHP
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC5674IPHPR
HTQFP
PHP
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PHP 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
DAC5674IPHPR
1000
Pack Materials-Page 2
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