DAC5688_14_技术文档

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

DUAL-CHANNEL, 16-BIT, 800 MSPS, 2x–8x INTERPOLATING

DIGITAL-TO-ANALOG CONVERTER (DAC)

Check for Samples: DAC5688

1

FEATURES

DESCRIPTION

•

Dual, 16-Bit, 800 MSPS DACs

The DAC5688 is a dual-channel 16-bit 800 MSPS

digital-to-analog converter (DAC) with dual CMOS

digital data bus, integrated 2x-8x interpolation filters,

•

Dual, 16-Bit, 250 MSPS CMOS Input Data

–

16 Sample Input FIFO

a

fine frequency mixer with 32-bit complex

Flexible input data bus options

numerically controlled oscillator (NCO), on-board

clock multiplier, IQ compensation, and internal

voltage reference. Different modes of operation

enable or bypass various signal processing blocks.

The DAC5688 offers superior linearity, noise,

crosstalk and PLL phase noise performance.

•

High Performance

81 dBc ACLR WCDMA TM1 at 70 MHz

–

•

2x-32x Clock Multiplying PLL/VCO

Selectable 2x–8x Interpolation Filters

–

Stop-band Attenuation > 80 dB

The DAC5688 dual CMOS data bus provides 250

MSPS input data transfer per DAC channel. Several

input data options are available: dual-bus data,

single-bus interleaved data, even and odd

multiplexing at half-rate, and an input FIFO with either

external or internal clock to ease interface timing.

Input data can interpolated 2x, 4x or 8x by on-board

digital interpolating FIR filters with over 80 dB of

stop-band attenuation.

•

Complex Mixer with 32-Bit NCO

Digital Quadrature Modulator Correction

–

Gain, Phase and Offset Correction

•

Digital Inverse SINC Filter

3- or 4-Wire Serial Control Interface

On Chip 1.2-V Reference

Differential Scalable Output: 2 to 20 mA

Package: 64-pin 9×9mm QFN

The DAC5688 allows both complex or real output. An

optional 32-bit NCO/mixer in complex mode provides

frequency upconversion and the dual DAC output

produces a complex Hilbert Transform pair. A digital

Inverse SINC filter compensates for natural DAC

sin(x)/x frequency roll-off. The digital Quadrature

Modulator Correction (QMC) feature allows IQ

compensation of phase, gain and offset to maximize

sideband rejection and minimize LO feed-through of

an external quadrature modulator performing the final

single sideband RF up-conversion.

APPLICATIONS

•

Cellular Base Stations

Broadband Wireless Access (BWA)

WiMAX 802.16

Fixed Wireless Backhaul

Cable Modem Termination System (CMTS)

The DAC5688 is pin compatible with the DAC5689

which does not include a clock-multiplying PLL. The

DAC5688 is characterized for operation over the

industrial temperature range of –40°C to 85°C and is

available in a 64-pin 9x9mm QFN package.

ORDERING INFORMATION⁽¹⁾

Order Code

T_A= –40°C to 85°C

Package Qty

Tape and Reel Format

Package

Drawing/Type^{(2) (3)}

DAC5688IRGCT

DAC5688IRGCR

250

RGC / 64QFN Quad Flatpack No-Lead

2000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Thermal Pad Size: 7,4 mm × 7,4 mm

(3) MSL Peak Temperature: Level-3-260C-168 HR

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FUNCTIONAL BLOCK DIAGRAM

CLKVDD

LPF

VFUSE

DVDD

CLK2

EXTIO

1.2 V

Reference

CLK2C

CLKOUT

Internal Clock Generation and

2x - 32x PLL Clock Multiplier

EXTLO

2-8x Fdata

CLKO_CLK1

BIASJ

LOCK_CLK1C

LOCK

A

gain

SYNC

QMC

A-Offset

TXENABLE

FIR4

FIR1

FIR2

FIR3

IOUTA1

IOUTA2

x

sin(x)

16-b DAC

DA[15:0]

x2

2x – 8x Interpolation

19 taps

67 taps

x2

11 taps

9 taps

IOUTB1

IOUTB2

x

sin(x)

DB[15:0]

RESETB

16-b DAC

x2

cos

sin

QMC

B-Offset

B

gain

32-bit NCO

SIF Control

AVDD

Updated: 2-Oct-07

IOVDD

SDIO SDO

GND

SDENB SCLK

PINOUT

1

48

CLKVDD

CLK2

SDENB

2

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

SCLK

SDIO

SDO

3

CLK2C

GND

4

5

SYNC

VFUSE

DB15

DB14

DB13

DB12

DVDD

DB11

DB10

DB9

6

TXENABLE

DA15

DAC5688

7

DA14

8

RGC Package

64QFN, 9x9mm

(Top View)

IOVDD

9

10

11

12

13

14

15

16

DVDD

DA13

DA12

DA11

DA10

DA9

DB8

DB7

DA8

DB6

2

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

PIN FUNCTIONS

I/O

DESCRIPTION

NAME

NO.

51, 54,

55, 59,

62

AVDD

I

Analog supply voltage. (3.3V)

BIASJ

CLK2

57

2

O

I

Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND.

With the clock multiplier PLL enabled, CLK2 provides lower frequency reference clock. If the PLL is disabled, CLK2

directly provides clock for DAC up to 800 MHz.

CLK2C

3

I

Complementary CLK2 input.

In Dual Clock Modes, provides lower frequency input clock (CLK1). Optionally provides clock (CLKO) output for data

bus. Internal pull-down.

CLKO_CLK1

LOCK_ CLK1C

CLKVDD

25

I/O

Complementary CLK1 signal if configured as a differential input. In PLL mode, optionally outputs PLL lock status. Internal

pull-down.

26

1

I/O

I

Internal clock buffer supply voltage. (1.8V)

It is recommended to isolate this supply from DVDD.

A-Channel Data Bits 0 through 15.

DA15 is most significant data bit (MSB) – pin 7

DA0 is least significant data bit (LSB) – pin 24

7, 8,

11–24

DA[15..0]

I

Internal pull-down. The order of bus can be reversed via CONFIG4 reva bit.

B-Channel Data Bits 0 through 15.

DB15 is most significant data bit (MSB) – pin 43

DB0 is least significant data bit (LSB) – pin 27

Internal pull-down. The order of bus can be reversed via CONFIG4 revb bit.

40–43,

27–38

DB[15..0]

DVDD

I

10, 39,

50, 63

Digital supply voltage. (1.8V)

For best performance it is recommended to isolate pins 10 and 39 from all other 1.8V supplies.

Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD). Used as internal

reference output when EXTLO = GND, requires a 0.1mF decoupling capacitor to GND when used as reference output

EXTIO

EXTLO

56

I/O

O

58

4,

Connect to GND for internal reference, or AVDD for external reference.

GND

I

Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD and IOVDD supplies.

Thermal

Pad

A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current

sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in a 0 mA current sink and

the most positive voltage on the IOUTA1 pin. In single DAC mode, outputs appear on the IOUTA1/A2 pair only.

IOUTA1

IOUTA2

52

53

O

A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1 described above.

An input data value of 0x0000 results in a 0mA sink and the most positive voltage on the IOUTA2 pin.

IOUTB1

IOUTB2

61

60

O

B-Channel DAC current output. Refer to IOUTA1 description above.

B-Channel DAC complementary current output. Refer to IOUTA2 description above.

3.3V supply voltage for all digital I/O. Note: This supply input should remain at 3.3V regardless of the 1.8V or 3.3V

selectable digital input switching thresholds via CONFIG26 io_1p8_3p3.

IOVDD

LPF

9

I

PLL loop filter connection. If not using the clock multiplying PLL, leave the LPF pin open. Set PLL_sleep and clear

PLL_ena control bits for reduced power dissipation.

64

SYNC

5

I

Optional SYNC input for internal clock dividers, FIFO, NCO and QMC blocks. Internal pull-down.

Resets the chip when low. Internal pull-up.

RESETB

SCLK

49

47

48

Serial interface clock. Internal pull-down.

SDENB

Active low serial data enable, always an input to the DAC5688. Internal pull-up.

Bi-directional serial data in 3-pin mode (default). In 4-pin interface mode (CONFIG5 sif4), the SDIO pin is an input only.

Internal pull-down.

SDIO

SDO

46

45

I/O

O

Uni-directional serial interface data in 4-pin mode (CONFIG5 sif4). The SDO pin is tri-stated in 3-pin interface mode

(default). Internal pull-down.

Transmit enable input. Internal pull-down. TXENABLE has two purposes. In all modes, TXENABLE must be high for the

DATA to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data is

ignored. In interleaved data mode, TXENABLE can be used to synchronize the data to channels A and B. The first

A-channels sample should be aligned with the rising edge of TXENABLE.

TXENABLE

VFUSE

6

I

Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to DVDD pins for

normal operation.

44

Submit Documentation Feedback

3

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

–0.5 to 2.3

UNIT

V

Supply Voltage Range

DVDD⁽²⁾

VFUSE⁽²⁾

CLKVDD⁽²⁾

AVDD⁽²⁾

–0.5 to 2.3

V

–0.5 to 2.3

V

–0.5 to 4

V

IOVDD⁽²⁾

–0.5 to 4

V

AVDD to DVDD

–2 to 2.6

V

CLKVDD to DVDD

–0.5 to 0.5

V

IOVDD to AVDD

–0.5 to 0.5

V

CLK2, CLK2C⁽²⁾

CLKO_CLK1, LOCK_CLK1C, SLEEP, TXENABLE⁽²⁾

–0.5 to CLKVDD + 0.5

–0.5 to IOVDD + 0.5

–0.5 to AVDD + 0.5

20 mA

V

(2)

DA[15..0] ,DB[15..0]

V

(2)

SDO, SDIO, SCLK, SDENB, RESETB

V

(2)

IOUTA1/B1, IOUTA2/B2

V

(2)

LPF, EXTIO, EXTLO, BIASJ

V

Peak input current (any input)

mA

°C

Peak total input current (all inputs)

–30 mA

Operating free-air temperature range, T_A: DAC5688I

Storage temperature range

–40 to 85

–65 to 150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of these or any other conditions beyond those indicated under recommended operating conditions is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to GND.

THERMAL INFORMATION

DAC5688

THERMAL CONDUCTIVITY

UNITS

64ld QFN

125

(1)(2)

T_J

Maximum junction temperature

°C

q_JA

Theta junction-to-ambient thermal resistance (still air)

Theta junction-to-ambient thermal resistance (200 lfm)

Psi junction-to-top of package characterization parameter

Theta junction-to-board characterization parameter

22

15

°C/W

y_JT

q_JB

0.2

3.5

(1) Air flow or heat sinking reduces q_JAand may be required for sustained operation at 85°C under maximum operating conditions.

(2) It is strongly recommended to solder the device thermal pad to the board ground plane.

4

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS)

over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, DVDD, CLKVDD = 1.8 V, IOUT_FS= 20 mA

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESOLUTION

DC ACCURACY

16

Bits

1 LSB = IOUT_FS/2¹⁶

INL

Integral nonlinearity

Differential nonlinearity

±4

±2

LSB

DNL

ANALOG OUTPUT

Coarse gain linearity

± 0.04

0.01

1

LSB

Offset error mid code offset

Gain error

%FSR

With external reference

With internal reference

0.7

Gain mismatch

With internal reference, dual DAC mode

–2

2

Minimum full scale output current

Maximum full scale output current

Output compliance range⁽¹⁾

Nominal full-scale current, IOUT_FS= 16 × IBIAS current.

2

mA

V

20

IOUT_FS= 20 mA

AVDD

– 0.5V

AVDD

+ 0.5V

Output resistance

Output capacitance

300

5

kΩ

pF

REFERENCE OUTPUT

V_REF

Reference output voltage

Reference output current⁽²⁾

Internal Reference Mode

External Reference Mode

1.14

0.1

1.2

1.26

1.25

V

100

nA

REFERENCE INPUT

V_EXTIOInput voltage range

V

Input resistance

1

95

MΩ

CONFIG26: isbiaslpf_a and isbiaslpf_b = 0

CONFIG26: isbiaslpf_a and isbiaslpf_b = 1

Small signal bandwidth

Input capacitance

kHz

pF

472

100

TEMPERATURE COEFFICIENTS

Offset drift

±1

±15

±30

±8

ppm of

FSR/°C

With external reference

With internal reference

Gain drift

Reference voltage drift

POWER SUPPLY

ppm/°C

AVDD, IOVDD

3.0

1.7

3.3

1.8

3.6

1.9

V

DVDD, CLKVDD

PSRR

Power supply rejection ratio

AVDD + IOVDD current, 3.3V

DVDD + CLKVDD current, 1.8V

Power Dissipation

±0.2

150

450

1300

140

520

1400

150

700

1750

12

%FSR/V

mA

Mode 1: ×8 Interp, PLL on, QMC = off, ISINC = off,

DAC A+B on, F_IN= 5 MHz Tone, NCO = 145 MHz,

F_OUT= 150 MHz, F_DAC= 500 MHz

mA

mW

mA

AVDD + IOVDD current, 3.3V

DVDD + CLKVDD current, 1.8V

Power Dissipation

Mode 2: ×8 Interp, PLL off, QMC = on, ISINC = on,

DAC A+B on, F_IN= 5 MHz Tone, NCO = 91 MHz

F_OUT= 96 MHz, F_DAC= 614.4 MHz

mA

mW

mA

P

AVDD + IOVDD current, 3.3V

DVDD + CLKVDD current, 1.8V

Power Dissipation

Mode 3 (Max): ×4 Interp, PLL on, QMC = on, ISINC = on,

DAC A+B on, F_IN= 5 MHz Tone, NCO = 135 MHz,

F_OUT= 140 MHz, F_DAC= 800 MHz

mA

1950

100

mW

mA

AVDD + IOVDD current, 3.3V

DVDD + CLKVDD current, 1.8V

Power Dissipation

Mode 4 (Sleep): ×8 Interp, PLL off, QMC = off, ISINC = off,

DAC A+B off, F_IN= 5 MHz Tone, NCO = off,

F_OUT= off, F_DAC= 800 MHz,

15

mA

65

mW

(1) The upper limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,

resulting in reduced reliability of the DAC5688 device. The lower limit of the output compliance is determined by the load resistors and

full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.

(2) Use an external buffer amplifier with high impedance input to drive any external load.

Submit Documentation Feedback

5

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS)

Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, DVDD, CLKVDD = 1.8 V, IOUT_FS= 20 mA

PARAMETER

ANALOG OUTPUT⁽¹⁾

TEST CONDITIONS

MIN

TYP MAX

UNIT

f_DAC

Maximum output update rate

Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF

800

MSPS

ns

t_s(DAC)

10.4

2

DAC outputs are updated on falling edge of DAC clock.

t_pd

Output propagation delay

ns

Does not include Digital Latency (see below).

t_r(IOUT)

t_f(IOUT)

Output rise time

Output fall time

10% to 90%

220

109

172

276

488

512

528

548

ps

90% to 10%

No Interp, NCO off, QMC off, ISINC = off

x2 Interpolation, NCO off, QMC off, ISINC = off

x4 Interpolation, NCO off, QMC off, ISINC = off

x8 Interpolation, NCO off, QMC off, ISINC = off

x8 Interpolation, NCO on, QMC off, ISINC = off

x8 Interpolation, NCO on, QMC on, ISINC = off

x8 Interpolation, NCO on, QMC on, ISINC = on

DAC

clock

cycles

Digital Latency

(2)

AC PERFORMANCE

×4 Interp, PLL off, CLK2 = 800 MHz,

DAC A+B on,

0 dBFS Single tone, F_OUT= F_IN

First Nyquist Zone < f_DATA/2

F_OUT= 10.1 MHz

F_OUT= 20.1 MHz

83

79

Spurious free dynamic

range

SFDR

dBc

×4 Interp, PLL off, CLK2 = 800 MHz,

DAC A+B on,

0 dBFS Single tone, F_IN= 10.1 MHz,

F_OUT= F_IN+ NCO

NCO= 10 MHz, F_OUT= 20.1 MHz

NCO= 60 MHz, F_OUT= 70.1 MHz

NCO= 140 MHz, F_OUT= 150.1 MHz

NCO= 290 MHz, F_OUT= 300.1 MHz

NCO= 40 MHz, F_OUT= 51±0.5 MHz

NCO= 60 MHz, F_OUT= 71±0.5 MHz

NCO= 130 MHz, F_OUT= 141±0.5 MHz

72

68

64

57

85

83

74

SNR

Signal-to-Noise Ratio

×4 Interp, PLL off, CLK2 = 800 MHz,

DAC A+B on,

F_IN= 10.5 and 11. 5 MHz,

F_OUT= F_IN+ NCO

Third-order

Two-Tone intermodulation

(Each tone at –6 dBFS)

IMD3

IMD

dBc

Four-tone Intermodulation

to Nyquist

(Each tone at –12 dBFS)

×4 Interp, PLL off, CLK2 = 800 MHz, DAC A+B on,

F_IN= 9.8, 10.4, 11.6 and 12.2 MHz (600kHz spacing), NCO = 129 MHz,

F_OUT= F_IN+ NCO = 140±1.2 MHz

73

81

×8 Interp, PLL off, CLK2 = 737.28 MHz,

DAC A+B on, F_IN= 23 .04 MHz, NCO = off

Single Carrier, F_OUT= 23.04 MHz

ACLR

Adjacent Channel

Leakage Ratio

×8 Interp, PLL off, CLK2 = 737.28 MHz,

DAC A+B on, F_IN= Baseband I/Q,

F_OUT= NCO

Single Carrier, F_OUT= 70MHz

Single Carrier, F_OUT= 140MHz

Four Carrier, F_OUT= 140MHz

Single Carrier Noise Floor

81

78

dBc

(3)

70

×8 Interp, PLL off, CLK2 = 737.28 MHz,

DAC A+B on,

F_IN= F_OUT= Baseband I/Q,

50 MHz offset, 1 MHz BW

101

161

101

161

dBm

dBm/Hz

dBm

Noise Floor,

Noise Spectral Density

Single Carrier NSD in 1 MHz BW

Four Carrier Noise Floor

(NSD)

(3)

Four Carrier NSD in 1 MHz BW

dBm/Hz

(1) Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25 Ω each to AVDD.

(2) 4:1 transformer output termination, 50Ω doubly terminated load

(3) W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF. TESTMODEL 1, 10 ms

6

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)

Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, DVDD, CLKVDD = 1.8V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB, DA[15:0], DB[15:0], SYNC, TXENABLE, CLKO_CLK1, LOCK_CLK1C

CONFIG26 io_1p8_3p3 = 0 (3.3V levels)

CONFIG26 io_1p8_3p3 = 1 (1.8V levels)

CONFIG26 io_1p8_3p3 = 0 (3.3V levels)

CONFIG26 io_1p8_3p3 = 1 (1.8V levels)

2.30

1.25

V_IH

V_IL

High-level input voltage

Low-level input voltage

V

1.00

0.54

I_IH

I_IL

C_I

High-level input current

Low-level input current

CMOS Input capacitance

SDO, SDIO

±20

2

mA

pF

I_LOAD= –100 mA

IOVDD

– 0.2

V_OH

V

SDO, SDIO

I_LOAD= –2 mA

0.8 ×

IOVDD

SDO, SDIO

I_LOAD= 100 mA

0.2

0.5

V_OL

V

SDO, SDIO

I_LOAD= 2 mA

Input data rate

0

20

10

5

250

MSPS

ns

t_s(SDENB)

t_s(SDIO)

t_h(SDIO)

t_SCLK

Setup time, SDENB to rising edge of SCLK

Setup time, SDIO valid to rising edge of SCLK

Hold time, SDIO valid to rising edge of SCLK

Period of SCLK

ns

100

40

ns

t_SCLKH

t_SCLK

t_d(Data)

t_RESET

High time of SCLK

ns

Low time of SCLK

ns

Data output delay after falling edge of SCLK

Minimum RESETB pulse width

10

25

ns

TIMING PARALLEL DATA INPUT: (DUAL CLOCK and DUAL SYNCHRONOUS CLOCK MODES: Figure 32)

t_s

t_h

Setup time

Hold time

1

ns

CLK1/C = input

1

Max timing offset between CLK1 and CLK2

rising edges

DUAL SYNCHRONOUS BUS MODE only

(Typical characteristic)

- 0.55

t_align

ns

2f_{CLK 2}

TIMING PARALLEL DATA INPUT (EXTERNAL CLOCK MODE: Figure 33 and PLL CLOCK MODE: Figure 34)

t_s

Setup time

Hold time

Delay time

1

ns

CLKO_CLK1 = input or output. Note: Delay

time increases with higher capacitive

loads.

t_h

t_d(CLKO)

4.5

1

CLOCK INPUT (CLK2/CLK2C)

CLK2/C Duty cycle

CLK2/C Differential voltage⁽¹⁾

40%

0.4

60%

V

CLK2/C Input common mode

2/3 ×

CLKVDD

CLK2C Input Frequency

800

MHz

CLOCK INPUT (CLK1/CLK1C)

CLK1/C Duty cycle

40%

0.4

60%

CLK1/C Differential voltage

CLK1/C Input common mode

1.0

V

IOVDD

/2

CLK1/C Input Frequency

250

160

MHz

CLOCK OUTPUT (CLKO)

CLKO Output Frequency⁽²⁾

with 3pF load

MHz

(1) Driving the clock input with a differential voltage lower than 1V will result in degraded performance.

(2) Specified by design and simulation. Not production tested. It is recommended to buffer CLKO.

Submit Documentation Feedback

7

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)

Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, DVDD, CLKVDD = 1.8V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PHASE LOCKED LOOP

Phase noise at 600 kHz offset

Phase noise at 6 MHz offset

100 MHz, 0-dBFS tone,

–125

–146

f_DATA= 200 MSPS, CLK2/C = 200 MHz,

PLL_m = '00111', PLL_n = '001', (M/N=4)

PLL_gain = '11', PLL_range = '1000' (8)

x4 Interpolation

dBc/ Hz

140

270

370

450

530

600

660

710

750

800

840

880

270

440

490

530

650

680

720

750

830

860

890

910

MHz

MHz/V

MHz

PLL_gain = '00', PLL_range = '0000' (0)

PLL_gain = '01', PLL_range = '0001' (1)

PLL_gain = '01', PLL_range = '0010' (2)

PLL_gain = '01', PLL_range = '0011' (3)

PLL_gain = '10', PLL_range = '0100' (4)

PLL_gain = '10', PLL_range = '0101' (5)

PLL_gain = '10', PLL_range = '0110' (6)

PLL_gain = '10', PLL_range = '0111' (7)

PLL_gain = '11', PLL_range = '1000' (8)

PLL_gain = '11', PLL_range = '1001' (9)

PLL_gain = '11', PLL_range = '1010' (A)

PLL_gain = '11', PLL_range = '1011' (B)

215

290

255

230

285

260

245

230

275

260

245

MHz/V

MHz

MHz/V

MHz

MHz/V

MHz

MHz/V

MHz

MHz/V

MHz

PLL/VCO Operating Frequency,

Typical VCO Gain

MHz/V

MHz

MHz/V

MHz

MHz/V

MHz

MHz/V

MHz

MHz/V

MHz

235

160

MHz/V

MHz

PFD Maximum Frequency

8

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

TYPICAL CHARACTERISTICS

Figure 1. Integral Nonlinearity

Figure 2. Differential Nonlinearity

vertical spacer

Figure 3. Single Tone Spectral Plot

Figure 4. Single Tone Spectral Plot

Submit Documentation Feedback

9

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

TYPICAL CHARACTERISTICS (continued)

85

Fdata = 200 MSPS

F_IN= 10.1 MHz, Sweep FMIX

80

x4 Interpolation

PLL off

75

70

65

60

55

50

0

50

100

150

200

250

300 350

F_OUT(MHz)

Figure 5. In-Band SFDR vs. Intermediate Frequency

Figure 6. Out-Of-Band SFDR vs Intermediate Frequency

vertical spacer

0

110

105

Fdata = 200 MSPS

IF = F_NCO

Fdata = 200 MSPS, IQ

F_IN= 20 MHz 0ꢀ5 MHz

-10

-20

-30

-40

-50

x4 Interpolation, PLL off

IF = 20 MHz

x4 Interpolation

PLL off

100

95

90

85

80

75

70

65

-6 dBFS

-60

-70

-80

-90

0 dBFS

60

55

-100

0

50

100

150

200

250

300

350

18

19

20

21

22

f - Input Frequency - MHz

IF - MHz

i

Figure 7. Two Tone IMD vs Intermediate Frequency

Figure 8. Two Tone IMD Spectral Plot

10

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

TYPICAL CHARACTERISTICS (continued)

85

80

75

70

0

Fdata = 200 MSPS, IQ

= 0 MHz

Fdata = 92.16 MSPS

IF = F_NCO

F

-10

IN

IF = 140 MHz

x4 Interpolation, FMIX

PLL off

x8 Interpolation

Fdac = 737.28 MSPS

-20

-30

-40

-50

-60

-70

PLL OFF

65

60

55

PLL ON

-80

-90

-100

138

139

140

141

142

0

50

100

150

200

250

300

350

IF - MHz

IF (MHz)

Figure 9. Two Tone IMD Spectral Plot

Figure 10. WCDMA ACLR vs Intermediate Frequency

vertical spacer

Figure 11. WCDMA TM1:Single Carrier, PLL Off

Figure 12. WCDMA TM1:Single Carrier, PLL On

Submit Documentation Feedback

11

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Figure 13. WCDMA TM1:Single Carrier, PLL Off

Figure 14. WCDMA TM1:Single Carrier, PLL On

vertical spacer

Figure 15. WCDMA TM1:Two Carriers, PLL Off

Figure 16. WCDMA TM1:Two Carriers, PLL On

12

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

TYPICAL CHARACTERISTICS (continued)

Figure 17. WCDMA TM1:Four Carriers, PLL Off

Figure 18. WCDMA TM1:Four Carriers, PLL On

Submit Documentation Feedback

13

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

TEST METHODOLOGY

Typical AC specifications were characterized with the DAC5688EVM. A sinusoidal master clock frequency is

generated by an HP8665B signal generator which drives an Agilent 8133A pulse generator to generate a square

wave output clock for the TSW3100 Pattern Generator and EVM input clock. On the EVM, the input clock is

driven by an CDCM7005 clock distribution chip that is configured to simply buffer the external clock or divide it

down for necessary test configurations.

The DAC5688 output is characterized with a Rohde and Schwarz FSU spectrum analyzer. For WCDMA signal

characterization, it is important to use a spectrum analyzer with high IP3 and noise subtraction capability so that

the spectrum analyzer does not limit the ACPR measurement.

DEFINITION OF SPECIFICATIONS

Adjacent Carrier Leakage Ratio (ACLR): Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a

3.84MHz bandwidth at a 5MHz offset from the carrier with a 12dB peak-to-average ratio.

Analog and Digital Power Supply Rejection Ratio (APSRR, DPSRR): Defined as the percentage error in the

ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.

Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB

change in the digital input code.

Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the

value at ambient (25°C) to values over the full operating temperature range.

Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output

current and the ideal full-scale output current.

Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output,

determined by a straight line drawn from zero scale to full scale.

Intermodulation Distortion (IMD3, IMD): The two-tone IMD3 or four-tone IMD is defined as the ratio (in dBc) of

the worst 3rd-order (or higher) intermodulation distortion product to either fundamental output tone.

Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C,

from the value at ambient (25°C) to values over the full operating temperature range.

Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output

current and the ideal mid-scale output current.

Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the

current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting

distortion performance.

Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius

from value at ambient (25°C) to values over the full operating temperature range.

Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the

output signal and the peak spurious signal.

Signal to Noise Ratio (SNR): Defined as the ratio of the RMS value of the fundamental output signal to the

RMS sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first

six harmonics and dc.

14

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

REGISTER DESCRIPTIONS

Table 1. Register Map

Name

Address

Default

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

STATUS0

CONFIG1

CONFIG2

CONFIG3

CONFIG4

CONFIG5

CONFIG6

CONFIG7

CONFIG8

CONFIG9

CONFIG10

CONFIG11

CONFIG12

CONFIG13

CONFIG14

CONFIG15

CONFIG16

CONFIG17

CONFIG18

CONFIG19

CONFIG20

CONFIG21

CONFIG22

CONFIG23

CONFIG24

CONFIG25

CONFIG26

CONFIG27

CONFIG28

CONFIG29

CONFIG30

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x01

0x0B

0xE1

0x00

0x22

0x00

0x24

0x00

0x15

0x80

0x00

0x0D

0xFF

0x00

PLL_lock

unused

device_ID(2:0)

twos

version(1:0)

interp_value(1:0)

insel_mode(1:0)

synchr_clkin

inv_inclk

diffclk_ena

clk1_in_ena

clk1c_in_ena

clko_SE_hold

fir4_ena

qmc_offset_ena

qmc_corr_ena

mixer_ena

diffclk_dly(1:0)

clko_dly(1:0)

reserved

ser_dac_data_ena

sif4

output_delay(1:0)

B_equals_A

A_equals_B

reserved

unused

reva

revb

sif_sync_sig

clkdiv_sync_ena

clkdiv_sync_sel

clkdiv_shift

mixer_gain

unused

phaseoffset(7:0)

phaseoffset(15:8)

phaseadd(7:0)

phaseadd(15:8)

phaseadd(23:16)

phaseadd(31:24)

qmc_gaina(7:0)

qmc_gainb(7:0)

qmc_phase(7:0)

qmc_phase(9:8)

qmc_gaina(10:8)

qmc_gainb(10:8)

qmc_offseta(7:0)

qmc_offsetb(7:0)

qmc_offseta(12:8)

qmc_offsetb(12:8)

unused

ser_dac_data(7:0)

ser_dac_data(15:8)

nco_sel(1:0)

unused

nco_reg_sel(1:0)

fifo_sel(2:0)

qmcorr_reg_sel(1:0)

qmoffset_reg_sel(1:0)

unused

aflag_sel

unused

PLL_ena

fifo_sync_strt(3:0)

unused

sleepb

unused

sleepa

unused

io_1p8_3p3

isbiaslpf_a

isbiaslpf_b

PLL_sleep

coarse_daca(3:0)

coarse_dacb(3:0)

reserved

PLL_m(4:0)

PLL_gain(1:0)

PLL_n(2:0)

PLL_range(3:0)

PLL_LPF_reset

VCO_div2

Submit Documentation Feedback

15

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

Register name: STATUS0 - Address: 0x00, Default 0x01

Bit 7

PLL_lock

0

Bit 6

unused

0

Bit 5

unused

0

Bit 4

Bit 3

Bit 2

Bit 1

0

Bit 0

1

device_ID (2:0)

0

version(1:0)

0

PLL_lock

:

Asserted when the internal PLL is locked. (Read Only)

Returns ‘000’ for DAC5688. (Read Only)

device_ID(2:0)

version(1:0)

A hardwired register that contains the version of the chip. (Read Only)

Register name: CONFIG1 Address: 0x01, Default 0x0B

Bit 7

Bit 6

Bit 5

unused

0

Bit 4

synchr_clkin

0

Bit 3

twos

1

Bit 2

inv_inclk

0

Bit 1

Bit 0

insel_mode (1:0)

interp_valule(1:0)

0

1

insel_mode(1:0)

:

Controls the expected format of the input data. For the interleaved modes, TXENABLE or the MSB of the port

that does not have data can be used to tell the chip which sample is the A sample. For TXENABLE the sample

aligned with the rising edge is A. For the MSB, it is presumed that this signal will toggle with A and B. The MSB

should be ‘1’ for A and ‘0’ for B. (*** See CONFIG23 ***)

insel_mode

Function

00

01

Normal input on A and B.

Interleaved input on A, which is de-interleaved and placed on

both A and B data paths. (*** See CONFIG23 ***)

10

11

Interleaved input on B, which is de-interleaved and placed on

both A and B data paths. (*** See CONFIG23 ***)

Half rate data on A and B inputs. This data is merge together

to form a single stream of data on the A data path.

synchr_clkin

twos

:

This turns on the synchronous mode of the dual-clock in mode. In this mode, the CLK2/C and CLK1/C must be

synchronous in phase since the slower clock is used to synchronize dividers in the clock distribution circuit.

When set (default), the input data format is expected to be 2’s complement. When cleared, the input is

expected to be offset-binary.

inv_inclk

This allows the input clock, the clock driving the input side of the FIFO to be inverted. This allows easier

registering of the data (more setup/hold time) in the single-clock mode of the device

interp_value(1:0)

These bits define the interpolation factor:

interp_value

Interpolation Factor

00

01

10

11

1X

2X

4X

8X

16

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

Register name: CONFIG2 Address: 0x02, Default 0xE1

Bit 7

diffclk_ena

1

Bit 6

clk1_in_ena

1

Bit 5

Bit 4

Bit 3

fir4_ ena

0

Bit 2

Bit 1

Bit 0

mixer_ena

1

clk1c_ in_ena

1

clko_SE_hold

0

qmc_ offset_ena

0

qmc_ corr_ena

0

diffclk_ena

:

When set (default), CLK1 and CLK1C pins are used as a differential clock input. Otherwise, CLK1 pin is used as

a single ended input.

clk1_in_ena

clk1c_in_ena

clko_SE_hold

When set (default), the CLKO_CLK1 pin is configured as the CLK1 input. If cleared, the pin is configured to

output an internally generated CLKO as a clock signal for the input data.

When set (default), the LOCK_CLK1C pin is configured as the CLK1C input. If cleared, the pin is configured to

output the PLL_LOCK status.

When set, the single ended (SE) clock is held to a value of ‘1’ so that the signal doesn’t toggle when using the

differential clock input.

fir4_ena

:

When set, the FIR4 Inverse SINC filter is enabled. Otherwise it is bypassed

When set, the digital Quadrature Modulator Correction (QMC) offset correction circuitry is enabled.

When set, the QMC phase and gain correction circuitry is enabled.

qmc_offset_ena

qmc_corr_ena

mixer_ena

When set, the Full Mixer (FMIX) is enabled. Otherwise it is bypassed.

Register name: CONFIG3 Address: 0x03, Default 0x00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

Bit 0

0

diffclk_dly(1:0)

clko_dly(1:0)

Reserved(3:0)

0

diffclk_dly(1:0)

:

To allow for a wider range of interfacing, the differential input clock (CLK1/CLK1C) has programmable delay

added to its tree.

diffclk_dly

Approximate additional delay

00

01

10

11

0

1.0 ns

2.0 ns

3.0 ns

clko_dly(1:0)

:

Same as above except these bits effect the single ended or internally generated clock

Register name: CONFIG4 Address: 0x04, Default 0x00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

unused

0

Bit 1

reva

0

Bit 0

revb

0

ser_dac_ data_ena

0

output_delay(1:0)

B_equals_A

0

A_equals_B

0

ser_dac_data_ena

output_delay(1:0)

B_equals_A

:

Muxes the ser_dac_data(15:0) to both DACs when asserted.

Delays the output to both DACs from 0 to 3 DAC clock cycles

When set, the DACA data is driving the DACB output.

When set, the DACB data is driving the DACA output.

A_equals_B

Bit 4

B_equals_A

Bit 3

A_equals_B

DACB

Output

DACA

Output

Description

Normal Output

0

1

0

1

0

1

B data

A data

B data

A data

B data

Both DACs driven by B data

Both DACs driven by A data

Swapped Output

reva

revb

:

Reverse the input bits of the A input port. MSB becomes LSB.

Reverse the input bits of the B input port. MSB becomes LSB

Submit Documentation Feedback

17

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

Register name: CONFIG5 Address: 0x05, Default 0x22

Bit 7

sif4

0

Bit 6

sif_ sync_sig

0

Bit 5

Bit 4

Bit 3

Reserved

0

Bit 2

clkdiv_shift

0

Bit 1

mixer_gain

1

Bit 0

unused

0

clkdiv_sync_ena

1

clkdiv_sync_sel

0

sif4

sif_sync_sig

:

When set, the serial interface (SIF) is a 4 bit interface, otherwise it is a 3 bit interface.

SIF created sync signal. Set to ‘1’ to cause a sync and then clear to ‘0’ to remove it.

Enables syncing of the clock divider using the sync or TXENABLE pins when the bit is asserted.

Selects the input pin to sync the clock dividers. (0 = SYNC, 1 = TXENABLE)

clkdiv_sync_ena

clkdiv_sync_sel

clkdiv_shift

:

When set, a rising edge on the selected sync (see clkdiv_sync_sel) for the clock dividers will cause a slip in the

synchronous counter by 1T and is useful for multi-DAC time alignment.

mixer_gain

:

When set, adds 6dB to the mixer gain output.

Register name: CONFIG6 Address: 0x06, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

phaseoffset(7:0)

0

phaseoffset(7:0)

:

See CONFIG7 below.

Register name: CONFIG7 Address: 0x07, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

phaseoffset(15:8)

0

phaseoffset(15:8)

:

This is the phase offset added to the NCO accumulator just before generation of the SIN and COS values. The

phase offset is added to the upper 16bits of the NCO accumulator results and these 16 bits are used in the

sin/cosine lookup tables.

Register name: CONFIG8 Address: 0x08, Default 0x00 (Synced)

Bit 7

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

phaseadd(7:0)

0

phaseadd(7:0)

:

See CONFIG11 below.

Register name: CONFIG9 Address: 0x09, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

phaseadd(15:8)

0

phaseadd(15:8)

:

See CONFIG11 below.

Register name: CONFIG10 Address: 0x0A, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

phaseadd(23:16)

0

phaseadd(23:16)

:

See CONFIG11 below.

18

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

Register name: CONFIG11 Address: 0x0B, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

phaseadd(31:24)

0

phaseadd(31:24)

:

The phaseadd(31:24) value is used to determine the frequency of the NCO. The two’s complement formatted value

can be positive or negative and the LSB is equal to Fs/(2^32).

Register name: CONFIG12 Address: 0x0C, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

qmc_gaina(7:0)

0

qmc_gaina(7:0)

:

Lower 8 bits of the 11-bit Quadrature Modulator Correction (QMC) gain word for DACA. The upper 3 bits are in

the CONFIG15 register. The full 11-bit qmc_gaina(10:0) word is formatted as UNSIGNED with a range of 0 to

1.9990 and the default gain is 1.0000. The implied decimal point for the multiplication is between bit 9 and bit 10.

Refer to formatting reference below.

qmc_gaina(10:0)

[Binary]

qmc_gaina(10:0)

[Decimal]

Format

Gain Value

00000000000

00000000001

…..

0

1

0 + 0/1024 =

0 + 1/1024 =

0.0000000

0.0009766

….

…..

1023 0 + 1023/1024 =

01111111111

10000000000

10000000001

…..

0.9990234

1.0000000

1.0009766

….

[Default] 1024

1 + 0/1024 =

1 + 1/1024 =

1025

…..

11111111111

2047 1 + 1023/1024 =

1.9990234

Register name: CONFIG13 Address: 0x0D, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

qmc_gainb(7:0)

0

qmc_gainb(7:0)

:

Lower 8 bits of the 11-bit QMC gain word for DACB. The upper 3 bits are in CONFIG15 register. Refer to CONFIG12

above for formatting.

Submit Documentation Feedback

19

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

Register name: CONFIG14 Address: 0x0E, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

qmc_phase(7:0)

0

qmc_phase(7:0)

:

Lower 8 bits of the 10-bit Quadrature Modulator Correction (QMC) phase word. The upper 2 bits are in the

CONFIG15 register. The full 11-bit qmc_phase(9:0) correction word is formatted as two’s complement and

scaled to occupy a range of –0.125 to 0.12475 and a default phase correction 0.00. To accomplish QMC phase

correction, this value is multiplied by the current ‘Q’ sample, then summed into the ‘I’ sample. Refer to formatting

reference below.

qmc_phase(9:0)

[Binary]

qmc_phase(9:0)

[Decimal]

Format

Phase

Correction

10000000000

10000000001

…..

–512

(–1 + 0/512) / 8 =

(–1 + 1/512) / 8 =

–0.1250000

–0.1234559

….

–511

…..

11111111111

00000000000

00000000001

…..

–1 (–1 + 511/512) / 8 =

–0.0002441

+0.0000000

+0.0002441

….

[Default] 0

(+0 + 0/512) / 8 =

(+0 + 1/512) / 8 =

1

…..

01111111111

511 (+0 + 511/512) / 8 =

+0.1247559

Register name: CONFIG15 Address: 0x0F, Default 0x24 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

qmc_phase(9:8)

qmc_gaina(10:8)

0

qmc_gainb(10:8)

0

1

0

1

qmc_phase(9:8)

qmc_gaina(10:8)

qmc_gainb(10:8)

:

Upper 2 bits of qmc_phase term. Defaults to zero.

Upper 3 bits of qmc_gaina term. Defaults to unity gain.

Upper 3 bits of the qmc_gainb term. Defaults to unity gain.

Register name: CONFIG16 Address: 0x10, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

qmc_offseta(7:0)

0

qmc_offseta(7:0)

:

Lower 8 bits of the DACA offset correction. The upper 5 bits are in CONFIG18 register. The offset is

measured in DAC LSBs.

Register name: CONFIG17 Address: 0x11, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

qmc_offsetb(7:0)

0

qmc_offsetb(7:0)

:

Lower 8 bits of the DACB offset correction. The upper 5 bits are in

CONFIG19 register. The offset is measured in DAC LSBs.

20

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

Register name: CONFIG18 Address: 0x12, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

unused

0

Bit 1

unused

0

Bit 0

unused

0

qmc_offseta(12:8)

0

qmc_offseta(12:8)

: Upper 5 bits of the DACA offset correction.

Register name: CONFIG19 Address: 0x13, Default 0x00 (Synced)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

unused

0

Bit 1

unused

0

Bit 0

unused

0

qmc_offsetb(12:8)

0

qmc_offsetb(12:8)

: Upper 5 bits of the DACB offset correction.

Register name: CONFIG20 Address: 0x14, Default 0x00

Bit 7

Bit 6

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

Bit 0

0

ser_dac_data(7:0)

0

ser_dac_data(7:0)

:

Lower 8 bits of the serial interface controlled DAC value. This data is routed to both DACs when enabled

via ser_dac_data_ena in CONFIG4. Value is expected in 2s complement format.

Register name: CONFIG21 Address: 0x15, Default 0x00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

Bit 0

0

ser_dac_data(15:8)

0

:

0

ser_dac_data(15:8)

Upper 8 bits of the serial interface controlled DAC value. This data is routed to both DACs when enabled via

ser_dac_data_ena in CONFIG4. Value is expected in 2's complement format.

Register name: CONFIG22 Address: 0x16, Default 0x15

Bit 7

Bit 6

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

nco_sel(1:0)

nco_reg_sel(1:0)

qmcorr_reg_sel(1:0)

qmoffset_reg_sel(1:0)

0

1

0

1

0

1

nco_sel(1:0)

:

Selects the signal to use as the sync for the NCO accumulator.

Selects the signal to use as the sync for loading the NCO registers.

Selects the signal to use as the sync for loading the QM correction registers.

nco_reg_sel(1:0)

qmcorr_reg_sel(1:0)

qmoffsest_reg_sel(1:0)

Selects the signal to use as the sync for loading the QM offset correction registers.

*_sel (1:0)

Sync selected

TXENABLE from FIFO output

SYNC from FIFO output

sync_SIF_sig (via CONFIG5)

Always zero

00

01

10

11

Submit Documentation Feedback

21

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

Register name: CONFIG23 Address: 0x17, Default 0x15

Bit 7

unused

0

Bit 6

unused

0

Bit 5

Bit 4

fifo_sel(2:0)

1

Bit 3

Bit 2

aflag_ sel

1

Bit 1

unused

0

Bit 0

unused

1

0

fifo_sel(2:0)

:

Selects the sync source for the FIFO from the table below. For the case where the sync is dependent on the first

transition of the input data MSB: Once the transition occurs, the only way to get another sync it to reset the device

or to program fifo_sel to another value

fifo_sel (2:0)

000

Sync selected

TXENABLE from pin

SYNC from pin

001

010

sync_SIF_sig (via CONFIG5)

Always zero

011

100

1^sttransition on DA MSB

1^sttransition on DB MSB

Always zero

101

110

111

Always one

aflag_sel

:

When set, the MSB of the input opposite of incoming data is used to determine the A sample. When cleared,

rising edge of TXENABLE is used. Refer to Figure 37.

Register name: CONFIG24 Address: 0x18, Default 0x80

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Unused

0

Bit 2

Unused

0

Bit 1

Unused

0

Bit 0

Unused

0

fifo_sync_strt(3:0)

1

0

fifo_sync_strt(3:0)

:

When the sync to the FIFO occurs, this is the value loaded into the FIFO output position counter. With this

value the initial difference between input and output pointers can be controlled. This may be helpful in

syncing multiple chips or controlling the delay through the device.

Register name: CONFIG25 Address: 0x19, Default 0x00

Bit 7

Unused

0

Bit 6

Bit 5

Unused

0

Bit 4

Unused

0

Bit 3

Unused

0

Bit 2

Unused

0

Bit 1

Unused

0

Bit 0

Unused

0

Unused

0

Register name: CONFIG26 Address: 0x1A, Default 0x0D

Bit 7

io_1p8_3p3

0

Bit 6

Unused

0

Bit 5

sleepb

0

Bit 4

sleepa

0

Bit 3

isbiaslpfb_a

1

Bit 2

isbiaslpf_b

1

Bit 1

PLL_ sleep

0

Bit 0

PLL_ena

1

io_1p8_3p3

:

Used to program the digital input voltage threshold levels. ‘0’=3.3V tolerate pads and ‘1’=1.8V tolerate pads.

Applies to following digital pins: CLKO_CLK1, LOCK_CLK1C, DA[15:0], DB[15:0], SYNC, RESETB, SCLK,

SDENB, SDIO (input only) and TXENABLE.

sleepb

:

When set, DACB is put into sleep mode. Putting the DAC into single DAC mode does not automatically assert this

signal, so for minimum power in single DAC mode, also program this register bit.

sleepa

When set, DACA is put into sleep mode. Note: If DACA channel is in sleep mode (sleepa = '1') the DACB channel

is also forced in to sleep mode.

isbiaslpfb_a

isbiaslpfb_b

Turns on the low pass filter for the current source bias in the DACA when cleared. The low pass filter will set a

corner at ~472kHz when low and ~95 kHz when high.

Turns on the low pass filter for the current source bias in the DACB when cleared. The low pass filter will set a

corner at ~472kHz when low and ~95 kHz when high.

PLL_sleep

PLL_ena

:

When set, the PLL is put into sleep mode. Bypassing the PLL does not automatically but it into sleep mode.

When set, the PLL is on and its output clock is being used as the DAC clock.

22

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

Register name: CONFIG27 Address: 0x1B, Default 0xFF

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

1

Bit 0

1

coarse_daca(3:0)

coarse_dacb(3:0)

1

coarse_daca(3:0)

:

Scales the output current is 16 equal steps.

V

EXTIO

(

)

DACA_gain ) 1

Rbias

coarse_dacb(3:0)

:

Same as above except for DACB.

Register name: CONFIG28 Address: 0x1C, Default 0x00

Bit 7

Reserved

0

Bit 6

Reserved

0

Bit 5

Reserved

0

Bit 4

Reserved

0

Bit 3

Reserved

0

Bit 2

Reserved

0

Bit 1

Reserved

0

Bit 0

Reserved

0

Register name: CONFIG29 Address: 0x1D, Default 0x00

Bit 7

0

Bit 6

0

Bit 5

PLL_m(4:0)

0

Bit 4

Bit 3

Bit 2

Bit 1

PLL_n(2:0)

0

Bit 0

0

PLL_m

:

M portion of the M/N divider of the PLL thermometer encoded:

PLL_m(4:0)

00000

M value

1

00001

2

4

00011

00111

8

01111

16

11111

32

All other values

Invalid

PLL_n

:

N portion of the M/N divider of the PLL thermometer encoded. If supplying a high rate CLK2/C frequency, the PLL_n value

should be used to divide down the input CLK2/C to maintain a maximum PFD operating of 160 MHz.

PLL_n(2:0)

n value

000

001

1

2

011

4

8

111

All other values

Invalid

PLL Function:

₊ƪ^(M)ƫ

ƒ

ref

vco

(N)

where ƒ_refis the frequency of the external DAC clock input on the CLK2/C pins

Submit Documentation Feedback

23

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

Register name: CONFIG30 Address: 0x1E, Default 0x00

Bit 7

Bit 6

VCO_div2

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

PLL_LPF_ reset

0

PLL_gain(1:0)

PLL_range(3:0)

0

PLL_LPF_reset

VCO_div2

:

When set, can be used to hold the PLL loop filter at 0 volts.

When set, the PLL CLOCK output is 1/2 the PLL VCO frequency. Used to run the VCO at 2X the desired clock

frequency to reduce phase noise for lower DAC clock rates.

PLL_gain(1:0)

:

Used to adjust the PLL’s Voltage Controlled Oscillator (VCO) gain, K_VCO. Refer to the Electrical Characteristics

table. By increasing the PLL_gain, the VCO can cover a broader range of frequencies; however, the higher gain

also increases the phase noise of the PLL. In general, lower PLL_gain settings result in lower phase noise. The

K_VCOof the VCO can also affect the PLL stability and is used to determine the loop filter components. See section

on determining the PLL filter components for more detail.

PLL_range(3:0)

:

Used to adjust the bias current of the VCO. By increasing the bias current, the oscillator can reach higher

frequencies. Refer to the Electrical Characteristics table.

'0000' – minimum bias current and lowest VCO frequency range

'1111' – maximum bias current and highest VCO frequency range

24

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

DETAILED DESCRIPTION

EXAMPLE SYSTEM DIAGRAM

GC5016

DAC5688 DAC

TRF3703 AQM

Antenna

5V

I-Signal

DA[15:0]

16

Term

DAC

LPF

DB[15:0]

16

5V

Term

PA

Digital

Up

Q-Signal

LPF

To TX

Feedback

Converter

(DUC)

TXENABLE

Clock, Sync & Control

90

CLK1

To RX

Path

opt.

PLL

0

76.8 MHz

Loop

Filter

~ 2.1 GHz

CK

76.8 MHz

TRF3761-X PLL/VCO

Div

1/2/4

614.4 MHz

VCO

VCTRL_IN

N-

Divider

10 MHz

REF

OSC

Term

÷1

Loop

Filter

CDCM7005

PFD

Charge

Pump

REF_IN

R-

Div

÷8

CPOUT

PLL

Synth

Loop

Filter

Clock Divider /

Distribution

Status& Control

Status &

Control

VCXO

614.4 MHz

Figure 19. Example System Diagram: Direct Conversion with 8x interpolation

SERIAL INTERFACE

The serial port of the DAC5688 is a flexible serial interface which communicates with industry standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the

operating modes of DAC5688. It is compatible with most synchronous transfer formats and can be configured as

a 3 or 4 pin interface by SIF4 in register CONFIG5. In both configurations, SCLK is the serial interface input

clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in

and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input into the device

with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,

depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle which

identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to

transfer the data. Table 2 indicates the function of each bit in the instruction cycle and is followed by a detailed

description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.

Submit Documentation Feedback

25

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

Table 2. Instruction Byte of the Serial Interface

Bit

Description

R/W

7

6

5

4

3

2

1

0

R/W

N1

N0

A4

A3

A2

A1

A0

Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from DAC5688 and

a low indicates a write operation to DAC5688.

[N1 : N0]

Identifies the number of data bytes to be transferred per Table 3. Data is transferred MSB first.

Table 3. Number of Transferred Bytes Within One

Communication Frame

N1

0

N0

0

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

0

1

0

1

[A4 : A0]

Identifies the address of the register to be accessed during the read or write operation. For multi-byte transfers, this address

is the starting address. Note that the address is written to the DAC5688 MSB first and counts down for each byte

Figure 20 shows the serial interface timing diagram for a DAC5688 write operation. SCLK is the serial interface

clock input to DAC5688. Serial data enable SDENB is an active low input to DAC5688. SDIO is serial data in.

Input data to DAC5688 is clocked on the rising edges of SCLK.

Data Transfer Cycle(s)

Instruction Cycle

SDENB

SCLK

SDIO

r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

(SDENB)

t_s

t_SCLK

SDENB

SCLK

SDIO

t_{h (}

)

SDIO

t_SCLKHt_SCLKL

(

t_{s SDIO}

)

Figure 20. Serial Interface Write Timing Diagram

Figure 21 shows the serial interface timing diagram for a DAC5688 read operation. SCLK is the serial interface

clock input to DAC5688. Serial data enable SDENB is an active low input to DAC5688. SDIO is serial data in

during the instruction cycle. In 3 pin configuration, SDIO is data out from DAC5688 during the data transfer

cycle(s), while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from DAC5688 during

the data transfer cycle(s). The SDIO/SDO data is output on the falling edge of SCLK. At the end of the data

transfer, SDO will output low on the final falling edge of SCLK until the rising edge of SDENB when it will 3-state.

26

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

Data Transfer Cycle(s)

Instruction Cycle

SDENB

SCLK

SDIO

N1 N0

-

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0

r/w

0

SDO

D7 D6 D5 D4 D3 D2 D1 D0

4 pin configuration

output

3 pin configuration

output

SDENB

SCLK

SDIO

SDO

Data n

Data n-1

t

d (Data)

Figure 21. Serial Interface Read Timing Diagram

FIR FILTERS

Figure 22 shows the magnitude spectrum response for FIR1, a 67-tap interpolating half-band filter. The transition

band is from 0.4 to 0.6 × f_IN(the input data rate for the FIR filter) with <0.002-dB of pass-band ripple and > 80-dB

stop-band attenuation. Figure 23 shows the transition band region from 0.37 to 0.47 × fIN. Up to 0.458 × f_INthere

is less than 0.5 dB of attenuation.

Figure 24 shows the magnitude spectrum response for the 19-tap FIR2 filter. The transition band is from 0.25 to

0.75 × f_IN(the input data rate for the FIR filter). For 4x interpolation modes, the composite filter response is

shown in Figure 25.

Figure 26 shows the magnitude spectrum response for the 11-tap FIR3 filter. For 8x interpolation modes, the

composite filter response is shown in Figure 27.

The DAC5688 also has a 9-tap non-interpolating inverse sinc filter (FIR4) running at the DAC update rate (f_DAC

)

that can be used to flatten the frequency response of the sample and hold output. The DAC sample and hold

output set the output current and holds it constant for one DAC clock cycle until the next sample, resulting in the

well known sin(x)/x or sinc(x) frequency response shown in Figure 28 (red dash-dotted line). The inverse sinc

filter response (Figure 28, blue dashed line) has the opposite frequency response between 0 to 0.4 × f_DAC

,

resulting in the combined response (Figure 28, green solid line). Between 0 to 0.4 × f_DAC, the inverse sinc filter

compensates the sample and hold rolloff with less than 0.03-dB error.

The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to FIR4 must be reduced from

full scale to prevent saturation in the filter. The amount of backoff required depends on the signal frequency, and

is set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0

dB). For example, if the signal input to FIR4 is at 0.25 × f_DAC, the response of FIR4 is 0.9 dB, and the signal must

be backed off from full scale by 0.9 dB. The gain function in the QMC block can be used to set reduce amplitude

of the input signal. The advantage of FIR4 having a positive gain at all frequencies is that the user is then able to

optimized backoff of the signal based on the signal frequency.

The filter taps for all digital filters are listed in Table 4. Note that the loss of signal amplitude may result in lower

SNR due to decrease in signal amplitude.

Submit Documentation Feedback

27

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

Magnitude Spectrum for FIR1

20

Magnitude Spectrum for FIR1

0.1

0

-20

-40

-0.1

-0.2

-0.3

-0.4

-0.5

-60

-80

-100

-120

-140

-160

0.37 0.38 0.39

0.4

0.41 0.42 0.43 0.44 0.45 0.46 0.47

f/Fin

0

0.1

0.2

0.3

0.4

0.5

f/Fin

0.6

0.7

0.8

0.9

1.0

Figure 22. Magnitude Spectrum for FIR1

Figure 23. FIR1 Transition Band

vertical spacer

4x Interpolation Composite Filtering Response

Magnitude Spectrum for FIR 2

20

0

-20

-40

-60

-20

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

2

1

0.5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

f/Fin

Figure 24. Magnitude Spectrum for FIR2

Figure 25. 4x Interpolation Composite Response

vertical spacer

28

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

8x Interpolation Composite Filtering Response

Magnitude Spectrum for FIR 3

20

0

-20

-40

-20

-40

-60

-80

-100

-120

-140

-100

-120

-140

-160

0

0.5

1

2

f/Fin

3

4

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

f/Fin

Figure 26. Magnitude Spectrum for FIR3

vertical spacer

Figure 27. 8x Interpolation Composite Response

vertical spacer

FIR 4 Inverse Corrected Spectrum

5

4

3

2

1

0

-1

-2

-3

-4

-5

0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45

0.5

f/fDAC

Figure 28. Magnitude Spectrum for FIR4

Submit Documentation Feedback

29

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

Table 4. FIR Filter Coefficients

2X Interpolating Half-band Filters

Non-Interpolating

Inverse-SINC Filter

FIR1

FIR2

FIR3

FIR4

67 Taps

19 Taps

11 Taps

9 Taps

2

0

2

0

9

0

9

0

31

0

31

0

1

-4

1

–4

–5

–58

0

–58

0

–219

0

–219

0

13

0

–50

592⁽¹⁾

–50

11

214

0

214

0

1212

2048⁽¹⁾

1212

0

–21

0

–21

0

–638

0

–638

0

37

2521

(1)

0

4096

–61

0

–61

0

97

0

–148

0

–148

0

218

0

218

0

–314

0

–314

0

444

0

444

0

–624

0

–624

0

877

0

877

0

–1260

0

–1260

0

1916

0

1916

0

–3372

0

–3372

0

10395

(1)

16384

(1) Center Taps are highlighted in BOLD.

30

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

Full Complex Mixer (FMIX)

The full complex Mixer (FMIX) block uses a Numerically Controlled Oscillator (NCO) with a 32-bit frequency

register phaseadd(31:0) and a 16-bit phase register phaseoffset(15:0) to provide sin and cos for mixing. The

NCO tuning frequency is programmed in CONFIG8 through CONFIG11 registers. Phase offset is programmed in

CONFIG6 and CONFIG7 registers. A block-diagram of the NCO is shown below in Figure 29.

32

16

sin

Accumulator

CLK RESET

32

16

Look Up

Table

Frequency

Register

16

cos

16

F_DAC

NCO SYNC

via

nco_sel(1:0)

Phase

Register

Figure 29. Block-Diagram of the NCO

Synchronization of the NCO occurs by resetting the NCO accumulator to zero. The synchronization source is

selected by CONFIG22 nco_sel(1:0). Frequency word f_refin the phaseadd register is added to the accumulator

every clock cycle, f_DAC. The output frequency of the NCO is

ƒ

ref

+

NCO_CLK

ƒ

2³²

NCO

(1)

Treating channels A and B as a complex vector I + I×Q where I(t) = A(t) and Q(t) = B(t), the output of FMIX

I_OUT(t) and Q_OUT(t) is

I

cos

-

(2)

(3)

+

Where t is the time since the last resetting of the NCO accumulator, d is the phase offset value and mixer_gain

is either 0 or 1. d is given by:

d + 2p phase(15 : 0)ń2¹⁶

(4)

The maximum output amplitude of FMIX occurs if I_IN(t) and Q_IN(t) are simultaneously full scale amplitude and the

sine and cosine arguments 2pf_NCOt + d (2N-1)×p/4 (N = 1, 2, ...).

With CONFIG5 mixer_gain = 0, the gain through FMIX is sqrt(2)/2 or –3 dB. This loss in signal power is in most

cases undesirable, and it is recommended that the gain function of the QMC block be used to increase the signal

by 3 dB to compensate. With mixer_gain = 1, the gain through FMIX is sqrt(2) or + 3 dB, which can cause

clipping of the signal if I_IN(t) and Q_IN(t) are simultaneously near full scale amplitude and should therefore be used

with caution.

Submit Documentation Feedback

31

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

Quadrature Modulator Correction (QMC)

The Quadrature Modulator Correction (QMC) block provides a means for adjusting the gain and phase of the

complex signal. At a quadrature modulator output, gain and phase imbalances result in an undesired sideband

signal.

The block diagram for the QMC is shown in Figure 30. The QMC block contains 3 programmable parameters:

qmc_gaina(10:0), qmc_gainb(10:0) and qmc_phase(9:0).

Registers qmc_gaina(10:0) and qmc_gainb(10:0) control the I and Q path gains and are 11 bit values with a

range of 0 to approximately 2. This value is used to scale the signal range. Register qmc_phase(9:0) controls the

phase imbalance between I and Q and is a 10-bit value that ranges from –1/8 to approximately +1/8. This value

is multiplied by each Q sample then summed into the I sample path. This operation is a simplified approximation

of a true phase rotation and covers the range from –7.5 to +7.5 degrees in 1024 steps.

qmc_gaina(10:0)

11

I(t)

X

S

10

X

qmc _phase (9:0)

Q(t)

X

11

qmc_gain b(10:0)

Figure 30. QMC Block Diagram

DAC Offset Control

The qmc_offseta(12:0) and qmc_offsetb(12:0) values can be used to independently adjust the I and Q path DC

offsets. Both offset values are in represented in 2s-complement format with a range from –4096 to 4095.

The offset value adds a digital offset to the digital data before digital-to-analog conversion. Since the offset is

added directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offset

values are LSB aligned.

qma_offset

{-4096, - 4095, … , 4095 }

13

I

S

Q

S

13

qmb_offset

{-4096, - 4095, … , 4095 }

Figure 31. DAC Offset Block

32

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

CLOCK MODES

The DAC5688 supports several different clocking modes for generating the internal clocks for the logic and DAC.

The clocking modes are selected by programming the register bits below and summarized in Table 5.

Register

Control Bits

CONFIG1

CONFIG2

CONFIG26

synchr_clkin

clk1_in_ena, clk1c_in_ena, diffclk_ena

PLL_ena

Table 5. Summary of Clock Modes and Options

CLKO_

CLK1

I/O

Programming Bits

clk1c_in_ena

synchr_clkin

clk1_in_en

diffclk_ena

PLL_ena

Clocking Mode

Option

Dual Synchronous Clock Mode

Diff. CLK1

S/E CLK1

Diff. CLK1

S/E CLK1

CLKO

Input

1

0

1

0

1

0

1

X

1

0

1

0

1

0

1

Dual Clock Mode

Input

X

1

External Clock Mode

PLL Clock Mode

Output

Input

Diff. CLK1

S/E CLK1

CLKO

Input

X

Output

DUAL SYNCHRONOUS CLOCK MODE

In DUAL SYNCHRONOUS CLOCK MODE, the user provides the CLK2/C clock signal at the DAC sample rate

and also provides a divided down CLK1 at the input data rate. The CLK1 signal can be differential or

single-ended. Refer to Figure 16 for the timing diagram. In this mode the relationship between CLK2 and CLK1

(t_{_align}) is critical and used as a synchronizing mechanism for the internal logic. This facilitates multi-DAC

synchronization by using dual external clock inputs CLK1 and CLK2 while FIFO data is always written and read

from location zero. It is highly recommended that a clock synchronizer device such as the CDCM7005 provide

both CLK2/C and CLK1/C inputs. Although CLK1 could be single-ended it is recommended to use a differential

clock to ensure proper skews between the two clock inputs.

DUAL CLOCK MODE

In DUAL CLOCK MODE, the user provides the CLK2/C clock signal at the DAC sample rate and also provides a

divided down CLK1 at the input data rate. The CLK1 signal can be differential or single-ended. Refer to Figure 32

for the timing diagram. Unlike the DUAL SYNCHRONOUS CLOCK MODE, the t_{_align}parameter is not critical

because these clocks are not used as a synchronizing mechanism for the internal logic and the FIFO is used as

an elastic buffer for the data. Synchronizing in this mode is provided by separate control inputs.

CLK 2

(only in dual synchronous clock mode)

D < t_{_align}

CLK 1

DA [0:15 ]

DB [0:15 ]

t_s

t_h

Figure 32. DUAL (SYNCHRONOUS) CLOCK MODE Timing Diagram

Submit Documentation Feedback

33

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

EXTERNAL CLOCK MODE

In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through CLK2/C.

The CLKO_CLK1 pin is configured as an output in this mode and will toggle at a required frequency for the

configured interpolation rate and data mode. The CLKO_CLK1 clock can be used to drive the input data source

(such as digital upconverter) that sends the data to the DAC. Note that the CKO_CLK1 delay relative to the input

CLK2 rising edge (t_d(CLKO) in Figure 33) will increase with increasing loads.

CLK 2

t

d(CLKO)

CLKO _ CLK 1

(output )

DA [0 :15 ]

DB [0 :15 ]

t

s

t

h

Figure 33. EXTERNAL CLOCK MODE Timing Diagram

PLL CLOCK MODE

In PLL CLOCK MODE, the user provides an external reference clock to the CLK2/C input pins. Refer to

Figure 34. An internal clock multiplying PLL uses the lower-rate reference clock to generate a high-rate clock for

the DAC. This function is very useful when a high-rate clock is not already available at the system level;

however, the internal VCO phase noise in PLL Clock Mode may degrade the quality of the DAC output signal

when compared to an external low jitter clock source.

CLK0_CLK1

(input or output)

DA [0:15]

DB [0:15]

t

s

t

h

Figure 34. PLL CLOCK MODE Timing Diagram

The internal PLL has a type four phase-frequency detector (PFD) comparing the CLK2/C reference clock with a

feedback clock to drive a charge pump controlling the VCO operating voltage and maintaining synchronization

between the two clocks. An external low-pass filter is required to control the loop response of the PLL. See the

Low-Pass Filter section for the filter setting calculations. This is the only mode where the LPF filter applies.

The input reference clock N-Divider is selected by CONFIG29 PLL_n(2:0) for values of ÷1, ÷2, ÷4 or ÷8. The

VCO feedback clock M-Divider is selected by CONFIG29 PLL_m(4:0) for values of ÷1, ÷2, ÷4, ÷8, ÷16 or ÷32.

The combination of M-Divider and N-Divider form the clock multiplying ratio of M/N. If the reference clock

frequency is greater than 160MHz, use a N-Divider of ÷2, ÷4 or ÷8 to avoid exceeding the maximum PFD

operating frequency.

For DAC sample rates less than the maximum VCO operating frequency of 910/2 or 455 MHz. The phase noise

of PLL may improved by using the output divider via CONFIG30 VCO_div2. If not using the PLL, clear

CONFIG26 PLL_ena and set CONFIG26 PLL_sleep to reduce power consumption. In some cases, it may be

useful to reset the VCO control voltage by toggling CONFIG30 PLL_LPF_reset.

34

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

External

Loop

Filter

PLL Bypass

Clock Multiplying PLL

To internal

DAC clock

distribution

CLK2

CLK2C

F_REF/N

F_VCO/M

N–Divider

(1, 2, 4, 8)

F_VCO

VCO

F_REF

Charge

Pump

PFD

F_PLL

F_VCO/2

M-Divider

( 1,2,4,8,16,32)

÷2

F_VCO

PLL Sleep

PLL_gain(1:0),

PLL_range(3:0)

(CONFIG30)

PLL_sleep

(CONFIG26)

PLL_m (4:0)

(CONFIG29)

VCO_div2

(CONFIG11)

PLL_ena

(CONFIG26)

PLL_n (2:0)

(CONFIG29)

PLL_LPF_reset

(CONFIG30)

Figure 35. Functional Block Diagram for PLL

DATA BUS MODES

The DAC5688 supports three DATA BUS MODES:

1. DUAL BUS MODE

2. INTERLEAVED BUS MODE

3. HALF RATE BUS MODE

DUAL BUS MODE

In DUAL BUS MODE, the user inputs data on both DA[15:0] and DB[15:0] ports. This mode is selected by setting

CONFIG1 insel_mode(1:0) = ‘00’. Refer to Figure 36.

CLK1

DA[15:0]

DB[15:0]

A₀

B₀

A₁

B₁

A₂

B₂

A₃

B₃

A_N

B_N

A_N+1

B_N+1

Figure 36. DUAL BUS MODE (Dual Clock Mode)

Submit Documentation Feedback

35

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

INTERLEAVED BUS MODE

In INTERLEAVED BUS MODE, the user inputs dual-channel data as an interleaved single data stream to either

DA[15:] or DB[15:0] ports. The DAC5688 de-interleaves the input data stream and routes to both A and B data

paths. For input data on DA[15:0], set CONFIG1 insel_mode[15:0] = ‘01’. For input data on DB[15:0], set

CONFIG1 insel_mode[15:0] = ‘10’. In this bus mode, a separate input flag is required to distinguish an A sample

from a B sample in the interleaved data stream. This flag can either be the single event rising edge of

TXENABLE or the continuous toggling MSB of the port inactive data port. For the TXENABLE flag option, set the

CONFIG23 aflag_sel bit and the A sample will be expected to be aligned with the rising edge of TXENABLE. For

the toggling MSB option, clear the CONFIG23 aflag_sel bit and the A sample will be expected for each ‘1’ of the

MSB with the B sample is flagged for each ‘0’ of the MSB. Refer to Figure 37.

CLK1

Single event rising edge

flags “A” sample if

aflag_sel = ‘1’

TXENABLE

Toggling MSB

flags “A” sample if

aflag_sel = ‘0’

DB15

DA[15:0]

A₀

B₀

A₁

B₁

A_N

B_N

Figure 37. INTERLEAVED BUS MODE on DA[15:0] port (Dual Clock Mode)

HALF RATE BUS MODE

In HALF RATE BUS MODE, the user inputs data on both DA[15:0] and DB[15:0] ports at half rate and input logic

merges both data streams into one DAC channel (A). This mode is selected by setting CONFIG1

insel_mode[15:0] = ‘11’. Refer to Figure 38.

CLK1

DA[15:0]

DB[15:0]

A₂

A₀

A_N

A₄

A₆

A₁

A_N+1

A₅

A₃

A₇

Figure 38. HALF RATE BUS MODE (Dual Clock Mode)

36

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

CLK2 and CLK2C Inputs

Figure 39 shows an equivalent circuit for the DAC input clock (CLK2/C).

CLKVDD

333 W

CLK2

2 KW

Note: Input common mode level is

approximately 2/3 * CLKVDD or 1.2 V.

CLK2C

666 W

GND

Figure 39. CLK2/C Equivalent Input Circuit

Figure 40 shows the preferred configuration for driving the CLK2/CLK2C input clock with a differential ECL/PECL

source.

0.1 mF

CLK 2

+

Differential

ECL

C

AC

100 W

or (LV)PECL

Source

-

CLK2C

0.1 mF

150 W

R

T

150 W

Figure 40. Preferred Clock Input Configuration With a Differential ECL/PECL Clock Source

Submit Documentation Feedback

37

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

CLKO_CLK1 and LOCK_CLK1C Pins

Figure 41 shows the functionality of the CLKO_CLK1 and LOCK_CLK1C pins. Refer to Table 5. The controls for

these pins are found in the CONFIG2 register and are used in selection of device clocking mode. In single-ended

mode (CONFIG2 diffclk_ena = ‘0’) refer to Figure 43, both CLKO_CLK1 and LOCK_CLK1C pins have an

internal pull-down resistor approximately equivalent to 100kΩ.

clk1_in_ena

clko_SE_hold

EN

Internal CLKO

0

Internal CLK1

Internal LOCK

CLKO _CLK1

1

EN

LOCK _CLK1C

EN

clk1c_in_ena

diffclk_ena

Figure 41. CLKO_CLK1 and LOCK_CLK1C pins bi-directional control

In differential mode (CONFIG2 diffclk_ena = ‘1’) the CLKO_CLK1 and LOCK_CLK1C input pins are configured

as a differential CLK1/C clock input. Refer Figure 39 for the equivalent circuit.

IOVDD

10 KW

CLKO _CLK1

10 KW

IOVDD

Note: Input common mode level is

approximately 0.5* IOVDD or 1.65 V.

GND

10 KW

LOCK _CLK1C

GND

Figure 42. CLKO_CLK1 and LOCK_CLK1C Differential Input Mode Equivalent Circuit

38

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

CMOS DIGITAL INPUTS

Figure 43 shows a schematic of the equivalent CMOS digital inputs of the DAC5688. SDIO, SCLK, SYNC,

TXENABLE, DA[15:0] and DB[15:0] have pull-down resistors while RESETB and SDENB have pull-up resistors

internal the DAC5688. See specification table for logic thresholds. The pull-up and pull-down circuitry is

approximately equivalent to 100kΩ.

The input switches levels for all CMOS digital inputs can be changed from 3.3V input levels to 1.8V input levers

by programming the CONFIG26 io_1p8_3p3 register bit. If io_1p8_3p3 is cleared, the input thresholds are set

for 3.3V CMOS levels. If io_1p8_3p3 is set, the input thresholds are set for 1.8V levels.

IOVDD

SCLK

SYNC

400 W

TXENABLE

DA[15:0]

Internal

RESETB

SDENB

digital in

400 W

DB[15:0]

CLKO _CLK 1**

** As an input

GND

Figure 43. CMOS/TTL Digital Equivalent Input

REFERENCE OPERATION

The DAC5688 uses a bandgap reference and control amplifier for biasing the full-scale output current. The

full-scale output current is set by applying an external resistor R_BIASto pin BIASJ. The bias current I_BIASthrough

resistor R_BIASis defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale

output current equals 16 times this bias current and can thus be expressed as:

IOUT_FS= 16 × I_BIAS= 16 × V_EXTIO/ R_BIAS

Each DAC has a 4-bit independent coarse gain control via coarse_daca(3:0) and coarse_dacb (3:0) in the

CONFIG27 register. Using gain control, the IOUT_FScan be expressed as:

IOUTA_FS= (DACA_gain + 1) × I_BIAS= (DACA_gain + 1) × V_EXTIO/ R_BIAS

IOUTB_FS= (DACB_gain + 1) × I_BIAS= (DACB_gain + 1) × V_EXTIO/ R_BIAS

where V_EXTIOis the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of

1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor

C_EXTof 0.1 mF should be connected externally to terminal EXTIO for compensation. The bandgap reference can

additionally be used for external reference operation. In that case, an external buffer with high impedance input

should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can

be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor C_EXTmay hence

be omitted. Terminal EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor R_BIASor changing the

externally applied reference voltage. The internal control amplifier has a wide input range, supporting the

full-scale output current range of 20 dB.

DAC TRANSFER FUNCTION

The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output

current up to 20 mA. Differential current switches direct the current to either one of the complementary output

nodes IOUT1 or IOUT2. (DACA = IOUTA1 or IOUTA2 and DACB = IOUTB1 or IOUTB2.) Complementary output

currents enable differential operation, thus canceling out common mode noise sources (digital feed-through,

on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a

factor of two.

Submit Documentation Feedback

39

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage

reference source (+1.2 V) and control amplifier. Current I_BIASthrough resistor R_BIASis mirrored internally to

provide a maximum full-scale output current equal to 16 times I_BIAS

.

The relation between IOUT1 and IOUT2 can be expressed as:

IOUT1 = – IOUT_FS– IOUT2

We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the

output stage is a current sink the current can only flow from AVDD into the IOUT1 and IOUT2 pins. The output

current flow in each pin driving a resistive load can be expressed as:

IOUT1 = IOUT_FS× (65536 – CODE) / 65536

IOUT2 = IOUT_FS× CODE / 65536

where CODE is the decimal representation of the DAC data input word.

For the case where IOUT1 and IOUT2 drive resistor loads R_Ldirectly, this translates into single ended voltages

at IOUT1 and IOUT2:

VOUT1 = AVDD – | IOUT1 | × R_L

VOUT2 = AVDD – | IOUT2 | × R_L

Assuming that the data is full scale (65536 in offset binary notation) and the R_Lis 25 Ω, the differential voltage

between pins IOUT1 and IOUT2 can be expressed as:

VOUT1 = AVDD – | –0mA | × 25 Ω = 3.3 V

VOUT2 = AVDD – | –20mA | × 25 Ω = 2.8 V

VDIFF = VOUT1 – VOUT2 = 0.5V

Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would

lead to increased signal distortion.

DAC OUTPUT SINC RESPONSE

Due to sampled nature of a high-speed DAC’s, the well known sin(x)/x (or SINC) response can significantly

attenuate higher frequency output signals. Refer to Figure 44 which shows the unitized SINC attenuation roll-off

with respect to the final DAC sample rate in 4 Nyquist zones. For example, if the final DAC sample rate F_S= 1.0

GSPS, then a tone at 440MHz will be attenuated by 3.0dB. Although the SINC response can create challenges

in frequency planning, one side benefit is the natural attenuation of Nyquist images. The increased over-sampling

ratio of the input data provided by the DAC5688’s 2x, 4x and 8x digital interpolation modes improve the SINC

roll-off (droop) within the original signal’s band of interest.

Figure 44. Unitized DAC sin(x)/x (SINC) Response

40

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

ANALOG CURRENT OUTPUTS

Figure 45 shows a simplified schematic of the current source array output with corresponding switches.

Differential switches direct the current of each individual NMOS current source to either the positive output node

IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of

the current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance of 5

pF.

The external output resistors are referred to an external ground. The minimum output compliance at nodes

IOUT1 and IOUT2 is limited to AVDD – 0.5 V, determined by the CMOS process. Beyond this value, transistor

breakdown may occur resulting in reduced reliability of the DAC5688 device. The maximum output compliance

voltage at nodes IOUT1 and IOUT2 equals AVDD + 0.5 V. Exceeding the minimum output compliance voltage

adversely affects distortion performance and integral non-linearity. The optimum distortion performance for a

single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not

exceed 0.5 V.

AVDD

R

LOAD

IOUT1

S(1)

IOUT2

S(2)

S(N)

S(2)C

S(N)C

S(1)C

...

Figure 45. Equivalent Analog Current Output

The DAC5688 can be easily configured to drive a doubly terminated 50Ω cable using a properly selected RF

transformer. Figure 46 and Figure 47 show the 50Ω doubly terminated transformer configuration with 1:1 and 4:1

impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be

connected to AVDD to enable a cd current flow. Applying a 20mA full-scale output current would lead to a 0.5

V_PPfor a 1:1 transformer and a 1 V_PPoutput for a 4:1 transformer. The low dc-impedance between IOUT1 or

IOUT2 and the transformer center tap sets the center of the ac-signal at AVDD, so the 1 V_PPoutput for the 4:1

transformer results in an output between AVDD + 0.5 V and AVDD – 0.5 V.

Submit Documentation Feedback

41

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

AVDD (3.3 V)

50 W

1:1

IOUT1

IOUT 2

R

LOAD

100 W

50 W

AVDD (3.3 V)

Figure 46. Driving a Doubly Terminated 50Ω Cable Using a 1:1 Impedance Ratio Transformer

AVDD (3.3 V)

100 W

4:1

IOUT 1

R

LOAD

50 W

IOUT 2

100 W

AVDD (3.3 V)

Figure 47. Driving a Doubly Terminated 50Ω Cable Using a 4:1 Impedance Ratio Transformer

PASSIVE INTERFACE TO ANALOG QUADRATURE MODULATORS

A common application in communication systems is to interface the DAC to an IQ modulator like the TRF3703

family of modulators from Texas Instruments. The input of the modulator is generally of high impedance and

requires a specific common-mode voltage. A simple resistive network can be used to maintain 50Ω load

impedance for the DAC5688 and also provide the necessary common-mode voltages for both the DAC and the

modulator.

42

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

V_in~ Varies

V_out~ 2.8 to 3.8 V

I1

I2

IOUTA1

IOUTA2

S

Q1

Q2

RF

IOUTB1

IOUTB2

Quadrature modulator

Figure 48. DAC to Analog Quadrature Modulator Interface

The DAC5688 has a maximum 20mA full-scale output and a voltage compliance range of AVDD ± 0.5 V. The

TRF3703 IQ modulator family can be operated at three common-mode voltages: 1.5V, 1.7V, and 3.3V.

Figure 49 shows the recommended passive network to interface the DAC5688 to the TRF3703-17 which has a

common mode voltage of 1.7V. The network generates the 3.3V common mode required by the DAC output and

1.7V at the modulator input, while still maintaining 50Ω load for the DAC.

V1

R1

I

R2

R3

DAC5688

TRF3703-17

V2

R2

/I

R1

V1

Figure 49. DAC5688 to TRF3703-17 Interface

If V1 is set to 5V and V2 is set to -5V, the corresponding resistor values are R1 = 57Ω, R2 = 80Ω, and R3 =

336Ω. The loss developed through R2 is about -1.86 dB. In the case where there is no –5V supply available and

V2 is set to 0V, the resistor values are R1 = 66Ω, R2 = 101Ω, and R3 = 107Ω. The loss with these values is

–5.76dB.

Figure 50 shows the recommended network for interfacing with the TRF3703-33 which requires a common mode

of 3.3V. This is the simplest interface as there is no voltage shift. Because there is no voltage shift there is any

loss in the network. With V1 = 5V and V2 = 0V, the resistor values are R1 = 66Ω and R3 = 208Ω.

Submit Documentation Feedback

43

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

V1

R1

I

R3

DAC5688

TRF3703-33

V2

/I

R1

V1

Figure 50. DAC5688 to TRF3703-33 Interface

In most applications a baseband filter is required between the DAC and the modulator to eliminate the DAC

images. This filter can be placed after the common-mode biasing network. For the DAC to modulator network

shown in Figure 51, R2 and the filter load R4 need to be considered into the DAC impedance. The filter has to be

designed for the source impedance created by the resistor combination of R3 // (R2+R1). The effective

impedance seen by the DAC is affected by the filter termination resistor resulting in R1 // (R2+R3 // (R4/2)).

V1

R1

R2

I

R3

R4

V2

R2

Filter

TRF3703

DAC5688

R3

/I

R1

V1

Figure 51. DAC5688 to Modulator Interface with Filter

Factoring in R4 into the DAC load, a typical interface to the TRF3703-17 with V1 = 5V and V2 = 0V results in the

following values: R1 = 72Ω, R2 = 116Ω, R3 = 124Ω and R4 = 150Ω. This implies that the filter needs to be

designed for 75Ω input and output impedance (single-ended impedance). The common mode levels for the DAC

and modulator are maintained at 3.3V and 1.7V and the DAC load is 50Ω. The added load of the filter

termination causes the signal to be attenuated by –10.8 dB.

A filter can be implemented in a similar manner to interface with the TRF3703-33. In this case it is much simpler

to balance the loads and common mode voltages due to the absence of R2. An added benefit is that there is no

loss in this network. With V1 = 5V and V2 = 0V the network can be designed such that R1 = 115Ω, R3 = 681Ω,

and R4 = 200Ω. This results in a filter impedance of R1 // R2=100Ω, and a DAC load of R1 // R3 // (R4/2) which

is equal to 50Ω. R4 is a differential resistor and does not affect the common mode level created by R1 and R3.

The common-mode voltage is set at 3.3 V for a full-scale current of 20mA.

For more information on how to interface the DAC5688 to an analog quadrature modulator please refer to the

application reports Passive Terminations for Current Output DACs (SLAA399) and Design of Differential Filters

for High-Speed Signal Chains (SLWA053).

44

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

RECOMMENDED STARTUP SEQUENCE

The following startup sequence is recommend to initialization the DAC5688:

1. Supply all 1.8V (CLKVDD, DVDD, VFUSE) and 3.3V (AVDD and IOVDD) voltages.

2. Toggle RESETB pin for a minimum 25 nSec active low pulse width.

3. Provide a stable CLK2/C input clock.

4. Program all desired SIF registers.

5. Provide a sync signal to all digital blocks. The sync input source may be either TXENABLE pin, SYNC pin or

a software sync via CONFIG5 sif_sync_sig bit; however, only the TXENABLE or SYNC pins are

recommended for multi-DAC synchronization. Refer to CONFIG5, CONFIG22 and CONFIG23 registers for

sync source selection. Note: Registers CONFIG6 through CONFIG13 all require a sync input to transfer the

contents of the control register inputs to the active digital blocks.

6. Provide data flow.

MULTI-DAC SYNCHRONIZATION

If the system has two or more DACs requiring synchronization, the sync signal in Step 5 of the RECOMMENDED

STARTUP SEQUENCE must be provided to all the DACs simultaneously. The sync input source must be either

the TXENABLE pin or the SYNC pin (the software sync is not recommended).

In some applications such as beamforming it is required that the multiple DACs in the system have constant

latency thus resulting in phase aligned outputs. As a result of the clock domain transfer on the DAC5688 FIFO,

the outputs of all DACs can only be synchronized to within ±1 DAC clock cycle in the External and Dual Clock

modes. In order to guarantee exact phase alignment between all devices it is required to set up the device in

Dual Synchronous Clock mode.

DESIGNING THE PLL LOOP FILTER

To minimize phase noise given for a given f_DACand M/N, the values of PLL_gain and PLL_range are selected

so that G_VCOis minimized and within the MIN and MAX frequency for a given setting.

The external loop filter components C1, C2, and R1 are set by the G_VCO, M/N, the loop phase margin f_dand the

loop bandwidth w_d. Except for applications where abrupt clock frequency changes require a fast PLL lock time, it

is suggested that f_dbe set to at least 80 degrees for stable locking and suppression of the phase noise side

lobes. Phase margins of 60 degrees or less can be sensitive to board layout and decoupling details.

See Figure 52 for the recommend external loop filter topology. C1, C2, and R1 are calculated by the following

equations

t3²

t1(t3 * t2)

t2

t3

t1 * t2

t3

ǒ Ǔ

C1 + t1 1 *

C2 +

R1 +

(5)

where

t1 +

K K

tan f ) sec f

^vcoǒ

_dǓ

d

1

tan f ) sec f

t2 +

t3 +

w²_d

d

w

d

ǒ

_dǓ

w tan f ) sec f

d

(6)

charge pump current: I_qp= 1 mA

vco gain: K_VCO= 2p × G_VCOrad/V

PFD Frequency: w_d≤ 160 MHz

phase detector gain: K_d= I_qp÷ (2 × p × M) A/rad

Submit Documentation Feedback

45

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

An Excel spreadsheet is provided by Texas Instruments for automatically calculating the values for C1, R1 and

C2.

DAC5688 PLL

LPF

Pin64

R 1

PLL

External

Loop

Filter

C 2

C 1

Figure 52. Recommended External Loop Filter Topology

46

Submit Documentation Feedback

Product Folder Link(s): DAC5688

DAC5688

www.ti.com

SLLS880B –DECEMBER 2007–REVISED MAY 2010

REVISION HISTORY

NOTE: Page numbers of previous versions may differ from current version.

Changes from Revision A (March 2008) to Revision B

Page

•

Changed Dual-Channel to first of title ................................................................................................................................... 1

Changed sin(x)/x from upper case to lower case ................................................................................................................. 1

Added sentence to DESCRIPTION section.."The DAC5688....multiplying PLL." ................................................................. 1

Changed to join last column 2 bottom rows as one .............................................................................................................. 1

Deleted "and External" from description of pin 25 ................................................................................................................ 3

Added sentence to description of pin 1 ................................................................................................................................ 3

Added sentence to description of pin 10,39,50,63 ............................................................................................................... 3

Added text to description of TXENABLE, pin 6 .................................................................................................................... 3

Deleted part of condition - Measured differential....to AVDD ................................................................................................ 5

Changed min value from 1.71 to 1.7, max value from 2.15 to 1.9 ....................................................................................... 5

Deleted min value -0.2 and max value 0.2, and added typ value of +/-0.2 .......................................................................... 5

Deleted "PLL = off" from 7 rows of Digital Latency description ............................................................................................ 6

Changed test conditions "NCO off" to "NCO on"; last row of Digital Latency, 2 places ....................................................... 6

Changed test conditions "NCO off" to "NCO" on next to last row of Digital Latency; and "QMC off" to "QMC on" ............. 6

Deleted min value -40 and max value 40 and added +/-20 to typ value in IIH row ............................................................. 7

Deleted min value -40 and max value 40 and added +/-20 to typ value in IIL row .............................................................. 7

Deleted 0.22xIOVDD from max value and added 0.5 in row of VOL ................................................................................... 7

Added 2 notes to EC digital specifications table .................................................................................................................. 7

Changed sentence in Offset Error: under TEST METHODOLOGY ................................................................................... 14

Added new register map table under REGISTER DESCRIPTIONS section ...................................................................... 15

Changed text in Register STATUS0 ................................................................................................................................... 16

Changed Bit 0 of Register CONFIG2 from 0 to 1 ............................................................................................................... 17

Changed text of Register CONFIG3 description ................................................................................................................ 17

Changed text of Register CONFIG4 description ................................................................................................................ 17

Deleted "Reserved" explanation from Register CONFIG5 description. .............................................................................. 18

Changed phaseoffset(15:0) to phaseoffset(15:8) in Register CONFIG7 description ......................................................... 18

Changed "Phaseadd(31:0)" to "phaseadd(31:24)" in Register CONFIG11 description ..................................................... 19

Deleted explanatory "Note" from Register CONFG14 description ..................................................................................... 20

Added text to Register CONFIG20 description. .................................................................................................................. 21

Added text to Register CONFIG21 description. .................................................................................................................. 21

Changed "Default 0x00" to "Default 0x15" for Register CONFIG23 Address .................................................................... 22

Changed text in Register CONFIG23 description ............................................................................................................... 22

Changed Register CONFIG28 description from "Reserved(7:0)" to "cleared" ................................................................... 23

Deleted "cleared" in description for Register CONFG28 .................................................................................................... 23

Deleted explanatory NOTE from Register CONFIG30 description. .................................................................................... 24

Added sentence to 1st paragraph of section "SERIAL INTERFACE" description. ............................................................. 25

Changed graphic entity for Figure 22, Magnitude Spectrum for FIR1 ................................................................................ 28

Changed text in section "Full Complex Mixer (FMIX)." ....................................................................................................... 31

Changed Q_OUTequation in Full Complex Mixer (FMIX) section. ........................................................................................ 31

Changed description for section "Quadrature Modulator Correction (QMC)." .................................................................... 32

Changed description for section "DAC Offset Control." ...................................................................................................... 32

Changed text in section "DUAL SYNCHRONOUS CLOCK MODE." ................................................................................. 33

Submit Documentation Feedback

47

Product Folder Link(s): DAC5688

DAC5688

SLLS880B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

•

Added text in section "DUAL CLOCK MODE." ................................................................................................................... 33

Changed Figure 36 , Figure 37, Figure 38, caption from "......(PLL Clock Mode)" to "......(Dual Clock Mode)" ................. 35

Changed graphic entity for Figure 40 ................................................................................................................................. 37

Added section "PASSIVE INTERFACE TO ANALOG QUADRATURE MODULATORS." ................................................. 42

Changed text in section "RECOMMENDED STARTUP SEQUENCE " ............................................................................. 45

48

Submit Documentation Feedback

Product Folder Link(s): DAC5688

PACKAGE OPTION ADDENDUM

www.ti.com

22-Apr-2010

PACKAGING INFORMATION

Orderable Device

DAC5688IRGC25

DAC5688IRGCR

DAC5688IRGCRG4

DAC5688IRGCT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

VQFN

RGC

64

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

VQFN

RGC

2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

DAC5688IRGCTG4

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Apr-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC5688IRGCR

DAC5688IRGCT

VQFN

RGC

64

2000

250

330.0

16.4

9.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Apr-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC5688IRGCR

DAC5688IRGCT

VQFN

RGC

64

2000

250

333.2

345.9

28.6

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

Automotive

www.ti.com/automotive

www.ti.com/communications

Communications and

Telecom

DSP

dsp.ti.com

Computers and

Peripherals

www.ti.com/computers

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

Consumer Electronics

Energy

www.ti.com/consumer-apps

www.ti.com/energy

Logic

Industrial

www.ti.com/industrial

Power Mgmt

Microcontrollers

RFID

power.ti.com

Medical

www.ti.com/medical

microcontroller.ti.com

www.ti-rfid.com

Security

www.ti.com/security

Space, Avionics &

Defense

www.ti.com/space-avionics-defense

RF/IF and ZigBee® Solutions www.ti.com/lprf

Video and Imaging

Wireless

www.ti.com/video

www.ti.com/wireless-apps

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DAC5688_14
厂家：	TEXAS INSTRUMENTS
描述：	DUAL-CHANNEL, 16-BIT, 800 MSPS, 2xâ8x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)
文件：	总55页 (文件大小：1371K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC5688_14 [TI]

相关型号：

DAC5689

DAC5689IRGCR

DAC5689IRGCT

DAC56P

DAC56U

DAC56U/1K

DAC56U/1K

DAC600

DAC60004

DAC60004IDMDR

DAC60004IDMDT

DAC60004IPW