DAC56U/1K [BB]
D/A Converter, 1 Func, Serial Input Loading, 1.5us Settling Time, PDSO16, SOIC-16;
| 型号： | DAC56U/1K |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 1.5us Settling Time, PDSO16, SOIC-16 光电二极管 转换器 |
| 文件： | 总6页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC56
49
FPO
®
DAC56
DAC56
Monolithic 16-Bit Resolution
DIGITAL-TO-ANALOG CONVERTER
APPLICATIONS
FEATURES
● PROCESS CONTROL
● COMPLETE D/A CONVERTER:
Internal Voltage Reference
● ATE PIN ELECTRONICS LEVEL SETTING
● CLOSED-LOOP SERVO-CONTROL
±3V Output Operational Amplifier
Pinout Allows IOUT (±1.0mA) Option
No external components required
● AUTO-CALIBRATION CIRCUIT FOR A/D
BOARDS
● 0.012% LINEARITY ERROR MAX
● UP-GRADE REPLACEMENT FOR
● 12-BIT MONOTONICITY GUARANTEED
OVER 0°C TO +70°C
MULTIPLYING D/A
● X-Y PLOTTER
● ±5V TO ±12V POWER SUPPLY
● DSP PROCESSOR BOARDS
● SETTLING TIME: VOUT = 1.5µs;
IOUT = 350ns
● SERIAL DATA INPUT: Binary Two’s
Complement
● 16-PIN PLASTIC DIP AND SOIC
DESCRIPTION
The DAC56 is a complete 16-bit monolithic D/A
converter. Completely self-contained with a stable,
low noise, internal zener voltage reference; high-speed
current switches; a resistor ladder network; and a low
noise output operational amplifier all on a single
monolithic chip. The DAC56 operates over a wide
power supply range from ±5V to ±12V.
A high-speed interface is capable of clocking in data
at a rate of 10MHz max, and its interface logic con-
tains a serial data clock (input), serial data (input) and
latch-enable (input). Serial data is clocked MSB first
into a 16-bit register and then latched into a 16-bit
parallel register.
The DAC56 is packaged in a 16-pin plastic DIP and
16-pin SOIC.
Differential linearity error (DLE) is guaranteed to
meet specifications without external adjustment. How-
ever, provisions for an externally adjustable circuit
controlling the MSB error, the differential linearity
error at bipolar zero, makes the DLE at BPZ essen-
tially zero and provides for high system performance.
The I/V amplifier stage includes an output current
limiting circuit to protect both amplifier and load from
excessive current. This assures the user of high system
reliability.
RF
16-Bit
IOUT DAC
Reference
Output
16-Bit Input Latch
16-Bit Serial-to-Parallel Conversion
Clock LE Data
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
®
PDS-1231A
DAC56
SBAS031
SPECIFICATIONS
ELECTRICAL
All specifications at +25°C, and power supply voltage of ±5V, unless otherwise noted.
DAC56
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
DIGITAL INPUT
Resolution
Digital Input Level: (1) VIH
VIL
16
Bits
V
V
µA
µA
MHz
+2.4
0
+VL
+0.8
+1
I
I
IH • VI = +2.7V
IL • VI = +0.4V
–50
Input Clock Frequency
10
ACCURACY
Integral Linearity Error
Differential Linearity Error
Gain Error
Bipolar Zero Error
Monotonicity
±0.012
±0.024
±1.5
±0.5
12
% of FSR(3)
% of FSR
% of FSR
% of FSR
Bits
0°C to +70°C
0°C to +70°C
TEMPERATURE DRIFT
Gain Drift
Bipolar Zero Drift
Linearity Drift
±60
±20
ppm of FSR/°C
ppm of FSR/°C
% of FSR
±0.012
±0.024
Differential Linearity Drift
% of FSR
POWER SUPPLY SENSITIVITY
Gain
Bipolar Zero
±VS = ±VL = ±5VDC
to ±0.006% of FSR
±0.0045
±0.0015
% of FSR/%V
% of FSR/%V
SETTLING TIME
Voltage Output
6V Step
1.5
1
µs
µs
1LSB
Current Output
1mA Step
10 to 100Ω Load
1kΩ Load(3)
350
350
ns
ns
Slew Rate
12
V/µs
ANALOG OUTPUT
Voltage Output Configuration
Bipolar Range
±2.66
±8
±3.0
±3.34
V
mA
Ω
Output Current
Output Impedance
Short Circuit Duration
Current Output Configuration
Bipolar Range
0.1
Indefinite to Common
±1
mA
Output Impedance
1.2
kΩ
WARMUP TIME
1
min
POWER SUPPLY REQUIREMENTS(4)
Supply Voltage
+VS and +VL
–VS and –VL
+4.75
–4.75
+5.00
–5.00
+13.2
–13.2
V
V
Supply Drain (No Load)
+V (+VS and +VL = +5V)
–V (–VS and –VL = –5V)
+V (+VS and +VL = +12V)
–V (–VS and –VL = –12V)
Power Dissipation
+10
–25
+12
–27
+17
–35
mA
mA
mA
mA
V
V
S and VL = ±5V
S and VL = ±12V
175
468
260
mW
mW
TEMPERATURE RANGE
Specification
Storage
0
–60
70
100
°C
°C
NOTES: (1) Logic input levels are TTL-/CMOS-compatible. (2) FSR means full-scale range and is equivalent to 6V (±3V) for DAC56 in the VOUT mode. (3) Measured
with an active clamp to provide a low impedance for approximately 200ns. (4) All specifications assume +VS connected to +VL and –VS connected to –VL. If supplies
are connected separately, –VL must not be more negative than –VS to assure proper operation. No similar restriction applies to the value of +VL with respect to +VS.
®
2
DAC56
PIN CONFIGURATION
–5V
–VS
+VL
+VS
+5V
1µF
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
LCOM
16-Bit
DAC Latch
1µF
TRIM
16-Bit
IOUT
DAC
+5V
1µF
16-Bit Serial
to Parallel
Conversion
MSB ADJ
IOUT
NC
CLK
LE
ACOM
SJ
Control
Logic and
Level
Shifting
Circuit
RF
Data
–VL
Analog
Output
–5V
1µF
VOUT
NOTES:
= Analog Common
(±3.0V)
= Logic Common
ABSOLUTE MAXIMUM RATINGS
PIN ASSIGNMENTS
DC Supply Voltage ....................................................................... ±15VDC
Input Logic Voltage........................................................... –1V to +VS/+VL
Power Dissipation .......................................................................... 850mW
Operating Temperature ................................................... –25°C to +70°C
Storage Temperature..................................................... –80°C to +100°C
Lead Temperature (soldering, 10s) ............................................... +300°C
PIN
NAME
FUNCTION
1
2
3
4
5
–VS
LCOM
+VL
NC
CLK
Analog Negative Supply
Logic Common
Logic Positive Supply
No Connection
Clock Input
6
7
8
9
10
11
12
13
14
15
16
LE
DATA
–VL
VOUT
RF
SJ
ACOM
IOUT
MSB ADJ
TRIM
+VS
Latch Enable Input
Serial Data Input
Logic Negative Supply
Voltage Output
Feedback Resistor
Summing Junction
Analog Common
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
Current Output
MSB Adjustment Terminal
MSB Trim-pot Terminal
Analog Positive Supply
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT
PACKAGE
NUMBER(1)
DAC56P
DAC56U
16-Pin Plastic DIP
16-Pin SOIC
180
211
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
DAC56
POWER SUPPLY CONNECTIONS
OPERATING INSTRUCTIONS
Power supply decoupling capacitors should be added as
shown in the Connection Diagram (Figure 2), for optimum
performance and noise rejection.
The accuracy of a D/A converter is described by the transfer
function as shown in Figure 1. Digital input to analog output
converter relationships are shown in Table I. The errors in
the D/A converter are combinations of analog errors due to
the linear circuitry, matching and tracking properties of the
ladder and scaling networks, power supply rejection, and
reference errors. In summary, these errors consist of initial
errors including gain, offset, linearity, differential linearity,
and power supply sensitivity. Gain drift over temperature
rotates the line (Figure 1) about the bipolar zero point and
offset drift shifts the line left or right over the operating
temperature range. Most of the offset and gain drift is due to
the drift of the internal reference zener diode with tempera-
ture or time.
These capacitors (1µF tantalum recommended) should be
connected as close as possible to the converter.
–5V
1µF
–VS
LCOM
+VS
+5V
1µF
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16-Bit
DAC Latch
TRIM
16-Bit
IOUT
DAC
+5V
1µF
+VL
16-Bit Serial
to Parallel
Conversion
MSB ADJ
IOUT
NC
CLK
LE
ACOM
Control
Logic and
Level
Shifting
Circuit
The converter is designed so that these drifts are in opposite
directions. This way the bipolar zero voltage is virtually
unaffected by variations in the reference voltage.
SJ
RF
Data
–VL
Analog
Output
–5V
1µF
VOUT
(±3.0V)
(+FSR/2) –1LSB
Gain
NOTES:
Drift
All Bits
On
= Analog Common
= Logic Common
FIGURE 2. Connection Diagram.
MSB ERROR ADJUSTMENT (OPTIONAL)
Offset
Bipolar
Drift
Zero
Differential linearity error at all codes of the DAC56 is
guaranteed to meet specifications without an external adjust-
ment. However, if adjustment of the differential linearity
error at bipolar zero is desired, it can be trimmed essentially
to zero using the circuit as shown in Figure 3.
–FSR/2
1000...0000
Digital Output
0111...1111
* See Table I for digital code definitions.
470kΩ
100kΩ(1)
200kΩ
FIGURE 1. Input vs Output for an Ideal Bipolar D/A
Converter.
Trim 15
1 –VS
MSB Adjust 14
NOTE: (1) 10-15 turns.
DIGITAL INPUT
ANALOG OUTPUT
Binary Two’s
Complement (BTC)
Voltage (V),
VOUT Mode
Current (mA),
IOUT Mode
FIGURE 3. MSB Adjustment Circuit.
DAC Output
7FFFH
8000H
0000H
FFFFH
+ Full Scale
– Full Scale
Bipolar Zero
Zero –1LSB
+2.999908
–3.000000
0.000000
–0.999970
+1.000000
0.000000
After allowing ample warm-up time (5 to 10 minutes) to
assure stable operation, select the input code FFFFH. Mea-
sure the output voltage using a 6-1/2 digit voltmeter and
record the measurement. Change the digital input code to
0000H. Adjust the 100kΩ potentiometer (TCR of 100ppm
per °C or less is recommended) to make the output voltage
read 1LSB more than the voltage reading of the previous
code (ex. 1LSB = 92µV at FSR = 6V).
–0.000092
+0.030500µA
TABLE I. Digital Input to Analog Output Relationship.
DIGITAL INPUT CODES
The DAC56 accepts serial input data (MSB first) in Binary
Two’s Complement form—Refer to Table I for input/output
relationships.
If the MSB adjustment circuit is not used, pins 14 and 15
should be left open.
®
4
DAC56
(1)
CLK
DATA
LE
MSB
1
LSB
16
(2)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
MSB
(3)
(4)
NOTES: (1) If clock is stopped between input of 16-bit data words, latch enable (LE) must remain low until after the first clock of the next 16-bit data
word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch
enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going
negative.
FIGURE 4. Input Timing Diagram.
INPUT TIMING CONSIDERATIONS
> 40ns
Figures 4 and 5 refer to the input timing required to interface
the inputs of DAC56 to a serial input data stream. Serial data
DATA
CLK
LSB
MSB
is accepted in Binary Two’s Complement with the MSB being
loaded first. Data is clocked in on positive going clock (CLK,
pin 5) edges and is latched into the DAC input register on
negative going latch enable (LE, pin 6) edges.
>15ns >15ns
The latch enable input must be high for at least one clock cycle
before going low, and then must be held low for at least one
clock cycle. The last 16 data bits clocked into the serial input
register are those that are transferred to the DAC input register
when latch enable goes low. In other words, when more than
16 clock cycles occur between a latch enable, only the data
present during the last 16 clocks will be transferred to the
DAC input register.
> 40ns
> 100ns
> 5ns
> 40ns
> 15ns
LE
> One Clock Cycle
> One Clock Cycle
Figure 4 gives the general input format required for the
DAC56. Figure 5 shows the specific relationships between the
various signals and their timing constraints.
FIGURE 5. Input Timing Relationships.
®
5
DAC56
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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