DAC60004IPWR [TI]
具有 1LSB INL/DNL 的超小型、真正 12 位四路电压输出 DAC | PW | 14 | -40 to 125;
| 型号： | DAC60004IPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1LSB INL/DNL 的超小型、真正 12 位四路电压输出 DAC | PW | 14 | -40 to 125 光电二极管 转换器 |
| 文件： | 总43页 (文件大小：2371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
DACx0004 四通道 16 位、14 位、12 位 1LSB INL 缓冲电压输出数模转换
器
1 特性
3 说明
1
•
真正的 16 位性能：1 LSB 积分非线性 (INL)/微分
DAC80004/70004/60004 (DACx0004) 分别为 16 位、
14 位和 12 位高精度、低功耗、电压输出、四通道数
模转换器 (DAC)。DACx0004 器件通过设计可保证单
调性，拥有低于 1 LSB（最大值）的出色线性度。
DAC 的基准输入在内部通过专用基准缓冲器进行缓
冲。
非线性 (DNL)（最大值）
超低毛刺脉冲能量：1nV-s
宽电源电压范围：2.7V 至 5.5V
支持轨到轨运行的输出缓冲器
电流消耗：1mA/通道
•
•
•
•
•
50Mhz、四线制或三线制串行外设接口 (SPI) 兼容
接口
DACx0004 器件配有上电复位电路，用于确保 DAC 输
出在零量程或量程中点处上电（具体取决于 POR 引脚
的状态）并保持该状态直到器件中写入有效编码为止。
这些器件的电流消耗非常低（1mA/通道），是便携
式、电池供电类设备的理想选择。这些器件还包含一种
掉电特性。该特性可将 5V 电压下的流耗降至 3µA（典
型值）。
•
•
•
•
用于回读和菊花链连接的 SDO 引脚
上电复位至零量程或量程中点
温度范围：-40°C 至 +125°C
多种封装：
–
微型 14 引脚超薄小外形尺寸无引线 (VSON) 封
装
–
14 引脚薄型小外形尺寸 (TSSOP) 封装
DACx0004 器件使用一个运行时钟速率高达 50MHz 的
通用三线制串口。DACx0004 器件还包含一个 SDO 引
脚，该引脚能够以菊花链形式连接多个器件。此接口与
标准 SPI™， QSPI™、Microwire 以及数字信号处理
器 (DSP) 接口兼容。DACx0004 器件采用易于装配的
14 引脚 TSSOP 封装或超小型 14 引脚 VSON 封装，
在 -40°C 至 +125°C 的扩展工业级温度范围内完全额
定运行.
2 应用
•
•
便携式仪表
可编程逻辑控制器 (PLC) 模拟输出模块(4mA-
20mA)
•
•
闭环伺服器控制
数据采集系统
器件信息(1)
器件型号
DACx0004
DACx0004
封装
VSON (14)
TSSOP (14)
封装尺寸（标称值）
3.00mm x 4.00mm
5.00mm x 4.40mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
DACx0004 框图
线性误差与数字输入编码间的关系
VDD
REFIN
1.00
0.75
0.50
0.25
0.00
-0.25
REF
BUF
SCLK
SDIN
DAC
Buffer
DAC
Register
DAC
BUF
VOUT
A
SYNC
SDO
CLR
LDAC
POR
Channel A
Channel B
Channel C
Channel D
VOUT
VOUT
VOUT
B
C
D
-0.50
-0.75
-1.00
Channel A
Channel B
Channel C
Channel D
tower 5own [ogic
ꢀesisꢁive beꢁwork
tower hn ꢀeseꢁ
DACx0004
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
GND
D001
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASED6
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
目录
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 20
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 DACx0004 Timing Requirements ............................. 8
7.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
9
9.2 Typical Application - Digitally Controlled Asymmetric
Bipolar Output .......................................................... 26
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 器件和文档支持 ..................................................... 30
12.1 接收文档更新通知 ................................................. 30
12.2 相关链接................................................................ 30
12.3 社区资源................................................................ 30
12.4 商标....................................................................... 30
12.5 静电放电警告......................................................... 30
12.6 Glossary................................................................ 30
13 机械、封装和可订购信息....................................... 31
8
4 修订历史记录
Changes from Revision C (August 2016) to Revision D
Page
•
•
Changed 2.4 µs From MAX to MIN value for t20 in the DACx0004 Timing Requirements table............................................ 8
Changed From: t19 To: t20 in Figure 1 .................................................................................................................................... 8
Changes from Revision B (June 2016) to Revision C
Page
•
Deleted thermal pad from PW-TSSOP pin configuration ....................................................................................................... 3
Changes from Revision A (June 2016) to Revision B
Page
•
已添加 将 DAC80004IPW 器件标识附录添加到了机械、封装和可订购信息 ........................................................................ 31
Changes from Original (April 2016) to Revision A
Page
•
已更改 产品预览至量产数据 ................................................................................................................................................... 1
2
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
5 Device Comparison Table
DEVICE
RESOLUTION
DAC80004
DAC70004
DAC60004
16
14
12
6 Pin Configuration and Functions
14-Pin VSON
DMD Package
Top View
14-Pin TSSOP
PW Package
Top View
LDAC
SYNC
VDD
1
2
3
4
5
6
7
14
13
12
11
10
9
SCLK
SDIN
GND
LDAC
SYNC
VDD
1
2
3
4
5
6
7
14
13
12
11
10
9
SCLK
SDIN
GND
V
A
V
V
B
D
OUT
OUT
OUT
Thermal
Pad
V
A
V
V
B
D
OUT
OUT
OUT
V
C
OUT
POR
REFIN
V
C
OUT
POR
REFIN
CLR
SDO
CLR
SDO
8
8
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
CLR
NUMBER
9
12
1
Digital Input
Power
Clear DAC pin, falling edge sensitive
Ground
GND
LDAC
Digital Input
Load DAC pin, active low
Power-on-reset configuration, Connecting the POR pin to GND powers up all four DACs
to zero scale. Connecting this pin to VDD powers up all four DACs to midscale.
POR
6
Digital Input
REFIN
SCLK
SDIN
SDO
7
14
13
8
Analog Input
Digital Input
Digital Input
Digital Output
Digital Input
Power
Voltage reference input for all channels
Serial interface shift clock
Serial interface digital input
Serial interface digital output for readback and daisy chaining
Serial interface synchronization, active low
Positive power supply (2.7 V to 5.5 V)
DAC A output
SYNC
VDD
2
3
VOUT
VOUT
VOUT
VOUT
A
B
C
D
4
Analog Output
Analog Output
Analog Output
Analog Output
11
5
DAC B output
DAC C output
10
DAC D output
Copyright © 2016–2017, Texas Instruments Incorporated
3
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–10
MAX
UNIT
Voltage, VDD to GND
7
V
Voltage, digital input or output to GND
Voltage, analog input (REFIN) or output (VOUTx) to GND
Input current to any pin except supply pins
Maximum junction temperature
VDD + 0.3
VDD + 0.3
10
V
V
mA
°C
°C
150
Storage temperature range, Tstg
-60
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
2.2
2.2
-40
NOM
MAX
5.5
UNIT
V
Voltage, VDD to GND
2.7 V ≤ VDD ≤ 4.5 V
4.5 V ≤ VDD ≤ 5.5 V
VDD – 0.2
VDD
V
Voltage, analog input (REFIN) or output
(VOUTx) to GND
V
Ambient Operating Temperature, TA
125
°C
7.4 Thermal Information
DACx0004
THERMAL METRIC(1)
DMD (VSON)
PW (TSSOP)
14 PINS
99.1
UNIT
14 PINS
39.6
27.3
9.0
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
23.4
42.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
0.9
ψJB
8.9
42.0
RθJC(bot)
6.5
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
7.5 Electrical Characteristics
All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN(1) ≤ VDD, Rload = 5 kΩ to
GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE(2)
DAC80004
16
14
12
Resolution
DAC70004
DAC60004
Bits
INL
Relative accuracy(3)
Differential nonlinearity(3)
±1
±1
1.5
2
LSB
LSB
DNL
Ensured monotonic
TA = +20°C to +40°C
TA = –40°C to +125°C
TUE
Total unadjusted error(3)
Zero code error
mV
TA = –40°C to +125°C, Code 0d into
DAC
±0.2
±2
ZCE
mV
TA = +25°C, Code 0d into DAC
TA = –40°C to +125°C
TA = +20°C to +40°C
TA = –40°C to +125°C
TA = +25°C
±0.1
±5
ZCE-TC Zero code error TC
µV/°C
±1.2
±1.8
OE
Offset error(3)
±0.2
±0.2
±4
mV
OE-TC
Offset error drift
TA = –40°C to +125°C
µV/°C
%FSR
TA = +20°C to +40°C, Code 65535d
into DAC
±0.05
±0.07
FSE
Full-scale error(4)
TA = –40°C to +125°C, Code
65535d into DAC
±0.01
±0.01
±2
%FSR
TA = +25°C
TA = –40°C to +125°C
ppm
FSR/°C
FSE-TC Full-scale error drift(4)
TA = –40°C to +125°C
TA = +25°C
±0.005
±0.005
±2
±0.05
GE
Gain error(3)
%FSR
TA = –40°C to +125°C
ppm
FSR/°C
GE-TC
Gain drift
TA = +25°C, Vout = ¾ of full scale,
1900 hr
Output voltage drift vs.Time
20
ppm FSR
dB
Load Regulation
DC Power supply rejection ratio(4)
TA = +25°C, Vout =Mid Scale
TA = +25°C, Vout = full scale
0.003%
–92
PSRR
(1) 200 mV headroom is required between REFIN and VDD when 2.7 V ≤ VDD ≤ 4.5 V.
(2) Output unloaded
(3) End point fit between codes Code 512 to Code 65,024 - DAC80004, Code 128 to Code 16,256 - DAC70004, Code 32 to Code 4064 -
DAC60004, Output unloaded.
(4) With 100 mV headroom between DAC output and VDD.
Copyright © 2016–2017, Texas Instruments Incorporated
5
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN(1) ≤ VDD, Rload = 5 kΩ to
GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
¼ to ¾ scale and ¾ to ¼ scale
settling to ±1 LSB, RL = 5 kΩ, Cload
= 200 pF to GND
Output voltage settling time
5.8
8
µs
Slew rate
Power-up time(5)
1.5
100
8
V/µs
µs
Power-on glitch energy
Supply slew rate <5 V/msec
mV
DAC in power down mode (1 kΩ-
GND), Supply slew rate <5 V/msec
Power-off glitch energy
Output noise
7
mV
0.1 Hz to 10 Hz
100 kHz BW
5
100
60
µVpp
µVRMS
Measured at 1 kHz
Measured at 10 kHz
Output noise density
nV/√Hz
55
REFIN = 3 V ± 0.2 Vpp, Frequency =
10 kHz, DAC at mid scale, specified
by design
THD
Total harmonic distortion
–80
dB
200 mV 50 Hz and 60 Hz sine wave
superimposed on power supply
voltage (AC analysis)
PSRR
AC power supply rejection ratio
Code change glitch impulse
-90
1
dB
1 LSB change around major carry,
Software LDAC mode
nV-s
nV-s
Channel-to-channel AC (analog)
crosstalk
Full-scale swing on adjacent
channel, Hardware LDAC mode
1
1
Full-scale swing on adjacent
channels, Measured channel at zero
scale
Channel-to-channel DC crosstalk
Digital crosstalk
LSB
Full-scale swing on all channel,
Measured channel at zero scale
1
DAC code mid scale, Adjacent input
buffer change from 0000h to FFFFh
or vice versa
0.2
nV-S
REFIN = 3 V ± 0.86 Vpp, Frequency
= 100 Hz to 100 kHz, DAC at zero
scale
Reference feedthrough
Digital feedthrough
–85
0.2
dB
At SCLK = 1 MHz, DAC output static
at mid scale
nV-s
OUTPUT CHARACTERISTICS
Voltage range
0
VDD
V
V
Output loaded 5 kΩ, DAC code
FFFFh
0.1
10
Headroom
Output loaded 0.5 kΩ, DAC code
FFFFh
%FSR
RL
CL
Resistive load
Capacitive load
0.5
kΩ
RL = ∞
1
2
nF
RL = 5 kΩ
Normal mode
0.5
100
1
Ω
RO
DC output impedance
Short circuit current
Power down with 100 kΩ network
Power down with 1 kΩ network
kΩ
kΩ
mA
36
(5) Time to exit power-down mode into normal mode. Measured from 32nd falling edge SCLK to 90% of DAC final value, Characterized at
mid scale.
6
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
Electrical Characteristics (continued)
All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN(1) ≤ VDD, Rload = 5 kΩ to
GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE INPUT
2.7 V ≤ VDD ≤ 4.5 V
2.2
2.2
VDD – 0.2
VDD
Reference input range
V
4.5 V ≤ VDD ≤ 5.5 V
Reference input current
450
µA
kΩ
Reference input impedance
Reference input capacitance
15
10
pF
MBW
Multiplying bandwidth
340
kHz
DIGITAL INPUTS
VIH
VIL
High-level input voltage
2.3
V
V
Low-level input voltage
Input leakage
0.7
±1
0 < VDIGITAL INPUT < VDD
µA
pF
Pin capacitance
4
7
DIGITAL OUTPUTS
VOH
VOL
High-level output voltage
IOH = 2 mA
IOL = 2 mA
VDD – 1
V
V
Low-level output voltage
Pin capacitance
0.7
pF
POWER SUPPLY REQUIREMENTS
VDD
Supply voltage
Supply current
2.7
5.5
5.5
V
TA = –40°C to +125°C, Normal
mode
4
3
mA
IVDD
TA = –40°C to +125°C, Power-down
mode
7
µA
TA = –40°C to +125°C, Normal
mode
Power dissipation
20
mW
TEMPERATURE RANGE
TA
Specified performance
–40
125
°C
Copyright © 2016–2017, Texas Instruments Incorporated
7
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
7.6 DACx0004 Timing Requirements
At TA = -40°C to +125°C, Trise = Tfall = 1 nV/sec (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2, SDO pin
loaded with 10 pF
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD ≤ 4.5 V
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
SERIAL WRITE and READ
tc
SCLK cycle time
20
10
10
15
5
40
20
20
30
10
10
10
35
20
30
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw1
tw2
tsu
tsu1
th1
td1
tw3
td2
tw4
td3
tw5
td4
tv
SCLK high pulse duration
SCLK low pulse duration
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
5
SCLK falling edge to SYNC rising edge delay time
Minimum SYNC high pulse duration(1)
SYNC rising edge to SCLK fall ignore delay time
LDAC pulse duration low
5
25
15
20
10
10
10
SCLK falling edge to LDAC rising edge delay time
CLR minimum pulse duration low
SCLK falling edge to LDAC falling edge delay time
SCLK rising edge to SDO valid time
SCLK falling edge to SYNC rising edge delay time
SYNC rising edge to SCLK rising edge delay time
18
18
td5
td6
5
5
10
10
SYNC rising edge to LDAC or CLR falling edge
delay time
td7
20
40
ns
t19
t20
CLR pulse activation time
Successive DAC Update
20
20
ns
µs
2.4
2.4
(1) Does not include output settling tiime
td2
tc
SCLK
1
2
32
tw3
tw2
tw1
td1
tsu
SYNC
SDIN
th1
t20
tsu1
DB31
DB0
td3
LDAC2
LDAC1
CLR
tw4
td4
tw5
t19
VOUTX
(1) Asynchronous LDAC update
(2) Synchronous LDAC update
Figure 1. Stand-Alone Timing
8
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
td6
SCLK
1
2
32
33
34
64
td5
SYNC
SDIN
Input Word for DAC-N
Input Word for DAC-N-1
DB0
DB31
DB0
DB31
DB31
Input Word for DAC-N
X
DB0
td7
SDO
tv
LDAC1
CLR
td7
(1) Asynchronous LDAC update
Figure 2. Daisy-Chain Timing
Copyright © 2016–2017, Texas Instruments Incorporated
9
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
7.7 Typical Characteristics
At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC outputs unloaded, unless otherwise noted.
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
Channel A
Channel B
Channel C
Channel D
Channel A
Channel B
Channel C
Channel D
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
D001
D001
Figure 3. Linearity Error vs Digital Input Code
Figure 4. Differential Linearity Error vs Digital Input Code
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
Channel A
Channel B
Channel C
Channel D
Channel A
Channel B
Channel C
Channel D
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
D001
D001
DAC load 5 kΩ//200 pF
DAC load 5 kΩ//200 pF
Figure 5. Linearity Error vs Digital Input Code
Figure 6. Differential Linearity Error vs Digital Input Code
2.0
1.5
2.0
1.5
1.0
0.5
0.0
-0.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-1.0
-1.5
-2.0
Channel A
Channel B
Channel C
Channel D
Channel A
Channel B
Channel C
Channel D
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
D001
D001
DAC load 5 kΩ//200 pF
Figure 8. Total Unadjusted Error vs Digital Input Code
Figure 7. Total Unadjusted Error vs Digital Input Code
10
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC outputs unloaded, unless otherwise noted.
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
Ch-A DNL Max
Ch-B DNL Max
Ch-C DNL Max
Ch-D DNL Max
Ch-A DNL Min
Ch-B DNL Min
Ch-C DNL Min
Ch-D DNL Min
Ch-A Max
Ch-B Max
Ch-C Max
Ch-D Max
Ch-A Min
Ch-B Min
Ch-C Min
Ch-D Min
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D001
D001
DAC load 5 kΩ//200 pF
Figure 9. Linearity Error (Max-Min) vs Temperature
DAC load 5 kΩ//200 pF
Figure 10. Differential Linearity Error (Max-Min) vs
Temperature
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
1.8
1.5
1.2
0.9
0.6
0.3
0.0
-0.3
-0.6
-0.9
-1.2
-1.5
-1.8
Ch-A TUE Max
Ch-B TUE Max
Ch-C TUE Max
Ch-D TUE Max
Ch-A TUE Min
Ch-B TUE Min
Ch-C TUE Min
Ch-D TUE Min
Channel A (5 kW//200 pF)
Channel B (5 kW//200 pF)
Channel C (5 kW//200 pF)
Channel D (5 kW//200 pF)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D001
D001
DAC load 5 kΩ//200 pF
Figure 11. Total Unadjusted Error Max/Min vs Temperature
Figure 12. Offset Error vs Temperature
0.05
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
0.04
0.03
0.02
0.01
0.00
-0.01
-0.02
Channel A (5 kW//200 pF)
Channel B (5 kW//200 pF)
Channel C (5 kW//200 pF)
Channel D (5 kW//200 pF)
Channel A (no load)
Channel B (no load)
Channel C (no load)
Channel D (no load)
Channel A (5 kW//200 pF)
Channel B (5 kW//200 pF)
Channel C (5 kW//200 pF)
Channel D (5 kW//200 pF)
Channel A (no load)
-0.03
-0.04
-0.05
Channel B (no load)
Channel C (no load)
Channel D (no load)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D001
D001
Figure 13. Gain Error vs Temperature
Figure 14. Full Scale Error vs Temperature
Copyright © 2016–2017, Texas Instruments Incorporated
11
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
At TA = 25°C, VDD = 2.7 V, REFIN = 2.5 V, DAC outputs unloaded, unless otherwise noted.
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
Channel A
Channel B
Channel C
Channel D
Channel A
Channel B
Channel C
Channel D
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
D001
D001
Figure 15. Linearity Error vs Digital Input Code
Figure 16. Differential Linearity Error vs Digital Input Code
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
Channel A
Channel B
Channel C
Channel D
Channel A
Channel B
Channel C
Channel D
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
D001
D001
DAC load 5 kΩ//200 pF
DAC load 5 kΩ//200 pF
Figure 17. Linearity Error vs Digital Input Code
Figure 18. Differential Linearity Error vs Digital Input Code
2.0
1.5
2.0
1.5
1.0
0.5
0.0
-0.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-1.0
-1.5
-2.0
Channel A
Channel B
Channel C
Channel D
Channel A
Channel B
Channel C
Channel D
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
D001
D001
DAC load 5 kΩ//200 pF
Figure 20. Total Unadjusted Error vs Digital Input Code
Figure 19. Total Unadjusted Error vs Digital Input Code
12
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
Typical Characteristics (continued)
At TA = 25°C, VDD = 2.7 V, REFIN = 2.5 V, DAC output unloaded, unless otherwise noted.
0.05
0.04
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
-0.04
-0.05
1.8
1.5
Channel A (5 kW//200 pF)
Channel B (5 kW//200 pF)
Channel C (5 kW//200 pF)
Channel D (5 kW//200 pF)
Channel A (no load)
Channel B (no load)
Channel C (no load)
Channel D (no load)
1.2
0.9
0.6
0.3
0.0
-0.3
-0.6
-0.9
-1.2
-1.5
-1.8
Channel A (5 kW//200 pF)
Channel B (5 kW//200 pF)
Channel C (5 kW//200 pF)
Channel D (5 kW//200 pF)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D001
D001
Figure 21. Offset Error vs Temperature
Figure 22. Gain Error vs Temperature
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
Channel A (5 kW//200 pF)
Channel B (5 kW//200 pF)
Channel C (5 kW//200 pF)
Channel D (5 kW//200 pF)
Channel A (no load)
Ch-A Max
Ch-B Max
Ch-C Max
Ch-D Max
Ch-A Min
Ch-B Min
Ch-C Min
Ch-D Min
Channel B (no load)
Channel C (no load)
Channel D (no load)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
D001
D001
DAC load 5 kΩ//200 pF
Figure 23. Full Scale Error vs Temperature
Figure 24. Linearity Error (Max-Min) vs Power Supply
Voltage
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
1.8
1.5
1.2
0.9
0.6
0.3
0.0
-0.3
-0.6
-0.9
-1.2
-1.5
-1.8
Ch-A DNL Max
Ch-B DNL Max
Ch-C DNL Max
Ch-D DNL Max
Ch-A DNL Min
Ch-B DNL Min
Ch-C DNL Min
Ch-D DNL Min
Channel A (5 kW//200 pF)
Channel B (5 kW//200 pF)
Channel C (5 kW//200 pF)
Channel D (5 kW//200 pF)
2.7
3.1
3.5
3.9
4.3
4.7
5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
VDD (V)
D001
D001
DAC load 5 kΩ//200 pF
Figure 25. Differential Linearity Error (Max-Min) vs Power
Supply Voltage
Figure 26. Offset Error vs Power Supply Voltage
Copyright © 2016–2017, Texas Instruments Incorporated
13
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, REFIN = 2.5 V, DAC output load = 5 kΩ||200 pF, unless otherwise noted.
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
Channel A (5 kW//200 pF)
Channel B (5 kW//200 pF)
Channel C (5 kW//200 pF)
Channel D (5 kW//200 pF)
Channel A (5 kW//200 pF)
Channel B (5 kW//200 pF)
Channel C (5 kW//200 pF)
Channel D (5 kW//200 pF)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
VDD (V)
D001
D001
Figure 27. Gain Error vs Power Supply Voltage
Figure 28. Full Scale Error vs Power Supply Voltage
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
Ch-A DNL Max
Ch-B DNL Max
Ch-C DNL Max
Ch-D DNL Max
Ch-A DNL Min
Ch-B DNL Min
Ch-C DNL Min
Ch-D DNL Min
Ch-A Max
Ch-B Max
Ch-C Max
Ch-D Max
Ch-A Min
Ch-B Min
Ch-C Min
Ch-D Min
2.5
2.9
3.3
3.7
4.1
4.5
4.9
5.3
2.5
2.9
3.3
3.7
4.1
4.5
4.9
5.3
REFIN (V)
REFIN (V)
D001
D001
Figure 29. Linearity Error (Max-Min) vs Reference Voltage
Figure 30. Differential Linearity Error (Max-Min) vs
Reference Voltage
0.05
0.04
0.03
0.02
0.01
0.00
-0.01
0.07
0.05
0.03
0.01
-0.01
-0.03
-0.05
-0.07
-0.02
Ch-A GE Max
Ch-B GE Max
Ch-C GE Max
Ch-D GE Max
5.0 5.5
Ch-A FSE Max
Ch-B FSE Max
Ch-C FSE Max
Ch-D FSE Max
-0.03
-0.04
-0.05
2.0
2.5
3.0
3.5
4.0
4.5
2
2.5
3
3.5
4
4.5
5
5.5
REFIN (V)
REFIN (V)
D001
D001
Figure 31. Gain Error (Max) vs Reference Voltage
Figure 32. Full Scale Error (Max) vs Reference Voltage
14
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC outputs unloaded, All channels active, unless otherwise noted.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
D001
D001
VDD = 2.7 V, REFIN = 2.5 V
Figure 33. Power Supply Current vs Digital Input Code
Figure 34. Power Supply Current vs Digital Input Code
5.5
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.5
Unit #1
1.0
0.5
0.0
Unit #2
Unit #3
Unit #4
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
D001
D001
DAC code = mid-scale code
REFIN = 2.5 V, DAC code = mid-scale code
Figure 35. Power Supply Current vs Temperature
Figure 36. Power Supply Current vs Power Supply Voltage
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.7
2.4
2.1
DAC Code - Full Scale
1.8
DAC Code - Full Scale
1.5
1.2
0.9
Ch-A
Ch-B
Ch-C
Ch-D
Ch-A
0.6
0.3
0.0
DAC Code - Zero Scale
DAC Code - Zero Scale
Ch-B
Ch-C
Ch-D
-20 -16 -12
-8
-4
0
4
8
12
16
20
-20 -16 -12
-8
-4
0
4
8
12
16
20
Load Current (mA)
Load Current (mA)
D001
D001
VDD = 2.7 V, REFIN = 2.5 V
Figure 37. DAC Output Voltage vs Load Current
Figure 38. DAC Output Voltage vs Load Current
Copyright © 2016–2017, Texas Instruments Incorporated
15
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC output load = 5 kΩ||200 pF, unless otherwise noted.
7
6
5
4
3
2
1
0
2.49960
2.49955
2.49950
2.49945
2.49940
2.49935
2.49930
2.49925
2.49920
Ch-A
Ch-B
Ch-C
Ch-D
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Power Supply Voltage (V)
Digital Input Pins Logic Level (V)
D001
D001
REFIN = 2.5 V, All channels active with full-scale code, DAC
unloaded
DAC unloaded, All channels to mid-scale
Figure 39. DAC Output Voltage vs Power Supply Voltage
Figure 40. Power Supply Current vs Digital Input Pins Logic
Level
0.020
5
0.020
5
0.015
0.010
0.005
0.000
-0.005
-0.010
-0.015
-0.020
0
0.015
0.010
0.005
0.000
-0.005
-0.010
-0.015
-0.020
0
LDAC Feedthrough
Glitch Impulse (1nV-sec)
LDAC Feedthrough
Glitch Impulse (1nV-sec)
-5
-5
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
-30
-35
VOUT (5 mV/div)
LDAC Trigger (5 V/div)
VOUT (5 mV/div)
LDAC Trigger (5 V/div)
0
1E-6
2E-6 3E-6
Time (0.5 msec/div)
4E-6
5E-6
0
1E-6
2E-6 3E-6
Time (0.5 msec/div)
4E-6
5E-6
D001
D001
DAC code transition from 8000h to 7FFFh
DAC code transition from 7FFFh to 8000h
Figure 41. Glitch Impulse, Falling Edge, 1LSB Step
Figure 42. Glitch Impulse, Rising Edge, 1LSB Step
[5!/ Trigger (5 V/div)
[5!/ Trigger (5 V/div)
Large Signal VOUT (2 V/div)
Small Signal VOUT
Large Signal VOUT (2 V/div)
Small Signal VOUT
Settling
Band
(±1 LSB)
(160 µV/div = 2 LSB)
(160 µV/div = 2 LSB)
Settling
Band
(±1 LSB)
Time (2 µsec/div)
Time (2 µsec/div)
From code 512d to 65024d, Typical channel shown
From code 65024d to 512d, Typical channel shown
Figure 43. Full-Scale Settling Time, Rising Edge
Figure 44. Full-Scale Settling Time, Falling Edge
16
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
Typical Characteristics (continued)
At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC output load = 5 kΩ||200 pF, unless otherwise noted.
Ch-A (20 mV/div)
Ch-B (20 mV/div)
Ch-C (20 mV/div)
Ch-D (20 mV/div)
Ch-A (1 mV/div)
Ch-B (1 mV/div)
Ch-C (1 mV/div)
Ch-D (1 mV/div)
VDD (5 V/div)
VDD (5 V/div)
Time (0.2 ms/div)
Time (2 ms/div)
D001
D001
DAC unloaded
DAC in power down mode (1 kΩ-GND)
Figure 45. Power-On Glitch, Reset to Zero Scale
Figure 46. Power-Off Glitch, Reset to Zero Scale
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
SCLK (5 V/div)
Clock Feedthrough Impulse
VOUT (2 mV/div)
Time (0.5 µsec/div)
10
100
1000
Frequency (Hz)
10000
100000
1000000
DAC unloaded, DAC code mid-scale, Typical channel shown
D001
VDD = 5.0 + 1 VPP (Sinusoid), REFIN = 2.5 V, DAC code full-
scale, Typical channel shown
Figure 47. Clock Feedthrough, 1MHz Midscale
Figure 48. DAC Output AC PSRR vs VDD
450.0
DAC Code = 32768
DAC Code = 512
DAC Code = 65024
400.0
350.0
300.0
250.0
200.0
150.0
100.0
50.0
= 4 µVPP
0.0
100
DAC unloaded, DAC code mid-scale, Typical channel shown
1000
10000
100000
Frequency (Hz)
D001
DAC unloaded, Typical channel shown
Figure 49. DAC Output Noise Density vs Frequency
Figure 50. DAC Output Noise, 0.1 Hz to 10 Hz
Copyright © 2016–2017, Texas Instruments Incorporated
17
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
8 Detailed Description
8.1 Overview
The DAC80004, DAC70004, and DAC60004 are quad-channel, 16-bit, voltage-output DACs with internal
reference buffers and output buffers. Each channel consists of an R-2R ladder configuration with the 4 MSBs
segmented, followed by an operational amplifier, as shown in Figure 51. The DACx0004 devices have a constant
impedance (30 kΩ typical), buffered reference input. The output of the reference buffers drives the R-2R ladders.
With the production trim process these devices have excellent dc accuracy and ac performance.
w
w
ëhÜÇ
.uffer
2w
2w
2w
2w
2w
2w
2w
{0
{11
{1
{12
{13
{15
w9CLb
.uffer
Figure 51. DACx0004 Architecture
The input coding to the DACx0004 is straight binary, so the ideal output voltage is given by Equation 1:
D
æ
IN ö
VOUT
=
x REFIN
ç
÷
2N
è
ø
(1)
Where:
N = resolution in bits; either 16 (DAC80004), 14 (DAC70004) or 12 (DAC60004)
DIN = decimal equivalent of the binary code that is loaded to the DAC register. DIN ranges from 0 to 2N –1
REFIN = DAC reference voltage
8.2 Functional Block Diagram
VDD
REFIN
REF
BUF
SCLK
SDIN
DAC
Buffer
DAC
Register
DAC
BUF
VOUTA
SYNC
SDO
CLR
LDAC
POR
Channel A
Channel B
Channel C
Channel D
VOUT
VOUT
VOUT
B
C
D
tower 5own [ogic
ꢀesisꢁive beꢁwork
tower hn ꢀeseꢁ
DACx0004
GND
Copyright © 2016, Texas Instruments Incorporated
18
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
8.3 Feature Description
8.3.1 Output Amplifier
The DACx0004 output buffer amplifier is capable of generating near rail-to-rail voltages on its output, giving a
maximum output range of 0 V to REFIN. It is capable of driving a load of 5 kΩ in parallel with 2 nF to GND. The
typical slew rate of this amplifier while driving no load is 1.5 V/µs, with a full-scale settling time of 8 µs to 1 LSB
of the final value as shown in Figure 43 and Figure 44. The current consumption of the amplifier (unloaded) is 1
mA/channel (typical). The DACx0004 output amplifier also implements a short circuit current limiting circuit. The
default value of short circuit limit is 40 mA, however this can be reduced to 30 mA using dedicated bits (1 per
channel) via SPI command 1010 (see Table 2).
8.3.2 Reference Buffer
The DACx0004 requires an external reference to operate. The reference input pin has the following input range:
2.2 V to (VDD – 0.2) for 2.7 V ≤ VDD ≤ 4.5 V
2.2 V to VDD for 4.5 V ≤ VDD ≤ 5.5 V
The DACx0004 contains a dedicated reference buffer for each DAC channel. The REFIN pin drives the input of
these buffers. The integrated reference buffers offers constant impedance of 30 kΩ (typical) at the REFIN pin.
This simplifies the external reference drive circuit for the device.
8.3.3 Power-On Reset
The DACx0004 contain a power-on-reset circuit that controls the output voltage during power up. The power-on
reset is useful in applications where it is important to know the state of the output of each DAC while the device
is in the process of powering up. At power up all DAC registers are filled with power-on reset code (see Table 1).
8.3.3.1 POR Pin Feature
The DAC power-on reset code for all of the channels depends on the state of the POR pin at power up (see Pin
Configuration and Functions).
Each DAC channel remains that way until a valid load command is written to it. All device registers are reset at
power up as shown in Table 1.
Table 1. DACx0004 Power-On Reset Values
DACx0004 - POWER-ON RESET VALUE
REGISTER NAME
TSSOP-/VSON-14
DAC latches (per channel)
DAC buffers (per channel)
Power down (per channel)
Clear mode
If POR pin = '0' then Zero Scale else Mid scale
If POR pin= '0' then Zero Scale else Mid scale
00 – Normal mode
00 – Clear to Zero
Ignore LDAC (per channel)
Daisy chain
0000 – Do not ignore
0 – Daisy chain disabled, DAC update at 32nd SCLK falling edge
0000 – all DACs 40 mA
Short circuit limit (per channel)
8.3.3.2 Internal Power-On Reset (IPOR) Levels
When the device powers up, an IPOR circuit sets the device in default mode as shown in Table 1. The IPOR
circuit requires specific VDD levels, as indicated in Figure 52, to ensure discharging of internal capacitors and to
reset the device on power up. In order to ensure a power-on reset, VDD must be below 0.7 V for at least 1 ms.
When VDD drops below 2.4 V but remains above 0.7 V (shown as the undefined region), the device may or may
not reset under all specified temperature and power supply conditions. In this case, In this case a power-down
reset is recommended. When VDD remains above 2.4 V, a power-on reset does not occur.
Copyright © 2016–2017, Texas Instruments Incorporated
19
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
VDD (V)
5.5 V
Specified Supply
Voltage Range
No Power-On Reset
2.7 V
2.4 V
Undefined
0.7 V
0.0 V
Power-On Reset
Figure 52. Relevant Voltage Levels for IPOR Circuit
8.4 Device Functional Modes
8.4.1 Serial Interface
The DACx0004 devices have a 4-wire serial interface: SYNC, SCLK, SDIN, and SDO (see Pin Configuration and
Functions). The serial interface (3-wire and 4-wire) is compatible with SPI, QSPI, and Microwire interface
standards, as well as most DSPs and it operates up to 50 MHz. See the Write Mode Stand-Alone Timing and
Write Mode Daisy-Chain Timing diagrams (see Figure 1 and Figure 2) for examples of typical write and read
sequences. The input shift register is 32 bits wide.
8.4.1.1 Stand-Alone Mode
The serial clock SCLK can be a continuous or a gated clock. The first falling edge of SYNC starts the operation
cycle. When SYNC is high, the SCLK and SDIN signals are blocked and the SDO pin (TSSOP-14 and VSON-14
packages) is in a Hi-Z state. The device internal registers are updated from the shift register on the 32nd falling
edge of SCLK.
8.4.1.1.1 SYNC Interrupt – Stand-Alone Mode
For stand-alone operation, the SYNC line stays low for at least 32 falling edges of SCLK and the addressed DAC
register updates on the 32nd SCLK falling edge. However, if SYNC is brought high before the 32nd SCLK falling
edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded.
Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs
(as shown in Figure 53).
SCLK
1
2
32
32
SYNC
SDIN
DB31
DB0
DB31
DB0
Invalid/Interrupted Write Sequence
Valid Write Sequence
Output/Mode Update on 32nd SCLK Falling Edge
Output/Mode Does Not Update on 32nd SCLK Falling Edge
Figure 53. SYNC Interrupt – Stand Alone Operation
20
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
Device Functional Modes (continued)
8.4.1.1.2 Read-Back Mode
The READ command is used to start read-back operation. However, before read-back operation can be initiated,
the SDO pin must be enabled by setting the DSDO bit to '1'; this bit is disabled by default. Read-back operation
is then started by executing a READ command (R/W bit = '1', see Table 3). Bits C3 to C0 select the register to
be read. The remaining data in the command are don’t care bits. During the next SPI operation, the data
appearing on the SDO output are from the previously addressed register. For a read of a single register, a NOP
(No Operation) command (1110) can be used to clock out the data from the selected register on SDO. Multiple
registers can be read if multiple READ commands are issued (see Figure 54).
SCLK
1
2
32
1
2
32
SYNC
SDIN
Read Command
X
NOP Command
Readback Data
DB31
DB0
DB31
DB31
DB0
DB0
SDO
t
v
Figure 54. Read-Back Operation
8.4.1.2 Daisy-Chain Mode
For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices
together (see Figure 55). Daisy-chain operation can be useful in system diagnostics and in reducing the number
of serial interface lines. The daisy-chain feature can be enabled by writing a logic '1' to the DSDO bit (see
Table 3); the SDO pin is set to HIZ when the DSDO bit is set to 0.
The first falling edge of SYNC starts the operating cycle. SCLK is continuously applied to the SPI shift register
when SYNC is low. If more than 32 clock pulses are applied, the data ripples out of the shift register and appear
on the SDO line. The data bits are clocked out on the rising edge of SCLK and are valid on the falling edge. By
connecting the SDO pin of the first device to the SDI input of the next device in the chain, a multiple-device
interface is constructed (see Figure 2). Each device in the system requires 32 clock pulses. Therefore, the total
number of clock cycles must equal 32 × N, where N is the total number of DACx0004s in the chain. When the
serial transfer to all devices is complete, SYNC is taken high. This action latches the data from the SPI shift
registers to the device internal registers for each device in the daisy-chain and prevents any further data from
being clocked in. The serial clock can be a continuous or a gated clock. Note that a continuous SCLK source can
only be used if SYNC is held low for the correct number of clock cycles. For gated clock mode, a burst clock
containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock in
order to latch the data.
C
B
A
DACx0004
DACx0004
DACx0004
SDIN
SDIN
SDIN
SDO
SDO
SDO
SCLK
SYNC
SCLK
SYNC
SCLK
SYNC
Figure 55. DACx0004 in Daisy Chain Mode
8.4.1.2.1 SYNC Interrupt – Daisy-Chain Mode
For daisy-chain operation, the SYNC line stays low for at least 32 × N SCLK cycles, where N is the number of
DACx0004s in the daisy chain. If SYNC is brought high before a multiple 32 SCLKs, it acts as an interrupt to the
write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer
contents, DAC register contents, nor a change in the operating mode occurs (see Figure 56).
Copyright © 2016–2017, Texas Instruments Incorporated
21
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
Device Functional Modes (continued)
SCLK
32XN
32XN
1
2
SYNC
SDIN
Invalid/Interrupted Write Sequence
Output/Mode Does Not Update on the Rising SYNC
Valid Write Sequence
Output/Mode Does Update on the Rising SYNC
Figure 56. SYNC Interrupt – Daisy-Chain Operation
8.4.2 SPI Shift Register
The SPI shift register is 32 bits wide, as shown in Table 2. The shift register command mapping is shown in
Table 3. The DACx0004 accepts DAC code in straight binary format. Note that, the DAC data is left alligned from
MSB (D19) to LSB (D4 - 16 bits, D6 - 14 bits, D8 - 12 bits).
Table 2. DACx0004 SPI Shift Register Format
D31
D30
D29
D28
D27-D24
D23-D20
D19-D04
D03-D00
Channel Address
Bits
16/14/12-Bit DAC Data left alligned/Power
Down Bits/Device Ready bit
Don't Cares
R/W
Command Bits
Mode Bits
Table 3. DAC Commands
D31 - D28
D27 - D24
D23 - D20
D19 - D16
D15 - D12
D11 - D08
D07 - D04
D03 - D00
Commands
Write to buffer n
Channel
Address
X
X
X
X
W/R
W
0
0
0
0
0
0
0
0
0
0
1
1
0
DAC Data
DAC Data
DAC Data
DAC Data
X
Channel
Address
1
0
1
X
X
X
X
X
X
X
Update DAC n
Channel
Address
Write to buffer n and update all
DACs (Software LDAC)
W
DAC Data
DAC Data
DAC Data
DAC Data
DAC Data
DAC Data
DAC Data
DAC Data
Channel
Address
Write to buffer and update DAC
n
W
X
X
X
X
W/R
W/R
W/R
W
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
PD1 PD0
Ch-D Ch-C Ch-B Ch-A Power up/down DAC n
CM1 CM0 Clear mode register
Ch-D Ch-C Ch-B Ch-A LDAC register
X
X
X
X
X
X
X
X
X
Software reset
Disable SDO register
Reserved
DSD
0
X
W/R
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
W/R
W
X
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Ch-D Ch-C Ch-B Ch-A Short circuit limit register
X
X
X
X
X
Software clear
Reserved
R
X
DRDY
Status register
No operation (NOP)
Reserved
W
X
X
X
Table 4. Channel Address Bits
CHANNEL ADDRESS BITS
DESCRIPTION
D23
0
D22
0
D21
0
D20
0
Select channel A
Select channel B
Select channel C
Select channel D
Select all channel
0
0
0
1
0
0
1
0
0
0
1
1
1
1
1
1
22
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
8.4.3 DAC Power-Down Modes
The DACx0004 use four modes of operation. These modes are accessed by setting command bits D28 – D24
and power-down register bits D09 and D08. The command bits must be set to 0100 (see Table 3). Once the
command bits are set correctly, the four different power-down modes are software programmable by setting bits
D09 and D08 in the shift register. Table 5 shows how to control the operating mode with data bits PD1 (D09),
PD0 (D08).
Table 5. Power-Down Bits
POWER DOWN BITS
DESCRIPTION
D09
0
D08
0
Normal operation/power up selected channel(s) (Default)
Power down selected channel(s) 1 kΩ-GND
Power down selected channel(s) 100 kΩ-GND
Power down selected channel(s) Hi-Z
0
1
1
0
1
1
It is possible to write to the DAC register/buffer of the DAC channel that is powered down. When the DAC
channel is then powered up, it powers up to this new value.
The advantage of the available power-down modes is that the output impedance of the device is known while it is
in power-down mode. As described in Table 5, there are three different power-down options. VOUTX can be
connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor, or open-circuited (Hi-Z). The DAC power-
down circuitry is shown in Figure 57.
R2R Ladder
Amplifier
VOUTX
Power-Down
Circuitry
Resistor
Network
Figure 57. DACx0004 Power Down
8.4.4 CLR Pin Functionality and Software CLEAR Mode
The CLR pin is an asynchronous input pin to the DAC. When activated, this falling edge sensitive pin clears the
DAC buffers and the DAC latches to zero, mid, full or user programmed code depending on the clear mode
register (see Table 6). The default setting for clear operation is clear to 0 V. The device exits clear mode on the
32nd falling edge of the next write to the device. If the CLR pin receives a falling edge signal during a write
sequence in normal operation, the clear mode is activated and changes the input and DAC registers
immediately. Additionally, all DAC registers can also be cleared via SPI command 1011. Note that the clear
mode bits determine the clear code for all the DACs upon clear operation.
8.4.4.1 DAC Clear Mode Registers
The DACx0004 implement four different clear modes. These modes are accessed by setting command bits
D28 – D24 and clear mode register bits D01 and D00. The command bits must be set to 0101 (see Table 3).
Based on the value of clear mode register (see Table 6), all of the DAC and the buffers are cleared to zero, mid,
or full-scale code, when the CLR pin sees a falling edge or after a software clear command is issued.
The user defined clear scale can be set by writing 16-/14-/12- data to 1001 to bits D28 – D24.
Copyright © 2016–2017, Texas Instruments Incorporated
23
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
Table 6. Clear Mode Bits
CLEAR MODE BITS
DESCRIPTION
D01
0
D00
0
All DACs clear to zero scale (default)
All DACs clear to mid scale
0
1
1
0
All DACs clear to full scale
8.4.5 LDAC Pin Functionality
The DACx0004 devices offer both a software and hardware simultaneous update and control function. The DAC
double-buffered architecture has been designed so that new data can be entered for each DAC without
disturbing the analog outputs. Data updates can be performed either in synchronous or in asynchronous mode.
In asynchronous mode, the LDAC pin is used as an active low signal for simultaneous DAC updates. Multiple
single-channel writes can be done in order to set different channel buffers to desired values and then pulse the
LDAC pin low to simultaneously update the DAC output registers. Data buffers of all channels must be loaded
with desired data before an LDAC low pulse. After a LDAC low pulse, all DACs are simultaneously updated with
the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the
corresponding DAC output remains unchanged after the LDAC pin is pulsed low.
In synchronous mode, data are updated with the falling edge of the 32nd SCLK cycle, which follows a falling
edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND
permanently or asserted and held low before sending commands to the device.
8.4.5.1 Software LDAC Mode Registers
Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The
LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be
updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 4-bit word
(D03 and D00) using command bits D28 – D24 (see Table 3). The default value for each bit, and therefore for
each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is
internally tied low for that particular DAC channel), and this DAC channel updates synchronously after the falling
edge of the 32nd SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the
LDAC pin.
See Table 7 for more information.
Table 7. LDAC Register
LDAC REGISTER BITS (D03 – D00)
DAC UPDATE
0
Determined by LDAC pin (Default)
DAC channel ignores LDAC pin, DAC updates on 32nd falling edge of SCLK, DAC channels
see LDAC as 0
1
8.4.6 Software Reset Mode
The DACx0004 implements a software reset feature. The software reset function uses command bits D28 – D24
(see Table 3). Table 1 shows the reset values for different registers.
24
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
8.4.7 Output Short Circuit Limit Register
The DACx0004 output amplifier has a default short circuit limit of 40 mA. However, this limit can be reduced to
30 mA by using command 1010 on bits D28 – D24 and selecting channel(s) (D03 – D00). Please note that
DACx0004 has a dedicated bit per channel, this allows the user to set different short circuit limit for different DAC
output channels.
Table 8. Short Circuit Limit Register
SHORT CIRCUIT LIMIT REGISTER BITS
DAC SHORT CIRCUIT LIMIT
(D03 – D00)
0
1
DAC output short circuit limit = 40 mA (Default)
DAC output short circuit limit = 30 mA
8.4.8 Status Register
The DACx0004 implements a read-only status register (see Table 3). This register can be read by using
command 1101 on bits D28 – D24, followed by a NOP command.
Logic ‘1’ on bit D04 indicates that the device is ready to be used. This feature is useful to check if the device is
ready to accept commands after power up.
Copyright © 2016–2017, Texas Instruments Incorporated
25
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application - Digitally Controlled Asymmetric Bipolar Output
RNEG
RFB
DACNEG
VOUT
DACx0004
VOUT
A
OPA277
RPOS
VOUT
+
B
DACPOS
RA
Figure 58. Asymmetric Bipolar Output Block Diagram
9.2.1 Design Requirements
This design requires two channels of the DACx0004 to generate a bipolar output. The design is very flexible and
allows for many different configurations. Typically, one channel is used to finely control the output, while the other
is used to offset the output. The direction of the offset depends on which channel is used as an offset. DACPOS
provides a positive offset and DACNEG has a negative offset.
9.2.2 Detailed Design Procedure
The output of each DAC can be modified via the digital interface and the gain of each output can be modified
independently by changing the external resistors. In order for the gain of each offset to be independent,
Equation 2 must be true.
æ
ç
è
ö-1
1
1
1
RA
=
+
-
÷
RFB RNEG RPOS ø
(2)
The output voltage range, VOUT, is adjusted according to Equation 3. Keep in mind that Equation 3 is only true
when Equation 2 is true.
RFB
RFB
VOUT = DACPOS
´
- DACNEG
´
RPOS
RNEG
(3)
=
Each DAC outputs a voltage from 0 to REFIN. As an example, if DACPOS gain is 1, DACNEG gain is 2 and RFB
2 kΩ, then RPOS = 2 kΩ, RNEG = 1 kΩ and RA = 1 kΩ. With the correct digital implementation it gives the output
an effective output range of ±15 V, with discrete 16-bit steps.
26
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
Typical Application - Digitally Controlled Asymmetric Bipolar Output (continued)
9.2.3 Application Curve
Figure 59 displays two different modes of operation. Mode 1 gains the output of DACNeg by a factor of 2 and
maintains DACPOS at unity gain. Mode 2 reverses the gains of each stage to invert the system. These are just
two examples of the types of outputs that can be achieved using this configuration.
15
Mode 1
Mode 2
10
5
0
-5
-10
512
11264
22016
32768
43520
54272
65024
Fine DAC Input Code
D001
Figure 59. Output Voltage vs Fine DAC Input Code
Copyright © 2016–2017, Texas Instruments Incorporated
27
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
10 Power Supply Recommendations
The DACx0004 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to
VDD should be well-regulated and have low-noise. Switching power supplies and DC-DC converters often have
high frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar
high frequency spikes. This noise can easily couple into the DAC output voltage through various paths between
the power connections and analog output. A 1 µF to 10 µF capacitor and 0.1 µF bypass capacitor is
recommended in order to further minimize noise from the power supply. The current consumption on the VDD
pin, the short-circuit current limit, and the load current for the device are listed in the Electrical Characteristics.
The power supply must meet the aforementioned current requirements.
28
Copyright © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
11 Layout
11.1 Layout Guidelines
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies. As a general rule it is important to keep digital traces as far away from analog traces when possible.
The DACx0004 is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital
signal processors. The more digital logic present in the design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at the output.
Due to the single ground pin of the DACx0004, all return currents, including digital and analog return currents for
the DAC, must flow through a single point. Ideally, GND must be connected directly to an analog ground plane.
This plane must be separate from the ground connection for the digital components until they were connected at
the power-entry point of the system.
As with the GND connection, VDD should be connected to a 5 V power-supply plane or trace that is separate
from the connection for digital logic until they are connected at the power-entry point. It is recommended to have
an additional 1 μF to 10 μF capacitor and 0.1 μF bypass capacitor. In some situations, additional bypassing may
be required, such as a 100 μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all
designed to essentially low-pass filter the 5 V supply, removing the high-frequency noise. In general it is always a
good idea to maintain the digital signals away from analog signals.
11.2 Layout Example
Figure 60. Layout Diagram
版权 © 2016–2017, Texas Instruments Incorporated
29
DAC80004, DAC70004, DAC60004
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
www.ti.com.cn
12 器件和文档支持
12.1 接收文档更新通知
如需接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 相关链接
下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的
快速链接。
表 9. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
DAC60004
DAC70004
DAC80004
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
30
版权 © 2016–2017, Texas Instruments Incorporated
DAC80004, DAC70004, DAC60004
www.ti.com.cn
ZHCSF34D –APRIL 2016–REVISED DECEMBER 2017
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
DAC80004IPW 器件标识附录：注意，DA80004 和 XDC84 均为 DAC80004IPW 可订购器件的有效器件标识
版权 © 2016–2017, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC60004IDMDR
DAC60004IDMDT
DAC60004IPW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
DMD
DMD
PW
14
14
14
14
14
14
14
14
14
14
14
14
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DA60004
250
90
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
DA60004
DA60004
DA60004
DA70004
DA70004
DA70004
DA70004
DA80004
DA80004
DA80004
DA80004
TSSOP
TSSOP
VSON
DAC60004IPWR
DAC70004IDMDR
DAC70004IDMDT
DAC70004IPW
PW
2000 RoHS & Green
3000 RoHS & Green
DMD
DMD
PW
VSON
250
90
RoHS & Green
RoHS & Green
TSSOP
TSSOP
VSON
DAC70004IPWR
DAC80004IDMDR
DAC80004IDMDT
DAC80004IPW
PW
2000 RoHS & Green
3000 RoHS & Green
DMD
DMD
PW
VSON
250
90
RoHS & Green
RoHS & Green
TSSOP
TSSOP
DAC80004IPWR
PW
2000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC60004IDMDR
DAC60004IDMDT
DAC60004IPWR
DAC70004IDMDR
DAC70004IDMDT
DAC70004IPWR
DAC80004IDMDR
DAC80004IDMDT
DAC80004IPWR
VSON
VSON
TSSOP
VSON
VSON
TSSOP
VSON
VSON
TSSOP
DMD
DMD
PW
14
14
14
14
14
14
14
14
14
3000
250
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
6.9
3.3
3.3
6.9
3.3
3.3
6.9
4.3
4.3
5.6
4.3
4.3
5.6
4.3
4.3
5.6
1.1
1.1
1.6
1.1
1.1
1.6
1.1
1.1
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
2000
3000
250
DMD
DMD
PW
2000
3000
250
DMD
DMD
PW
2000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC60004IDMDR
DAC60004IDMDT
DAC60004IPWR
DAC70004IDMDR
DAC70004IDMDT
DAC70004IPWR
DAC80004IDMDR
DAC80004IDMDT
DAC80004IPWR
VSON
VSON
TSSOP
VSON
VSON
TSSOP
VSON
VSON
TSSOP
DMD
DMD
PW
14
14
14
14
14
14
14
14
14
3000
250
367.0
213.0
356.0
367.0
213.0
356.0
367.0
213.0
356.0
367.0
191.0
356.0
367.0
191.0
356.0
367.0
191.0
356.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
35.0
35.0
2000
3000
250
DMD
DMD
PW
2000
3000
250
DMD
DMD
PW
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DAC60004IPW
DAC70004IPW
DAC80004IPW
PW
PW
PW
TSSOP
TSSOP
TSSOP
14
14
14
90
90
90
530
530
530
10.2
10.2
10.2
3600
3600
3600
3.5
3.5
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
DMD0014A
VSON - 1 mm max height
SCALE 3.500
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
4.1
3.9
0.55
0.35
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
(0.2) TYP
1.6
1.4
0.05
0.00
EXPOSED
THERMAL PAD
SEE TERMINAL
DETAIL
7
8
3.5
3.3
2X
3
1
14
12X 0.5
0.3
14X
0.2
0.55
0.35
PIN 1 ID
14X
0.1
C A
C
B
(OPTIONAL)
0.05
4221688/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DMD0014A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
14X (0.65)
14X (0.25)
SYMM
1
14
12X (0.5)
SYMM
(3.4)
(1.2)
TYP
8
7
(1) TYP
(2.75)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221688/A 09/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DMD0014A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.38)
SYMM
14X (0.65)
14X (0.25)
METAL
TYP
1
14
2X (1.47)
12X (0.5)
SYMM
(0.835)
8
7
(2.75)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4221688/A 09/2014
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明