DAC60501ZDQFT [TI]
采用 WSON 封装、具有精密内部基准电压的真正 12 位、单通道、SPI/I2C、电压输出 DAC | DQF | 8 | -40 to 125;
| 型号： | DAC60501ZDQFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 WSON 封装、具有精密内部基准电压的真正 12 位、单通道、SPI/I2C、电压输出 DAC | DQF | 8 | -40 to 125 光电二极管 转换器 |
| 文件： | 总53页 (文件大小：3152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
具有精密内部基准的 DACx0501 16/14/12 位 1LSB INL 电压输出 DAC
1 特性
3 说明
1
•
16 位性能：1LSB INL 和 DNL（最大值）
低毛刺脉冲能量：4nV-s
DAC80501、DAC70501 和 DAC60501 (DACx0501)
数模转换器 (DAC) 分别为 16 位、14 位和 12 位的高
精度、低功耗、电压输出器件。DACx0501 按设计要
求具有单调性，并可提供低于 1LSB 的线性度。这些
器件包括一个 2.5V、5ppm/˚C 内部基准，可提供
1.25V、2.5V 或 5V 的满量程输出电压范围。
DACx0501 采用了上电复位电路，可确保 DAC 输出以
零电平或中间电平上电，并在向器件写入有效代码之前
一直保持该电平。这类器件消耗 1mA 的低电流，并具
有断电功能，可在 5V 时将电流消耗降至 15µA（典型
值）。
•
•
•
•
•
•
宽电源电压范围：2.7V 至 5.5V
缓冲输出范围：5V、2.5V 或 1.25V
极低功耗：1mA (5.5V)
集成 5ppm/˚C（最大值）、2.5V 精密基准
引脚可选串行接口：
–
–
3 线制，兼容 SPI，高达 50MHz
两线制，兼容 I2C
•
•
•
•
上电复位：零电平或中间电平
VDD = 5.5V 时的 VIH 为 1.62V
温度范围：–40˚C 至 +125˚C
DACx0501 的数字接口可通过 SPI2C 引脚配置为 SPI
或 I2C 模式。在 SPI 模式下，DACx0501 使用一个在
高达 50MHz 的时钟频率下运行的通用 3 线制串行接
口。在 I2C 模式下，DACx0501 支持标准 (100kbps)、
快速 (400kbps) 和快速+ (1.0Mbps) 工作模式。
封装：小型 8 引脚 WSON 和 10 引脚 VSSOP
2 应用
•
•
•
•
•
•
•
•
示波器 (DSO)
半导体测试
DACx0501 采用易于组装的
数据采集 (DAQ)
10 引脚 VSSOP 封装和小型 2mm × 2mm、8 引脚
WSON 封装。这类器件的额定工业温度范围均为
–40°C 至 +125°C。
LCD 测试
小型蜂窝基站
模拟输出模块
器件信息(1)
过程分析（pH、气体、浓度、力和湿度）
直流电源、交流电源、电子负载
器件型号
DAC80501
DAC70501
DAC60501
封装
WSON (8)
VSSOP (10)
封装尺寸（标称值）
2.00mm × 2.00mm
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
功能方框图
使用 DACx0501 进行失调电压修整
VREFIO
VDD
Signal
Input
Internal
Reference
OPAMP
Serial
Interface
OPAMP
+
Signal
Output
DACx0501
VREFIO
+
SPI2C
DAC
Buffer
DAC
Register
BUF
VOUT
DAC
œ
SCLK or SCL
œ
SDIN or SDA
Bipolar
Output
or A0
SYNC
Power On Reset
Power Down Logic
Resistive Network
AGND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS794
DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
目录
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 23
8.5 Programming........................................................... 23
8.6 Register Map........................................................... 31
Application and Implementation ........................ 35
9.1 Application Information............................................ 35
9.2 Typical Application .................................................. 35
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements : SPI Mode............................. 9
7.7 Timing Requirements : I2C Standard Mode.............. 9
7.8 Timing Requirements : I2C Fast Mode...................... 9
7.9 Timing Requirements : I2C Fast-Mode Plus ........... 10
7.10 Typical Characteristics.......................................... 11
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ....................................... 20
9
10 Power Supply Recommendations ..................... 38
11 Layout................................................................... 38
11.1 Layout Guidelines ................................................. 38
11.2 Layout Example .................................................... 38
12 器件和文档支持 ..................................................... 39
12.1 文档支持 ............................................................... 39
12.2 相关链接................................................................ 39
12.3 接收文档更新通知 ................................................. 39
12.4 支持资源................................................................ 39
12.5 商标....................................................................... 39
12.6 静电放电警告......................................................... 39
12.7 Glossary................................................................ 39
13 机械、封装和可订购信息....................................... 39
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (November 2019) to Revision D
Page
•
•
已更改 Figure 29 to remove broken text from x axis (typo).................................................................................................. 15
已更改 Figures 33, 34 and 35; updated for clarity................................................................................................................ 16
Changes from Revision B (August 2019) to Revision C
Page
•
•
•
•
已更改 将采用 DGS (VSSOP) 封装的器件从“预发布”更改为“生产数据（正在供货）” ........................................................... 1
Added TUE parameter for DGS package to electrical characteristics table........................................................................... 5
Added gain error parameter for DGS package to electrical characteristics table .................................................................. 5
Added full-scale error parameter for DGS package to electrical characteristics table........................................................... 6
Changes from Revision A (August 2019) to Revision B
Page
•
已更改 将 DAC70501 和 DAC60501 器件从“预发布”更改为“生产数据（正在供货）” ............................................................ 1
Changes from Original (November 2018) to Revision A
Page
•
已更改 将采用 DQF (WSON) 封装的 DAC80501 从“预告信息（预发布）”更改为“生产数据（正在供货）”........................... 1
2
Copyright © 2018–2020, Texas Instruments Incorporated
DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
5 Device Comparison Table
DEVICE
RESOLUTION
REFERENCE
POWER-ON RESET
Zero Scale
Midscale
DAC80501Z
DAC80501M
DAC70501Z
DAC70501M
DAC60501Z
DAC60501M
16-Bit
16-Bit
14-Bit
14-Bit
12-Bit
12-Bit
Internal (default) or External
Internal (default) or External
Internal (default) or External
Internal (default) or External
Internal (default) or External
Internal (default) or External
Zero Scale
Midscale
Zero Scale
Midscale
6 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
DQF Package
8-Pin WSON
Top View
VDD
VOUT
NC
1
2
3
4
5
10
9
VREFIO
NC
VDD
VOUT
AGND
SPI2C
1
2
3
4
8
7
6
5
VREFIO
SDIN/SDA
SYNC/A0
SCLK/SCL
8
SDIN/SDA
SYNC/A0
SCLK/SCL
AGND
SPI2C
7
6
Not to scale
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
DGS
DQF
3
AGND
NC
4
3
9
6
Ground
—
Ground reference point for all circuitry on the device.
No connection. Leave floating.
—
—
5
NC
—
No connection. Leave floating.
SCLK/SCL
Input
Serial interface clock. SPI or I2C mode.
SPI mode: Serial interface data input. Data are clocked into the input shift
register on each falling edge of the SCLK pin.
SDIN/SDA
8
7
Input/output I2C mode: Data are clocked into or out of the input register. This pin is a
bidirectional, SDA drain data line that must be connected to the supply voltage
with an external pullup resistor.
Interface select pin.
Digital interface in SPI mode if SPI2C = 0
SPI2C
5
7
4
6
Input
Digital interface in I2C mode if SPI2C = 1
SPI2C pin must be kept static after device powers up.
SPI mode: Active low serial data enable. This input is the frame synchronization
signal for the serial data. When the signal goes low, the serial interface input
SYNC/A0
Input
shift register is enabled.
I2C mode: Four-state address input 0.
VDD
1
2
1
2
Power
Output
Analog supply voltage (2.7 V to 5.5 V)
Analog output voltage from the DAC
VOUT
When using the internal reference, this pin is the reference output voltage pin
(default). Reference input to the device when operating with external reference.
VREFIO
10
8
Input/output
Copyright © 2018–2020, Texas Instruments Incorporated
3
DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–10
MAX
6
UNIT
VDD to AGND
Input voltage
VREFIO to AGND
VDD + 0.3
VDD + 0.3
VDD + 0.3
10
V
Digital input(s) to AGND
VOUT to AGND
Output voltage
Input current
V
Current into any pin
Junction temperature (TJ)
Storage temperature (Tstg
mA
–40
150
Temperature
°C
)
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-
001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
UNIT
POWER SUPPLY
VDD to AGND
DIGITAL INPUTS
VIH
Positive supply voltage to ground
5.5
V
Input high voltage
Input low voltage
1.62
V
V
VIL
0.45
REFERENCE INPUT
2.7 V ≤ VDD < 3.3 V,
reference divider disabled (REF-DIV bit = 0)
VREFIO to AGND
VREFIO to AGND
VREFIO to AGND
VREFIO to AGND
1.2
2.4
1.2
2.4
0.5 × (VDD – 0.2)
(VDD – 0.2)
0.5 × VDD
VDD
V
V
V
V
2.7 V ≤ VDD < 3.3 V,
reference divider enabled (REF-DIV bit = 1)
3.3 V ≤ VDD ≤ 5.5 V,
reference divider disabled (REF-DIV bit = 0)
3.3 V ≤ VDD ≤ 5.5 V,
reference divider enabled (REF-DIV bit = 1)
TEMPERATURE
TA
Operating temperature
–40
125
°C
4
Copyright © 2018–2020, Texas Instruments Incorporated
DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
7.4 Thermal Information
DACx0501
THERMAL METRIC(1)
DGS (VSSOP)
10 PINS
170.1
DQF (WSON)
8 PINS
122.6
58.3
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
60.5
92.6
50
Junction-to-top characterization parameter
Junction-to-board characterization parameter
7.8
1.5
ΨJB
90.7
49.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC80501
DAC70501
DAC60501
16
14
12
–1
–1
Resolution
Bits
INL
Integral nonlinearity(1)
Differential nonlinearity(1)
1
1
LSB
LSB
DNL
DAC80501,
reference divider disabled (REF-DIV bit = 0)
–0.08
–0.06
–0.07
-0.02
0.025
0.025
0.08
0.06
0.07
DAC80501,
reference divider enabled (REF-DIV bit = 1)
TUE
Total unadjusted error(1)
%FSR
DAC80501, DGS package
reference divider enabled (REF-DIV bit = 1)
DAC70501, DAC60501
–0.1
–1.5
0.04
0.5
0.1
1.5
Zero code error(1)
DAC loaded with zero scale code
mV
µV/°C
mV
Zero code error temperature
coefficient(1)
Offset error(1)
±2
0.5
±2
–1.5
1.5
Offset error temperature
µV/°C
(1)
coefficient
DAC80501,
reference divider disabled (REF-DIV bit = 0)
–0.08
–0.06
-0.02
0.025
0.08
0.06
DAC80501,
reference divider enabled (REF-DIV bit = 1)
Gain error(1)
%FSR
DAC80501, DGS package
reference divider enabled (REF-DIV bit = 1)
–0.07
–0.1
0.025
0.04
±1
0.07
0.1
DAC70501, DAC60501
Gain error temperature
coefficient(1)
ppm
FSR/°C
(1) End point fit between code 256 to code 64,511 for 16-bit, code 64 to code 16,127 for 14-bit, code 16 to code 4031 for 12 bit, DAC output
unloaded, performance under resistive and capacitice load conditions are specified by design and characterization, DAC output range ≥
2.5 V.
Copyright © 2018–2020, Texas Instruments Incorporated
5
DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC80501, DAC loaded with full scale,
reference divider disabled (REF-DIV bit = 0)
–0.08
-0.02
0.08
DAC80501, DAC loaded with full scale,
reference divider enabled (REF-DIV bit = 1)
–0.06
0.025
0.06
Full-scale error(1)
%FSR
DAC80501, DGS package
reference divider enabled (REF-DIV bit = 1)
–0.07
–0.1
0.025
0.04
±2
0.07
0.1
DAC70501, DAC60501
Full-scale error temperature
coefficient(1)
ppm
FSR/°C
OUTPUT CHARACTERISTICS
2 ×
VREFIO
BUFF-GAIN bit set to 1, REF-DIV bit set to 0
BUFF-GAIN bit set to 1, REF-DIV bit set to 1
BUFF-GAIN bit set to 0, REF-DIV bit set to 1
0
0
0
VO
Output voltage
VREFIO
V
0.5 ×
VREFIO
VDD = 2.7 V
0.25
0.5
RLOAD
Resistive load(2)
kΩ
VDD = 5.5 V
RLOAD = infinite
2
CLOAD
Capacitive load(2)
Load regulation
nF
µV/mA
mA
RLOAD = 2 kΩ
10
DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA
Full scale output shorted to AGND
Zero output shorted to VDD
80
30
30
Short circuit current
to VDD, DAC at full code, IOUT = 10 mA
(sourcing)
Output voltage headroom
Output voltage footroom
0.3
0.3
0.1
V
V
to AGND, DAC at zero code, IOUT = 10 mA
(sinking)
DAC at midscale
0.1
10
ZO
DC small signal output impedance DAC at code 256
DAC at code 65279
Ω
10
Power supply rejection ratio (DC) DAC at midscale; VDD = 5 V ± 10%
0.15
mV/V
ppm of
FSR
Output voltage drift vs time
TA = 35°C, VOUT = midscale, 1900 hr
20
VOLTAGE REFERENCE INPUT
Reference input impedance
(VREFIO)
ZVREFIO
100
5
kΩ
Reference input capacitance
(VREFIO)
CVREFIO
pF
(2) Not production tested.
6
Copyright © 2018–2020, Texas Instruments Incorporated
DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
VOLTAGE REFERENCE OUTPUT
Output (initial accuracy)(3)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
DAC80501
2.4975
2.5025
V
5
Output drift(3)
ppm/℃
DAC70501, DAC60501
10
Output impedance(3)
Output noise(3)
Output noise density(3)
Load current(3)
0.1
14
Ω
µVPP
nV/√Hz
mA
0.1 Hz to 10 Hz
Measured at 10 kHz, reference load = 10 nF
140
±5
Load regulation(3)
Line regulation(3)
Output voltage drift vs time(3)
Sourcing and sinking
90
µV/mA
µV/V
µV
20
TA = 35°C, 1900 hr
1st cycle
20
500
25
µV
Thermal hysteresis(3)
Additional cycle
µV
DYNAMIC PERFORMANCE
¼ to ¾ scale and ¾ to ¼ scale settling to ±2
LSB, VDD = 5.5 V, VREFIO = 2.5 V
5
3
ts
Output voltage settling time(4)
µs
10-mV settling to ±2 LSB, VDD = 5.5 V,
VREFIO = 2.5 V
Slew rate(4)
VDD = 5.5 V, VREFIO = 2.5 V
CLOAD = 50 pF
2
V/µs
mV
Power on glitch magnitude
200
0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V
14
23
µVPP
Vn
Output noise(4)
100-kHz Bandwidth, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V
µVrms
Measured at 1 kHz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V,
gain = 2X (BUFF-GAIN bit = 1)
78
74
55
Measured at 10 kHz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V,
gain = 2X (BUFF-GAIN bit = 1)
Vn
Output noise density
nV/√Hz
Measured at 1 kHz, DAC at full scale,
VDD = 2.7 V, external VREFIO = 2.5 V,
gain = 1X (BUFF-GAIN bit = 0)
Measured at 10 kHz, DAC at full scale,
VDD = 2.7 V, external VREFIO = 2.5 V,
gain = 1X (BUFF-GAIN bit = 0)
50
70
70
85
1-kHz sinusiod at DAC output, DAC updated
at 500 kHz, include up to 7th harmonics, no
filter on DAC output
SFDR
THD
Spurious free dynamic range
Total harmonic distortion
dB
dB
dB
1-kHz sinusiod at DAC output, DAC updated
at 500 kHz, include up to 7th harmonics, no
filter on DAC output
200-mV 50-Hz to 60-Hz sine wave
superimposed on power supply voltage, DAC
at midscale. (ac analysis)
Power supply rejection ratio (ac)
Code change glitch impulse
Code change glitch magnitude
Midcode ±1 LSB (including feedthrough)
4
nV-s
mV
Midcode ±1 LSB (including feedthrough)
gain = 1X (BUFF-GAIN bit = 0)
7.5
(3) Characterized on 8-pin DQF package.
(4) Output buffer in gain = 2X setting (BUFF-GAIN bit = 1).
Copyright © 2018–2020, Texas Instruments Incorporated
7
DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital feedthrough
At SCLK = 1 MHz, DAC output at midscale
4
nV-s
DIGITAL INPUTS
Hysteresis voltage
Input current
0.4
10
V
–5
5
µA
pF
Pin capacitance
Per pin
POWER REQUIREMENTS
Normal mode, internal reference enabled,
DAC at full scale, SPI static
1.5
1
2.0
1.4
mA
IVDD
Current flowing into VDD
Normal mode, external reference = 2.5 V,
DAC at full scale, SPI static
DAC and Internal reference power-down
0-V to 5-V range, midscale code
15
25
µA
µA
IVREFIO
Current flowing into VREFIO
8
Copyright © 2018–2020, Texas Instruments Incorporated
DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
7.6 Timing Requirements : SPI Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V to 5.5 V, and TA = –40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
ns
fSCLK
SCLK frequency
50
tSCLKHIGH
tSCLKLOW
tSDIS
SCLK high time
9
9
SCLK low time
ns
SDIN setup
5
ns
tSDIH
SDIN hold
10
13
10
160
ns
tSYNCS
tSYNCH
SYNC falling edge to SCLK falling edge setup
SCLK falling edge to SYNC rising edge
ns
ns
tSYNCHIGH SYNC high time
tSYNCIGNOR
ns
SCLK falling edge to SYNC ignore
15
1
ns
µs
E
tDACWAIT
Sequential DAC update wait time
7.7 Timing Requirements : I2C Standard Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
0.1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
4.7
4
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
4.7
4
µs
µs
0
ns
Data setup time
250
4700
4000
ns
SCL clock low period
ns
tHIGH
tR
SCL clock high period
ns
Clock and data fall time
Clock and data rise time
Sequential DAC update wait time
300
ns
tF
1000
ns
tUPDATE
1
µs
7.8 Timing Requirements : I2C Fast Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
0.4
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
1.3
0.6
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
0.6
µs
0.6
µs
0
ns
Data setup time
100
1300
600
ns
SCL clock low period
ns
tHIGH
tR
SCL clock high period
ns
Clock and data fall time
Clock and data rise time
Sequential DAC update wait time
300
300
ns
tF
ns
tUPDATE
1
µs
Copyright © 2018–2020, Texas Instruments Incorporated
9
DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
7.9 Timing Requirements : I2C Fast-Mode Plus
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
0.5
0.26
0.26
0.26
0
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
µs
µs
ns
Data setup time
50
ns
SCL clock low period
500
260
ns
tHIGH
tR
SCL clock high period
ns
Clock and data fall time
Clock and data rise time
Sequential DAC update wait time
120
120
ns
tF
ns
tUPDATE
1
µs
tSYNCHIGH
tSYNCH
tSYNCS
SYNC
tSYNCIGNORE
tSCLKLOW
SCLK
tSCLKHIGH
SDIN
Bit 23
Bit 1
Bit 0
tSDIS
tSDIH
图 1. SPI Mode Timing
Low byte ACK cycle
tR
tLOW
tF
SCL
tSUSTA
tHDSTA
tHIGH
tSUSTO
tHDDAT
tSUDAT
tHDSTA
SDA
tBUF
S
P
S
P
图 2. I2C Mode Timing
10
版权 © 2018–2020, Texas Instruments Incorporated
DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
7.10 Typical Characteristics
at TA = 25°C, VDD = 5.5 V, Internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, and DAC outputs unloaded (unless
otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
Unloaded
5 kW || 200 pF
Unloaded
5 kW || 200 pF
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D001
D002
图 3. Integral Linearity Error vs Digital Input Code
图 4. Differential Linearity Error vs Digital Input Code
0.08
0.06
0.04
0.02
0
1
Unloaded
5 kW || 200 pF
INL Max, Unloaded
INL Min, Unloaded
INL Max, 5 kW || 200 pF
INL Min, 5 kW || 200 pF
0.75
0.5
0.25
0
-0.02
-0.04
-0.06
-0.08
-0.25
-0.5
-0.75
-1
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D003
D004
图 5. Total Unadjusted Error vs Digital Input Code
图 6. Integral Linearity Error vs Temperature
1
0.75
0.5
0.08
0.06
0.04
0.02
0
DNL Max, Unloaded
DNL Min, Unloaded
DNL Max, 5 kW || 200 pF
DNL Min, 5 kW || 200 pF
Unloaded
5 kW || 200 pF
0.25
0
-0.25
-0.5
-0.75
-1
-0.02
-0.04
-0.06
-0.08
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D005
D006
图 7. Differential Linearity Error vs Temperature
图 8. Total Unadjusted Error vs Temperature
版权 © 2018–2020, Texas Instruments Incorporated
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DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, Internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, and DAC outputs unloaded (unless
otherwise noted)
1.5
1.5
1.25
1
Unloaded
5 kW || 200 pF
1
0.5
0
0.75
0.5
0.25
0
-0.5
-1
-1.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D007
D008
图 9. Zero Code Error vs Temperature
图 10. Offset Error vs Temperature
0.08
0.06
0.04
0.02
0
0.08
0.06
0.04
0.02
0
Unloaded
5 kW || 200 pF
Unloaded
5 kW || 200 pF
-0.02
-0.04
-0.06
-0.08
-0.02
-0.04
-0.06
-0.08
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
DD0a0t9a
D010
图 11. Full Scale Error vs Temperature
图 12. Gain Error vs Temperature
1
0.75
0.5
1
0.75
0.5
Max INL
Min INL
Max DNL
Min DNL
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
VDD (V)
D011
D012
REF-DIV = 0 and BUFF-GAIN = 0
图 13. Integral Linearity Error vs Supply Voltage
REF-DIV = 0 and BUFF-GAIN = 0
图 14. Differential Linearity Error vs Supply Voltage
12
版权 © 2018–2020, Texas Instruments Incorporated
DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, Internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, and DAC outputs unloaded (unless
otherwise noted)
0.08
0.06
0.04
0.02
0
1.5
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
1
0.5
0
-0.02
-0.04
-0.06
-0.08
-0.5
-1
-1.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
VDD (V)
D013
D014
图 15. Total Unadjusted Error vs Supply Voltage
图 16. Zero Code Error vs Supply Voltage
1.5
1
0.08
0.06
0.04
0.02
0
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
0.5
0
-0.02
-0.04
-0.06
-0.08
-0.5
-1
-1.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
VDD (V)
D015
D016
图 17. Offset Error vs Supply Voltage
图 18. Gain Error vs Supply Voltage
0.08
0.06
0.04
0.02
0
1
0.75
0.5
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
Max, REFDIV = 0
Max, REFDIV = 1
Min, REFDIV = 0
Min, REFDIV = 1
0.25
0
-0.02
-0.04
-0.06
-0.08
-0.25
-0.5
-0.75
-1
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
5.5
D017
D018
图 19. Full Scale Error vs Supply Voltage
图 20. Integral Linearity Error vs Reference Voltage
版权 © 2018–2020, Texas Instruments Incorporated
13
DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, Internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, and DAC outputs unloaded (unless
otherwise noted)
1
0.75
0.5
0.08
0.06
0.04
0.02
0
Max, REFDIV = 0
Max, REFDIV = 1
Min, REFDIV = 0
Min, REFDIV = 1
REFDIV = 0
REFDIV = 1
0.25
0
-0.25
-0.5
-0.75
-1
-0.02
-0.04
-0.06
-0.08
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
5.5
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
5.5
D019
D020
图 21. Differential Linearity Error vs Reference Voltage
图 22. Total Unadjusted Error vs Reference Voltage
1.5
1.5
1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-1.5
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
5.5
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
5.5
D021
D022
图 23. Zero Code Error vs Reference Voltage
图 24. Offset Error vs Reference Voltage
0.08
0.06
0.04
0.02
0
0.08
0.06
0.04
0.02
0
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
-0.02
-0.04
-0.06
-0.08
-0.02
-0.04
-0.06
-0.08
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
5.5
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
5.5
D023
D024
图 25. Gain Error vs Reference Voltage
图 26. Full Scale Error vs Reference Voltage
14
版权 © 2018–2020, Texas Instruments Incorporated
DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, Internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, and DAC outputs unloaded (unless
otherwise noted)
2
1.75
1.5
1.25
1
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
Internal Reference, BUFF-GAIN = 0
Internal Reference, BUFF-GAIN = 1
External Reference, BUFF-GAIN = 0
External Reference, BUFF-GAIN = 1
Internal Reference, BUFF-GAIN = 0
Internal Reference, BUFF-GAIN = 1
External Reference, BUFF-GAIN = 0
External Reference, BUFF-GAIN = 1
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D025
D026
DAC code at midscale
图 27. Supply Current vs Digital Input Code
图 28. Supply Current vs Temperature
2
1.75
1.5
1.25
1
12
10
8
Internal Reference, BUFF-GAIN = 0
Internal Reference, BUFF-GAIN = 1
External Reference, BUFF-GAIN = 0
External Reference, BUFF-GAIN = 1
6
0.75
0.5
0.25
0
4
2
0
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D027
D028
DAC code at midscale
图 29. Supply Current vs Supply Voltage
REF-DIV = 0 and BUFF-GAIN = 0
图 30. Power Down Current vs Temperature
1
0.8
0.6
0.4
0.2
0
15
12
9
-0.2
-0.4
-0.6
-0.8
-1
6
Sourcing 5.5V
Sourcing 2.7V
Sinking 5.5V
Sinking 2.7V
3
0
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
0
5
10
15
Load Current (mA)
20
25
30
D029
D033
External reference = 2.5 V, REF-DIV = 1 and BUFF-GAIN = 0
External reference = 2.5 V
图 31. Power Down Current vs Supply Voltage
图 32. Headroom and Footroom vs Load Current
版权 © 2018–2020, Texas Instruments Incorporated
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DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, Internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, and DAC outputs unloaded (unless
otherwise noted)
7
8
0xFFFF
0xC000
0x8000
0x4000
0x0
0xFFFF
0xC000
0x8000
0x4000
0x0
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-1
-1
-50 -40 -30 -20 -10
0
Loading Current (mA)
10
20
30
40
50
-50 -40 -30 -20 -10
0
Loading Current (mA)
10
20
30
40
50
D031
D032
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 1
图 33. Source and Sink Capability
图 34. Source and Sink Capability
7
6
0xFFFF
0xC000
0x8000
0x4000
0x0
5
4
3
3 nV-sec
2
1
VOUT (2.5 mV/div)
CS (5 V/div)
0
-1
Time (0.5 ms/div)
-50 -40 -30 -20 -10
0
Loading Current (mA)
10
20
30
40
50
D034
D033
DAC code transition from midscale – 1 to midscale LSB,
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 1 and BUFF-GAIN = 0
图 36. Glitch Impulse, Rising Edge, 1 LSB Step
图 35. Source and Sink Capability
Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div)
CS (5 V/div)
2 nV-sec
VOUT (2.5mV/div)
CS (5 V/div)
Time (0.5 ms/div)
Time (2 msec/div)
D035
D036
DAC code transition from midscale to midscale – 1 LSB,
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 0
图 37. Glitch Impulse, Falling Edge, 1 LSB Step
图 38. Full-Scale Settling Time, Rising Edge
版权 © 2018–2020, Texas Instruments Incorporated
16
DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, Internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, and DAC outputs unloaded (unless
otherwise noted)
Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div)
CS (5 V/div)
VDD (2 V/div)
DAC Output (40 mV/div)
Time (2 msec/div)
Time (1 ms/div)
D037
D038
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 0
图 39. Full-Scale Settling Time, Falling Edge
图 40. Power-on Glitch
0
-10
VDD (2 V/div)
DAC Output (40 mV/div)
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
Time (1 ms/div)
1
10
100 1000
Frequency (Hz)
10000
100000
D039
D040
REF-DIV = 0 and BUFF-GAIN = 0
DAC code at midscale, VDD = 5.0 V + 0.2 VPP
,
REF-DIV = 0 and BUFF-GAIN = 0
图 41. Power-off Glitch
图 42. DAC Output AC PSRR vs Frequency
20
0
300
250
200
150
100
50
DAC Code = 0x0
DAC Code = 0x8000
DAC Code = 0xFFFF
-20
-40
-60
-80
-100
-120
-140
0
0
4000
8000 12000
Frequency (Hz)
16000
20000
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
D041
D042
fo = 1 kHz, fs = 400 kHz, includes 7 harmonics,
Gain = 1X (REF-DIV = 1 and BUFF-GAIN = 1),
external reference = 2.5 V,
measurement bandwidth = 20 kHz, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 0
图 43. DAC Output THD+N vs Frequency
图 44. DAC Output Noise Spectral Density
版权 © 2018–2020, Texas Instruments Incorporated
17
DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, Internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, and DAC outputs unloaded (unless
otherwise noted)
D043
D044
DAC code at midscale, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
DAC code at midscale, internal reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
图 45. DAC Output Noise 0.1 Hz to 10 Hz
图 46. DAC Output Noise 0.1 Hz to 10 Hz
2.505
SCLK (5 V/div)
2.5025
2.5
VOUT (1 mV/div)
2.4975
2.495
Time (5 msec/div)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D045
D046
SCLK = 1 MHz, DAC code at midscale, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
30 units
图 47. Clock Feedthrough
图 48. Internal Reference Voltage vs Temperature
2.505
100
75
2.5025
2.5
50
25
0
-25
-50
-75
-100
2.4975
2.495
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
0
200
400
600
Time (Hours)
800
1000
1200
D047
D048
图 49. Internal Reference Voltage vs Supply Voltage
图 50. Internal Reference Voltage vs Time
18
版权 © 2018–2020, Texas Instruments Incorporated
DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
Typical Characteristics (接下页)
at TA = 25°C, VDD = 5.5 V, Internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, and DAC outputs unloaded (unless
otherwise noted)
800
700
600
500
400
300
200
100
0
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
D050
D049
图 52. Internal Reference Noise, 0.1 Hz to 10 Hz
图 51. Internal Reference Noise Density vs Frequency
55
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
Presolder Heat Reflow
Postsolder Heat Reflow
50
45
40
35
30
25
20
15
10
5
0
0
1
2
3
4
5
2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010
VREFOUT (V)
D051
D053
Temperature Drift (ppm/èC)
图 53. Internal Reference Temperature Drift Histogram
图 54. Internal Reference Initial Accuracy (Pre and Post
Solder) Histogram
28%
26%
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
D054
VREFOUT Drift Delta (ppm/èC)
图 55. Internal Reference Temperature Drift (Pre and Post Solder) Histogram
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8 Detailed Description
8.1 Overview
The DAC80501, DAC70501, DAC60501 (DACx0501) family of devices are buffered voltage output, 16-bit, 14-bit,
or 12-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 5-ppm/˚C internal
reference, giving full-scale output voltage ranges of 1.25 V, 2.5 V, or 5 V. The DACx0501 devices incorporate a
power-on-reset circuit that makes sure that the DAC output powers up at zero scale or midscale, and remains at
that scale until a valid code is written to the device.
The digital interface of the DACx0501 can be configured to SPI or I2C mode using the SPI2C pin. In SPI mode,
the DACx0501 family uses a 3-wire serial interface that operates at clock rates up to 50 MHz. In I2C mode, the
DACx0501 devices operate in standard mode (100 kbps), fast mode (400 kbps), and fast mode plus (1.0 Mbps).
8.2 Functional Block Diagram
VREFIO
VDD
Internal
Reference
SPI2C
DAC
Buffer
DAC
Register
BUF
VOUT
DAC
SCLK or SCL
SDIN or SDA
or A0
SYNC
Power On Reset
Power Down Logic
Resistive Network
AGND
8.3 Feature Description
8.3.1 DAC Architecture
The output channel in the DACx0501 family of devices consists of a rail-to-rail ladder architecture with an output
buffer amplifier. The devices include an internal 2.5-V reference. 图 56 shows a block diagram of the DAC
architecture.
VREFIO
2.5-V
Reference
REF Divider
REF-DIV Bit
(x1 or x0.5)
Serial Interface
DAC Data Register
Gain
(x1 or x2)
BUFF-GAIN Bit
VOUT
DAC
Buffer
Register
DAC
Active
Register
R-2R
BUF
DAC
Output
AGND
图 56. DACx0501 DAC Block Diagram
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Feature Description (接下页)
8.3.1.1 DAC Transfer Function
The input data writes to the individual DAC data registers in straight binary format. After a power-on or a reset
event, all DAC registers are set to zero code (DACx0501Z devices) or midscale code (DACx0501M devices).
The DAC transfer function is shown by 公式 1.
DAC_DATA VREFIO
ì
VOUT
=
ì GAIN
2N
DIV
where:
•
•
N = resolution in bits = either 12 (DAC60501), 14 (DAC70501) or 16 (DAC80501).
DAC_DATA = decimal equivalent of the binary code that is loaded to the DAC register (address 8h).
DAC_DATA ranges from 0 to 2N – 1.
•
VREFIO = DAC reference voltage at the VREFIO pin. Either VREFIO from the internal 2.5-V reference or
VREFIO from an external reference.
•
•
DIV = 1 (default) or 2, as set by the REF-DIV bit in the GAIN register (address 4h).
GAIN = 1 or 2 (default), as set by the BUFF-GAIN bit in the GAIN register (address 4h).
(1)
8.3.1.2 DAC Register Structure
Data written to the DAC data registers are initially stored in the DAC buffer registers. The update mode of the
DAC output is determined by the status of the DAC_SYNC_EN bit (address 2h).
In asynchronous mode (default, DAC_SYNC_EN = 0), a write to the DAC buffer register results in an immediate
update of the DAC active register. In SPI mode, the DAC output (VOUT pin) updates on the rising edge of
SYNC. In I2C mode, the DAC output (VOUT pin) updates on the falling edge of SCL on the last acknowledge bit.
In synchronous mode (DAC_SYNC_EN = 1), writing to the DAC buffer register does not automatically update the
DAC active register. Instead, the update occurs only after a software LDAC trigger event. A software LDAC
trigger generates through the LDAC bit in the TRIGGER register (address 5h). When the host reads from a DAC
buffer register, the value held in the DAC buffer register is returned (not the value held in the DAC active
register).
8.3.1.3 Output Amplifier
The output buffer amplifier generates rail-to-rail voltages on the output, giving a maximum output range of 0 V to
VDD. 公式 1 shows that the full-scale output range of the DAC output is determined by the voltage on the
VREFIO pin, the reference divider setting (DIV) as set by the REF-DIV bit (address 4h), and the gain
configuration for that channel set by the corresponding BUFF-GAIN bit (address 4h).
8.3.2 Internal Reference
The DAx0501 family of devices includes a 2.5-V precision band-gap reference that is enabled by default.
Operation from an external reference is supported by disabling the internal reference in the REF_PWDWN bit
(address 3h). The internal reference is externally available at the VREFIO pin, and sources up to 5 mA. For noise
filtering, use a minimum 150-nF capacitor between the reference output and AGND.
The reference voltage to the device, either from the internal reference or an external one, can be divided by a
factor of two by setting the REF-DIV bit (address 4h) to 1. The REF-DIV bit provides additional flexibility in setting
the full-scale output range of the DAC output. Make sure to configure REF-DIV so that there is sufficient
headroom from VDD to the DAC operating reference voltage, VREFIO (see 公式 1). See the Recommended
Operating Conditions for more information.
Improper configuration of the reference divider triggers a reference alarm condition. In this case, the reference
buffer is shut down, and all the DAC outputs go to 0 V. The DAC data registers are unaffected by the alarm
condition, thus enabling the DAC output to return to normal operation after the reference divider is configured
correctly.
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Feature Description (接下页)
8.3.2.1 Solder Heat Reflow
A known behavior of IC reference voltage circuits is the shift induced by the soldering process. 图 54 and 图 55
show the effect of solder heat reflow for the DACx0501 internal reference.
8.3.3 Power-On-Reset (POR)
The DACx0501 family of devices includes a power-on reset (POR) function that controls the output voltage at
power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to
initialize to default values, and communication with the device is valid only after a 250-µs POR delay. The default
value for the DAC data registers is zero-code for the DACx0501Z devices and midscale code for the
DACx0501M devices. The DAC output remains at the power-up voltage until a valid command is written to a
channel.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in 图 57, to make sure that the internal capacitors discharge and reset the device at
power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD drops to
less than 2.2 V but remains greater than 0.7 V (shown as the undefined region), the device may or may not reset
under all specified temperature and power-supply conditions. In this case, initiate a POR. When VDD remains
greater than 2.2 V, a POR does not occur.
VDD (V)
5.50
Specified supply
voltage range
No power-on reset
2.70
2.20
Undefined
0.70
Power-on reset
0.00
图 57. Threshold Levels for VDD POR Circuit
8.3.4 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to the SOFT-RESET bit in the
TRIGGER register (address 5h). A software reset initiates a POR event.
22
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8.4 Device Functional Modes
The DACx0501 has two modes of operation: normal and power-down.
8.4.1 Power-Down Mode
The DACx0501 output amplifiers and internal reference can be independently powered down through the
CONFIG register (3h). At power up, the DAC output and the internal reference are active by default. In power-
down mode, the DAC output (VOUT pin) is internally connected to AGND through a 1-kΩ resistor.
8.5 Programming
8.5.1 Serial Interface
The DACx0501 family of devices is controlled through either a 3-wire SPI or a 2-wire I2C interface. The type of
interface is determined at device power up based on the logic level of the SPI2C pin. A logic 0 on the SPI2C pin
puts the DACx0501 in SPI mode; whereas, logic 1 on SPI2C puts the DACx0501 in I2C mode. The SPI2C pin
must be kept static after the device powers up.
8.5.1.1 SPI Mode
The DACx0501 digital interface is programmed to work in SPI mode when the logic level of the SPI2C pin is 0 at
power up. In SPI mode, the DACx0501 have a 3-wire serial interface: SYNC, SCLK, and SDIN, as shown in the
Pin Configuration and Functions section. The serial interface is compatible with SPI, QSPI, and Microwire
interface standards, and most digital signal processors (DSPs). The serial interface operates at up to 50 MHz.
The input shift register is 24 bits wide.
The serial clock SCLK is a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle.
When SYNC is high, the SCLK and SDIN signals are blocked. The device internal registers are updated from the
shift register on the rising edge of SYNC.
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Programming (接下页)
8.5.1.1.1 SYNC Interrupt
For SPI mode operation, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed DAC
register updates on the SYNC rising edge. However, if the SYNC line is brought high before the 24th SCLK
falling edge, this event acts as an interrupt to the write sequence. The shift register resets and the write
sequence is discarded. Neither an update of the data buffer or DAC register contents, nor a change in the
operating mode occurs, as shown in 图 58.
SCLK
1
2
24
SYNC
SDIN
DB23
DB0
Invalid/Interrupted write sequence
SCLK
1
2
24
SYNC
SDIN
DB23
DB0
Valid write sequence
图 58. SYNC Interrupt
24
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Programming (接下页)
8.5.1.2 I2C Mode
The DACx0501 digital interface is programmed to work in I2C mode when the logic level of the SPI2C pin is 1 at
power up. In I2C mode, the DACx0501 have a 2-wire serial interface: SCL, SDA, and one address pin, A0, as
shown in the Pin Configuration and Functions section. The I2C bus consists of a data line (SDA) and a clock line
(SCL) with pull-up structures. When the bus is idle, both the SDA and SCL lines are pulled high. All the I2C-
compatible devices connect to the I2C bus through the open-drain I/O pins, SDA and SCL.
The I2C specification states that the device that controls communication is called a master, and the devices that
are controlled by the master are called slaves. The master device generates the SCL signal. The master device
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device
on an I2C bus is typically a microcontroller or DSP. The DACx0501 operate as a slave device on the I2C bus. A
slave device acknowledges master commands, and upon master control, receives or transmits data.
Typically, the DACx0501 operate as a slave receiver. A master device writes to the DACx0501, a slave receiver.
However, if a master device requires the DACx0501 internal register data, the DACx0501 operate as a slave
transmitter. In this case, the master device reads from the DACx0501 According to I2C terminology, read and
write refer to the master device.
The DACx0501 are slave devices that support the following data transfer modes:
1. Standard mode (100 kbps)
2. Fast mode (400 kbps)
3. Fast mode plus (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, these modes are referred
to as F/S-mode in this document. The fast-mode plus (FM+) protocol is supported in terms of data transfer
speed, but not output current. The low-level output current would be 3 mA, similar to the case of standard and
fast modes. The DACx0501 support 7-bit addressing. The 10-bit addressing mode is not supported. These
devices support the general call reset function. Send the following sequence to initiate a software reset within the
device: Start/Repeated Start, 0x00, 0x06, Stop. The reset is asserted within the device on the falling edge of the
ACK bit, following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low during the
high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of
the ninth clock cycle as shown in 图 59.
Data output
by Transmitter
Not acknowledge
Data output
by Receiver
Acknowledge
2
9
1
8
SCL from
Master
S
Clock pulse for
acknowledgement
Start
condition
图 59. Acknowledge and Not Acknowledge on the I2C Bus
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Programming (接下页)
8.5.1.2.1 F/S Mode Protocol
1. The master initiates data transfer by generating a start condition. The start condition is when a high to-low
transition occurs on the SDA line while SCL is high, as shown in 图 60. All I2C-compatible devices recognize
a start condition.
SDA
SCL
S
P
Start
condition
Stop
condition
图 60. Start and Stop Conditions
SDA
SCL
Change of data
allowed
Data line stable
Data valid
图 61. Bit Transfer on the I2C Bus
2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in 图
61. All devices recognize the address sent by the master and compare it to their internal fixed addresses.
Only the slave device with a matching address generates an acknowledge by pulling the SDA line low during
the entire high period of the ninth SCL cycle, as shown in 图 59 by pulling the SDA line low during the entire
high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows the communication
link with a slave has been established.
3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
either case, the receiver must acknowledge the data sent by the transmitter. Therefore, the acknowledge
signal can be generated by the master or by the slave, depending on which one is the receiver. The 9-bit
valid data sequences consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.
4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see 图 60). This action releases the bus and stops the communication link
with the addressed slave. All I2C-compatible devices recognize the stop condition. Upon receipt of a stop
condition, the bus is released, and all slave devices then wait for a start condition followed by a matching
address.
26
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Programming (接下页)
8.5.1.2.2 DACx0501 I2C Update Sequence
For a single update, the DACx0501 requires a start condition, a valid I2C address byte, a command byte, and two
data bytes: the most significant data byte (MSDB), and least significant data byte (LSDB), as listed in 表 1.
表 1. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
Address (A) byte
DB [32:24]
Command byte
DB [23:16]
MSDB
LSDB
DB [7:0]
DB [15:8]
After each byte is received, the DACx0501 acknowledge the byte by pulling the SDA line low during the high
period of a single clock pulse, as shown in 图 62. These four bytes and acknowledge cycles make up the 36
clock cycles required for a single update to occur. A valid I2C address byte selects the DACx0501 devices.
Recognize
START or
REPEATED
Recognize
STOP or
REPEATED
Generate ACKNOWLEDGE
START
START
signal
condition
condition
P
SDA
Sr
MSB
Acknowledgement
signal from Slave
Address
R/W
1
SCL
1
7
8
9
2 - 8
9
Sr
S
or
Sr
or
P
ACK
ACK
START or
REPEATED
START or
STOP
REPEATED
START
condition
Clock line held low while
interrupts are serviced
condition
图 62. I2C Bus Protocol
The command byte sets the operational mode of the selected DACx0501 device. When the operational mode is
selected by this byte, the DACx0501 must receive two data bytes, the most significant data byte (MSDB) and
least significant data byte (LSDB), for a data update to occur. The DACx0501 devices perform an update on the
falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 11.11 kSPS. Using the
fast-mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 27.77 kSPS. When a stop condition
is received, the DACx0501 release the I2C bus and await a new start condition.
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8.5.1.2.2.1 DACx0501 Address Byte
The address byte, as shown in 表 2, is the first byte received following the START condition from the master
device. The first four bits (MSBs) of the address are factory preset to 1001. The next three bits of the address
are controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is
sampled during the first byte of each data frame to determine the address. The device latches the value of the
address pin, and consequently, responds to that particular address according to 表 3.
表 2. DACx0501 Address Byte
MSB
AD3
1
LSB
R/W
ADDRESS TYPE
AD6
AD5
AD4
AD2
AD1
AD0
General address
1
0
0
See 表 3 (slave address column)
0 or 1
表 3. Address Format
SLAVE ADDRESS
A0 PIN
1001 000
1001 001
1001 010
1001 011
AGND
VDD
SDA
SCL
8.5.1.2.2.2 DACx0501 Command Byte
The DACx0501 command byte (shown in 表 4) controls which command is executed and which register is being
accessed when writing to or reading from the DACx0501 series.
表 4. DACx0501 Command Byte
B23
0
B22
0
B21
0
B20
0
B19
0
B18
0
B17
0
B16
0
REGISTER
NOOP
0
0
0
0
0
0
0
1
DEVID
0
0
0
0
0
0
1
0
SYNC
0
0
0
0
0
0
1
1
CONFIG
GAIN
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
TRIGGER
STATUS
DAC DATA
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
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8.5.1.2.2.3 DACx0501 Data Byte (MSDB and LSDB)
The MSDB and LSDB contain the data that are passed to the register or registers specified by the command byte, as shown in 表 5. The DACx0501
update at the falling edge of the acknowledge signal that follows the LSDB[0] bit.
表 5. DACx0501 Data Byte
DATA BITS
COMMAND BITS
REGISTER
NOOP
LSDB
B3
B19 B18 B17 B16 B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B2
B1
B0
NOOP
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
NOOP
DEVID
0
RESOLUTION
0
0
1
0
RSTSEL
0
0
1
0
1
0
1
SYNC
RESERVED
REF-PWDWN
REF-DIV
DAC_SYNC_EN
DAC_PWDWN
BUF-GAIN
CONFIG
GAIN
RESERVED
RESERVED
RESERVED
RESERVED
LDAC
TRIGGER
STATUS
DAC DATA
SOFT-RESET [3:0]
REF-ALARM
RESERVED
DAC-DATA [15:0] for 16-bit, DAC-DATA [13:0] for 14-bit, DAC-DATA [11:0] for 12-bit, left aligned
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8.5.1.2.3 DACx0501 I2C Read Sequence
To read any register, use the following command sequence:
1. Send a start or repeated start command with a slave address and the R/W bit set to 0 for writing. The device acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the slave address and the R/W bit set to 1 for reading. The device acknowledges this event.
4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register.
An alternative reading method allows for reading back the value of the last register written. The sequence is a start or repeated start with the slave
address and the R/W bit set to 1, and the two bytes of the last register are read out. All the registers in DACx0501 family can be read out with the
exception of SOFT-RESET register. 表 5 shows the read command set.
表 6. Read Sequence
R/W
(0)
R/W
(1)
S
MSB
…
ACK
MSB
…
LSB
ACK
Sr
MSB
…
ACK
MSB
…
LSB
ACK
MSB
…
LSB
NACK
ADDRESS
BYTE
COMMAND
BYTE
ADDRESS
BYTE
Sr
MSDB
LSDB
From Master
Slave
From Master
Slave
From Master
Slave
From Slave
Master
From Slave
Master
30
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8.6 Register Map
Table 7. Register Map
OFFSET
0h
REGISTER NAME
NOOP
REGISTER DESCRIPTION
No operation
SECTION
NOOP Register
DEVID Register
SYNC Register
CONFIG Register
GAIN Register
1h
DEVID
Device identification
Synchronization
Configuration
2h
SYNC
3h
CONFIG
GAIN
4h
Gain
5h
TRIGGER
STATUS
DAC
Trigger
TRIGGER Register
STATUS Register
DAC Register
7h
Status
8h
Digital-to-analog converter
8.6.1 NOOP Register (offset = 0h) [reset = 0000h]
Figure 63. NOOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOOP
W-0h
Table 8. NOOP Register Field Descriptions
Bit
15-0
Field
No operation
Type
Reset
Description
W
0h
No Operation command
8.6.2 DEVID Register (offset = 1h)
Figure 64. DEVID Register
15
0
14
13
12
11
0
10
0
9
1
8
0
7
6
0
5
0
4
1
3
0
2
1
1
0
1
RESOLUTION
RSTSEL
0
R-0h R-0000h (DAC80501) R-0h
or 0001h (DAC70501)
R-0h
R-1h
R-0h
R-0h
(DACx0501Z)
or 1h
R-0h
R-0h
R-1h
R-0h
R-1h
R-0h
R-1h
or 0020h (DAC60501)
(DACx0501M)
Table 9. DEVID Register Field Descriptions
Bit
15
Field
Type
R
Reset
Description
RESERVED
RESOLUTION
0h
RESERVED
14-12
R
0000h
DAC Resolution:
(DAC80501)
0000h (DAC80501 16-bit)
0001h
0001h (DAC70501 14-bit)
(DAC70501)
0020h
0020h (DAC60501 12-bit)
(DAC60501)
11-8
7
RESERVED
RSTSEL
R
R
4h
0h
RESERVED
DAC Power on Reset:
(DAC80501Z) 0h (DAC80501Z reset to zero scale)
1h
1h (DAC80501M reset to midscale)
(DAC70501M)
6-0
RESERVED
015h
RESERVED
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8.6.3 SYNC Register (offset = 2h) [reset = 0000h]
Figure 65. SYNC Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
DAC_SYNC_EN
R/W-0h
Table 10. SYNC Register Field Descriptions
Bit
Field
RESERVED
DAC_SYNC_EN
Type
RW
Reset
0h
Description
15-1
0
RESERVED
RW
0h
When set to 1, the DAC output is set to update in response to
an LDAC trigger (synchronous mode).
When cleared to 0 ,the DAC output is set to update immediately
(asynchronous mode), default.
8.6.4 CONFIG Register (offset = 3h) [reset = 0000h]
Figure 66. CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
REF_PWDWN
R/W-0h
RESERVED
R/W-0h
DAC_PWDWN
R/W-0h
Table 11. CONFIG Register Field Descriptions
Bit
Field
Type
RW
RW
RW
RW
Reset
0h
Description
15-9
8
RESERVED
RESERVED
REF_PWDWN
RESERVED
0h
When set to 1, this bit disables the device internal reference.
RESERVED
7-1
0
0h
DAC_PWDWN
0h
When set to 1, the DAC in power-down mode and the DAC
output is connected to GND through a 1-kΩ internal resistor.
32
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DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
8.6.5 GAIN Register (offset = 4h) [reset = 0001h]
Figure 67. GAIN Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
REF-DIV
R/W-0h
RESERVED
R/W-0h
BUFF-GAIN
R/W-1h
Table 12. GAIN Register Field Descriptions
Bit
Field
Type
RW
Reset
0h
Description
15-9
8
RESERVED
REF-DIV
RESERVED
RW
0h
The reference voltage to the device (either from the internal or
external reference) can be divided by a factor of two by setting
the REF-DIV bit to 1. Make sure to configure REF-DIV so that
there is sufficient headroom from VDD to the DAC operating
reference voltage. Improper configuration of the reference
divider triggers a reference alarm condition. In the case of an
alarm condition, the reference buffer is shut down, and all the
DAC outputs go to 0 V. The DAC data registers are unaffected
by the alarm condition, and thus enable the DAC output to return
to normal operation after the reference divider is configured
correctly.
When REF-DIV set to 1, the reference voltage is internally
divided by a factor of 2.
When REF-DIV is cleared to 0, the reference voltage is
unaffected.
7-1
0
RESERVED
BUFF-GAIN
RW
RW
0h
1h
RESERVED
When set to 1, the buffer amplifier for corresponding DAC has a
gain of 2.
When cleared to 0, the buffer amplifier for corresponding DAC
has a gain of 1.
8.6.6 TRIGGER Register (offset = 5h) [reset = 0000h]
Figure 68. TRIGGER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
LDAC
W-0h
SOFT-RESET [3:0]
W-0h
Table 13. TRIGGER Register Field Descriptions
Bit
Field
Type
RW
W
Reset
0h
Description
15-5
4
RESERVED
LDAC
RESERVED
0h
Set this bit to 1 to synchronously load the DAC in synchronous
mode, This bit is self resetting.
3-0
SOFT-RESET [3:0]
W
0h
When set to the reserved code of 1010, this bit resets the device
to the default state. These bits are self resetting.
Copyright © 2018–2020, Texas Instruments Incorporated
33
DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
8.6.7 STATUS Register (offset = 7h) [reset = 0000h]
Figure 69. STATUS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
REF-ALARM
R-0h
Table 14. STATUS Register Field Descriptions
Bit
Field
Type
RW
R
Reset
0h
Description
15-1
0
RESERVED
REF-ALARM
RESERVED
0
REF-ALARM bit. Reads 1 when the difference between the
reference and supply pins is below a minimum analog threshold.
Reads 0 otherwise. When 1, the reference buffer is shut down,
and the DAC outputs are all zero volts. The DAC codes are
unaffected, and the DAC output returns to normal when the
difference is above the analog threshold.
8.6.8 DAC Register (offset = 8h) [reset = 0000h for DACx0501Z or reset = 8000h for DACx0501M]
Figure 70. DAC Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-DATA [15:0]
R/W-0000h (DACx0501Z) or 8000h (DACx0501M)
Table 15. DAC Register Field Descriptions
Bit
15-0
Field
DAC-DATA [15:0]
Type
Reset
Description
RW
0000h for
DACx0501Z
DAC data register.
Data are MSB aligned in straight binary format, and
use the following format:
8000h for
DACx0501M
DAC80501: DATA[15:0]
DAC70501: DATA[13:0], 0, 0
DAC60501: DATA[11:0], 0, 0, 0, 0
34
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DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications that incorporate analog circuits often require trimming, control, biasing, or a combination of all three.
These functions require high-accuracy, simple-to-implement compact solutions. The DACx0501 family of
precision DACs are an excellent choice for such applications. The DACx0501 tiny package, high resolution, and
simple interface makes these devices suitable for applications such as offset and gain control, VCO tuning,
programmable reference, and more. With the aforementioned features, this family of DACs caters to a wide
range of end equipment, such as battery testers, communications equipment, factory automation and control, test
and measurement, and more.
9.2 Typical Application
End equipment, such as oscilloscopes, battery test equipment, and other lab instruments require precision
calibration and control signals to tune the system accuracy. Precision DACs are typically used to generate these
signals. The complexity and accuracy of these systems are driving the need for multiple precision signals to be
generated in the system. The common approach for generating these signal is by using a multichannel DAC. An
alternative way to generate these signal is to use a single channel DAC with sample and hold circuit to produce
multichannel output. Using this approach, the users can generate customized number of channel instead of using
a fixed number of channels available in multichannel DACs.
RL
œ
SW
RS
VOUT0
DAC80501
+
CL
CH
RL
œ
SPI
SW
RS
VOUT1
+
CL
CH
MCU
RL
œ
SW
RS
VOUTN
SYNC
+
CL
CH
SEQUENCER
DEMUX
2-N
N
图 71. Multichannel Sample-and-Hold Circuit
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DAC80501, DAC70501, DAC60501
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
www.ti.com.cn
Typical Application (接下页)
9.2.1 Design Requirements
The design requirements for this circuit are as follows:
•
•
•
Output range: 0-V to 5-V
Channels: 10
Output offset error: ±3-mV
9.2.2 Detailed Design Procedure
A basic sample-and-hold circuit consists of a voltage source (DAC in this case), a switch, a capacitor, and a
buffer. As the name implies, this circuit has two modes of operation: sample and hold. In sample mode, the
switch is closed connecting the DAC output to the hold capacitor, CH. In hold mode, the switch opens,
disconnecting the DAC output from CH. Thus, the final output is held to the sampled value because of the charge
stored on hold capacitor CH. The output buffer is needed for delivering the required current. In a practical circuit,
the switch leakage and the amplifier bias current make the capacitor drift from the stored value. Therefore, the
sample-and-hold circuit must be refreshed, even if the DAC value does not change. The key design parameters
of a sample-and-hold circuit are charge injection and voltage droop.
9.2.2.1 Charge Injection
During the sample-to-hold transition, a small amount of charge is injected onto the hold capacitor, mostly
because of the stray capacitance of the switch that creates small level changes when transitioning between
states. The resulting dc offset is typically referred to as pedestal error. This error contributes to the offset error of
the system. The pedestal error, ΔVOUT, is the measured offset voltage resulting from charge injection when the
switch transitions to hold state. ΔVOUT is related to charge injection through 公式 2.
Q
DVOUT
=
C
where
•
•
Q is the injected charge coulombs.
C is the value of the hold capacitor in farads.
(2)
In most solid-state switch data sheets, charge injection is graphed with respect to supply voltage, analog input, or
temperature. A charge injection value of 3-pC is typical in many solid-state switches under the conditions: 25°C,
5-V supply, and 0-V analog input.
9.2.2.2 Voltage Droop
In hold mode, the voltage across CH that should have remained constant suffers a droop because of the leakage
resistance of the switch and the amplifier bias current. A simplified equation for calculating the voltage droop is
given by 公式 3
I
+ IBIAS
(
)
DV
Dt
LEAK
=
C
where
•
•
•
ILEAK is the leakage current through the switch in amperes.
IBIAS is the bias current of the amplifier in amperes.
C is the value of the hold capacitance in farads.
(3)
36
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DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
Typical Application (接下页)
9.2.2.3 Output Offset Error
The output offset error of an sample-and-hold channel is the cumulative error contributed by the DAC offset error,
amplifier offset error, and sample-and-hold pedestal error due to charge injection. The amplifier offset error can
be made negligible by choosing a low-offset amplifier such as the OPA4317. The OPA4317 has an offset error of
0.1-mV max. The DAC80501 has a max offset error of ±1.5-mV. Thus, in order to achieve an total offset error
less than ±3-mV, the offset error contributed by the sample-and-hold circuit must be limited to ±1.5-mV.
Considering the bias current of 300-pA in the OPA4317, and a typical switch leakage current of 1-nA, a 2-nF hold
capacitor results in a droop rate of 0.65 V/s. When the sample-and-hold circuit refreshes at a rate of more than
100-µs, the voltage droop is 65-µV. This small offset error can be ignored for the simplicity of calculation. Thus,
the only contributor to the sample-and-hold offset error is the pedestal error. For a charge injection of 3-pC and a
pedestal error of 1.5-mV, the value of the hold capacitor is calculated as 2-nF, according to 公式 2. A capacitive
load of 2-nF can be handled by the DAC80501. The switch on resistance and optional series resistance RS
further helps in the stability of the DAC output amplifier. RS can be omitted for better settling time.
9.2.2.4 Switch Selection
The switch in the design must feature low on-state resistance and low off leakage, and must conduct rail-to-rail
analog signals. Very low charge injection is also a primary factor for selecting the switch. The TS12A4515 are
single pole and single throw (SPST), low-voltage, single-supply CMOS analog switches with 20-Ω on-state
resistance, 3 pC of charge-injection (5-V supply), and an off-Leakage current value of 1 nA.
9.2.2.5 Amplifier Selection
The key parameters for the amplifier in this system are low offset voltage and low input bias current. The
OPA4317 is a quad amplifier that has a max offset voltage of 100 µV and a max bias current of 300 pA. As a
result of the quad package, less board area is used.
9.2.2.6 Hold Capacitor Selection
Use a hold capacitor that has high insulation resistance, low temperature coefficient, and low dielectric
absorption. Low temperature coefficient NP0/C0G ceramic capacitors are a great choice for this purpose. As
calculated in 公式 2, a 2-nF capacitor provides a total offset error of ±3 mV per channel.
9.2.3 Application Curves
图 72. Sample-and-Hold Pedestal Error With 3-pC Charge Injection
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DAC80501, DAC70501, DAC60501
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www.ti.com.cn
10 Power Supply Recommendations
The DACx0501 operate within the specified VDD supply range of 2.7 V to 5.5 V. The DACx0501 do not require
specific supply sequencing.
The VDD supply must be well regulated and low noise. Switching power supplies and DC/DC converters often
have high-frequency glitches or spikes riding on the output voltage. In addition, digital components create similar
high-frequency spikes. This noise can easily couple into the DAC output voltage through various paths between
the power connections and analog output. To further minimize noise from the power supply, include a 1-μF to 10-
μF capacitor and 0.1-μF bypass capacitor. The current consumption on the VDD pin, the short-circuit current
limit, and the load current for the device is listed in the Electrical Characteristics section. The power supply must
meet the aforementioned current requirements.
11 Layout
11.1 Layout Guidelines
A precision analog component requires careful layout. The following list provides some insight into good layout
practices.
•
•
•
•
Bypass the VDD to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass
capacitance is 0.1-µF to 0.22-µF ceramic capacitor, with a X7R or NP0 dielectric.
Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize
performance.
Use a high-quality, ceramic-type NP0 or X7R for optimal performance across temperature, and a very low
dissipation factor.
The digital and analog sections must have proper placement with respect to the digital pins and analog pins
of the DACx0501 devices. The separation of analog and digital blocks minimizes coupling into neighboring
blocks, as well as interaction between analog and digital return currents.
11.2 Layout Example
GND
Decoupling
Capacitor
GND
Reference
Bypass
Capacitor
Optional
REFIN or
REFOUT
DACx0501
VDD
1
2
3
4
8
7
6
5
SDIN/SDA
VOUT
Pull-up
GND
VDD
SYNC/A0
SCLK/SCL
Pull-down for
SPI Mode
(Note: Ground and Power planes omitted for clarity)
图 73. Layout Example
38
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DAC80501, DAC70501, DAC60501
www.ti.com.cn
ZHCSJ19D –NOVEMBER 2018–REVISED FEBRUARY 2020
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：德州仪器 (TI)，DAC80501EVM 用户指南
12.2 相关链接
表 16 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具与软件，以及申请样片或购买产品的快速
链接。
表 16. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
DAC80501
DAC70501
DAC60501
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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39
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC60501MDGSR
DAC60501MDGST
DAC60501MDQFR
DAC60501MDQFT
DAC60501ZDGSR
DAC60501ZDGST
DAC60501ZDQFR
DAC60501ZDQFT
DAC70501MDGSR
DAC70501MDGST
DAC70501MDQFR
DAC70501MDQFT
DAC70501ZDGSR
DAC70501ZDGST
DAC70501ZDQFR
DAC70501ZDQFT
DAC80501MDGSR
DAC80501MDGST
DAC80501MDQFR
DAC80501MDQFT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
DGS
DGS
DQF
DQF
DGS
DGS
DQF
DQF
DGS
DGS
DQF
DQF
DGS
DGS
DQF
DQF
DGS
DGS
DQF
DQF
10
10
8
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
651M
651M
651M
651M
651Z
651Z
651Z
651Z
751M
751M
751M
751M
751Z
751Z
751Z
751Z
851M
851M
851M
851M
NIPDAUAG
NIPDAU
8
NIPDAU
10
10
8
NIPDAUAG
NIPDAUAG
NIPDAU
8
NIPDAU
10
10
8
NIPDAUAG
NIPDAUAG
NIPDAU
8
NIPDAU
10
10
8
NIPDAUAG
NIPDAUAG
NIPDAU
8
NIPDAU
10
10
8
NIPDAUAG
NIPDAUAG
NIPDAU
8
250
RoHS & Green
NIPDAU
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC80501ZDGSR
DAC80501ZDGST
DAC80501ZDQFR
DAC80501ZDQFT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
WSON
WSON
DGS
DGS
DQF
DQF
10
10
8
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
851Z
851Z
851Z
851Z
NIPDAUAG
NIPDAU
8
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC60501MDGSR
DAC60501MDGST
DAC60501MDQFR
DAC60501MDQFT
DAC60501ZDGSR
DAC60501ZDGST
DAC60501ZDQFR
DAC60501ZDQFT
DAC70501MDGSR
DAC70501MDGST
DAC70501MDQFR
DAC70501MDQFT
DAC70501ZDGSR
DAC70501ZDGST
DAC70501ZDQFR
DAC70501ZDQFT
DAC80501MDGSR
DAC80501MDGST
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
DGS
DGS
DQF
DQF
DGS
DGS
DQF
DQF
DGS
DGS
DQF
DQF
DGS
DGS
DQF
DQF
DGS
DGS
10
10
8
2500
250
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
12.4
12.4
8.4
5.3
5.3
2.2
2.2
5.3
5.3
2.2
2.2
5.3
5.3
2.2
2.2
5.3
5.3
2.2
2.2
5.3
5.3
3.4
3.4
2.2
2.2
3.4
3.4
2.2
2.2
3.4
3.4
2.2
2.2
3.4
3.4
2.2
2.2
3.4
3.4
1.4
1.4
1.2
1.2
1.4
1.4
1.2
1.2
1.4
1.4
1.2
1.2
1.4
1.4
1.2
1.2
1.4
1.4
8.0
8.0
4.0
4.0
8.0
8.0
4.0
4.0
8.0
8.0
4.0
4.0
8.0
8.0
4.0
4.0
8.0
8.0
12.0
12.0
8.0
Q1
Q1
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q1
3000
250
8
8.4
8.0
10
10
8
2500
250
12.4
12.4
8.4
12.0
12.0
8.0
3000
250
8
8.4
8.0
10
10
8
2500
250
12.4
12.4
8.4
12.0
12.0
8.0
3000
250
8
8.4
8.0
10
10
8
2500
250
12.4
12.4
8.4
12.0
12.0
8.0
3000
250
8
8.4
8.0
10
10
2500
250
12.4
12.4
12.0
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC80501MDQFR
DAC80501MDQFT
DAC80501ZDGSR
DAC80501ZDGST
DAC80501ZDQFR
DAC80501ZDQFT
WSON
WSON
VSSOP
VSSOP
WSON
WSON
DQF
DQF
DGS
DGS
DQF
DQF
8
8
3000
250
180.0
180.0
330.0
330.0
180.0
180.0
8.4
8.4
2.2
2.2
5.3
5.3
2.2
2.2
2.2
2.2
3.4
3.4
2.2
2.2
1.2
1.2
1.4
1.4
1.2
1.2
4.0
4.0
8.0
8.0
4.0
4.0
8.0
8.0
Q2
Q2
Q1
Q1
Q2
Q2
10
10
8
2500
250
12.4
12.4
8.4
12.0
12.0
8.0
3000
250
8
8.4
8.0
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC60501MDGSR
DAC60501MDGST
DAC60501MDQFR
DAC60501MDQFT
DAC60501ZDGSR
DAC60501ZDGST
DAC60501ZDQFR
DAC60501ZDQFT
DAC70501MDGSR
DAC70501MDGST
DAC70501MDQFR
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
DGS
DGS
DQF
DQF
DGS
DGS
DQF
DQF
DGS
DGS
DQF
10
10
8
2500
250
366.0
366.0
213.0
213.0
366.0
366.0
213.0
213.0
366.0
366.0
213.0
364.0
364.0
191.0
191.0
364.0
364.0
191.0
191.0
364.0
364.0
191.0
50.0
50.0
35.0
35.0
50.0
50.0
35.0
35.0
50.0
50.0
35.0
3000
250
8
10
10
8
2500
250
3000
250
8
10
10
8
2500
250
3000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC70501MDQFT
DAC70501ZDGSR
DAC70501ZDGST
DAC70501ZDQFR
DAC70501ZDQFT
DAC80501MDGSR
DAC80501MDGST
DAC80501MDQFR
DAC80501MDQFT
DAC80501ZDGSR
DAC80501ZDGST
DAC80501ZDQFR
DAC80501ZDQFT
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
DQF
DGS
DGS
DQF
DQF
DGS
DGS
DQF
DQF
DGS
DGS
DQF
DQF
8
10
10
8
250
2500
250
213.0
366.0
366.0
213.0
213.0
366.0
366.0
213.0
213.0
366.0
366.0
213.0
213.0
191.0
364.0
364.0
191.0
191.0
364.0
364.0
191.0
191.0
364.0
364.0
191.0
191.0
35.0
50.0
50.0
35.0
35.0
50.0
50.0
35.0
35.0
50.0
50.0
35.0
35.0
3000
250
8
10
10
8
2500
250
3000
250
8
10
10
8
2500
250
3000
250
8
Pack Materials-Page 3
PACKAGE OUTLINE
DQF0008A
WSON - 0.8 mm max height
S
C
A
L
E
6
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.05 C
0.05
0.00
SYMM
(0.2) TYP
4
5
SYMM
2X 1.5
6X 0.5
8
1
0.3
8X
0.2
0.1
0.05
0.7
0.5
C A B
PIN 1 ID
0.6
0.4
7X
4220563/A 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DQF0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SEE SOLDER MASK
DETAIL
SYMM
(0.8)
8
8X (0.25)
1
SYMM
6X (0.5)
(R0.05) TYP
4
5
7X (0.7)
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220563/A 03/2021
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DQF0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.8)
8X (0.25)
1
8
SYMM
6X (0.5)
(R0.05) TYP
5
4
SYMM
(1.7)
7X (0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 30X
4220563/A 03/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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