DAC61402 [TI]

具有精密内部基准的双通道、12 位、±20V 电压范围、缓冲输出 DAC;


型号：	DAC61402
厂家：	TEXAS INSTRUMENTS
描述：	具有精密内部基准的双通道、12 位、±20V 电压范围、缓冲输出 DAC
文件：	总55页 (文件大小：5253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC81402, DAC61402

ZHCSLN9A –OCTOBER 2020 –REVISED MAY 2021

具有内部基准的DACx1402 双路16 位和12 位高压输出DAC

1 特性

3 说明

• 性能：

16 位 DAC81402 和 12 位 DAC61402 (DACx1402) 是

引脚兼容的双通道缓冲式高压输出数模转换器

(DAC)。这些器件包括一个低漂移 2.5V 内部电压基

准，因此在大多数应用中无需使用外部精密基准。这些

器件具有单调性，并能提供 ±1LSB INL 的高线性度。

此外，这些器件采用每通道检测引脚来消除 IR 压降并

可检测高达±12V 的地弹。

– 在16 位分辨率下具有单调性

– INL：16 位分辨率下为±1LSB（最大值）

– TUE：±0.05% FSR（最大值）

• 集成输出缓冲器

– 满量程输出电压：±5V、±10V、±20V、5V、

10V、20V、40V

– 高驱动能力：±15mA

– 每通道检测引脚

• 集成2.5V 精密基准

用户可自行选择输出配置，包括满量程双极输出电压

±20V、±10V 和 ±5V，以及满量程非双极输出电压

40V、20V、10V 和 5V。而且，每个 DAC 通道的满量

程输出范围都是独立可编程的。集成的 DAC 输出缓冲

器可实现高达 15mA 的灌电流或拉电流，从而减少了

对额外的运算放大器的需求。

– 初始精度：±2.5mV（最大值）

– 低漂移：10ppm/°C（最大值）

• 可靠性特性：

– CRC 误差校验

– 短路限制

– 故障引脚

DACx1402 包含的上电复位电路可在上电时将 DAC 输

出端连接至接地端。输出端会保持该模式，直至器件得

到适当的运行配置。这些器件还包括其他可靠性特性，

例如CRC 误差校验、短路保护以及过热报警。

• 50MHz SPI 兼容型串行接口

– 4 线制模式，工作电压为1.7V 至5.5V

– 回读和菊链运行方式

• 温度范围：–40°C 至+125°C

• 封装：5mm × 5mm 32 引脚QFN

通过一个支持 1.7V 至 5.5V 工作电压的 4 线制串行接

口，支持器件间通信。

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

DAC81402

DAC61402

2 应用

• 伺服驱动器控制模块

• 模拟输出模块

VQFN (32)

5.00mm × 5.00mm

• 实验室和现场仪表

• 数据采集(DAQ)

• 半导体测试

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

IOVDD DVDD

FAULT

REFIO

AVDD

R_LIMIT

SENSEP

Internal Reference

Ccomp

DAC61402

CCOMP

Power On

Reset

REF

BUF

SCLK

SDIN

R_LIMIT

VOUT

IO Protection

Cable

Driver

Stage

DAC Ladder

REF

SYNC

SENSEN

DAC

Ladder

Buffer

Active

CCOMP[A:B]

OUT[A:B]

SDO

Motor

LDAC

RST

Position

Encoder

40 kΩ

SENSEP[A:B]

SENSEN[A:B]

40 kΩ

CLR

Analog Output Module

Motor Control Module

Channel

40 kΩ

电机驱动器应用

Resistor Gain

Network

REF

GND

AGND

REFGND

AVSS

功能方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASEH3

DAC81402, DAC61402

ZHCSLN9A –OCTOBER 2020 –REVISED MAY 2021

www.ti.com.cn

Table of Contents

7.13 Typical Characteristics............................................17

8 Detailed Description......................................................25

8.1 Overview...................................................................25

8.2 Functional Block Diagram.........................................25

8.3 Feature Description...................................................26

8.4 Device Functional Modes..........................................30

8.5 Programming............................................................ 31

8.6 Register Map.............................................................34

9 Application and Implementation..................................41

9.1 Application Information............................................. 41

9.2 Typical Application.................................................... 41

10 Power Supply Recommendations..............................44

11 Layout...........................................................................44

11.1 Layout Guidelines................................................... 44

11.2 Layout Example...................................................... 44

12 Device and Documentation Support..........................45

12.1 Documentation Support.......................................... 45

12.2 接收文档更新通知................................................... 45

12.3 支持资源..................................................................45

12.4 Trademarks.............................................................45

12.5 静电放电警告.......................................................... 45

12.6 术语表..................................................................... 45

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 Recommended Operating Conditions ........................6

7.4 Thermal Information ...................................................6

7.5 Electrical Characteristics ............................................7

7.6 Timing Requirements: Write, IOV_DD: 1.7 V to 2.7

V .................................................................................13

7.7 Timing Requirements: Write, IOV_DD: 2.7 V to 5.5

V .................................................................................13

7.8 Timing Requirements: Read and Daisy Chain,

FSDO = 0, IOV_DD: 1.7 V to 2.7 V ............................... 14

7.9 Timing Requirements: Read and Daisy Chain,

FSDO = 1, IOV_DD: 1.7 V to 2.7 V ............................... 14

7.10 Timing Requirements: Read and Daisy Chain,

FSDO = 0, IOV_DD: 2.7 V to 5.5 V ............................... 15

7.11 Timing Requirements: Read and Daisy Chain,

FSDO = 1, IOV_DD: 2.7 V to 5.5 V ............................... 15

7.12 Timing Diagrams.....................................................16

Information.................................................................... 45

4 Revision History

Changes from Revision * (November 2020) to Revision A (May 2021)

Page

• 添加了DAC81402 和相关内容........................................................................................................................... 1

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5 Device Comparison Table

DEVICE

RESOLUTION

16-Bit

DAC81402

DAC61402

12-Bit

6 Pin Configuration and Functions

Thermal pad

SENSENA

SENSEPA

CCOMPA

OUTA

SENSENB

SENSEPB

CCOMPB

OUTB

Not to scale

图6-1. RHB (32-pin VQFN) Package, Top View

表6-1. Pin Functions

TYPE

DESCRIPTION

NO.

NAME

No connection.

—

SENSENA

SENSEPA

Input

Channel-A sense pin for the negative voltage output load connection.

Channel-A sense pin for the positive voltage output load connection.

Channel-A external compensation capacitor connection pin.

The addition of an external capacitor improves the output buffer stability with high capacitive

loads at the OUTA pin by reducing the bandwidth of the output amplifier at the expense of

increased settling time.

CCOMPA

OUTA

SDO

Input

Output

Input

Channel-A analog output voltage.

Serial interface data output.

The SDO pin must be enabled before operation by setting the SDO-EN bit. Data are clocked out

of the input shift register on either rising or falling edges of the SCLK pin as specified by the

FSDO bit (rising edge by default).

SCLK

Serial interface clock.

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表6-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

Serial interface data input. Data are clocked into the input shift register on each falling edge of the

SCLK pin.

SDIN

Input

Active low serial data enable. This input is the frame synchronization signal for the serial data.

The serial serial interface input shift register is enabled when SYNC is low.

SYNC

LDAC

Active low synchronization signal. The DAC outputs of those channels configured in synchronous

mode are updated simultaneously when the LDAC pin is low. Connect to IOVDD if unused.

GND

Ground

Power

Digital ground reference point.

IOVDD

IO supply voltage. This pin sets the digital I/O operating voltage for the device.

Active-low clear input. Logic low on this pin clears all outputs to their clear code. Connect to

IOVDD if unused.

CLR

Input

OUTB

Output

Channel-B analog output voltage.

Channel-B external compensation capacitor connection pin.

The addition of an external capacitor improves the output buffer stability with high capacitive

loads at the OUTB pin by reducing the bandwidth of the output amplifier at the expense of

increased settling time.

CCOMPB

Input

SENSEPB

SENSENB

Input

Channel-B sense pin for the positive voltage output load connection.

Channel-B sense pin for the negative voltage output load connection.

No connection.

—

No connection.

—

No connection.

—

REFGND

Ground

Ground reference point for the internal reference.

Reference input to the device when operating with an external reference. Reference output

voltage pin when using the internal reference. Connect a 150-nF capacitor to ground.

REFIO

Input/Output

AVSS

AVDD

AGND

DVDD

Power

Ground

Power

Output buffers negative supply voltage.

Output buffers positive supply voltage.

Analog ground reference point.

Digital and analog supply voltage.

FAULT is an open-drain, fault-condition output. An external 10-kΩpullup resistor to a voltage no

higher than IOV_DDis required.

FAULT

RST

Output

Input

—

Active-low reset input. Logic low on this pin causes the device to issue a power-on-reset event.

Thermal

Pad

The thermal pad is located on the package underside. The thermal pad should be connected to

any internal PCB ground plane through multiple vias for good thermal performance.

Thermal pad

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

DV_DDto GND

IOV_DDto GND

–0.3

Supply voltage

AV_DDto GND

–0.3

AV_SSto GND

0.3

–22

AV_DDto AV_SS

–0.3

V_OUTXto GND

AV_DD+ 0.3

DV_DD+ 0.3

+0.3

AV_SS–0.3

–0.3

V_SENSEPXto GND

V_SENSENXto GND

V_REFIOto GND

Pin voltage

V_REFGNDto GND

Digital inputs to GND

SDO to GND

–0.3

IOV_DD+ 0.3

–0.3

FAULT to GND

Current into any digital pin

–0.3

Input current

°C

–10

T_J

Junction temperature

Storage temperature

150

–40

T_stg

150

°C

–60

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001⁽¹⁾

±1000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per

JEDEC specification JESD22-C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

MAX

UNIT

DV_DDto GND

IOV_DDto GND

5.5

41.5

1.7

AV_DDto GND

AV_SSto GND

AV_DDto AV_SS

V_SENSENXto GND

4.5

Supply voltage

–21.5

4.5

Pin voltage

–12

–40

T_A

Ambient temperature

125

°C

7.4 Thermal Information

DACx1402

THERMAL METRIC⁽¹⁾

RHB (VQFN)

32 PINS

29.3

UNIT

R_ΘJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

℃/W

R_ΘJC(top)

R_ΘJB

17.0

9.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JT

9.5

Ψ_JB

R_ΘJC(bot)

1.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics

all minimum/maximum specifications at T_A= –40°C to +125°C and all typical specifications at T_A= 25°C, AV_DD= 4.5 V to

41.5 V, AV_SS= –21.5 V to 0 V, DV_DD= 5.0 V, internal reference enabled, IOV_DD= 1.7 V, V_SENSENX= 0 V, C_COMPXfloating,

DAC outputs unloaded, and digital inputs at IOV_DDor GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STATIC PERFORMANCE

DAC81402

Resolution

Bits

DAC61402

DAC81402. All ranges, except 0-V to

40-V and overranges

–1

INL

Relative accuracy⁽¹⁾

LSB

DAC81402. 0-V to 40-V range

DAC61402

–2

–1

DNL

Differential nonlinearity⁽¹⁾

–1

Unipolar ranges, AV_SS= 0 V

0.07

–0.07

Unipolar ranges, AV_SS= 0 V,

0℃≤T_A≤50℃

0.05

–0.05

TUE

Total unadjusted error⁽¹⁾

%FSR

Bipolar ranges, –21.5 V ≤AV_SS< 0

Unipolar ranges, AV_SS= 0 V

Bipolar ranges, –21.5 V ≤AV_SS< 0

Offset error⁽¹⁾

0.05

%FSR

–0.05

Unipolar ranges, AV_SS= 0 V

Offset error temperature coefficient

±2

ppmFSR/°C

Bipolar ranges, –21.5 V ≤AV_SS< 0

All unipolar ranges, AV_SS= 0 V

0.15

0.05

Zero-code (negative full scale) error

%FSR

All bipolar ranges,

–21.5 V ≤AV_SS< 0 V

All unipolar ranges, AV_SS= 0 V

All bipolar ranges,

–21.5 V ≤AV_SS< 0 V

Zero-code (negative full scale) error

temperature coefficient

ppm of

FSR/°C

Full-scale error⁽²⁾

0.06

%FSR

–0.06

Full-scale error temperature

coefficient⁽²⁾

ppm of

FSR/°C

±3

±2

Gain error⁽¹⁾

%FSR

ppm of

FSR/°C

Gain error temperature coefficient

All bipolar ranges,

–21.5 V ≤AV_SS< 0 V

Bipolar-zero (midscale) error

0.03

%FSR

–0.03

All bipolar ranges,

–21.5 V ≤AV_SS< 0 V

Bipolar-zero (midscale) error

temperature coefficient

ppm of

FSR/°C

±2

±6

T_A= 40℃, DAC code = full scale,

1000 hours

Output voltage drift over time

ppm FSR

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7.5 Electrical Characteristics (continued)

all minimum/maximum specifications at T_A= –40°C to +125°C and all typical specifications at T_A= 25°C, AV_DD= 4.5 V to

41.5 V, AV_SS= –21.5 V to 0 V, DV_DD= 5.0 V, internal reference enabled, IOV_DD= 1.7 V, V_SENSENX= 0 V, C_COMPXfloating,

DAC outputs unloaded, and digital inputs at IOV_DDor GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT CHARACTERISTICS

20% overrange

V_OUT

Output voltage

-5

20% overrange

-6

–10

–12

–20

to AV_SSand AV_DD

−10 mA ≤load current ≤10 mA

1.25

Output voltage headroom and

footroom

to AV_SSand AV_DD

5.5 V < AV_DD≤41.5 V,

1.5

−15 mA ≤load current ≤15 mA

Full-scale output shorted to AV_SS

Zero-scale output shorted to AV_DD

5.5 V < AV_DD≤41.5 V,

Short circuit current⁽³⁾

Zero-scale output shorted to AV_DD

4.5 V ≤AV_DD≤5.5 V

DAC at midscale,

−15 mA ≤load current ≤15 mA

Load regulation

µV/mA

R_LOAD= open, C_COMPXpin left floating

C_L

Capacitive load⁽⁴⁾

R_LOAD= open,

C_COMPX= 500 pF ± 10% to V_OUTX

µF

5.5 V < AV_DD≤41.5 V

Load current⁽⁴⁾

4.5 V ≤AV_DD≤5.5 V

DAC code at midscale, DAC unloaded

DAC code at full scale, DAC unloaded

0.05

V_OUTdc output impedance

DAC code at negative full scale,

DAC unloaded

DAC code at midscale, 10-V span

DAC disabled

V_SENSEPdc output impedance

V_SENSENdc output impedance

kΩ

DAC code at midscale, 10-V span

DAC disabled

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7.5 Electrical Characteristics (continued)

all minimum/maximum specifications at T_A= –40°C to +125°C and all typical specifications at T_A= 25°C, AV_DD= 4.5 V to

41.5 V, AV_SS= –21.5 V to 0 V, DV_DD= 5.0 V, internal reference enabled, IOV_DD= 1.7 V, V_SENSENX= 0 V, C_COMPXfloating,

DAC outputs unloaded, and digital inputs at IOV_DDor GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DYNAMIC PERFORMANCE

5-V span, 1/4 to 3/4 scale and 3/4 to

1/4 scale, settling time to ±2 LSB

10-V span, 1/4 to 3/4 scale and 3/4 to

1/4 scale, settling time to ±2 LSB

µs

20-V span, 1/4 to 3/4 scale and 3/4 to

1/4 scale, settling time to ±2 LSB

40-V span, 1/4 to 3/4 scale and 3/4 to

1/4 scale, settling time to ±2 LSB

5-V span, 1/4 to 3/4 scale and 3/4 to

1/4 scale, settling time to ±2 LSB,

C_L= 1 µF, C_COMPX= 500 pF to V_OUTX

0.6

1.2

Output voltage settling time

10-V span, 1/4 to 3/4 scale and 3/4 to

1/4 scale, settling time to ±2 LSB,

C_L= 1 µF, C_COMPX= 500 pF to V_OUTX

20-V span, 1/4 to 3/4 scale and 3/4 to

1/4 scale, settling time to ±2 LSB,

C_L= 1 µF, C_COMPX= 500 pF to V_OUTX

40-V span, 1/4 to 3/4 scale and 3/4 to

1/4 scale, settling time to ±2 LSB,

C_L= 1 µF, C_COMPX= 500 pF to V_OUTX

0-V to 5-V range (10% to 90% of full-

scale range)

0.8

All other output ranges except 40-V

span (10% to 90% of full-scale range)

Slew rate

V/µs

0-V to 5-V range, C_L= 1 µF,

C_COMPX= 500 pF to V_OUTX

0.04

All other ranges, C_L= 1 µF,

C_COMPX= 500 pF to V_OUTX

AV_SSand AV_DDramped symmetrically,

ramp rate = 18 V/ms, output unloaded,

internal reference

Power-on glitch magnitude

0.1

0.35

AV_SSand AV_DDramped, output

unloaded, internal reference, gain = 1x

Output enable glitch magnitude

0.1 Hz to 10 Hz, DAC code at

midscale, 5-V span, external reference

= 2.5 V, output unloaded

Output noise

µV_PP

0.1 Hz to 10 Hz, DAC code at

midscale, 5-V span, internal reference

= 2.5 V, output unloaded

1 kHz, DAC code at midscale, 5-V

span, output unloaded, external

reference

115

Output noise density

nV/√Hz

10 kHz, DAC code at midscale, 5-V

span, output unloaded, external

reference

105

1-kHz sine wave on V_OUTX, output

unloaded, DAC update rate = 400 kHz

THD

Total harmonic distortion

V_OUTX= 0 V (midscale), output

unloaded, ±10-V output,

frequency = 60 Hz,

PSRR-AC

Power supply ac rejection ratio

amplitude 200 mV_PP

superimposed on AV_DD, DV_DDor AV_SS

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7.5 Electrical Characteristics (continued)

all minimum/maximum specifications at T_A= –40°C to +125°C and all typical specifications at T_A= 25°C, AV_DD= 4.5 V to

41.5 V, AV_SS= –21.5 V to 0 V, DV_DD= 5.0 V, internal reference enabled, IOV_DD= 1.7 V, V_SENSENX= 0 V, C_COMPXfloating,

DAC outputs unloaded, and digital inputs at IOV_DDor GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OUTX= 0 V (midscale), ±10-V output,

DV_DD= 5 V, AV_DD= 15 V ± 20%,

AV_SS= –15 V, output unloaded

µV/V

V_OUTX= 0 V (midscale), ±10-V output,

DV_DD= 5 V, AV_DD= 15 V,

AV_SS= –15 V ± 20%, output

unloaded

PSRR-DC

Power supply dc rejection ratio

V_OUTX= 0 V (midscale), ±10-V output,

DV_DD= 5 V ± 5%, AV_DD= 15 V,

AV_SS= –15 V, output unloaded

0.2

mV/V

nV-s

1-LSB change around midscale,

0-V to 5-V range, output unloaded

1-LSB change around midscale,

0-V to 10-V range, output unloaded

Code change glitch impulse

1-LSB change around midscale,

–5-V to +5-V range, output unloaded

1-LSB change around midscale,

–10-V to +10-V range, output

unloaded

1-LSB change around midscale,

0-V to 5-V, 0-V to 10-V, –5-V to +5-V

and –10-V to +10-V ranges, output

unloaded

Code change glitch amplitude

±10

10-V span, full-scale swing on all other

channel, measured channel at

midscale, output unloaded

Channel-to-channel ac crosstalk

Channel-to-channel dc crosstalk

nV-s

LSB

10-V span, full-scale swing on all other

channel, measured channel at

midscale, output unloaded

10-V span, full-scale swing on all other

input buffer, measured channel at

midscale, output unloaded

Digital crosstalk

nV-s

DAC code at midscale, f_SCLK= 1 MHz,

output unloaded

Digital feedthrough

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7.5 Electrical Characteristics (continued)

all minimum/maximum specifications at T_A= –40°C to +125°C and all typical specifications at T_A= 25°C, AV_DD= 4.5 V to

41.5 V, AV_SS= –21.5 V to 0 V, DV_DD= 5.0 V, internal reference enabled, IOV_DD= 1.7 V, V_SENSENX= 0 V, C_COMPXfloating,

DAC outputs unloaded, and digital inputs at IOV_DDor GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EXTERNAL REFERENCE INPUT

V_REFIO

Reference input voltage

Reference input current

Reference input impedance

Reference input capacitance

2.49

2.5

2.51

µA

kΩ

INTERNAL REFERENCE

Reference output voltage

T_A= 25°C

2.4975

2.5025

Reference output drift

0.15

ppm/°C

Reference output impedance

Reference output noise

0.1 Hz to 10 Hz

µV_PP

Reference output noise density

Reference load current

10 kHz, V_REFIO= 10 nF

240

nV/√Hz

Reference load regulation

Reference line regulation

Reference output drift over time

Source

120

100

±300

±125

±25

µV/mA

µV/V

µV

T_A= 40°C, 1000 hours

First cycle

Reference thermal hysteresis

µV

Additional cycle

DIGITAL INPUTS AND OUTPUTS

0.7 × IO

V_DD

V_IH

V_IL

Input high voltage

Input low voltage

0.3

× IOV_DD

Input current

±2

µA

Input pin capacitance

IOV_DD

–0.2

V_OH

V_OL

SDO, high-level output voltage

SDO load current = 0.2 mA

SDO, low-level output voltage

FAULT, low-level output voltage

Output pin capacitance

SDO load current = 0.2 mA

FAULT load current = 10 mA

0.4

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7.5 Electrical Characteristics (continued)

all minimum/maximum specifications at T_A= –40°C to +125°C and all typical specifications at T_A= 25°C, AV_DD= 4.5 V to

41.5 V, AV_SS= –21.5 V to 0 V, DV_DD= 5.0 V, internal reference enabled, IOV_DD= 1.7 V, V_SENSENX= 0 V, C_COMPXfloating,

DAC outputs unloaded, and digital inputs at IOV_DDor GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER REQUIREMENTS

Normal mode, internal reference

Normal mode, external reference

Power-down mode

AI_DD

DI_DD

AV_DDsupply current⁽⁵⁾

DV_DDsupply current⁽⁵⁾

µA

Digital interface static

Normal mode, internal reference

Normal mode, external reference

Power-down mode

–8

–7

AI_SS

AV_SSsupply current⁽⁵⁾

IOV_DDsupply current⁽⁵⁾

µA

–10

I_IOVDD

SCLK toggling at 1 MHz

100

(1) End point fit between codes. 16-bit: 512 to 65024 for AV_DD≥5.5 V, 512 to 63488 for AV_DD≤5.5 V, 0.2-V headroom between V_REFIO

and AV_DD; 12-bit: 32 to 4064 for AV_DD≥5.5 V, 32 to 3968 for AV_DD≤5.5 V, 0.2-V headroom between V_REFIOand AV_DD

(2) Full-scale code written to the DAC for AV_DD≥5.5 V. 16-bit: code 63488 written to the DAC for AV_DD≤5.5 V; 12-bit: code 3968 written

to the DAC for AV_DD≤5.5 V.

(3) Temporary overload condition protection. junction temperature can be exceeded during current limit. operation above the specified

maximum junction temperature may impair device reliability.

(4) Specified by design and characterization, not production tested.

(5) AV_DD= +15 V, AV_SS= –15 V, DV_DD= 5 V, SPI static, 10-V output span, all DAC at full scale, V_OUTXunloaded.

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7.6 Timing Requirements: Write, IOV_DD: 1.7 V to 2.7 V

all specifications at T_A= –40°C to +125°C, input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of IOV_DD) and timed

from a voltage level of (V_IL+ V_IH) / 2, SDO loaded with 20 pF, 1.7 V ≤IOV_DD< 2.7 V

PARAMETER

MIN

NOM

MAX

UNIT

MHz

f_SCLK

SCLK frequency

SCLK high time

SCLK low time

SDIN setup

t_SCLKHIGH

t_SCLKLOW

t_SDIS

2.4

t_SDIH

SDIN hold

t_CSS

SYNC to SCLK falling edge setup

SCLK falling edge to SYNC rising edge

SYNC high time

t_CSH

t_CSHIGH

t_DACWAIT

t_BCASTWAIT

t_LDACAL

t_LDACW

t_CLRW

Sequential DAC update wait time

Broadcast DAC update wait time

SYNC rising edge to LDAC falling edge

LDAC low time

µs

CLR low time

t_RSTW

RST low time

7.7 Timing Requirements: Write, IOV_DD: 2.7 V to 5.5 V

all specifications at T_A= –40°C to +125°C, input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of IOV_DD) and timed

from a voltage level of (V_IL+ V_IH) / 2, SDO loaded with 20 pF, 2.7 V ≤IOV_DD≤5.5 V

PARAMETER

MIN

NOM

MAX

UNIT

MHz

f_SCLK

SCLK frequency

SCLK high time

SCLK low time

SDIN setup

t_SCLKHIGH

t_SCLKLOW

t_SDIS

t_SDIH

SDIN hold

t_CSS

SYNC to SCLK falling edge setup

SCLK falling edge to SYNC rising edge

SYNC high time

t_CSH

t_CSHIGH

t_DACWAIT

t_BCASTWAIT

t_LDACAL

t_LDACW

t_CLRW

2.4

Sequential DAC update wait time

Broadcast DAC update wait time

SYNC rising edge to LDAC falling edge

LDAC low time

µs

CLR low time

t_RSTW

RST low time

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7.8 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOV_DD: 1.7 V to 2.7 V

all specifications at T_A= –40°C to +125°C, input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of IOV_DD) and timed

from a voltage level of (V_IL+ V_IH) / 2, SDO loaded with 20 pF, 1.7 V ≤IOV_DD< 2.7 V

PARAMETER

MIN

NOM

MAX

UNIT

MHz

f_SCLK

SCLK frequency

SCLK high time

SCLK low time

SDIN setup

12.5

t_SCLKHIGH

t_SCLKLOW

t_SDIS

t_SDIH

SDIN hold

t_CSS

SYNC to SCLK falling edge setup

SCLK falling edge to SYNC rising edge

SYNC high time

t_CSH

t_CSHIGH

t_SDOZ

SDO driven to tri-state mode

t_SDODLY

SDO output delay from SCLK rising edge

7.9 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOV_DD: 1.7 V to 2.7 V

all specifications at T_A= –40°C to +125°C, input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of IOV_DD) and timed

from a voltage level of (V_IL+ V_IH) / 2, SDO loaded with 20 pF, 1.7 V ≤IOV_DD< 2.7 V

PARAMETER

MIN

NOM

MAX

UNIT

MHz

f_SCLK

SCLK frequency

SCLK high time

SCLK low time

SDIN setup

t_SCLKHIGH

t_SCLKLOW

t_SDIS

t_SDIH

SDIN hold

t_CSS

SYNC to SCLK falling edge setup

SCLK falling edge to SYNC rising edge

SYNC high time

t_CSH

t_CSHIGH

t_SDOZ

SDO driven to tri-state mode

t_SDODLY

SDO output delay from SCLK rising edge

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7.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOV_DD: 2.7 V to 5.5 V

all specifications at T_A= –40°C to +125°C, input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of IOV_DD) and timed

from a voltage level of (V_IL+ V_IH) / 2, SDO loaded with 20 pF, 2.7 V ≤IOV_DD≤5.5 V

PARAMETER

MIN

NOM

MAX

UNIT

MHz

f_SCLK

SCLK frequency

SCLK high time

SCLK low time

SDIN setup

t_SCLKHIGH

t_SCLKLOW

t_SDIS

t_SDIH

SDIN hold

t_CSS

SYNC to SCLK falling edge setup

SCLK falling edge to SYNC rising edge

SYNC high time

t_CSH

t_CSHIGH

t_SDOZ

SDO driven to tri-state mode

t_SDODLY

SDO output delay from SCLK rising edge

7.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOV_DD: 2.7 V to 5.5 V

all specifications at T_A= –40°C to +125°C, input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of IOV_DD) and timed

from a voltage level of (V_IL+ V_IH) / 2, SDO loaded with 20 pF, 2.7 V ≤IOV_DD≤5.5 V

PARAMETER

MIN

NOM

MAX

UNIT

MHz

f_SCLK

SCLK frequency

SCLK high time

SCLK low time

SDIN setup

t_SCLKHIGH

t_SCLKLOW

t_SDIS

t_SDIH

SDIN hold

t_CSS

SYNC to SCLK falling edge setup

SCLK falling edge to SYNC rising edge

SYNC high time

t_CSH

t_CSHIGH

t_SDOZ

SDO driven to tri-state mode

t_SDODLY

SDO output delay from SCLK rising edge

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7.12 Timing Diagrams

t_CSS

t_CSH

t_CSHIGH

SYNC

SCLK

SDIN

t_SCLKLOW

t_SCLKHIGH

t_SDIH

t_SDIS

Bit 23

Bit 1

Bit 0

LDAC^(A)

LDAC^(B)

CLR

t_CLRW

t_LDACALt_LDACW

t_RSTW

RST

A. Asynchronous update.

B. Synchronous update.

图7-1. Serial Interface Write Timing Diagram

t_CSHIGH

t_CSS

t_CSH

SYNC

SCLK

t_SCLKLOW

t_SCLKHIGH

FIRST READ COMMAND

Bit 22

ANY COMMAND

Bit 22

SDIN

SDO

Bit 23

Bit 0

Bit 23

Bit 0

t_SDIH

t_SDIS

DATA FROM FIRST

READ COMMAND

Bit 22

Bit 0

t_SDOZ

t_SDODLY

图7-2. Serial Interface Read Timing Diagram

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7.13 Typical Characteristics

at T_A= 25°C, DV_DD= 5.0 V, IOV_DD= 1.8 V, internal reference enabled, unipolar ranges: AV_SS= 0 V and AV_DD≥V_MAX+ 1.5

V for the DAC range, bipolar ranges: AV_SS≤V_MIN− 1.5 V and AV_DD≥V_MAX+ 1.5 V for the DAC range, and DAC outputs

unloaded (unless otherwise noted)

图7-3. DAC81402 INL vs Digital Input Code

图7-4. DAC81402 INL vs Digital Input Code

(Bipolar Outputs)

(Unipolar Outputs)

图7-5. DAC81402 DNL vs Digital Input Code

图7-6. DAC81402 DNL vs Digital Input Code

(Bipolar Outputs)

(Unipolar Outputs)

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7.13 Typical Characteristics (continued)

at T_A= 25°C, DV_DD= 5.0 V, IOV_DD= 1.8 V, internal reference enabled, unipolar ranges: AV_SS= 0 V and AV_DD≥V_MAX+ 1.5

V for the DAC range, bipolar ranges: AV_SS≤V_MIN− 1.5 V and AV_DD≥V_MAX+ 1.5 V for the DAC range, and DAC outputs

unloaded (unless otherwise noted)

图7-7. DAC81402 TUE vs Digital Input Code

图7-8. DAC81402 TUE vs Digital Input Code

(Bipolar Outputs)

(Unipolar Outputs)

图7-9. DAC61402 INL vs Digital Input Code

图7-10. DAC61402 INL vs Digital Input Code

(Bipolar Outputs)

(Unipolar Outputs)

图7-11. DAC61402 DNL vs Digital Input Code

图7-12. DAC61402 DNL vs Digital Input Code

(Bipolar Outputs)

(Unipolar Outputs)

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7.13 Typical Characteristics (continued)

at T_A= 25°C, DV_DD= 5.0 V, IOV_DD= 1.8 V, internal reference enabled, unipolar ranges: AV_SS= 0 V and AV_DD≥V_MAX+ 1.5

V for the DAC range, bipolar ranges: AV_SS≤V_MIN− 1.5 V and AV_DD≥V_MAX+ 1.5 V for the DAC range, and DAC outputs

unloaded (unless otherwise noted)

图7-13. DAC61402 TUE vs Digital Input Code

图7-14. DAC61402 TUE vs Digital Input Code

(Bipolar Outputs)

(Unipolar Outputs)

图7-15. DAC81402 INL vs Temperature

图7-16. DAC81402 DNL vs Temperature

图7-17. DAC61402 INL vs Temperature

图7-18. DAC61402 DNL vs Temperature

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7.13 Typical Characteristics (continued)

at T_A= 25°C, DV_DD= 5.0 V, IOV_DD= 1.8 V, internal reference enabled, unipolar ranges: AV_SS= 0 V and AV_DD≥V_MAX+ 1.5

V for the DAC range, bipolar ranges: AV_SS≤V_MIN− 1.5 V and AV_DD≥V_MAX+ 1.5 V for the DAC range, and DAC outputs

unloaded (unless otherwise noted)

图7-19. TUE vs Temperature

图7-20. Unipolar Offset Error vs Temperature

图7-21. Unipolar Zero Code Error vs Temperature

图7-22. Bipolar Zero Code Error vs Temperature

图7-23. Bipolar Zero Error vs Temperature

图7-24. Gain Error vs Temperature

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7.13 Typical Characteristics (continued)

at T_A= 25°C, DV_DD= 5.0 V, IOV_DD= 1.8 V, internal reference enabled, unipolar ranges: AV_SS= 0 V and AV_DD≥V_MAX+ 1.5

V for the DAC range, bipolar ranges: AV_SS≤V_MIN− 1.5 V and AV_DD≥V_MAX+ 1.5 V for the DAC range, and DAC outputs

unloaded (unless otherwise noted)

图7-26. Supply Current (DI_DD

)

图7-25. Full-Scale Error vs Temperature

vs Digital Input Code

图7-27. Supply Current (AI_DD, AI_SS

)

图7-28. Supply Current (I_IOVDD

)

vs Digital Input Code

vs Supply Voltage

DAC range: ±20 V

图7-29. Supply Current vs Temperature

DAC range: ±20 V

图7-30. Power-Down Current vs Temperature

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7.13 Typical Characteristics (continued)

at T_A= 25°C, DV_DD= 5.0 V, IOV_DD= 1.8 V, internal reference enabled, unipolar ranges: AV_SS= 0 V and AV_DD≥V_MAX+ 1.5

V for the DAC range, bipolar ranges: AV_SS≤V_MIN− 1.5 V and AV_DD≥V_MAX+ 1.5 V for the DAC range, and DAC outputs

unloaded (unless otherwise noted)

图7-32. Source and Sink Capability

图7-31. Headroom and Footroom from Supply

vs Output Current

DAC range: ±10 V

图7-33. Full-Scale Settling Time, Rising Edge

图7-34. Full-Scale Settling Time, Falling Edge

DAC range: ±20 V

DAC range: ±10 V

图7-35. DAC Output Enable Glitch

图7-36. Glitch Impulse, 1 LSB Step,

Rising Edge

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7.13 Typical Characteristics (continued)

at T_A= 25°C, DV_DD= 5.0 V, IOV_DD= 1.8 V, internal reference enabled, unipolar ranges: AV_SS= 0 V and AV_DD≥V_MAX+ 1.5

V for the DAC range, bipolar ranges: AV_SS≤V_MIN− 1.5 V and AV_DD≥V_MAX+ 1.5 V for the DAC range, and DAC outputs

unloaded (unless otherwise noted)

DAC range: ±10 V

图7-37. Glitch Impulse, 1 LSB Step,

图7-38. Power-Up Response

Falling Edge

DAC range: ±20 V

图7-40. Clear Command Response

图7-39. Power-Down Response

DAC range: 0 V to 5 V, midscale code

图7-42. DAC Output Noise

DAC range: 0 V to 5 V, midscale code

图7-41. DAC Output Noise Density vs Frequency

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7.13 Typical Characteristics (continued)

at T_A= 25°C, DV_DD= 5.0 V, IOV_DD= 1.8 V, internal reference enabled, unipolar ranges: AV_SS= 0 V and AV_DD≥V_MAX+ 1.5

V for the DAC range, bipolar ranges: AV_SS≤V_MIN− 1.5 V and AV_DD≥V_MAX+ 1.5 V for the DAC range, and DAC outputs

unloaded (unless otherwise noted)

图7-43. Internal Reference Voltage vs Temperature

图7-44. Internal Reference Voltage

vs Supply Voltage

图7-45. Internal Reference Voltage vs Time

图7-46. Internal Reference Noise Density vs Frequency

图7-48. Internal Reference Temperature Drift Histogram

图7-47. Internal Reference Noise

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8 Detailed Description

8.1 Overview

The 16-bit DAC81402 and 12-bit DAC61402 (DACx1402) are pin-compatible, dual-channel, high-voltage-output

digital-to-analog converters (DACs). The DACx1402 consist of an R-2R based ladder followed by an output

buffer. These devices also include a precision reference and a reference buffer. The R-2R-based ladder is

production trimmed to provide monotonicity and a linearity of ±1 LSB. The devices are also optimized to reduce

the code-to-code change glitch to less than 2 nV-s.

The DACx1402 output amplifier provides bipolar voltage outputs up to ±20 V, and unipolar voltage outputs up to

40 V. Each output channel includes sense pins that eliminate the IR drop across load connections and sense a

difference of up to ±12 V between the load and DAC grounds. Alternatively, the sense pins can also be used for

output offset adjustment. An external capacitor compensation pin is also provided to stabilize the output amplifier

for high capacitive loads.

Communication to the DACx1402 is performed through a 4-wire serial interface that supports stand-alone and

daisy-chain operation. An optional frame-error check provides added robustness to the device serial interface.

The DACx1402 incorporate a power-on-reset circuit that connects the DAC outputs to ground at power up. The

outputs remain in this mode until the device is properly configured for operation. The devices include additional

reliability features such as short-circuit protection and a thermal alarm.

8.2 Functional Block Diagram

IOVDD DVDD

FAULT

REFIO

AVDD

Internal Reference

Power On

Reset

REF

BUF

SCLK

SDIN

REF

SYNC

DAC

Ladder

Buffer

Active

CCOMP[A:B]

OUT[A:B]

SDO

LDAC

RST

40 kΩ

SENSEP[A:B]

SENSEN[A:B]

40 kΩ

CLR

Channel

40 kΩ

Resistor Gain

Network

REF

GND

AGND

REFGND

AVSS

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8.3 Feature Description

Each output channel in the device consists of an R-2R ladder digital-to-analog converter (DAC) with dedicated

reference and ground buffers, and an output buffer amplifier capable of rail-to-rail operation. The device also

includes an internal 2.5-V reference. 图8-1 shows a simplified diagram of the device architecture.

DVDD

IOVDD

REFIO

Internal

Reference

REF

BUF

REF

DAC

Ladder

Buffer

Active

AVDD

(async mode)

CCOMPX

OUTX

Clear Signal

LDAC Trigger

(synchronous mode)

AVSS

40 k

SENSEPX

SENSENX

40 k

Resistor Gain

Network

REF

GND

AGND

REFGND

图8-1. Device Architecture

8.3.1 R-2R Ladder DAC

The DAC architecture consists of a voltage-output, segmented, R-2R ladder as shown in 图 8-2. The device

incorporates a dedicated reference buffer per output channel that provides constant input impedance with code

at the REFIO pin. The output of the reference buffers drives the R-2R ladders. A production trim process

provides excellent linearity and low glitch.

Output

Amplifier

OUTX

Internal

Reference

REFIO

Reference

Buffer

REFGND

图8-2. R-2R Ladder

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8.3.2 Programmable-Gain Output Buffer

The voltage output stage as conceptualized in 图8-3 provides the voltage output according to the DAC code and

the output range setting.

REFIO

AVDD

DAC

CCOMPX

OUTX

Ladder

AVSS

40 k

SENSEPX

SENSENX

40 k

REFIO

Resistor Gain

Network

REFGND

图8-3. Voltage Output Buffer

For unipolar output mode, the output range can be programmed as:

• 0 V to 5 V

• 0 V to 10 V

• 0 V to 20 V

• 0 V to 40 V

For bipolar output mode, the output reange can be programmed as:

• ±5 V

• ±10 V

• ±20 V

In addition, 20% overrange is available on all ranges except for 0 V to 40 V and ±20 V.

The input data are written to the individual DAC data registers in straight-binary format for all output ranges. The

output voltage (V_OUTX) can be expressed as 方程式1 and 方程式2.

For unipolar output mode

CODE

V_OUTX= V_REFIOìGAINì

2^N

(1)

(2)

For bipolar output mode

V_REFIO

CODE

2^N

V_OUTX= V_REFIOìGAINì

- GAINì

where:

• CODE is the decimal equivalent of the binary code loaded to the DAC data register.

• N is the DAC resolution in bits.

• V_REFIOis the reference voltage (internal or external).

• GAIN is the gain factor assigned to each output voltage output range as shown in 表8-1.

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表8-1. Voltage Output Range vs Gain Setting

MODE

VOLTAGE OUTPUT RANGE

GAIN

2.0

5 V

6 V (20% overrange)

10 V

2.4

4.0

Unipolar

12 V (20% overrange)

20 V

4.8

8.0

24 V (20% overrange)

40 V

9.6

16.0

4.0

±5 V

±6 V (20% overrange)

±10 V

4.8

Bipolar

8.0

±12 V (20% overrange)

±20 V

9.6

16.0

The output amplifiers can drive up to ±15 mA with 1.5-V supply headroom while maintaining the specified TUE

specification for the device. The output stage has short-circuit current protection that limits the output current to

40 mA. The device is able to drive capacitive loads up to 1 µF. For loads greater than 2 nF, an external

compensation capacitor must be connected between the CCOMPx and OUTx pins to keep the output voltage

stable, but at the expense of reduced bandwidth and increased settling time.

8.3.2.1 Sense Pins

The SENSEPx pins are provided to enable sensing of the load by connecting to points electrically closer to the

load. This configuration allows the internal output amplifier to make sure that the correct voltage is applied

across the load, as long as headroom is available on the power supply. The SENSEPx pins are used to correct

for resistive drops on the system board, and are connected to V_OUTXat the pins. In some cases, both V_OUTXand

V_SENSEPXare brought out through separate lines and connected remotely together at the load. In such cases, if

the V_SENSEPXline is cut, then the amplifier loop is broken; use a 5-kΩresistor between the OUTx and SENSEPx

pins to maintain proper amplifier operation.

The SENSENx pins are provided as remote ground sense reference outputs from the internal V_OUTXamplifier.

The output swing of the V_OUTXamplifier is relative to the voltage seen at these pins. The voltage difference

between V_SENSENXand the device ground must be lower than ±12 V.

At device start up, the power-on-reset circuit makes sure that all registers are at default values. The voltage

output buffer is in a Hi-Z state; however, the SENSEPx pins connect to the amplifier inputs through an internal

40-kΩ feedback resistor (图 8-3). If the OUTx and SENSEPx pins are connected together, the OUTx pins are

also connected to the same node through the feedback resistor. This node is protected by internal circuitry and

settles to a value between GND and the reference input.

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8.3.3 DAC Register Structure

Data written to the DAC data registers is initially stored in the DAC buffer registers. The transfer of data from the

DAC buffer registers to the active registers can be configured to occur immediately (asynchronous mode) or be

initiated by a DAC trigger signal (synchronous mode). After the active registers are updated, the DAC outputs

change to the new values.

After a power-on or reset event, all DAC registers set to zero code, the DAC output amplifiers power down, and

the DAC outputs connect to ground.

8.3.3.1 DAC Output Update

The DAC double-buffered architecture enables data updates without disturbing the analog outputs. Data updates

can be performed either in synchronous or asynchronous mode. The device offers both software and hardware

data update control.

The update mode for each DAC channel is determined by the status of the corresponding SYNC-EN bit. In both

update modes, a minimum wait time of 2.4 μs is required between DAC output updates.

8.3.3.1.1 Synchronous Update

In synchronous mode, writing to the DAC data register does not automatically update the DAC output. Instead

the update occurs only after a trigger event. A DAC trigger signal is generated eigher through the SOFT-LDAC

bit or by the LDAC pin. The synchronous update mode enables simultaneous update of multiple DAC outputs.

8.3.3.1.2 Asynchronous Update

In asynchronous mode, a DAC data register write results in an immediate update of the DAC active register and

DAC output on a SYNC rising edge.

8.3.3.2 Broadcast DAC Register

The DAC broadcast register enables a simultaneous update of multiple DAC outputs with the same value with a

single register write.

Each DAC channel can be configured to update or remain unaffected by a broadcast command by setting the

corresponding DAC-BRDCAST-EN bit. A register write to the BRDCAST-DATA register forces those DAC

channels that have been configured for broadcast operation to update their DAC buffer registers to this value.

The DAC outputs update to the broadcast value according to their synchronous mode configuration.

8.3.3.3 Clear DAC Operation

The DAC outputs are set in clear mode either through the CLR pin or the SOFT-CLR bit. In clear mode, each

DAC data register is set to either zero code (if configured for unipolar range operation) or midscale code (if set

for bipolar range operation). A clear command forces all DAC channels to clear the contents of their buffer and

active registers to the clear code regardless of their synchronization setting.

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8.3.4 Internal Reference

The device includes a precision 2.5-V band-gap reference with a maximum temperature drift of 10 ppm/°C. The

internal reference is in power-down mode by default.

The internal reference voltage is available at the REFIO pin and can source up to 5 mA. To filter noise, place a

minimum 150-nF capacitor between the reference output and ground.

External reference operation is also supported. The external reference is applied to the REFIO pin. If using an

external reference, power down the internal reference.

8.3.5 Power-On Reset (POR)

The device incorporates a power-on-reset function. After the supplies reach their minimum specified values, a

POR event is issued. Additionally, a POR event can be initiated by the RST pin or a SOFT-RESET command.

A POR event causes all registers to initialize to default values, and communication with the device is valid only

after a 1 ms POR delay. After a POR event, the device is set to power-down mode, where all DAC channels and

internal reference are powered down and the DAC outputs are connected to ground through a 10-kΩ internal

resistor.

8.3.5.1 Hardware Reset

A device hardware reset event is initiated by a minimum 20-ns logic low on the RST pin.

8.3.5.2 Software Reset

The device implements a software reset feature. A device software reset is initiated by writing reserved code

0x1010 to SOFT-RESET in the TRIGGER register. The software reset command is triggered on the SYNC rising

edge of the instruction.

8.3.6 Thermal Alarm

The device incorporates a thermal shutdown that is triggered when the die temperature exceeds 140°C. A

thermal shutdown sets the TEMP-ALM bit, and causes all DAC outputs to power-down; however, the internal

reference remains powered on. The FAULT pin can be configured to monitor a thermal shutdown condition by

setting the TEMPALM-EN bit. After a thermal shutdown is triggered, the device stays in shutdown even after the

device temperature lowers.

The die temperature must fall to less than 140°C before the device can be returned to normal operation. To

resume normal operation, the thermal alarm must be cleared through the ALM-RESET bit while the DAC

channels are in power-down mode.

8.4 Device Functional Modes

8.4.1 Power-Down Mode

The device output amplifiers and internal reference power-down status can be individually configured and

monitored though the PWDWN registers. Setting a DAC channel in power-down mode disables the output

amplifier and clamps the output pin to ground through an internal 10-kΩresistor.

The DAC data registers are not cleared when the DAC goes into power-down mode. Therefore, upon return to

normal operation, the DAC output voltages return to the same respective voltages prior to the device entering

power-down mode. The DAC data registers can be updated while in power-down mode, which allows for

changing the power-on voltage, if required.

After a power-on or reset event, all the DAC channels and the internal reference are in power-down mode. The

entire device can be configured into power-down or active modes through the DEV-PWDWN bit.

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8.5 Programming

The device is controlled through an SPI-compatible, flexible, four-wire, serial interface. The interface provides

access to the device registers, and can be configured to daisy-chain multiple devices for write operations. The

device incorporates an optional error-checking mode to validate SPI data communication integrity in noisy

environments.

8.5.1 Stand-Alone Operation

A serial interface access cycle is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be a

continuous or gated clock. SDIN data are clocked on SCLK falling edges. A regular serial interface access cycle

is 24 bits long with error checking disabled and 32 bits long with error checking enabled. Therefore, the SYNC

pin must stay low for at least 24 or 32 SCLK falling edges. The access cycle ends when the SYNC pin is

deasserted high. If the access cycle contains less than the minimum clock edges, the communication is ignored.

If the access cycle contains more than the minimum clock edges, only the first 24 or 32 bits are used by the

device. When SYNC is high, the SCLK and SDIN signals are blocked, and SDO is in a Hi-Z state.

表 8-2 describes the format for an error-checking-disabled access cycle (24-bits long). The first byte input to

SDIN is the instruction cycle. The instruction cycle identifies the request as a read or write command and the 6-

bit address that is to be accessed. The last 16 bits in the cycle form the data cycle.

表8-2. Serial Interface Access Cycle

BIT

FIELD

DESCRIPTION

Identifies the communication as a read or write command to the address

R/W = 0 sets a write operation.

R/W = 1 sets a read operation

Don't care bit

write operation

21-16

A[5:0]

Data cycle bits:

If a write command, the data cycle bits are the values to be written to the

15-0

DI[15:0]

If a read command, the data cycle bits are don't care values

Read operations require that the SDO pin is first enabled by setting the SDO-EN bit. A read operation is initiated

by issuing a read command access cycle. After the read command, a second access cycle must be issued to get

the requested data. The output data format is shown in 表 8-3. Data are clocked out on the SDO pin either on

the falling edge or rising edge of SCLK according to the FSDO bit.

表8-3. SDO Output Access Cycle

BIT

FIELD

DESCRIPTION

Echo RW from previous access cycle

Echo bit 22 from previous access cycle

21-16

15-0

A[5:0]

DO[15:0]

Echo address from previous access cycle

Readback data requested on previous access cycle

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8.5.2 Daisy-Chain Operation

For systems that contain several devices, the SDO pin can be used to daisy-chain the devices together. Daisy-

chain operation is useful in reducing the number of serial interface lines.The SDO pin must be enabled by setting

the SDO-EN bit before initiating daisy-chain operation.

The first falling edge on the SYNC pin starts the operation cycle (see 图 8-4). If more than 24 clock pulses are

applied while the SYNC pin is kept low, the data ripple out of the shift register and are clocked out on the SDO

pin, either on the falling edge or rising edge of SCLK according to the FSDO bit. By connecting the SDO output

of the first device to the SDIN input of the next device in the chain, a multiple-device interface is constructed.

Each device in the daisy-chain system requires 24 clock pulses. As a result the total number of clock cycles

must be equal to 24 × N, where N is the total number of devices in the daisy chain. When the serial transfer to all

devices is complete, the SYNC signal is taken high. This action transfers the data from the SPI shift registers to

the internal register of each device in the daisy chain, and prevents any further data from being clocked into the

input shift register.

SYNC

SCLK

Device A command

Device B command

NOP

D23

D16

D15

SDIN

D23 œ D1

SDO

Device A command

Device B command

图8-4. Serial Interface Daisy-Chain Write Cycle

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8.5.3 Frame Error Checking

If the device is used in a noisy environment, error checking can be used to check the integrity of SPI data

communication between the device and the host processor. This feature is enabled by setting the CRC-EN bit.

The error checking scheme is based on the CRC-8-ATM (HEC) polynomial: x⁸+ x²+ x + 1 (that is, 100000111).

When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data are

appended with an 8-bit CRC polynomial by the host processor before feeding the data to the device. In all serial

interface readback operations, the CRC polynomial is output on the SDO pin as part of the 32-bit cycle.

表8-4. Error Checking Serial Interface Access Cycle

BIT

FIELD

DESCRIPTION

Identifies the communication as a read or write command to the address

R/W = 0 sets a write operation.

R/W = 1 sets a read operation.

CRC-ERROR

A[5:0]

Reserved bit. Set to zero.

write operation.

29-24

Data cycle bits.

If a write command, the data cycle bits are the values to be written to the

If a read command, the data cycle bits are don't care values.

23-8

7-0

DI[15:0]

CRC

8-bit CRC polynomial.

The device decodes the 32-bit access cycle to compute the CRC remainder on SYNC rising edges. If no error

exists, the CRC remainder is zero and data are accepted by the device.

A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a

second access cycle can be issued to determine the error checking results (CRC-ERROR bit) on the SDO pin.

If there is a CRC error, the CRC-ALM bit of the status register is set to 1. The FAULT pin can be configured to

monitor a CRC error by setting the CRCALM-EN bit.

表8-5. Write Operation Error Checking Cycle

BIT

FIELD

DESCRIPTION

Echo RW from previous access cycle (RW = 0).

Returns a 1 when a CRC error is detected; otherwise, returns a 0.

Echo address from previous access cycle.

Echo data from previous access cycle.

CRC-ERROR

A[5:0]

29-24

23-8

7-0

DO[15:0]

CRC

Calculated CRC value of bits 31:8.

A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The

error check result (CRC-ERROR bit) from the read command is output on the SDO pin.

As in the case of a write operation failing the CRC check, the CRC-ALM bit of the status register is set to 1, and

the ALMOUT pin, if configured for CRC alerts, is set low.

表8-6. Read Operation Error Checking Cycle

BIT

FIELD

DESCRIPTION

Echo RW from previous access cycle (RW = 1).

Returns a 1 when a CRC error is detected; otherwise, returns a 0.

Echo address from previous access cycle.

CRC-ERROR

A[5:0]

29-24

23-8

7-0

DO[15:0]

CRC

Readback data requested on previous access cycle.

Calculated CRC value of bits 31:8.

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8.6 Register Map

表 8-7 lists the memory-mapped registers for the device. All register addresses not listed should be considered as reserved locations and the register

contents should not be modified.

表8-7. Register Map

BIT DESCRIPTION

ADDR

(HEX)

RESET

(HEX)

TYPE

NOP

0000

NOP[15:0]

0A70⁽¹⁾

DEVICEID

DEVICEID[13:0]

VERSIONID[1:0]

0930⁽²⁾

DAC-

BUSY

TEMP-

ALM

STATUS

0000

0AA4

4000

RESERVED

CRC-ALM

SDO-EN

TEMPALM- DACBUSY- CRCALM-

EN EN EN

DEV-

PWDWN

SPICONFIG

GENCONFIG

R/W

RESERVED

CRC-EN

RSVD

FSDO

RSVD

REF-

PWDWN

RSVD

RESERVED

DACB-

DACA-

BRDCAST BRDCAST

BRDCONFIG

R/W

000F

0000

RESERVED

RSVD

-EN

DACB-

DACA-

SYNC-EN SYNC-EN

SYNCCONFIG

RESERVED

RSVD

DACB-

PWDWN

DACA-

PWDWN

DACPWDWN

DACRANGE

TRIGGER

R/W

FFFF

0000

RESERVED

DACB-RANGE[3:0]

DACA-RANGE[3:0]

RESERVED

SOFT-RESET[3:0]

ALM-

RESET

SOFT-

LDAC

R/W

RESERVED

SOFT-CLR

BRDCAST

DACA

0000

BRDCAST-DATA[15:0]

DACA-DATA[15:0]

DACB-DATA[15:0]

DACB

(1) Reset code for DAC81402.

(2) Reset code for DAC61402.

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8.6.1 NOP Register (address = 00h) [reset = 0000h]

Return to Register Map.

图8-5. NOP Register

NOP[15:0]

W-0000h

表8-8. NOP Register Field Descriptions

Bit

15-0

Field

NOP[15:0]

Type

Reset

Description

0000h

No operation. Write 0000h for proper no-operation command.

8.6.2 DEVICEID Register (address = 01h) [reset = 0A70h or 0930h]

Return to Register Map.

图8-6. DEVICEID Register

DEVICEID[13:6]

DEVICEID[5:0]

VERSIONID[1:0]

R-0h

表8-9. DEVICEID Register Field Descriptions

Bit

Field

Type

Reset

029Ch

024Ch

Description

15-2

DEVICEID[13:0]

DAC81402 device ID.

DAC61402 device ID.

Version ID. Subject to change.

1-0

VERSIONID[1:0]

8.6.3 STATUS Register (address = 02h) [reset = 0000h]

Return to Register Map.

图8-7. STATUS Register

RESERVED

R-00h

RESERVED

R-00h

CRC-ALM

R-0h

DAC-BUSY

R-0h

TEMP-ALM

R-0h

表8-10. STATUS Register Field Descriptions

Bit

Field

Type

Reset

0000h

Description

15-3

RESERVED

CRC-ALM

Reserved for factory use

CRC-ALM = 1 indicates a CRC error.

DAC-BUSY

TEMP-ALM

DAC-BUSY = 1 indicates DAC registers are not ready for updates.

TEMP-ALM = 1 indicates die temperature is over 140°C. A thermal

alarm event forces the DAC outputs to go into power-down mode.

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8.6.4 SPICONFIG Register (address = 03h) [reset = 0AA4h]

Return to Register Map.

图8-8. SPICONFIG Register

CRCALM-EN

R/W-1h

RESERVED

R-0h

RESERVED

R-0h

TEMPALM-EN DACBUSY-EN

R/W-1h

R/W-0h

RESERVED

DEV-PWDWN

R/W-1h

CRC-EN

R/W-0h

RESERVED

R-0h

SDO-EN

R/W-1h

FSDO

RESERVED

R-0h

R-1h

R-0h

R/W-0h

表8-11. SPICONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

RESERVED

Reserved for factory use

TEMPALM-EN

DACBUSY-EN

R/W

When set to 1, a thermal alarm triggers the FAULT pin.

When set to 1, the FAULT pin is set between DAC output updates.

Contrary to other alarm events, this alarm resets automatically.

8-6

CRCALM-EN

RESERVED

DEV-PWDWN

R/W

When set to 1, a CRC error triggers the FAULT pin..

Reserved for factory use

R/W

DEV-PWDWN = 1 sets the device in power-down mode.

DEV-PWDWN = 0 sets the device in active mode.

CRC-EN

RESERVED

SDO-EN

FSDO

R/W

When set to 1, frame error checking is enabled.

Reserved for factory use

R/W

When set to 1, the SDO pin is operational.

Fast SDO bit (half-cycle speedup).

When 0, SDO updates on SCLK rising edges.

When 1, SDO updates on SCLK falling edges.

RESERVED

Reserved for factory use

8.6.5 GENCONFIG Register (address = 04h) [reset = 4000h]

Return to Register Map.

图8-9. GENCONFIG Register

RESERVED

R-0h

REF-PWDWN

R/W-1h

RESERVED

R-00h

RESERVED

R-00h

表8-12. GENCONFIG Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

Reserved for factory use

REF-PWDWN

R/W

REF-PWDWN = 1 powers down the internal reference.

REF-PWDWN = 0 activates the internal reference.

13-0

RESERVED

0000h

Reserved for factory use

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8.6.6 BRDCONFIG Register (address = 05h) [reset = 000Fh]

Return to Register Map.

图8-10. BRDCONFIG Register

RESERVED

R-00h

RESERVED

R-0h

RESERVED

R-1h

DACB-

DACA-

RESERVED

BRDCAST-EN BRDCAST-EN

R/W-1h R/W-1h

R-1h

表8-13. BRDCONFIG Register Field Descriptions

Bit

Field

Type

Reset

000h

Description

15-4

RESERVED

Reserved for factory use

RESERVED

DACB-BRDCAST-EN

DACA-BRDCAST-EN

R/W

When set to 1, the corresponding DAC is set to update the output to

the value set in the BDCAST register.

When cleared to 0, the corresponding DAC output remains

unaffected by a BRDCAST command.

RESERVED

Reserved for factory use

8.6.7 SYNCCONFIG Register (address = 06h) [reset = 0000h]

Return to Register Map.

图8-11. SYNCCONFIG Register

RESERVED

R-00h

RESERVED

R-0h

RESERVED

DACB-SYNC-

DACA-SYNC-

RESERVED

R-0h

R/W-0h

R-0h

表8-14. SYNCCONFIG Register Field Descriptions

Bit

Field

Type

Reset

000h

Description

15-4

RESERVED

Reserved for factory use

RESERVED

DACB_SYNC_EN

DACA_SYNC_EN

R/W

When set to 1, the corresponding DAC is set to update in response

to an LDAC trigger (synchronous mode).

When cleared to 0, the corresponding DAC output is set to update

immediately on SYNC rising edge (asynchronous mode).

RESERVED

Reserved for factory use

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8.6.8 DACPWDWN Register (address = 09h) [reset = FFFFh]

Return to Register Map.

图8-12. DACPWDWN Register

RESERVED

R-FFh

RESERVED

R-Fh

RESERVED DACB-PWDWN DACA-PWDWN RESERVED

R-1h R/W-1h R/W-1h R-1h

表8-15. DACPWDWN Register Field Descriptions

Bit

Field

Type

Reset

FFFh

Description

15-4

RESERVED

Reserved for factory use

RESERVED

DACB-PWDWN

DACA-PWDWN

RESERVED

R/W

When set to 1, the corresponding DAC is in power-down mode, and

the output is connected to ground through a 10-kΩinternal resistor.

Reserved for factory use

8.6.9 DACRANGE Register (address = 0Ah) [reset = 0000h]

Return to Register Map.

图8-13. DACRANGE Register

RESERVED

W-0h

DACB-RANGE[3:0]

W-0h

DACA-RANGE[3:0]

W-0h

RESERVED

W-0h

表8-16. DACRANGE Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-8

7-4

RESERVED

Reserved for factory use

DACB-RANGE[3:0]

DACA-RANGE[3:0]

Sets the output range for the corresponding DAC.

0000: 0 V to 5 V

1000: 0 V to 6 V

0001: 0 V to 10 V

1001: 0 V to 12 V

0010: 0 V to 20 V

1010: 0 V to 24 V

0011: 0 V to 40 V

0101: –5 V to +5 V

1101: –6 V to +6 V

0110: –10 V to +10 V

1110: –12 V to +12 V

0111: –20 V to +20 V

All others: invalid

3-0

RESERVED

Reserved for factory use

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8.6.10 TRIGGER Register (address = 0Eh) [reset = 0000h]

Return to Register Map.

图8-14. TRIGGER Register

SOFT-CLR

W-0h

ALM-RESET

W-0h

RESERVED

W-00h

RESERVED

W-0h

SOFT-LDAC

W-0h

SOFT-RESET[3:0]

W-0h

表8-17. TRIGGER Register Field Descriptions

Bit

Field

Type

Reset

00h

Description

15-10

RESERVED

SOFT-CLR

ALM-RESET

Reserved for factory use

Set this bit to 1 to clear all DAC outputs.

Set this bit to 1 to clear an alarm event. Not applicable for a DAC-

BUSY alarm event.

7-5

RESERVED

SOFT-LDAC

Reserved for factory use

Set this bit to 1 to synchronously load the DACs that have been set

in synchronous mode in the SYNCCONFIG register.

3-0

SOFT_RESET[3:0]

Set these bits to reserved code 1010 to reset the device to the

default state.

8.6.11 BRDCAST Register (address = 0Fh) [reset = 0000h]

Return to Register Map.

图8-15. BRDCAST Register

BRDCAST-DATA[15:0]

W-0000h

表8-18. BRDCAST Register Field Descriptions

Bit

15-0

Field

BRDCAST_DATA[15:0]

Type

Reset

Description

0000h

Writing to the BRDCAST register forces the DAC channels that have

been set to broadcast in the BRDCONFIG register to update the data

Data are MSB aligned in straight-binary format:

DAC81402: { DATA[15:0] }

DAC61402: { DATA[11:0], x, x, x, x }

x − Don't care bits

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8.6.12 DACn Register (address = 11h to 12h) [reset = 0000h]

Return to Register Map.

图8-16. DACn Register

DACn-DATA[15:0]

W-0000h

表8-19. DACn Register Field Descriptions

Bit

15-0

Field

DACn-DATA[15:0]

Type

Reset

Description

0000h

Stores the data to be loaded to DACn in MSB-aligned, straight-binary

format:

DAC81402: { DATA[15:0] }

DAC61402: { DATA[11:0], x, x, x, x }

x − Don't care bits

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The primary applications for the device include motor-drive circuits in industrial environments, and

programmable power supplies commonly used in automated test equipment and laboratory power supplies. In

these applications, high precision and programmable voltage ranges are important considerations. The excellent

device linearity of ±1 LSB INL and inherently monotonic design meets the criteria for these applications.

9.2 Typical Application

In industrial automation and process control applications, voltage and current analog output signals are used to

operate control sources such as motors, solenoids and valve based actuators. The DAC provides a voltage

output which is then used by control modules to drive industrial motors. Standard analog output ranges provided

by these programmable logic control (PLC) systems include: 5 V, 10 V, ± 5 V and ± 12 V.

The end application and user requirements determine the appropriate output range, so software programmability

of the output range is a desirable function in many system designs. Furthermore force-sense of the output

voltage, capacitive load stability even with long cables at the DAC outputs, and smaller packages which enable

multi-channel systems, are all important factors in these applications. Motor drive applications require a high

precision voltage output to precisely control the motor movements in factory automations. 图 9-1 illustrates a

simple voltage output module driving motors in an industrial CNC control application

R_LIMIT

SENSEP

Ccomp

DAC61402

CCOMP

R_LIMIT

VOUT

IO Protection

Cable

Driver

Stage

DAC Ladder

SENSEN

Motor

Position

Encoder

Analog Output Module

Motor Control Module

图9-1. Motor Drive Circuit

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9.2.1 Design Requirements

• Voltage range: 0 to 5 V, 0 to 10 V, 0 to 40 V, and ± 20 V

• Capacitive load: 1 μF

• Bipolar supply voltage: AV_DD= 21 V, AV_SS= −21 V

• Unipolar supply voltage: AV_DD= 41.5 V, AV_SS= 0 V

• EOS protection: Required

9.2.2 Detailed Design Procedure

The DACx1402 are an excellent choice for this application because of their exceptional linearity and

programmable output ranges which simplify the drive stage design. Since the maximum output voltage

requirements is ±20 V, the AV_DDand AV_SSsupplies should be set to 21 V and −21 V, respectively. In unipolar

output range, the AV_DDsupply should be set to 41 V for a full-scale output voltage of 40 V. In unipolar designs,

the AV_SSsupply can be tied to ground. In all cases, the supply voltages must be selected such that the AV_DD

AV_SSvoltage does not exceed 41.5 V.

−

The analog output module design includes an external electrical overstress protection circuit for short circuit

events. R_LIMIT sets the maximum current flowing into the device in the event of an electrical overstress

condition. The design uses a compensation capacitor for driving large cables such as the ones found in

industrial environments. A C_COMPvalue of 470 pF is sufficient to drive capacitive loads as large as 1 μF.

图 9-2 shows a simplified structure of the device output pins, represented as a pair of clamp-to-rail diodes

connected to the AV_DDand AV_SSsupply rails.

AVSS

AVDD

AVSS

AVDD

SENSEP

AVDD

AVSS

AVDD

Voltage

Output

FB1

OUT

AVDD

C_ext

TVS

AVSS

AVDD

CCOMP

AVSS

SENSEN

AVSS

(Single Channel Illustrated for Simplicity)

图9-2. Electrical Overstress (EOS) Protection Scheme

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If the device output pins are exposed to industrial transient testing without external protection components, the

diode structures will become forward biased and conduct current. If the conducted current is large, as is common

in high-voltage industrial transient tests, the structures will become permanently damaged and impact the device

functionality.

Both attenuation and diversion strategies are implemented to protect the device. Attenuation is realized by the

capacitor C_extwhich forms an RC low-pass filter when interacting with the source impedance of the transient

generator. The ferrite bead FB1 also helps attenuate high-frequency currents, along with both AC and DC

current limiters realized by the series pass elements R1, R2, and R3.

Diversion is achieved by the transient voltage suppressor (TVS) diode D3 and clamp-to-rail diodes D1 and D2.

The combined effects of both strategies effectively limits the current flowing into the device internal diode

structures to prevent permanent damage. If we assume the schottky diode clamps V_OUTto ±1.5 V from rail, then

the peak current entering the device is equal to 80 mA, assuming R1 = 10 Ω and the diode FB is 0.7 V. It is

important to also include the TVS diodes D4 and D5 at the AVDD and AVSS nodes in order to provide a

discharge path for the energy sent to these nodes through diodes D4, D5, and the internal diode structures. In

the abscensce of these diodes when current is diverted to these nodes decoupling capacitors will charge, slowly

increasing the voltage at these nodes which can exceed the threshold limits of AVDD and AVSS.

9.2.3 Application Curves

图9-3. Output Voltage vs DAC Code Sweep

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10 Power Supply Recommendations

The device requires four power-supply inputs: IOVDD, DVDD, AVDD, and AVSS. A 0.1-µF ceramic capacitor

must be connected close to each power-supply pin. In addition, a 4.7-µF or 10-µF bulk capacitor is

recommended for each power supply. Tantalum or aluminum types can be chosen for the bulk capacitors.

There is no sequencing requirement for the power supplies. The DAC output range is configurable; therefore,

sufficient power-supply headroom is required to achieve linearity at codes close to the power-supply rails. When

sourcing or sinking current from or to the DAC output, make sure to account for the effects of power dissipation

on the temperature of the device, and ensure the device does not exceed the maximum junction temperature.

11 Layout

11.1 Layout Guidelines

Printed circuit board (PCB) layout plays a significant role in achieving desired ac and dc performance from the

device. The device has a pinout that supports easy splitting of the noisy and quiet grounds. The digital and

analog signals are available on separate sides of the package for easy layout. 图 11-1 shows an example layout

where the different ground planes have been clearly demarcated, as well as the best position for the single-point

shorts between the planes.

For best power-supply bypassing, place the bypass capacitors close to the respective power-supply pins.

Provide unbroken ground reference planes for the digital signal traces, especially for the SPI and LDAC signals.

The RST and FAULT signals are static lines; therefore these lines can lie on the analog side of the ground plane.

11.2 Layout Example

VOUT A

Ccomp

AGND PLANE

DGND PLANE

SDO

SCLK

SDIN

AVDD

SYNCZ

LDACZ

IOVDD

AVSS

CLRZ

REFIO

Ccomp

VOUT B

图11-1. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, BP-DAC81404EVM, BP-DAC61402EVM user's guide

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

29-May-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DAC61402RHBR

DAC61402RHBT

DAC81402RHBR

DAC81402RHBT

ACTIVE

VQFN

RHB

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

NIPDAUAG

Level-2-260C-1 YEAR

-40 to 125

D61402

NIPDAUAG

D61402

D81402

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

29-May-2021

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC61402RHBR

DAC61402RHBT

DAC81402RHBR

DAC81402RHBT

VQFN

RHB

3000

250

330.0

180.0

330.0

180.0

12.4

12.5

12.4

12.5

5.25

1.1

8.0

12.0

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC61402RHBR

DAC61402RHBT

DAC81402RHBR

DAC81402RHBT

VQFN

RHB

3000

250

338.0

205.0

338.0

205.0

355.0

200.0

355.0

200.0

50.0

33.0

50.0

33.0

3000

250

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

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PACKAGE OUTLINE

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

PIN 1 INDEX AREA

(0.1)

5.1

4.9

SIDE WALL DETAIL

20.000

OPTIONAL METAL THICKNESS

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.45 0.1

EXPOSED

THERMAL PAD

28X 0.5

SEE SIDE WALL

DETAIL

SYMM

3.5

0.3

0.2

32X

0.1

C A B

0.05

PIN 1 ID

(OPTIONAL)

SYMM

0.5

0.3

32X

4223442/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32X (0.6)

32X (0.25)

(1.475)

28X (0.5)

SYMM

(4.8)

(

0.2) TYP

VIA

(R0.05)

TYP

(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223442/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32X (0.6)

32X (0.25)

28X (0.5)

(0.845)

SYMM

(4.8)

METAL

TYP

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DAC61402 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E