DAC70504RTER [TI]
采用微型 QFN 封装、具有精密内部基准电压的真正 14 位、4 通道、SPI、电压输出 DAC | RTE | 16 | -40 to 125;
| 型号： | DAC70504RTER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用微型 QFN 封装、具有精密内部基准电压的真正 14 位、4 通道、SPI、电压输出 DAC | RTE | 16 | -40 to 125 转换器 |
| 文件： | 总50页 (文件大小：2484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC80504, DAC70504, DAC60504
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
带有内部基准电压的 DACx0504 四通道 16、14、12 位 SPI 电压输出
DAC
1 特性
3 说明
1
•
性能
DAC80504、DAC70504 和 DAC60504 (DACx0504)
是引脚兼容系列低功耗、四通道、缓冲电压输出的数模
转换器 (DAC)，具有 16、14 和 12 位分辨率。
DACx0504 包括一个低漂移 2.5V 内部基准电压，大多
数应用中无需使用外部精度 基准. 用户可选增益配置提
供 1.25V（增益 = ½）、2.5V（增益 = 1）或 5V（增
益 = 2）满量程输出电压。这些器件由 2.7V 至 5.5V
单电源供电，具有指定单调性，并能提供 ±1LSB INL
的高线性度。
–
–
INL：16 位分辨率下为 ±1 LSB（最大值）
TUE：FSR 最大值 ±0.1%
•
集成 2.5V 精密内部基准电压
–
–
初始精度：±5 mV，最大值
低温漂：2ppm/°C（典型值）
•
•
高驱动能力：20mA 0.5V 电源轨
灵活的输出配置
–
–
用户可选增益：2、1 或 ½
复位至零标度或中标度
通过一个运行时钟速率为 50MHz 的 4 线制串行接口与
DACx0504 通信。VIO 引脚使串行接口可在 1.7V 至
5.5V 电压范围内运行。DACx0504 灵活接口使其能够
用于广泛的行业标准微处理器和微控制器。
•
•
宽运行范围：
–
–
电源：2.7V 至 5.5V
温度：–40˚C 至 +125˚C
50MHz，SPI 兼容串行接口
DACx0504 采用了上电复位电路，上电后可以将 DAC
输出保持在零电平或中间电平，直到在器件中写入一个
有效代码。这些器件在 5.5V 时消耗 0.7mA/通道的低
电流，因此非常适用于依靠电池供电的设备。每通道断
电特性可将器件电流消耗量降低至 15µA。
–
–
–
4 线制模式，1.7V 至 5.5V 工作电压
菊链运行
CRC 误差校验
•
•
低功耗：0.7mA/通道 (5.5V)
小型封装：3mm × 3mm，16 引脚 WQFN
DACx0504 可在 –40°C 至 +125°C 的温度范围内正常
运行，采用 3mm × 3mm QFN 小型封装。
2 应用
•
•
•
•
光纤网络
器件信息(1)
无线基础设施
工业自动化
器件型号
DACx0504
封装
WQFN (16)
封装尺寸（标称值）
3.00mm × 3.00mm
数据采集系统
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
简化方框图
VDD
REF
GAIN
VIO
REFDIV
Internal
Reference
DACx0504
÷1 or ÷2
GAIN
×1 or ×2
SCLK
SDI
DAC
Register
DAC
Buffer
DAC
BUF
OUT0
SDO/ALARM
CS
Channel 0
OUT1
OUT2
OUT3
Channel 1
Channel 2
Channel 3
LDAC
Power Down Logic
Power On Reset
Resistive Network
RSTSEL
GND
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS871
DAC80504, DAC70504, DAC60504
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
www.ti.com.cn
目录
8.5 Programming........................................................... 28
8.6 Register Map........................................................... 30
Application and Implementation ........................ 36
9.1 Application Information............................................ 36
9.2 Typical Application .................................................. 38
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Typical Characteristics............................................ 10
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 25
9
10 Power Supply Recommendations ..................... 40
11 Layout................................................................... 40
11.1 Layout Guidelines ................................................. 40
11.2 Layout Example .................................................... 40
12 器件和文档支持 ..................................................... 41
12.1 文档支持 ............................................................... 41
12.2 相关链接................................................................ 41
12.3 接收文档更新通知 ................................................. 41
12.4 社区资源................................................................ 41
12.5 商标....................................................................... 41
12.6 静电放电警告......................................................... 41
12.7 术语表 ................................................................... 41
13 机械、封装和可订购信息....................................... 41
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (September 2018) to Revision C
Page
•
•
•
•
•
•
•
•
•
已添加 向数据表中增加了 DAC60504 器件 ............................................................................................................................ 1
Changed TUE values for DAC70504 in Electrical Characteristics ......................................................................................... 7
Changed Full-scale error values for DAC70504 in Electrical Characteristics ........................................................................ 7
Changed Gain error values for DAC70504 in Electrical Characteristics................................................................................ 7
Changed channel-to-channel dc crosstalk values for DAC70504 in Electrical Characteristics.............................................. 8
Changed reference output drift values for DAC70504 in Electrical Characteristics............................................................... 9
Changed reference thermal hysteresis values for DAC70504 in Electrical Characteristics................................................... 9
Deleted Figure 58, DAC70504 Solder Heat Reflow Reference Voltage Shift...................................................................... 23
Changed reset value for VERSIONID from 10 to 11 in Table 10, DEVICE ID Field Descriptions ...................................... 31
Changes from Revision A (December 2017) to Revision B
Page
•
•
•
•
•
•
•
•
已更改 将 特性 中的 TUE 从 ±0.14% 更改为 ±0.1% .............................................................................................................. 1
已更改 将 特性 中的低温漂从 5ppm/°C 更改为 2ppm/°C，并且增加了 DAC80504 ............................................................... 1
已删除 删除了器件信息中的 DAC80504 产品预览 ................................................................................................................. 1
Deleted Product Preview for DAC80504 from Device Comparison Table ............................................................................ 4
Added Added TUE DAC80504. All Gains row in Electrical Characteristics .......................................................................... 7
Added Added Full-scale error DAC80504. All Gains row in Electrical Characteristics ......................................................... 7
Added Added Gain error DAC80504. All Gains row in Electrical Characteristics ................................................................. 7
Changed Short circuit current, DAC code = full scale, output shorted to GND in Electrical CharacteristicsTYP from
35 mA to 30 mA ..................................................................................................................................................................... 8
•
•
Changed Short circuit current, DAC code = zero scale, output shorted to VDD in Electrical Characteristics TYP from
30 mA to 35 mA ..................................................................................................................................................................... 8
Added Channel-to channel dc crosstalk, Measured channel at midscale. Adjacent channel at full scale. DAC80504
in Electrical Characteristics ................................................................................................................................................... 8
•
Added Channel-to-channel crosstalk, Measured channel at midscale. All other channels at full scale. DAC80504 in
2
版权 © 2017–2019, Texas Instruments Incorporated
DAC80504, DAC70504, DAC60504
www.ti.com.cn
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
Electrical Characteristics ....................................................................................................................................................... 8
Added Added Reference output drift, DAC80504 in Electrical Characteristics ..................................................................... 9
Added Reference thermal hysteresis, DAC80504. First cycle in Electrical Characteristics................................................... 9
Changed some graphs in Typical Characteristics ............................................................................................................... 10
Added Figure 59, Solder Heat Reflow Reference Voltage Shift........................................................................................... 23
Added tLDACS and tLDACH to Table 7 ...................................................................................................................................... 28
Added 010 (12-bit) to D14:12 Description in Table 10......................................................................................................... 31
•
•
•
•
•
•
Changes from Original (August 2017) to Revision A
Page
•
已更改 将“预告信息”更改为“混合状态”.................................................................................................................................... 1
Copyright © 2017–2019, Texas Instruments Incorporated
3
DAC80504, DAC70504, DAC60504
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
www.ti.com.cn
5 Device Comparison Table
DEVICE
RESOLUTION
16-Bit
REFERENCE
DAC80504
DAC70504
DAC60504
Internal (default) or External
Internal (default) or External
Internal (default) or External
14-Bit
12-Bit
4
Copyright © 2017–2019, Texas Instruments Incorporated
DAC80504, DAC70504, DAC60504
www.ti.com.cn
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
6 Pin Configuration and Functions
RTE Package
16-Pin WQFN
Top View
REF
OUT0
OUT1
OUT2
1
2
3
4
12
11
10
9
CS
LDAC
Thermal Pad
REFDIV
RSTSEL
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
When using internal reference, this is the reference output voltage pin (default). When using an
external reference, this is the reference input pin to the device.
REF
1
I/O
OUT0
OUT1
OUT2
OUT3
GND
2
3
4
5
6
7
O
O
O
O
Analog output voltage from DAC 0.
Analog output voltage from DAC 1.
Analog output voltage from DAC 2.
Analog output voltage from DAC 3.
GND Ground reference point for all circuitry on the device.
VDD
PWR Analog supply voltage (2.7 V to 5.5 V).
Sets the gain configuration after a power-up or reset event. When tied to GND, the initial buffer
GAIN
8
9
I
I
I
I
amplifier gain for all four channels is set to 1. When tied to VIO the initial buffer amplifier gain is 2.
Changing the state of this pin after power-up does not affect the device operation.
Reset select pin. When tied to GND all four DACs reset to zero scale. When connected to VIO all four
DACs reset to midscale.
RSTSEL
REFDIV
LDAC
Sets the reference divider configuration after a power-up or reset event. When tied to GND, the
reference voltage is not divided down. When tied to VIO the reference voltage is divided by 2. Changing
the state of this pin after power-up does not affect the device operation.
10
11
A high-to-low transition on the LDAC pin causes the DAC outputs of those channels configured in
synchronous mode to update simultaneously. The pin can be tied permanently to GND.
Active low serial data enable. This input is the frame synchronization signal for the serial data. When
the signal goes low, it enables the serial interface input shift register.
CS
12
13
14
I
I
I
SCLK
SDI
Serial interface clock.
Serial interface data input. Data are clocked into the input shift register on each falling edge of the
SCLK pin.
Serial interface data output (default). The SDO pin is in high impedance when CS pin is high. Data are
clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by
the FSDO bit. Alternatively the pin can be configured as an ALARM open-drain output to indicate a
CRC or reference alarm event. If configured as ALARM a 10 kΩ, pull-up resistor to VIO is required.
SDO/ALARM
15
O
VIO
16
–
PWR IO supply voltage (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the serial interface.
The thermal pad is located on the bottom-side of the QFN package. The thermal pad should be
Thermal Pad
–
connected to any internal PCB ground plane using multiple vias for good thermal performance.
Copyright © 2017–2019, Texas Instruments Incorporated
5
DAC80504, DAC70504, DAC60504
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–10
–40
–40
–60
MAX
6
UNIT
VDD to GND
Suppy voltage
V
VIO to GND
6
DAC outputs to GND
VDD + 0.3
VDD + 0.3
VIO + 0.3
10
Pin voltage
Input current
Temperature
REF to GND
V
Digital pins to GND
Input current to any pin except supply pins
Operating free-air, TA
Junction, TJ
mA
°C
125
150
Storage, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±3000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
POWER SUPPLY
VDD
Analog supply voltage
IO supply voltage
2.7
1.7
5.5
5.5
VIO
DIGITAL INPUTS
Digital input voltage
0
VIO
V
REFERENCE INPUT
Reference divider disabled
Reference divider enabled
Reference divider disabled
Reference divider enabled
1.2
2.4
1.2
2.4
(VDD – 0.2)/2
VDD – 0.2
VDD/2
VDD = 2.7 V to 3.3 V
VREFIN
V
VDD = 3.3 V to 5.5 V
VDD
TEMPERATURE
TA
Operating free-air temperature
–40
125
°C
6
Copyright © 2017–2019, Texas Instruments Incorporated
DAC80504, DAC70504, DAC60504
www.ti.com.cn
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
7.4 Thermal Information
DACx0504
THERMAL METRIC(1)
RTE (WQFN)
16 PINS
33.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.5
Junction-to-board thermal resistance
7.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
7.4
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
all minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ
to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE(1)
DAC80504
DAC70504
DAC60504
DAC80504
DAC70504
DAC60504
16
14
12
Resolution
Bits
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.05
±0.75
0.5
±1
±1
INL
Integral nonlinearity
Differential nonlinearity
LSB
LSB
±1
DAC80504, specified 16-bit monotonic
DAC70504, specified 14-bit monotonic
DAC60504, specified 12-bit monotonic
±1
DNL
TUE
±1
±1
Total unadjusted error
Offset error
±0.1
±1.5
1.5
±0.1
±0.1
%FSR
mV
Zero-code error
DAC code = zero scale
mV
Full-scale error
±0.05
±0.05
±1
%FSR
Gain error
%FSR
Offset error drift
Zero-code error drift
Full-scale error drift
Gain error drift
µV/°C
±2
µV/°C
±2
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR
±1
Output voltage drift over time
TA = 25°C, DAC code = midscale, 1600 hours
20
(1) Static performance specified with DAC outputs unloaded for all gain options, unless otherwise noted. End point fit between codes. 16-
bit: Code 256 to 65280, 14-bit: Code 128 to 16127, 12-bit: Code 16 to 4031.
Copyright © 2017–2019, Texas Instruments Incorporated
7
DAC80504, DAC70504, DAC60504
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
www.ti.com.cn
Electrical Characteristics (continued)
all minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ
to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT CHARACTERISTICS
Gain = 2 (BUFF-GAIN = 1, REF-DIV = 0)
Gain = 1 (BUFF-GAIN = 1, REF-DIV = 1)
Gain = ½ (BUFF-GAIN = 0, REF-DIV = 1)
to GND or VDD (unloaded)
0
0
0
2 × VREF
VREF
Voltage range
V
½ × VREF
0.004
to GND or VDD (–5 mA ≤ IOUT ≤ 5 mA)
to GND or VDD (–10 mA ≤ IOUT ≤ 10 mA)
to GND or VDD (–20 mA ≤ IOUT ≤ 20 mA)
DAC code = full scale, output shorted to GND
DAC code = zero scale, output shorted to VDD
DAC code = midscale, -10 mA ≤ IOUT ≤ 10 mA
RLOAD = ∞
0.15
0.3
Output voltage headroom
V
0.5
30
35
85
Short circuit current(2)
Load regulation
mA
µV/mA
nF
0
0
2
Maximum capacitive load(3)
RLOAD = 2 kΩ
10
DAC code = midscale
0.085
15
DC output impedance
Ω
DAC code at GND or VDD
DYNAMIC PERFORMANCE
¼ to ¾ scale and ¾ to ¼ scale settling time to ±2
LSB, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2
Output voltage settling time
Slew rate
5
1.8
12
µs
V/µs
µs
VDD = 5.5 V, VREFIN = 2.5 V, gain = 2
DACx-PWDWN 1 to 0 transition, DAC code = full
Power-up time
scale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2(4)
DAC code = zero scale, VDD = 5.5 V, VREFIN = 2.5 V,
gain = 2. CLOAD = 50 pF
Power-up glitch magnitude
Output noise
25
14
78
74
55
50
85
mV
0.1 Hz to 10 Hz, DAC code = midscale, VDD = 5.5 V,
VREFIN = 2.5 V, gain = 2
µVPP
1 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN
2.5 V, gain = 2
=
10 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN
2.5 V, gain = 2
=
=
Output noise density
nV/√Hz
1 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN
2.5 V, gain = 1
=
10 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN
2.5 V, gain = 1
DAC code = midscale, frequency = 60 Hz,
amplitude = 200 mVPP superimposed on VDD
AC PSRR
dB
DC PSRR
DAC code = midscale, VDD = 5 V ± 10%
1 LSB change around major carrier
10
4
µV/V
nV-s
Code change glitch impulse
DAC code = midscale. Code 32 to full-scale swing on
adjacent channel
Channel-to-channel ac crosstalk
0.2
5
nV-s
Measured channel at midscale, adjacent channel at
full scale
Channel-to-channel dc crosstalk
Digital feedthrough
µV
Measured channel at midscale, all other channels at
full scale
10
DAC code = midscale. fSCLK = 1 MHz, SDO disabled
0.1
nV-s
EXTERNAL REFERENCE INPUT
Reference input current
VREFIN = 2.5 V
25
100
5
µA
kΩ
pF
Reference input impedance
Reference input capacitance
(2) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified
maximum junction temperature may impair device reliability.
(3) Specified by design and characterization. Not tested during production.
(4) Time to exit DAC power-down mode. Measured from CS rising edge to 90% of DAC final value.
8
Copyright © 2017–2019, Texas Instruments Incorporated
DAC80504, DAC70504, DAC60504
www.ti.com.cn
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
Electrical Characteristics (continued)
all minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ
to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE
VREFOUT
Reference output voltage
Reference output drift
TA = 25°C
2.495
2.5
2
2.505
5
V
ppm/°C
Ω
Reference output impedance
Reference output noise
0.1
15
0.1 Hz to 10 Hz
µVPP
nV/√Hz
mA
Reference output noise density
Reference load current
10 kHz, REFLOAD = 10 nF
130
±5
Reference load regulation
Reference line regulation
Reference output drift over time
Source and sink
100
20
µV/mA
µV/V
ppm
TA = 25°C, 1600 hours
First cycle
4.8
50
Reference thermal hysteresis
ppm
Additional cycle
18
DIGITAL INPUTS
VIH
VIL
High-level input voltage
0.7 × VIO
V
V
Low-level input voltage
Input current
0.3 × VIO
±2
2
µA
pF
Input pin capacitance
DIGITAL OUTPUTS
VOH
VOL
High-level output voltage
ILOAD = 0.2 mA
ILOAD = –0.2 mA
VIO – 0.4
V
V
Low-level output voltage
Output pin capacitance
0.4
4
pF
POWER SUPPLY REQUIREMENTS
Active mode, internal reference enabled, gain = 1,
DAC code = full scale, outputs unloaded, SPI static
2.8
2.3
3.6
3
mA
IDD
VDD supply current
VIO supply current
Active mode, internal reference disabled, gain = 1,
DAC code = full scale, outputs unloaded, SPI static
Power-down
15
2
µA
µA
IIO
3
Copyright © 2017–2019, Texas Instruments Incorporated
9
DAC80504, DAC70504, DAC60504
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
www.ti.com.cn
7.6 Typical Characteristics
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
OUT0
OUT1
OUT2
OUT3
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
OUT0
OUT1
OUT2
OUT3
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
D001
D002
Figure 1. Integral Linearity Error vs Digital Input Code
Figure 2. Differential Linearity Error vs Digital Input Code
0.1
1
OUT0
OUT1
OUT2
OUT3
INL Max
INL Min
0.08
0.06
0.04
0.02
0
0.8
0.6
0.4
0.2
0
-0.02
-0.04
-0.06
-0.08
-0.1
-0.2
-0.4
-0.6
-0.8
-1
0
8192 16384 24576 32768 40960 49152 57344 65536
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
Code
D003
D004
Figure 3. Total Unadjusted Error vs Digital Input Code
Figure 4. Integral Linearity Error vs Temperature
1
0.1
0.08
0.06
0.04
0.02
0
DNL Max
DNL Min
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.02
-0.04
-0.06
-0.08
-0.1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D005
D006
Figure 5. Differential Linearity Error vs Temperature
Figure 6. Total Unadjusted Error vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
1.5
1
1.5
1.25
1
0.5
0
0.75
0.5
0.25
0
-0.5
-1
-1.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D007
D008
Figure 7. Offset Error vs Temperature
Figure 8. Zero Code Error vs Temperature
0.1
0.08
0.06
0.04
0.02
0
0.1
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
-0.02
-0.04
-0.06
-0.08
-0.1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D009
D010
Figure 9. Gain Error vs Temperature
Figure 10. Full Scale Error vs Temperature
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
INL Max
INL Min
DNL Max
DNL Min
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
VDD (V)
D011
D012
Gain = 1
Gain = 1
Figure 11. Integral Linearity Error vs Supply Voltage
Figure 12. Differential Linearity Error vs Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
0.1
0.08
0.06
0.04
0.02
0
1.5
1
0.5
0
-0.02
-0.04
-0.06
-0.08
-0.1
-0.5
-1
REF-DIV = 1
REF-DIV = 0
REF-DIV = 1
REF-DIV = 0
-1.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
VDD (V)
D013
D014
Gain = 1
Gain = 1
Figure 13. Total Unadjusted Error vs Supply Voltage
Figure 14. Offset Error vs Supply Voltage
1.5
0.1
0.08
0.06
0.04
0.02
0
REF-DIV = 1
REF-DIV = 0
1.25
1
0.75
0.5
0.25
0
-0.02
-0.04
-0.06
-0.08
-0.1
REF-DIV = 1
REF-DIV = 0
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
D015
VDD (V)
D016
Gain = 1
Gain = 1
Figure 15. Zero Code Error vs Supply Voltage
Figure 16. Gain Error vs Supply Voltage
0.1
0.08
0.06
0.04
0.02
0
1
0.8
0.6
0.4
0.2
0
REF-DIV = 1
REF-DIV = 0
INL Max
INL Min
-0.02
-0.04
-0.06
-0.08
-0.1
-0.2
-0.4
-0.6
-0.8
-1
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
1.25
2
2.75
3.5
4.25
5
5.5
VREFIN (V)
D017
D018
Gain = 1
Gain = 1
Figure 17. Full Scale Error vs Supply Voltage
Figure 18. Integral Linearity Error vs Reference Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
0.1
0.08
0.06
0.04
0.02
0
1
0.8
0.6
0.4
0.2
0
REFDIV = 0
REFDIV = 1
DNL Max
DNL Min
-0.2
-0.4
-0.6
-0.8
-1
-0.02
-0.04
-0.06
-0.08
-0.1
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
5.5
1.25
2
2.75
3.5
4.25
5
5.5
VREFIN (V)
D019
D020
Gain = 1
Gain = 1
Figure 19. Differential Linearity Error vs Reference Voltage
Figure 20. Total Unadjusted Error vs Reference Voltage
1.5
1.5
REFDIV = 0
REFDIV = 1
REFDIV = 0
REFDIV = 1
1
1.25
0.5
0
1
0.75
0.5
-0.5
-1
0.25
0
-1.5
1.25
2
2.75
3.5
4.25
5
5.5
1.25
2
2.75
3.5
4.25
5
5.5
VREFIN (V)
VREFIN (V)
D021
D022
Gain = 1
Gain = 1
Figure 21. Offset Error vs Reference Voltage
Figure 22. Zero Code Error vs Reference Voltage
0.1
0.08
0.06
0.04
0.02
0
0.1
0.08
0.06
0.04
0.02
0
REFDIV = 0
REFDIV = 1
REFDIV = 0
REFDIV = 1
-0.02
-0.04
-0.06
-0.08
-0.1
-0.02
-0.04
-0.06
-0.08
-0.1
1.25
2
2.75
3.5
4.25
5
5.5
1.25
2
2.75
3.5
4.25
5
5.5
VREFIN (V)
VREFIN (V)
D023
D024
Gain = 1
Gain = 1
Figure 23. Gain Error vs Reference Voltage
Figure 24. Full Scale Error vs Reference Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
3
2.5
2
3
6.5
3.25
3
6
5.5
5
2.75
2.5
2.25
2
2.5
2
4.5
4
3.5
3
1.75
1.5
1.5
1
1.5
1
IDD, Gain = 2
IIO, Gain = 2
IDD, Gain = 1
IIO, Gain = 1
IDD, Gain = 2
2.5
2
1.25
1
IIO, Gain = 2
IDD, Gain = 1
IIO, Gain = 1
1.5
1
0.75
0.5
0.25
0
0.5
0
0.5
0
0.5
0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
Code
D025
D026
Gain = 1, external reference = 2.5 V
Gain = 1
Figure 25. Supply Current With External Reference vs
Digital Input Code
Figure 26. Supply Current With Internal Reference vs
Digital Input Code
3
2.5
2
3
3.5
3
3.5
3
2.5
2
2.5
2
2.5
2
1.5
1
1.5
1
1.5
1
1.5
IDD, Gain = 2
IIO, Gain = 2
IDD, Gain = 1
IIO, Gain = 1
IDD, Gain = 2
IIO, Gain = 2
IDD, Gain = 1
IIO, Gain = 1
1
0.5
0
0.5
0
0.5
0
0.5
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Temperature (èC)
D027
D028
Gain = 1, external reference = 2.5 V
Gain = 1
Figure 27. Supply Current With External Reference vs
Temperature
Figure 28. Supply Current With Internal Reference vs
Temperature
3
2.5
2
3
6
5.5
5
3
2.75
2.5
2.25
2
2.5
2
4.5
4
3.5
3
1.75
1.5
1.5
1
1.5
2.5
2
1.25
IDD
IIO
IDD
IIO
1
1
1.5
1
0.75
0.5
0.25
0
0.5
0
0.5
0
0.5
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
VDD (V)
D029
D030
Gain = 1, external reference = 2.5 V
Gain = 1
Figure 29. Supply Current With External Reference vs
Supply Voltage
Figure 30. Supply Current With Internal Reference vs
Supply Voltage
14
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
25
22.5
20
2
25
22.5
20
0.5
IDD
IIO
IDD
IIO
1.8
1.6
1.4
1.2
1
0.45
0.4
17.5
15
17.5
15
0.35
0.3
12.5
10
12.5
10
0.25
0.2
0.8
0.6
0.4
0.2
0
7.5
5
7.5
5
0.15
0.1
2.5
0
2.5
0
0.05
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
Temperature (èC)
D031
D032
Figure 31. Supply Current and Input Current vs Temperature
Figure 32. Supply Current and Input Current vs Supply
Voltage
1
0.8
0.6
0.4
0.2
0
4
Code 0x0000
Code 0x4000
Code 0x8000
Code 0xC000
Code 0xFFFF
3
2
1
0
-0.2
-0.4
Sourcing 5.5V
Sourcing 2.7V
-0.6
-1
-2
Sinking 5.5V
Sinking 2.7V
-0.8
-1
0
5
10
15
20
25
30
-60
-40
-20
0
20
40
60
Load Current (mA)
Load Current (mA)
D033
D034
Figure 33. Headroom/Footroom vs Load Current
Figure 34. Source and Sink Capability With Gain = ½
4
3
7
6
0xFFFF
0xC000
0xFFFF
0xC000
5
2
4
0x8000
3
0x8000
0x4000
1
0x4000
0x0000
2
0
1
0x0000
0
-1
-2
-1
-2
-60
-40
-20
0
20
40
60
-60
-40
-20
0
20
40
60
Load Current (mA)
Load Current (mA)
D035
D036
Figure 35. Source and Sink Capability With Gain = 1
Figure 36. Source and Sink Capability With Gain = 2
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div)
CS (5 V/div)
Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div)
CS (5 V/div)
Time (2 msec/div)
Time (2 msec/div)
D037
D038
Gain = 1
Gain = 1
Gain = 1
Gain = 1
Gain = 1
Gain = 1
Figure 37. Full-Scale Settling Time, Rising Edge
Figure 38. Full-Scale Settling Time, Falling Edge
VOUT (2.5 mV/div)
CS (5 V/div)
VOUT (2.5mV/div)
CS (5 V/div)
Time (0.5 ms/div)
Time (0.5 ms/div)
D039
D040
Figure 39. Glitch Impulse, Falling Edge, 1 LSB Step
Figure 40. Glitch Impulse, Rising Edge, 1 LSB Step
VDD (1.5 V/div)
VOUT (10 mV/div)
VDD (1.5 V/div)
VOUT (1 V/div)
Time (600 ms/div)
Time (600ms/div)
D041
D042
Figure 41. Power-On, Reset to Zero Scale
Figure 42. Power-On, Reset to Midscale
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
VDD (1.5 V/div)
VOUT (1 V/div)
VIO (1.5 V/div)
VOUT (1 V/div)
Time (600ms/div)
Time (600ms/div)
D044
D060
Gain = 1, DAC code at midscale
Figure 43. VDD Power-Down
Gain = 1, DAC code at midscale
Figure 44. VIO Power-Down
SCLK (5 V/div)
VOUT (1 mV/div)
VOUT (200 mV/div)
CS (5 V/div)
Time (2 msec/div)
Time (5 msec/div)
D045
D046
Gain = 1, measured DAC at midscale,
Gain = 1, DAC code at midscale
all other DACs switch from code 32 to full scale
Figure 45. Channel to Channel Crosstalk
Figure 46. Clock Feedthrough With SCLK = 1 MHz
0
-10
300
250
200
150
100
50
Gain = 1
Gain = 2
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
1
10
100
1000
10000
100000
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
Frequency (Hz)
D047
D048
Gain = 1, VDD = 5 V + 200 mVPP (Sinusoid), DAC code at fullscale
External reference = 2.5 V, DAC code at midscale
Figure 48. DAC Output Noise Density vs Frequency
Figure 47. DAC Output AC PSRR vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
D049
D050
Gain = 1, external reference = 2.5 V, DAC code at midscale
Gain = 1, DAC code at midscale
Figure 49. DAC Output Noise With External Reference
0.1 Hz to 10 Hz
Figure 50. DAC Output Noise With Internal Reference
0.1 Hz to 10 Hz
2.505
2.5025
2.5
2.505
2.5025
2.5
2.4975
2.4975
2.495
2.495
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D053
D051
Figure 52. Internal Reference Voltage vs Supply Voltage
Figure 51. Internal Reference Voltage vs Temperature
2.505
800
700
600
500
400
300
200
100
0
2.5025
2.5
2.4975
2.495
0
200
400
600
800 1000 1200 1400 1600
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
Hours
D055
D056
Figure 53. Internal Reference Voltage vs Time
Figure 54. Internal Reference Noise Density vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
45
40
35
30
25
20
15
10
5
0
0
1
2
3
4
5
D058
Temperature Drift (ppm/èC)
D057
0.1 Hz to 10 Hz
Figure 55. Internal Reference Noise
Figure 56. Internal Reference Temperature Drift Histogram
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8 Detailed Description
8.1 Overview
The DACx0504 is a pin-compatible family of low-power, four-channel, buffered voltage-output digital-to-analog
converters (DACs) with 16-, 14-, and 12-bit resolution. The DACx0504 include a 2.5-V internal reference and
user-selectable gain configuration. providing full-scale output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1), or 5
V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is specified monotonic, and provides high
linearity of ±1 LSB INL.
Communication to the DACx0504 is performed through a 4-wire serial interface that supports stand-alone and
daisy-chain operation. The optional frame-error checking provides added robustness to the DACx0504 serial
interface.
The DACx0504 incorporates a power-on-reset circuit and RSTSEL pin that powers up and maintains the DAC
outputs at either zero scale or midscale until a valid code is written to the device.
8.2 Functional Block Diagram
VDD
REF
GAIN
VIO
REFDIV
Internal
Reference
DACx0504
÷1 or ÷2
GAIN
×1 or ×2
SCLK
SDI
DAC
Register
DAC
Buffer
DAC
OUT0
BUF
SDO/ALARM
CS
Channel 0
OUT1
OUT2
OUT3
Channel 1
Channel 2
Channel 3
LDAC
Power Down Logic
Power On Reset
Resistive Network
RSTSEL
GND
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8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC)
Each output channel in the DACx0504 consists of an R-2R ladder architecture followed by an output buffer
amplifier. Figure 57 shows a block diagram of the DAC architecture.
REF
2.5-V
Reference
REF Divider
(÷1 or ÷2)
DIV
Serial Interface
DAC Data Register
Gain
(×1 or ×2)
GAIN
READ
WRITE
DAC
Buffer
DAC
Active
R-2R
VOUT
DAC Output
Register
Register
(asynchronous mode)
LDAC Trigger
(synchronous mode)
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 57. DACx0504 DAC Block Diagram
8.3.1.1 DAC Transfer Function
The input data are written to the individual DAC data registers in straight binary format. After a power-on or a
reset event, all DAC registers are set to either zero code or midscale code, as determined by the RSTSEL pin.
The DAC transfer function is given by Equation 1.
VREF
DIV
CODE
2n
VOUT
=
ì
ì GAIN
where
•
CODE = decimal equivalent of the binary code that is loaded to the DAC register. CODE ranges from 0 to 2n –
1.
•
VREF = DAC reference voltage. Either VREFOUT from the internal 2.5 V reference or VREFIN if using an external
one.
•
•
•
n = resolution in bits. Either 16 (DAC80504), 14 (DAC70504), or 12 (DAC60504).
DIV = 1 or 2 as set by the REFDIV pin after a reset event or by the REF-DIV bit in the GAIN register.
GAIN = 1 or 2 as set by the GAIN pin after a reset event or by the BUFF-GAIN bit for that DAC channel in the
GAIN register.
(1)
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Feature Description (continued)
8.3.1.2 Output Amplifiers
The DACx0504 output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a
maximum output range of 0 V to VDD. Each buffer amplifier is capable of driving a load of 2 kΩ in parallel with
10 nF to GND.
The full-scale output voltage for each channel is determined by the reference voltage (VREF), the reference
divider setting (DIV), and the output buffer gain for that channel (GAIN), as shown in Table 1. After a power-up or
reset event the DIV and GAIN settings are set by the REFDIV and GAIN pins, respectively. During normal
operation the DIV and GAIN settings can be reconfigured through the REF-DIV and BUFF-GAIN bit (see
Equation 1). The GAIN setting for each output channel can be individually configured thus enabling independent
output voltage ranges for each DAC output.
Table 1. DAC Output Range Configuration
DIV SETTING
GAIN SETTING
DAC OUTPUT RANGE
0 V to ½ × VREF
÷2
÷1
÷2
÷1
×1
×1
×2
×2
Not recommended
0 V to VREF
0 V to 2 × VREF
8.3.1.3 DAC Register Structure
Data written to the DAC data registers is initially stored in the DAC buffer registers. Transfer of data from the
DAC buffer registers to the active DAC registers can be configured to happen immediately (asynchronous mode)
or initiated by an LDAC trigger (synchronous mode). Once the DAC active registers are updated, the DAC
outputs change to their new values. When the host reads from a DAC Data register, the value held in the DAC
buffer register is returned (not the value held in the DAC active register).
8.3.1.3.1 DAC Register Synchronous and Asynchronous Updates
The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In
asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register
and DAC output on CS rising edge. In synchronous mode, writing to the DAC data register does not
automatically update the DAC output. Instead the update occurs only after an LDAC trigger event. An LDAC
trigger is generated either through the LDAC bit in the TRIGGER register or by the LDAC pin. The synchronous
update mode enables simultaneous update of multiple DAC outputs. In both update modes a minimum wait time
of 1 µs is required between DAC output updates.
8.3.1.3.2 Broadcast DAC Register
The DAC broadcast register enables a simultaneous update of multiple DAC outputs with the same value with a
single register write. Each DAC channel can be configured to update or remain unaffected by a broadcast
command by setting the corresponding DAC-BRDCAST-EN bit in the SYNC register. A register write to the
BRDCAST-DATA register forces those DAC channels that have been configured for broadcast operation to
update their outputs. The DAC ouputs update to the broadcast value on CS rising edge independently of their
synchronous mode configuration.
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8.3.2 Internal Reference
The DACx0504 includes a 2.5 V precision bandgap reference enabled by default. Operation from an external
reference is supported by disabling the internal reference in the CONFIG register. The internal reference is
externally available at the REF pin.
A minimum 150 nF capacitor is recommended between the reference output and GND for noise filtering.
8.3.2.1 Reference Divider
The reference voltage to the device, either from the internal reference or an external one can be divided by a
factor of two by tying the REFDIV pin high at power-up or by setting the REF-DIV bit in the GAIN register to 1
during normal operation. The reference voltage divider provides additional flexibility in setting the full-scale output
voltage for each DAC output and must be configured to make certain that there is sufficient headroom from VDD
to the DAC operating reference voltage (VREF/DIV). See the Recommended Operating Conditions table for more
information.
Improper configuration of the reference divider issues a reference alarm condition. In this case, the reference
buffer is shut down, and all the DAC outputs go to 0 V. The DAC data registers are unaffected by the alarm
condition thus enabling the DAC output to return to normal operation once the reference divider is configured
correctly. The reference alarm status can be read from the REF-ALM bit in the STATUS register. Additionally by
setting ALM-EN = 1 and ALM-SEL = 1 in the CONFIG register, the SDO/ALARM pin is configured as a reference
alarm pin.
8.3.2.2 Solder Heat Reflow
A known behavior of IC reference voltage circuits is the shift induced by the soldering process. Figure 58 shows
the effect of solder heat reflow for the DACx0504 internal reference.
70%
Presolder Heat Reflow
Postsolder Heat Reflow
60%
50%
40%
30%
20%
10%
0
2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010
D061
VREFOUT (V)
Figure 58. Solder Heat Reflow Reference Voltage Shift
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8.3.3 Device Reset Options
8.3.3.1 Power-on-Reset (POR)
The DACx0504 includes a power-on reset function that controls the output voltage at power up. After the VDD
and VIO supplies have been established a POR event is issued. The POR causes all registers to initialize to their
default values and communication with the device is valid only after a 250 µs power-on-reset delay. The default
value for all DACs is either zero-code or midscale-code as determined by the RSTSEL pin. Each DAC channel
remains at the power-up voltage until a valid command is written to it.
The POR circuit requires specific supply levels to discharge the internal capacitors and to reset the device on
power up, as indicated in Figure 59 and Figure 60. In order to initiate a POR event, VDD or VIO must be below
their corresponding low thresholds for at least 100 µs. If VDD and VIO remain above their specified high threshold
a POR event will not occur. When the supplies drop below their high threshold but remain over the lower one
(shown as the undefined region), the device may or may not reset under all specified temperature and power-
supply conditions.
VDD (V)
VIO (V)
5.50
5.50
Specified Supply
Voltage Range
No Power-On Reset
Specified Supply
Voltage Range
No Power-On Reset
2.70
2.20
Undefined
1.70
1.50
1.20
Undefined
0.70
0.00
Power-On Reset
Power-On Reset
0.00
Figure 59. Threshold Levels for VDD POR Circuit
Figure 60. Threshold Levels for VIO POR Circuit
8.3.3.2 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to SOFT-RESET in the TRIGGER
register. The software reset command is triggered on the CS rising edge of the instruction. A software reset
initiates a POR event.
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8.4 Device Functional Modes
8.4.1 Stand-Alone Operation
A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a
continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is
24 bits long with error checking disabled and 32 bits long with error checking enabled, thus the CS pin must stay
low for at least 24 or 32 SCLK falling edges. The access cycle ends when the CS pin is de-asserted high. If the
access cycle contains less than the minimum clock edges, the communication is ignored. If the access cycle
contains more than the minimum clock edges are present, only the last 24 or 32 bits are used by the device.
When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a Hi-Z state.
In an error checking disabled access cycle (24-bits long) the first byte input to SDI is the instruction cycle which
identifies the request as a read or write command and the 4-bit address to be accessed. The following bits in the
cycle form the data cycle, as shown in Table 2.
Table 2. Serial Interface Access Cycle
BIT
FIELD
DESCRIPTION
Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a
write operation. R/W = 1 sets a read operation.
23
RW
22:20
19:16
Reserved
A[3:0]
Reserved bits. Must be filled with zeros.
Register address. Specifies the register to be accessed during the read or write operation.
Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with
address A[3:0]. If a read command, the data cycle bits are don’t care values.
15:0
DI[15:0]
A read operation is initiated by issuing a read command access cycle. After the read command, a second access
cycle must be issued to get the requested data, as shown in Table 3. Data are clocked out on SDO pin either on
the falling edge or rising edge of SCLK according to the FSDO bit in the CONFIG register.
Table 3. SDO Output Access Cycle
BIT
23
FIELD
RW
DESCRIPTION
Echo RW from previous access cycle.
22:20
19:16
15:0
Reserved
A[3:0]
Echo bits 22:20 from previous access cycle (all zeros).
Echo address from previous access cycle.
DO[15:0]
Readback data requested on previous access cycle.
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8.4.2 Daisy-Chain Operation
For systems that contain more than one DACx0504 devices, the SDO pin can be used to daisy-chain them
together. Daisy-chain operation is useful in reducing the number of serial interface lines.
The first falling edge on the CS pin starts the operation cycle. If more than 24 SCLK pulses are applied while the
CS pin is kept low, the data ripples out of the shift register and is clocked out on the SDO pin either on the falling
edge or rising edge of SCLK according to the FSDO bit. By connecting the SDO output of the first device to the
SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system
requires 24 clock pulses. As a result the total number of clock cycles must be equal to 24 × N, where N is the
total number of DACx0504 devices in the daisy chain. When the serial transfer to all devices is complete the CS
signal is taken high. This action transfers the data from the serial peripheral interface (SPI) shift registers to the
internal registers of each device in the daisy chain and prevents any further data from being clocked into the
input shift register.
C
B
A
DACx0504
DACx0504
DACx0504
SDO
SDO
SDO
SDI
SDI
SDI
SCLK
SCLK
SCLK
CS
CS
CS
Copyright © 2017, Texas Instruments Incorporated
Figure 61. Daisy-Chain Layout
8.4.3 Frame Error Checking
If the DACx0504 is used in a noisy environment, error checking can be used to check the integrity of SPI data
communication between the device and the host processor. This feature can be enabled by setting the CRC-EN
bit in the CONFIG register.
The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111).
When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data are
appended with an 8-bit CRC polynomial by the host processor before feeding it to the device, as shown in
Table 4. In all serial interface readback operations the CRC polynomial is output on the SDO pin as part of the
32-bit cycle.
Table 4. Error Checking Serial Interface Access Cycle
BIT
FIELD
DESCRIPTION
Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a
write operation. R/W = 1 sets a read operation.
31
RW
30
CRC-ERROR Reserved bit. Set to zero.
29:28
27:24
Reserved
A[3:0]
Reserved bits. Must be filled with zeros.
Register address. Specifies the register to be accessed during the read or write operation.
Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with
address A[3:0]. If a read command, the data cycle bits are don’t care values.
23:8
7:0
DI[15:0]
CRC
8-bit CRC polynomial.
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The DACx0504 decodes the 32-bit access cycle to compute the CRC remainder on CS rising edges. If no error
exists, the CRC remainder is zero and data are accepted by the device.
A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a
second access cycle can be issued to determine the error checking result (CRC-ERROR bit) on the SDO pin, as
shown in Table 5. Additionally, by setting ALM-EN = 1 and ALM-SEL = 0 in the CONFIG register, the
SDO/ALARM pin is configured as a CRC alarm pin.
Table 5. Write Operation Error Checking Cycle
BIT
31
FIELD
DESCRIPTION
Echo RW from previous access cycle (RW = 0).
RW
30
CRC-ERROR Returns a 1 when a CRC error is detected, 0 otherwise.
29:28
27:24
23:8
7:0
Reserved
A[3:0]
Echo bits 29:28 from previous access cycle (all zeros).
Echo address from previous access cycle.
Echo data from previous access cycle.
DO[15:0]
CRC
Calculated CRC value of bits 31:8.
A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The
error check result (CRC-ERROR bit) from the read command is output on the SDO pin, as shown in Table 6. As
in the case of a write operation failing the CRC check, the SDO/ALARM pin if configured as a CRC alarm pin can
be used to indicate a read command CRC failure.
Table 6. Read Operation Error Checking Cycle
BIT
31
FIELD
DESCRIPTION
Echo RW from previous access cycle (RW = 1).
RW
30
CRC-ERROR Returns a 1 when a CRC error is detected, 0 otherwise.
29:28
27:24
23:8
7:0
Reserved
A[3:0]
Echo bits 29:28 from previous access cycle (all zeros).
Echo address from previous access cycle.
Readback data requested on previous access cycle.
Calculated CRC value of bits 31:8.
DO[15:0]
CRC
8.4.4 Power-Down Mode
The DACx0504 DAC output amplifiers and internal reference can be independently powered down through the
CONFIG register. At power-up all output channels and the device internal reference are active by default. A DAC
output channel in power-down mode is connected internally to GND through a 1-kΩ resistor.
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8.5 Programming
The DACx0504 is controlled through a flexible four-wire serial interface that is compatible with SPI type
interfaces used on many microcontrollers and DSP controllers. The interface provides read and write access to
all DACx0504 registers and can also be configured to daisy-chain multiple devices for write operations. The
DACx0504 incorporates an optional error checking mode to validate SPI data communication integrity in noisy
environments. Table 7 shows the SPI timing requirements. Figure 62 and Figure 63 show the SPI write and read
timing diagrams, respectively. Figure 64 shows the digital logic timing diagram.
Table 7. Programming Timing Requirements(1)
VIO = 1.7 V to 2.7 V
VIO = 2.7 V to 5.5 V
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
SERIAL INTERFACE – WRITE OPERATION
fSCLK
SCLK frequency
50
50
MHz
ns
tSCLKHIGH
tSCLKLOW
tSDIS
SCLK high time
9
9
9
9
SCLK low time
ns
SDI setup
5
5
ns
tSDIH
SDI hold
10
13
10
15
7
10
13
10
15
7
ns
tCSS
CS to SCLK falling edge setup
SCLK falling edge to CS rising edge
CS high time
ns
tCSH
ns
tCSHIGH
tCSIGNORE
ns
SCLK falling edge to CS ignore
ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 0
fSCLK
SCLK frequency
12
18
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCLKHIGH
tSCLKLOW
tSDIS
SCLK high time
35
35
5
25
25
5
SCLK low time
SDI setup
tSDIH
SDI hold
10
32
10
15
3.5
0
10
20
10
15
3.5
0
tCSS
CS to SCLK falling edge setup
SCLK falling edge to CS rising edge
CS high time
tCSH
tCSHIGH
tSDODLY
tSDODZ
tCSIGNORE
SDO output delay from SCLK rising edge
SDO driven to tri-state
SCLK falling edge to CS ignore
33.5
30
23
25
7
7
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 1
fSCLK
SCLK frequency
20
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCLKHIGH
tSCLKLOW
tSDIS
SCLK high time
22
22
5
18
18
5
SCLK low time
SDI setup
tSDIH
SDI hold
10
32
10
15
3.5
0
10
20
10
15
3.5
0
tCSS
CS to SCLK falling edge setup
SCLK falling edge to CS rising edge
CS high time
tCSH
tCSHIGH
tSDODLY
tSDODZ
SDO output delay from SCLK falling edge
SDO driven to tri-state
SCLK falling edge to CS ignore
45
30
32
25
tCSIGNORE
DIGITAL LOGIC
tRSTDLYPOR
tDACWAIT
tLDACS
7
7
POR reset delay
Sequential DAC output updates
LDAC setup
170
250
170
250
µs
µs
ns
ns
1
0
5
1
0
5
tLDACH
LDAC hold
(1) All input signals are specified at tR = tF = 1 ns/V (10% to 90% of VIO), timed from a voltage level of (VIL + VIH) / 2, VDD = 2.7 V to 5.5 V,
VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted)
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tCSHIGH
tCSS
tCSH
CS
SCLK
SDI
tCSIGNORE
tSCLKLOW
tSCLKHIGH
Bit 23
Bit 1
Bit 0
tSDIH
tSDIS
Figure 62. Serial Interface Write Timing Diagram
tCSHIGH
tCSS
tCSH
CS
tCSIGNORE
tSCLKLOW
SCLK
tSCLKHIGH
FIRST READ COMMAND
Bit 22
ANY COMMAND
Bit 1
SDI
Bit 23
tSDIS
tSDIH
Bit 0
Bit 23
Bit 23
Bit 0
Bit 0
SDO
FSDO = 0
Bit 1
tSDODZ
tSDODLY
DATA FROM FIRST READ COMMAND
SDO
FSDO = 1
Bit 23
Bit 1
Bit 0
X
tSDODZ
tSDODLY
DATA FROM FIRST READ COMMAND
Figure 63. Serial Interface Read Timing Diagram
tLDACS
tLDACH
CS
LDAC
Figure 64. Digital Logic Timing Diagram
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8.6 Register Map
Table 8. Register Map
ADDRESS BITS
DATA BITS
D8 D7
REGISTER
TYPE RESET
A3 A2 A1 A0
D15
D14
D13
D12
D11
D10
D9
D6
D5
D4
D3
D2
D1
D0
NOP
DEVICE ID
SYNC
W
R
0000
—
0
0
0
0
0
0
0
0
1
0
1
0
NOP
DEVICEID
DACx-BRDCAST-EN
REF
VERSIONID
R/W
FF00
RESERVED
RESERVED
RESERVED
DACx-SYNC-EN
ALM ALM CRC
SEL EN EN
F
D
CONFIG
GAIN
R/W
R/W
0000
0000
0
0
0
1
1
0
1
0
RESERVED
PWD
WN
DACx-PWDWN
SDO SDO
REF
DIV-
EN
RESERVED
RESERVED
BUFFx-GAIN
L
DAC
TRIGGER
BRDCAST
STATUS
W
0000
0000
0000
0
0
0
1
1
1
0
1
1
1
0
1
RESERVED
SOFT-RESET[3:0]
R/W
R/W
BRDCAST-DATA[15:0]
RESERVED
REF
ALM
DAC0
DAC1
R/W
R/W
R/W
R/W
—
0000
0000
0000
0000
—
1
1
0
0
0
0
0
1
DAC0-DATA[15:0]
DAC1-DATA[15:0]
DAC2-DATA[15:0]
DAC3-DATA[15:0]
RESERVED
DAC2
1
0
1
0
DAC3
1
0
1
1
All Others
—
—
—
—
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8.6.1 NOP Register (address = 0x00) [reset = 0x0000]
Figure 65. NOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOP
W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. NOP Register Field Descriptions
Bit
Field
Type
Reset
Description
No operation. Write 0000h for proper no-operation command
15:0
NOP
W
0x0000
8.6.2 DEVICE ID Register (address = 0x01) [reset = 0x---]
Figure 66. DEVICE ID Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEVICEID
R
VERSIONID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. DEVICE ID Field Descriptions
Bit
Field
Type
Reset
Description
15:2
DEVICEID
R
----
Device ID:
D15 Reserved - 0
D14:12 Resolution - 000 (16-bit); 001 (14-bit); 010 (12-bit)
D11:4 Channels - 0100 (4 channels)
D7 Reset - Determined by RSTSEL pin. 0 (reset to zero); 1
(reset to midscale)
D6:2 Reserved - 00101
1:0
VERSIONID
R
11
Version ID. Subject to change
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8.6.3 SYNC Register (address = 0x2) [reset = 0xFF00]
Figure 67. SYNC Register
15
7
14
6
13
5
12
11
10
9
8
Reserved
—
DAC3-
DAC2-
DAC1-
DAC0-
BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN
R/W
3
R/W
2
R/W
1
R/W
0
4
Reserved
—
DAC3-SYNC-
EN
DAC2-SYNC-
EN
DAC1-SYNC-
EN
DAC0-SYNC-
EN
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. SYNC Register Field Descriptions
Bit
15:12
11
10
9
Field
Type
—
Reset
Description
Reserved
1111
Reserved for factory use
DAC3-BRDCAST-EN
DAC2-BRDCAST-EN
DAC1-BRDCAST-EN
DAC0-BRDCAST-EN
Reserved
R/W
R/W
R/W
R/W
—
1
When set to 1 the corresponding DAC is set to update its output
after a serial interface write to the BRDCAST register.
When cleared to 0 the corresponding DAC output remains
unaffected after a serial interface write to the BRDCAST
register.
1
1
8
1
7:4
3
0000
Reserved for factory use
DAC3-SYNC-EN
DAC2-SYNC-EN
DAC1-SYNC-EN
DAC0-SYNC-EN
R/W
R/W
R/W
R/W
0
0
0
0
When set to 1 the corresponding DAC output is set to update in
response to an LDAC trigger (synchronous mode).
When cleared to 0 the corresponding DAC output is set to
update immediately on a CS rising edge (asynchronous mode).
2
1
0
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8.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]
Figure 68. CONFIG Register
15
7
14
6
13
12
11
10
9
8
Reserved
—
ALM-SEL
R/W
ALM-EN
R/W
CRC-EN
R/W
FSDO
R/W
DSDO
R/W
REF-PWDWN
R/W
5
4
3
2
1
0
Reserved
DAC3-PWDWN DAC2-PWDWN DAC1-PWDWN DAC0-PWDWN
R/W R/W R/W R/W
—
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. CONFIG Register Field Descriptions
Bit
15:14
13
Field
Type
—
Reset
00
Description
Reserved
ALM-SEL
Reserved for factory use
R/W
0
ALARM select.
0: ALARM pin is CRC-ERROR
1: ALARM pin is REF-ALARM
12
ALM-EN
R/W
0
Configure SDO/ALARM pin. When 1: SDO/ALARM pin is an
active-low, open-drain, alarm pin. An external 10 kΩ pullup
resistor to VIO is required. FSDO and DSDO bits are ignored.
When 0: SDO/ALARM pin is a serial interface, push-pull, SDO
pin
11
10
CRC-EN
FSDO
R/W
R/W
0
0
CRC enable bit. Set to 1 to enable CRC. Set to 0 to disable
Fast SDO bit (half-cycle speedup). When 0, SDO updates on an
SCLK rising edge. When 1, SDO updates a half-cycle earlier,
during an SCLK falling edge.
9
DSDO
R/W
0
Disable SDO bit. When 1, SDO is always tri-stated. When 0,
SDO is driven while CS is low, and tri-stated while CS is high
8
7:4
3
REF-PWDWN
Reserved
R/W
—
0
When set to 1 disables the device internal reference
Reserved for factory use
0000
DAC3-PWDWN
DAC2-PWDWN
DAC1-PWDWN
DAC0-PWDWN
R/W
R/W
R/W
R/W
0
0
0
0
When set to 1 the corresponding DAC is set in power-down
mode and its output is connected to GND through a 1 kΩ
internal resistor.
2
1
0
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8.6.5 GAIN Register (address = 0x04) [reset = 0x---]
Figure 69. GAIN Register
15
7
14
6
13
5
12
Reserved
—
11
10
9
8
REFDIV-EN
R/W
4
3
2
1
0
Reserved
—
BUFF3-GAIN
R/W
BUFF2-GAIN
R/W
BUFF1-GAIN
R/W
BUFF0-GAIN
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. GAIN Register Field Descriptions
Bit
15:9
8
Field
Type
—
Reset
0
Description
Reserved
REFDIV-EN
Reserved for factory use.
R/W
0/1
When set to 1 the reference voltage is internally divided by a
factor of 2.
When cleared to 0 the reference voltage is unaffected.
Default value is determined by the REFDIV pin.
7:4
3
Reserved
—
0000
0/1
Reserved for factory use
BUFF3-GAIN
BUFF2-GAIN
BUFF1-GAIN
BUFF0-GAIN
R/W
R/W
R/W
R/W
When set to 1 the buffer amplifier for corresponding DAC has a
gain of 2.
When cleared to 0 the buffer amplifier for corresponding DAC
has a gain of 1.
2
0/1
1
0/1
Default value is determined by the GAIN pin.
0
0/1
8.6.6 TRIGGER Register (address = 0x05) [reset = 0x0000]
Figure 70. TRIGGER Register
15
14
13
12
11
10
9
8
7
6
5
4
LDAC
W
3
2
1
0
Reserved
—
SOFT-RESET[3:0]
W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. TRIGGER Register Field Descriptions
Bit
15:5
4
Field
Type
—
Reset
Description
Reserved
LDAC
0
0
Reserved for factory use.
W
Set this bit to 1 to synchronously load those DACs that have
been set in synchronous mode in the SYNC register.
3:0
SOFT-RESET[3:0]
W
0x0
When set to the reserved code 1010 resets the device to its
default state.
34
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DAC80504, DAC70504, DAC60504
www.ti.com.cn
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
8.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]
Figure 71. BRDCAST Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BRDCAST-DATA[15:0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. BRDCAST Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
BRDCAST-DATA[15:0]
R/W
0x0000
Writing to the BRDCAST register forces those DAC channels
that have been set to broadcast in the SYNC register to update
their active data register with the BRDCAST-DATA value.
Data are MSB aligned in straight binary format and follows the
format below:
DAC80504: { DATA[15:0] }
DAC70504: { DATA[13:0], x, x }
DAC60504: { DATA[11:0], x, x, x, x }
x – Don’t care bits
8.6.8 STATUS Register (address = 0x7) [reset = 0x0000]
Figure 72. STATUS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
REF-
ALM
—
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. STATUS Register Field Descriptions
Bit
15:1
0
Field
Type
—
Reset
Description
Reserved
REF-ALM
0
0
Reserved for factory use.
R
Reference alarm bit. Reads 1 when the difference between
VREF/DIV and VDD is below the required minimum analog
threshold. Reads 0 otherwise.
8.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]
Figure 73. DACx Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DACx-DATA[15:0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. DACx Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
DACx-DATA[15:0]
R/W
0x0000 or Stores the 16- or 14-bit data to be loaded to DACx in MSB
0x8000
aligned straight binary format. The default value is determined
by the RSTSEL pin.
Data follows the format below:
DAC80504: { DATA[15:0] }
DAC70504: { DATA[13:0], x, x }
DAC60504: { DATA[11:0], x, x, x, x }
x – Don’t care bits
Copyright © 2017–2019, Texas Instruments Incorporated
35
DAC80504, DAC70504, DAC60504
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The high linearity, small package size and wide temperature range make the DACx0504 suitable in applications
such as optical networking, wireless infrastructure, industrial automation and data acquisition systems. The
device incorporates a 2.5 V internal reference with an internal reference divider circuit that enables full-scale
DAC output voltages of 1.25 V, 2.5 V, or 5 V.
9.1.1 Interfacing to a Microcontroller
Figure 74 displays a typical serial interface that may be observed when connecting the DACx0504 SPI serial
interface to a (master) microcontroller type platform. The setup for the interface is as follows: the microcontroller
output SPI CLK drives the SCLK pin of the DACx0504, while the DACx0504 SDI pin is driven by the MOSI pin of
the microcontroller. The CS pin of the DACx0504 can be asserted from a general program input/output pin of the
microcontroller. When data are to be transmitted to the DACx0504, the CS pin is taken low. The data from the
microcontroller is then transmitted to the DACx0504, totaling 24 bits latched into the DACx0504 device through
the falling edge of SCLK. CS is then brought high after the completed write. The DACx0504 requires data with
the MSB as the first bit received.
Microcontroller
DACx0504
CS
CS
SCLK
SCLK
MOSI
MISO
SDI
SDO
Copyright © 2017, Texas Instruments Incorporated
Figure 74. Typical Serial Interface
36
Copyright © 2017–2019, Texas Instruments Incorporated
DAC80504, DAC70504, DAC60504
www.ti.com.cn
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
Application Information (continued)
9.1.2 Programmable Current Source Circuit
The DACx0504 can be integrated into the circuit in Figure 75 to implement an improved Howland current pump
for precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two
features of the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 2.
R2 + R3 / R1
(
)
CODE
2n
IL
=
ì VREF ì
R3
(2)
The value of R3 in Equation 2 can be reduced to increase the output current drive of U3. U3 can drive ±20 mV in
both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the circuit
compensation capacitor C1 in the circuit is not suggested as a result of the change in the output impedance ZO,
according to Equation 3.
'
R1 R3 R1+ R2
(
)(
)
(
)
ZO
=
R1 R2' + R3' -R1 R2 + R3
'
(
)
(3)
As shown in Equation 3, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems
are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a
value of several pF is suggested.
R2'
15 kꢀ
C1
VDD REF
VDD VREF
10 pF
R1'
150 kꢀ
R3'
50 ꢀ
VDAC
DACx0504
U3
V
OPA277
OUT
GND
R3
50 ꢀ
GND
R1
R2
150 kꢀ
15 kꢀ
IL
LOAD
Copyright © 2017, Texas Instruments Incorporated
Figure 75. Programmable Bidirectional Current Source Circuit
Copyright © 2017–2019, Texas Instruments Incorporated
37
DAC80504, DAC70504, DAC60504
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
www.ti.com.cn
9.2 Typical Application
The DACx0504 is designed for single-supply operation; however, a bipolar output is also possible using the
circuit shown in Figure 76.
GND
15 V
VDAC
DACx0504
OPA192
VOUT
R2
REF
VREF
œ15 V
R3
R1
VREF
Copyright © 2017, Texas Instruments Incorporated
Figure 76. Bipolar Operation Using the DACx0504
9.2.1 Design Requirements
The circuit shown in Figure 76 gives a bipolar output voltage at VOUT. When GAIN = 1, VOUT can be calculated
using Equation 4:
»
ÿ
Ÿ
≈
∆
«
’
÷
≈
’
÷
R3 R3
R3
CODE
2n
≈
’
VOUT CODE = VREF
ì
1+
+
- VREF ì
(
)
…
…
∆
∆
÷
◊
R2 R1 ◊
R1 ◊
«
Ÿ
⁄
«
where
•
•
•
•
VOUT(CODE) = output voltage versus code
CODE = 0 to 2n – 1. This is the digital code loaded to the DAC
VREF = reference voltage applied to the DACx0504
n = resolution in bits
(4)
Table 18. Design Parameters
PARAMETER
VALUE
±10 V
2.5 V
12
VOUT
VREF
n
9.2.2 Detailed Design Procedure
The bipolar output span can be calculated through Equation 4 by defining a few parameters, the first being the
value for the reference voltage. Once a reference voltage is chosen, the gain resistors can be set accordingly by
determining the desired VOUT at code 0 and code 2n. For a VREF of 2.5 V and a desired output voltage range of
±10 V the calculation is as follows.
CODE = 0:
≈
’
÷
≈
’
÷
R3
R3
VOUT 0 = - VREF ì
= - 2.5V ì
( )
∆
∆
R1 ◊
R1 ◊
«
«
(5)
Setting the equation to minimum output span, VOUT(0) = –10 V, will reduce the equation to: R3/R1 = 4:
CODE = 4096:
Setting the equation to maximum output scan, VOUT(4096) = 10 V, and R3/R1 = 4 will reduce the equation to:
R3/R2 = 3
It is important to note that the maximum code of a 12-bit DAC is 4095; code 4096 was used to simplify the
equation above. For practical use, the true output span will encompass a range of –10 V to (10 V – 1 LSB),
which in this case is –10 V to 9.995 V.
38
Copyright © 2017–2019, Texas Instruments Incorporated
DAC80504, DAC70504, DAC60504
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ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
9.2.3 Application Curve
The ±10 V output span with a reference voltage of 2.5 V can be achieved by using values of 30 kΩ, 10 kΩ, and
7.5 kΩ for R3, R2, and R1, respectively. A curve to illustrate this output span is shown in Figure 77. For this
example, 1% tolerance resistors were used in evaluating bipolar operation.
10
5
0
-5
-10
0
512 1024 1536 2048 2560 3072 3584 4096
DAC Code
D001
Figure 77. Bipolar Operation
Copyright © 2017–2019, Texas Instruments Incorporated
39
DAC80504, DAC70504, DAC60504
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
www.ti.com.cn
10 Power Supply Recommendations
The DACx0504 operates within the specified VDD supply range of 2.7 V to 5.5 V, and VIO supply range of 1.7 V to
5.5 V. The DACx0504 does not require specific supply sequencing.
The VDD supply must be well-regulated and low-noise. Switching power supplies and dc-dc converters often have
high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar
high-frequency spikes. This noise can easily couple into the DAC output voltage through various paths between
the power connections and analog output. In order to further minimize noise from the power supply, include a 1-
μF to 10-μF capacitor and 0.1-μF bypass capacitor. The current consumption on the VDD pin, the short-circuit
current limit, and the load current for the device is listed in the Electrical Characteristics. The power supply must
meet the aforementioned current requirements.
11 Layout
11.1 Layout Guidelines
A precision analog component requires careful layout, the list below provides some insight into good layout
practices.
•
•
•
•
Bypass all power supply pins to ground with a low-ESR ceramic bypass capacitor. The typical recommended
bypass capacitance is 0.1-µF to 0.22-µF ceramic with a X7R or NP0 dielectric.
Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize
performance.
Use a high-quality ceramic type NP0 or X7R for its optimal performance across temperature, and very low
dissipation factor.
The digital and analog sections must have proper placement with respect to the digital pins and analog pins
of the DACx0504 device. The separation of analog and digital blocks minimizes coupling into neighboring
blocks, as well as interaction between analog and digital return currents.
11.2 Layout Example
ANALOG SIDE
GND POUR
BYPASS CAPACITOR
2
1
4
3
16
15
14
13
5
6
7
8
BYPASS CAPACITORS
10 11
12
9
GND POUR
DIGITAL SIDE
Figure 78. DACx0504 Layout Example
40
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DAC80504, DAC70504, DAC60504
www.ti.com.cn
ZHCSH59C –AUGUST 2017–REVISED JANUARY 2019
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档： 《DACx0504 评估模块用户指南》
12.2 相关链接
表 19 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具与软件，以及立即订购快速访问。
表 19. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
DAC80504
DAC70504
DAC60504
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2019, Texas Instruments Incorporated
41
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC60504BRTER
DAC60504BRTET
DAC70504RTER
DAC70504RTET
DAC80504RTER
DAC80504RTET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTE
RTE
RTE
RTE
RTE
RTE
16
16
16
16
16
16
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
654B
654B
70504
70504
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(80504, 854)
(80504, 854)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC60504BRTER
DAC60504BRTET
DAC70504RTER
DAC70504RTET
DAC80504RTER
DAC80504RTET
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTE
RTE
RTE
RTE
RTE
RTE
16
16
16
16
16
16
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.0
1.0
1.0
1.0
1.0
1.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC60504BRTER
DAC60504BRTET
DAC70504RTER
DAC70504RTET
DAC80504RTER
DAC80504RTET
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTE
RTE
RTE
RTE
RTE
RTE
16
16
16
16
16
16
3000
250
367.0
213.0
367.0
213.0
367.0
213.0
367.0
191.0
367.0
191.0
367.0
191.0
38.0
35.0
38.0
35.0
38.0
35.0
3000
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016D
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.15
2.85
A
B
PIN 1 INDEX AREA
3.15
2.85
C
0.8
0.7
SEATING PLANE
0.08 C
0.05
0.00
2X 1.5
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
SYMM
17
2X 1.5
0.8 0.1
12X 0.5
1
12
PIN 1 ID
0.30
0.18
16X
16
13
0.5
0.3
0.1
C A B
16X
0.05
4219118/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.8)
SYMM
SEE SOLDER MASK
DETAIL
16
13
16X (0.6)
12
16X (0.24)
1
17
SYMM
(2.8)
12X (0.5)
(R0.05) TYP
4
9
(
0.2) TYP
VIA
5
8
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219118/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.76)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
12X (0.5)
(2.8)
9
4
(R0.05) TYP
5
8
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219118/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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