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DAC7562T, DAC7563T, DAC8162T

DAC8163T, DAC8562T, DAC8563T

ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

DACxx6xT 具有 2.5V、4PPM/°C 内部基准和 5V TTL I/O 的双路 16 位、

14 位、12 位低功耗电压输出 DAC

1 特性

3 说明

1

•

相对精度：16 位时为 4 最低有效位 (LSB) 最大积

分非线性 (INL)

DAC856xT、DAC816xT 和 DAC756xT 器件分别为 16

位、14 位和 12 位低功耗电压输出双通道数模转换器

(DAC)。这些器件包括一个 2.5V、

•

低毛刺脉冲：0.1nV-s

双向基准引脚：输入或 2.5V 输出

4ppm/°C 内部基准，从而提供了一个 2.5V 或 5V 的满

量程输出电压范围。此内部基准有一个 ±5mV 的初始

精度，并且能够在 V_REFIN/V_REFOUT引脚上提供或吸收高

达 20mA 的电流。

–

4ppm/°C 温度漂移（典型值）

•

上电复位至零量程或量程中点

低功耗：5V AVDD 时为 4mW

宽电源范围：2.7V 至 5.5V

这些器件是单片器件，从而提供了出色的线性并大大降

低了有害的代码至代码转换时的瞬态电压（毛刺脉

冲）。它们使用一个运行时钟速率高达 50MHz 的多

用途 3 线制串口。此接口与标准 SPI™， QSPI™，

Microwire，以及数字信号处理器 (DSP) 接口兼容。

DACxx62T 器件配有一个上电复位电路，此电路可确

保在一个有效代码被写入此器件前，DAC 输出上电并

保持零量程，而 DACxx63T 在量程中点上电。这些器

件包含一个断电特性，此特性可将 5V 电压时的流耗减

少至 550nA（典型值）。此低功耗、内部基准和小封

装尺寸使得这些器件非常适合于便携式、电池供电运行

类设备。

带有施密特触发输入的 50MHz 串行外设接口 (SPI)

LDAC 和 CLR 功能

支持轨到轨运行的输出缓冲器

与 DAC8562 系列引脚到引脚兼容

支持 5V 晶体管晶体管逻辑电路 (TTL) I/O

封装：晶圆级小外形无引线 (WSON)-10 (3mm ×

3mm)，超薄小外形尺寸 (VSSOP)-10

•

温度范围：-40°C 至 125°C

2 应用

•

便携式仪表

可编程逻辑控制器 (PLC) 模拟输出模块

双极输出（第 9.2.2 节）

闭环伺服器控制

与 DACxx62T 器件一样，DACxx63T 器件之间可互相

插接并且功能兼容。整个系列均提供 VSSOP-10 和

WSON-10 封装。

压控振荡器调谐

数据采集系统

器件信息⁽¹⁾

可编程增益和偏移调整

器件型号

DAC8562T

封装

封装尺寸（标称值）

VSSOP (10)，

WSON (10)

DAC8162T

DAC7562T

3.00mm × 3.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

简化框图

GND

AVDD

LDAC

CLR

V_REFIN/V_REFOUT

Power-

Down

Control

Logic

D_IN

Buffer Control

Register Control

2.5-V

Reference

Input Control Logic

SCLK

SYNC

Control Logic

DAC Register B

DAC Register A

V_OUT

B

Data Buffer B

Data Buffer A

DAC

DAC756xT (12-Bit)

DAC816xT (14-Bit)

DAC856xT (16-Bit)

V_OUTA

DAC

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLASE61

DAC7562T, DAC7563T, DAC8162T

DAC8163T, DAC8562T, DAC8563T

ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

www.ti.com

8.4 Device Functional Modes........................................ 32

8.5 Programming........................................................... 36

Application and Implementation ........................ 39

9.1 Application Information............................................ 39

9.2 Typical Applications ................................................ 41

9.3 System Examples ................................................... 45

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements................................................ 9

7.7 Typical Characteristics............................................ 10

Detailed Description ............................................ 28

8.1 Overview ................................................................. 28

8.2 Functional Block Diagram ....................................... 28

8.3 Feature Description................................................. 28

9

10 Power Supply Recommendations ..................... 46

11 Layout................................................................... 46

11.1 Layout Guidelines ................................................. 46

11.2 Layout Example .................................................... 47

12 器件和文档支持 ..................................................... 49

12.1 相关链接................................................................ 49

12.2 社区资源................................................................ 49

12.3 Trademarks........................................................... 49

12.4 Electrostatic Discharge Caution............................ 49

12.5 Glossary................................................................ 49

13 机械、封装和可订购信息....................................... 49

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (September 2015) to Revision A

Page

•

从产品预览改为量产数据 ........................................................................................................................................................ 1

2

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

5 Device Comparison Table

MAXIMUM

DIFFERENTIAL

NONLINEARITY (LSB)

MAXIMUM RELATIVE

ACCURACY (LSB)

MAXIMUM REFERENCE

RESET TO

DEVICE

DRIFT (ppm/°C)

DAC7562T

DAC7563T

DAC8162T

DAC8163T

DAC8562T

DAC8563T

Zero

±0.75

±0.25

±0.5

±1

10

Mid-scale

Zero

±3

10

Mid-scale

Zero

±12

10

Mid-scale

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

www.ti.com

6 Pin Configuration and Functions

DGS Package

10-Pin VSSOP

(Top View)

DSC Package

10-Pin WSON

(Top View)

1

2

3

4

5

10

9

V_OUT

A

V_REFIN/V_REFOUT

AV_DD

1

2

3

4

5

10

V_OUT

A

V_REFIN/V_REFOUT

V_OUT

B

9

8

7

6

V_OUT

B

AV_DD

D_IN

8

D_IN

GND

LDAC

CLR

GND

LDAC

CLR

Thermal Pad⁽¹⁾

7

SCLK

SYNC

6

SYNC

(1) TI recommends connecting the thermal pad to the ground plane for better thermal dissipation.

Pin Functions

I/O

DESCRIPTION

NAME

AV_DD

NO.

9

I

Power-supply input, 2.7 V to 5.5 V

Asynchronous clear input. The CLR input is falling-edge sensitive. On activation of CLR, zero

scale (DACxx62T) or mid-scale (DACxx63T) is loaded to all input and DAC registers. This sets the

DAC output voltages accordingly. The device exits clear code mode on the 24^thfalling edge of the

next write to the device. Activating CLR during a write sequence aborts the write.

CLR

5

I

Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the

serial clock input. Schmitt-trigger logic input

D_IN

8

3

I

GND

—

Ground reference point for all circuitry on the device

In synchronous mode, data update occurs with the falling edge of the 24^thSCLK cycle, which

follows a falling edge of SYNC. Such synchronous updates do not require the LDAC, which must

be connected to GND permanently or asserted and held low before sending commands to the

device.

In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for

simultaneous DAC updates. Multiple single-channel commands can be written in order to set

different channel buffers to desired values and then make a falling edge on the LDAC pin to

update the DAC output registers simultaneously.

LDAC

4

I

SCLK

SYNC

7

6

I

Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input

Level-triggered control input (active-low). This input is the frame synchronization signal for the

input data. When SYNC goes low, it enables the input shift register, and data are sampled on

subsequent falling clock edges. The DAC output updates following the 24^thclock falling edge. If

SYNC is taken high before the 23^rdclock edge, the rising edge of SYNC acts as an interrupt, and

the write sequence is ignored by the DAC756xT, DAC816xT, and DAC856xT devices. Schmitt-

trigger logic input

V_OUT

A

B

1

2

O

Analog output voltage from DAC-A

V_OUT

Analog output voltage from DAC-B

V_REFIN/V_REFOUT

10

I/O

Bidirectional voltage reference pin. If internal reference is used, 2.5-V output.

4

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

Over operating ambient temperature range (unless otherwise noted).

MIN

–0.3

–40

MAX

6

UNIT

V

AV_DDto GND

CLR, D_IN, LDAC, SCLK and SYNC input voltage to GND

V_OUT[A, B] to GND

AV_DD+ 0.3

125

V

V_REFIN/V_REFOUTto GND

V

Operating temperature range

Junction temperature, T_J

°C

150

Storage temperature, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

2.7

0

NOM

MAX

5.5

UNIT

V

POWER SUPPLY

Supply voltage

DIGITAL INPUTS

Digital input voltage

AV_DDto GND

CLR, D_IN, LDAC, SCLK and SYNC

AV_DD

125

V

REFERENCE INPUT

V_REFINReference input voltage

TEMPERATURE RANGE

0

V

T_A

Operating ambient temperature

–40

°C

7.4 Thermal Information

DAC756xT, DAC816xT, DAC856xT

THERMAL METRIC

DSC (WSON)

10 PINS

62.8

DGS (VSSOP)

10 PINS

173.8

48.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

44.3

26.5

79.9

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

1.7

ψ_JB

25.5

68.4

R_θJC(bot)

46.2

N/A

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

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7.5 Electrical Characteristics

At AV_DD= 2.7 V to 5.5 V and T_A= –40°C to 125°C (unless otherwise noted).

PARAMETER

STATIC PERFORMANCE⁽¹⁾

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

12

Bits

LSB

Bits

LSB

Bits

LSB

DAC756xT

DAC816xT

DAC856xT

Relative accuracy

Using line passing through codes 32 and 4,064

±0.3

±0.75

±0.25

Differential nonlinearity 12-bit monotonic

±0.05

Resolution

14

16

Relative accuracy

Using line passing through codes 128 and 16,256

±1

±3

Differential nonlinearity 14-bit monotonic

Resolution

±0.1

±0.5

Relative accuracy

Using line passing through codes 512 and 65,024

±4

±0.2

±1

±12

±1

Differential nonlinearity 16-bit monotonic

Offset error

Extrapolated from two-point line⁽¹⁾, unloaded

±4

mV

µV/°C

% FSR

mV

Offset error drift

Full-scale error

Zero-code error

Zero-code error drift

Gain error

±2

DAC register loaded with all 1s, DAC output unloaded

DAC register loaded with all 0s, DAC output unloaded

±0.03

1

±0.2

4

±2

µV/°C

% FSR

Extrapolated from two-point line⁽¹⁾, unloaded

±0.01

±0.15

ppm

FSR/°C

Gain temperature coefficient

±1

OUTPUT CHARACTERISTICS⁽²⁾

Output voltage range

0

AV_DD

V

µs

DACs unloaded

7

10

Output voltage settling time⁽³⁾

Slew rate

R_L= 1 MΩ

Measured between 20%–80% of a full-scale transition

R_L= ∞

0.75

1

V/µs

nF

Capacitive load stability

R_L= 2 kΩ

3

Code-change glitch impulse

Digital feedthrough

1-LSB change around major carry

SCLK toggling, SYNC high

R_L= 2 kΩ, C_L= 470 pF, AV_DD= 5.5 V

0.1

40

nV-s

mV

Power-on glitch impulse

Full-scale swing on adjacent channel,

External reference

5

Channel-to-channel dc crosstalk

µV

Full-scale swing on adjacent channel,

Internal reference

15

5

DC output impedance

Short-circuit current

At mid-scale input

Ω

mA

µs

DAC outputs at full-scale, DAC outputs shorted to

GND

40

50

Power-up time, including settling time

AC PERFORMANCE⁽²⁾

DAC output noise density

DAC output noise

Coming out of power-down mode

T_A= 25°C, at mid-scale input, f_OUT= 1 kHz

T_A= 25°C, at mid-scale input, 0.1 Hz to 10 Hz

90

nV/√Hz

2.6

µV_PP

LOGIC INPUTS⁽²⁾

Input-pin leakage current

Logic input LOW voltage V_IL

Logic input HIGH voltage V_IH

Pin capacitance

–1

0

±0.1

1

0.8

µA

V

2.1

AV_DD

3

V

pF

(1) 16-bit: codes 512 and 65,024; 14-bit: codes 128 and 16,256; 12-bit: codes 32 and 4,064, All digital inputs kept at same IO levels before

and after write to the DAC

(2) Specification based on design or characterization

(3) Transition time between 1 / 4 scale and 3 / 4 scale, including settling to within ±0.024% FSR

6

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

Electrical Characteristics (continued)

At AV_DD= 2.7 V to 5.5 V and T_A= –40°C to 125°C (unless otherwise noted).

PARAMETER

REFERENCE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

External V_REF= 2.5 V (when internal reference is

disabled), all channels active using gain = 1

External reference current

Reference input impedance

15

µA

Internal reference disabled, gain = 1

Internal reference disabled, gain = 2

170

85

kΩ

REFERENCE OUTPUT

Output voltage

T_A= 25°C

2.495

–5

2.5

2.505

5

V

Initial accuracy

±0.1

mV

Internal reference output voltage temperature drift is

characterized from –40°C to 125°C.

Output-voltage temperature drift

Output-voltage noise

4

10

ppm/°C

µV_PP

f = 0.1 Hz to 10 Hz

12

250

30

T_A= 25°C, f = 1 kHz, C_L= 0 µF

T_A= 25°C, f = 1 MHz, C_L= 0 µF

T_A= 25°C, f = 1 MHz, C_L= 4.7 µF

T_A= 25°C

Output-voltage noise density (high-

frequency noise)

nV/√Hz

10

Load regulation, sourcing⁽⁴⁾

Load regulation, sinking⁽⁴⁾

Output-current load capability⁽²⁾

Line regulation

20

µV/mA

mA

T_A= 25°C

185

±20

50

T_A= 25°C

µV/V

ppm

Long-term stability or drift (aging)⁽⁴⁾

T_A= 25°C, time = 0 to 1900 hours

First cycle

100

200

50

Thermal hysteresis⁽⁴⁾

ppm

Additional cycles

POWER REQUIREMENTS⁽⁵⁾

AV_DD= 3.6 V to 5.5 V, normal mode, internal

reference off, Digital inputs at VDD or GND

0.25

0.9

0.5

4

AV_DD= 3.6 V to 5.5 V, normal mode, internal

reference off, Digital inputs at TTL level

mA

µA

AV_DD= 3.6 V to 5.5 V, normal mode, internal

reference on, Digital inputs at VDD or GND

1.6

5

AV_DD= 3.6 V to 5.5 V, normal mode, internal

reference on, Digital inputs at TTL level

AV_DD= 3.6 V to 5.5 V, power-down modes, Digital

inputs at VDD or GND

0.55

0.2

4

Power supply current (I_DD

)

AV_DD= 2.7 V to 3.6 V, normal mode, internal

reference off, Digital inputs at VDD or GND

0.4

0.8

1.4

1.8

3

AV_DD= 2.7 V to 3.6 V, normal mode, internal

reference off, Digital inputs at TTL level

mA

µA

AV_DD= 2.7 V to 3.6 V, normal mode, internal

reference on, Digital inputs at VDD or GND

0.73

0.35

AV_DD= 2.7 V to 3.6 V, normal mode, internal

reference on, Digital inputs at TTL level

AV_DD= 2.7 V to 3.6 V, power-down modes, Digital

inputs at VDD or GND

(4) See the Application Information section of this data sheet.

(5) Input code = mid-scale, no load

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Electrical Characteristics (continued)

At AV_DD= 2.7 V to 5.5 V and T_A= –40°C to 125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AV_DD= 3.6 V to 5.5 V, normal mode, internal

reference off, Digital inputs at VDD or GND

0.9

2.75

mW

AV_DD= 3.6 V to 5.5 V, normal mode, internal

reference on, Digital inputs at VDD or GND

3.2

2

8.8

22

AV_DD= 3.6 V to 5.5 V, power-down modes, Digital

inputs at VDD or GND

µW

mW

µW

Power dissipation

AV_DD= 2.7 V to 3.6 V, normal mode, internal

reference off, Digital inputs at VDD or GND

0.54

1.97

0.95

1.44

5

AV_DD= 2.7 V to 3.6 V, normal mode, internal

reference on, Digital inputs at VDD or GND

AV_DD= 2.7 V to 3.6 V, power-down modes, Digital

inputs at VDD or GND

10.8

8

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

7.6 Timing Requirements⁽¹⁾⁽²⁾

At AV_DD= 2.7 V to 5.5 V, external V_REFIN= 2.5 V to 5.5 V, and over –40°C to 125°C (unless otherwise noted). See Figure 1.

DAC756xT, DAC816xT,

DAC856xT

UNIT

MIN

TYP

MAX

f_(SCLK)

t₍₁₎

Serial clock frequency

50

MHz

ns

SCLK falling edge to SYNC falling edge (for successful write operation)

SCLK cycle time

SYNC rising edge to 23^rdSCLK falling edge (for successful SYNC interrupt)

10

20

13

15

13

8

t₍₂₎

t₍₃₎

t₍₄₎

Minimum SYNC HIGH time

t₍₅₎

SYNC to SCLK falling edge setup time

SCLK LOW time

t₍₆₎

t₍₇₎

SCLK HIGH time

8

t₍₈₎

SCLK falling edge to SYNC rising edge

Data setup time

10

6

t₍₉₎

t₍₁₀₎

t₍₁₁₎

t₍₁₂₎

t₍₁₃₎

t₍₁₄₎

Data hold time

6

SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode

LDAC pulse duration, LOW time

5

10

80

CLR pulse duration, LOW time

CLR falling edge to start of V_OUTtransition

100

(1) All input signals are specified with t_r= t_f= 1 ns/V (10% to 90% of AV_DD) and timed from a voltage level of (V_IL+ V_IH) / 2.

(2) See the Serial Write Operation timing diagram (Figure 1).

t₍₁₎

t₍₂₎

SCLK

SYNC

D_IN

t₍₅₎

t₍₆₎

t₍₃₎

t₍₇₎

t₍₈₎

t₍₄₎

t₍₁₀₎

t₍₉₎

DB23

DB0

t₍₁₁₎

t₍₁₂₎

LDAC⁽¹⁾

LDAC⁽²⁾

t₍₁₃₎

CLR

t₍₁₄₎

V_OUT

x

(1) Asynchronous LDAC update mode. For more information, see the LDAC Functionality section.

(2) Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section.

Figure 1. Timing Diagram, Serial Write Operation

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7.7 Typical Characteristics

Table 1. Typical Characteristics: Internal Reference Performance

POWER-SUPPLY

VOLTAGE

MEASUREMENT

Internal Reference Voltage vs Temperature

FIGURE NUMBER

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Internal Reference Voltage Temperature Drift Histogram

Internal Reference Voltage vs Load Current

Internal Reference Voltage vs Time

5.5 V

Internal Reference Noise Density vs Frequency

Internal Reference Voltage vs Supply Voltage

2.7 V–5.5 V

Table 2. Typical Characteristics: DAC Static Performance

POWER-SUPPLY

MEASUREMENT

VOLTAGE

FIGURE NUMBER

FULL-SCALE, GAIN, OFFSET AND ZERO-CODE ERRORS

Full-Scale Error vs Temperature

Gain Error vs Temperature

Offset Error vs Temperature

Zero-Code Error vs Temperature

Full-Scale Error vs Temperature

Gain Error vs Temperature

Offset Error vs Temperature

Zero-Code Error vs Temperature

LOAD REGULATION

Figure 16

Figure 17

Figure 18

Figure 19

Figure 63

Figure 64

Figure 65

Figure 66

5.5 V

2.7 V

5.5 V

2.7 V

Figure 30

Figure 74

DAC Output Voltage vs Load Current

DIFFERENTIAL NONLINEARITY ERROR

T = –40°C

T = 25°C

T = 125°C

Figure 9

Figure 11

Figure 13

Figure 15

Figure 56

Figure 58

Figure 60

Figure 62

Differential Linearity Error vs Digital Input Code

Differential Linearity Error vs Temperature

Differential Linearity Error vs Digital Input Code

Differential Linearity Error vs Temperature

5.5 V

2.7 V

T = –40°C

T = 25°C

T = 125°C

INTEGRAL NONLINEARITY ERROR (RELATIVE ACCURACY)

T = –40°C

Figure 8

Figure 10

Figure 12

Figure 14

Figure 55

Figure 57

Figure 59

Figure 61

Linearity Error vs Digital Input Code

Linearity Error vs Temperature

Linearity Error vs Digital Input Code

Linearity Error vs Temperature

T = 25°C

5.5 V

2.7 V

T = 125°C

T = –40°C

T = 25°C

T = 125°C

10

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

Table 2. Typical Characteristics: DAC Static Performance (continued)

POWER-SUPPLY

VOLTAGE

MEASUREMENT

FIGURE NUMBER

POWER-DOWN CURRENT

Power-Down Current vs Temperature

Power-Down Current vs Power-Supply Voltage

Power-Down Current vs Temperature

POWER-SUPPLY CURRENT

5.5 V

2.7 V – 5.5 V

2.7 V

Figure 28

Figure 29

Figure 73

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 49

Figure 50

Figure 51

Figure 52

Figure 53

Figure 54

Figure 67

Figure 68

Figure 69

Figure 70

Figure 71

Figure 72

Power-Supply Current vs Temperature

Power-Supply Current vs Digital Input Code

Power-Supply Current Histogram

5.5 V

2.7 V – 5.5 V

3.6 V

Power-Supply Current vs Power-Supply Voltage

Power-Supply Current vs Temperature

Power-Supply Current vs Digital Input Code

Power-Supply Current Histogram

Power-Supply Current vs Temperature

Power-Supply Current vs Digital Input Code

Power-Supply Current Histogram

2.7 V

Table 3. Typical Characteristics: DAC Dynamic Performance

POWER-SUPPLY

MEASUREMENT

VOLTAGE

FIGURE NUMBER

CHANNEL-TO-CHANNEL CROSSTALK

5-V Rising Edge

5-V Falling Edge

Figure 43

Figure 44

Channel-to-Channel Crosstalk

CLOCK FEEDTHROUGH

Clock Feedthrough

5.5 V

2.7 V

Figure 48

Figure 87

500 kHz, Midscale

GLITCH IMPULSE

Rising Edge, Code 7FFFh to 8000h

Falling Edge, Code 8000h to 7FFFh

Rising Edge, Code 7FFCh to 8000h

Falling Edge, Code 8000h to 7FFCh

Rising Edge, Code 7FF0h to 8000h

Falling Edge, Code 8000h to 7FF0h

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

Figure 42

Glitch Impulse, 1-LSB Step

Glitch Impulse, 4-LSB Step

Glitch Impulse, 16-LSB Step

5.5 V

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Table 3. Typical Characteristics: DAC Dynamic Performance (continued)

POWER-SUPPLY

VOLTAGE

MEASUREMENT

FIGURE NUMBER

Rising Edge, Code 7FFFh to 8000h

Figure 79

Figure 80

Figure 81

Figure 82

Figure 83

Figure 84

Glitch Impulse, 1-LSB Step

Glitch Impulse, 4-LSB Step

Falling Edge, Code 8000h to 7FFFh

Rising Edge, Code 7FFCh to 8000h

Falling Edge, Code 8000h to 7FFCh

Rising Edge, Code 7FF0h to 8000h

Falling Edge, Code 8000h to 7FF0h

2.7 V

Glitch Impulse, 16-LSB Step

NOISE

External V_REF

Internal V_REF

External V_REF

Figure 45

Figure 46

Figure 47

DAC Output Noise Density vs

Frequency

5.5 V

DAC Output Noise 0.1 Hz to 10 Hz

POWER-ON GLITCH

Reset to Zero Scale

Reset to Midscale

Reset to Zero Scale

Reset to Midscale

Figure 35

Figure 36

Figure 85

Figure 86

5.5 V

2.7 V

Power-On Glitch

SETTLING TIME

Rising Edge, Code 0h to FFFFh

Falling Edge, Code FFFFh to 0h

Rising Edge, Code 4000h to C000h

Falling Edge, Code C000h to 4000h

Rising Edge, Code 0h to FFFFh

Falling Edge, Code FFFFh to 0h

Rising Edge, Code 4000h to C000h

Falling Edge, Code C000h to 4000h

Figure 31

Figure 32

Figure 33

Figure 34

Figure 75

Figure 76

Figure 77

Figure 78

Full-Scale Settling Time

5.5 V

2.7 V

Half-Scale Settling Time

Full-Scale Settling Time

Half-Scale Settling Time

12

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

7.7.1 Typical Characteristics: Internal Reference

At T_A= 25°C, AV_DD= 5.5 V, gain = 2, and V_REFOUTunloaded, unless otherwise noted.

30

25

20

15

10

5

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

60 units shown

(30 MSOP, 30 SON-10)

0

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Temperature Drift (ppm/èC)

Figure 2. Internal Reference Voltage vs Temperature

Figure 3. Internal Reference Voltage, Temperature Drift

Histogram

2.510

400

300

200

100

0

2.505

2.500

2.495

2.490

−100

−200

−300

−400

16 units shown (8 MSOP, 8 SON-10)

Average shown in dashed line

−20

−15

−10

−5

0

5

10

15

20

0

250

500

750

1000

1250

1500

Load Current (mA)

Elapsed Time (Hours)

Figure 4. Internal Reference Voltage vs Load Current

Figure 5. Internal Reference Voltage vs Time

400

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

No Load

4.7 µF Load

−40°C

+25°C

+125°C

350

300

250

200

150

100

50

0

10

100

1k

10k

100k

1M

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

Frequency (Hz)

AV_DD(V)

Figure 6. Internal Reference Noise Density vs Frequency

Figure 7. Internal Reference Voltage vs Supply Voltage

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7.7.2 Typical Characteristics: DAC at AV_DD= 5.5 V

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

−40°C

Typical channel shown

−40°C

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 8. Linearity Error vs Digital Input Code (–40°C)

Figure 9. Differential Linearity Error vs Digital Input Code

(–40°C)

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−3

−6

−9

Typical channel shown

25°C

Typical channel shown

−0.8

25°C

−1.0

−12

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 10. Linearity Error vs Digital Input Code (25°C)

Figure 11. Differential Linearity Error vs Digital Input Code

(25°C)

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−3

−6

−9

Typical channel shown

125°C

Typical channel shown

−0.8

125°C

−1.0

−12

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 12. Linearity Error vs Digital Input Code (125°C)

Figure 13. Differential Linearity Error vs Digital Input Code

(125°C)

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

Typical Characteristics: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

12

1.0

INL Max

INL Min

DNL Max

DNL Min

0.8

9

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

−40 −25 −10

Typical channel shown

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 14. Linearity Error vs Temperature

Figure 15. Differential Linearity Error vs Temperature

0.20

0.15

Ch A

Ch B

Ch A

Ch B

0.10

0.05

0.10

0.05

0.00

−0.05

−0.10

−0.15

−0.20

−0.05

−0.10

−0.15

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 16. Full-Scale Error vs Temperature

Figure 17. Gain Error vs Temperature

4

3

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Ch A

Ch B

Ch A

Ch B

2

1

0

−1

−2

−3

−4

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 18. Offset Error vs Temperature

Figure 19. Zero-Code Error vs Temperature

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Typical Characteristics: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

Internal reference enabled

DACs at midscale code, Gain = 2

DACs at midscale code

−40 −25 −10 20 35 50 65 80 95 110 125

Temperature (°C)

5

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 20. Power-Supply Current vs Temperature

Figure 21. Power-Supply Current vs Temperature

0.50

1.3

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

Internal reference enabled, Gain = 2

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 22. Power-Supply Current vs Digital Input Code

Figure 23. Power-Supply Current vs Digital Input Code

30

Internal reference enabled

Gain = 2

25

20

15

10

5

0

Power Supply Current (mA)

Figure 24. Power-Supply Current Histogram

Figure 25. Power-Supply Current Histogram

16

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

Typical Characteristics: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

V_REFIN= 2.5 V

DACs at midscale code, Gain = 1

Internal reference enabled

DACs at midscale code, Gain = 1

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

AV_DD(V)

Figure 26. Power-Supply Current vs Power-Supply Voltage

Figure 27. Power-Supply Current vs Power-Supply Voltage

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0.60

I_DD(µA)

I_REFIN(µA)

0.50

0.40

0.30

0.20

0.10

0.00

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

AV_DD(V)

G028

G029

Figure 28. Power-Down Current vs Temperature

Figure 29. Power-Down Current vs Power-Supply Voltage

7.0

Typical channel shown

Full scale

Mid scale

Zero scale

6.0

5.0

4.0

3.0

2.0

1.0

0.0

−1.0

−20

−15

−10

−5

0

5

10

15

20

I_LOAD(mA)

Figure 30. DAC Output Voltage vs Load Current

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Typical Characteristics: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

LDAC Trigger (5 V/div)

Large Signal V_OUT(2 V/div)

Small Signal Settling

(1.22 mV/div = 0.024% FSR)

Small Signal Settling (1.22 mV/div = 0.024% FSR)

From Code: 0h

To Code: FFFFh

From Code: FFFFh

To Code: 0h

Time (5 μs/div)

Figure 31. Full-Scale Settling Time, Rising Edge

Figure 32. Full-Scale Settling Time, Falling Edge

LDAC Trigger (5 V/div)

Large Signal V_OUT(2 V/div)

Small Signal Settling (1.22 mV/div = 0.024% FSR)

From Code: 4000h

To Code: C000h

From Code: C000h

To Code: 4000h

Time (5 μs/div)

Figure 33. Half-Scale Settling Time, Rising Edge

AV_DD(2 V/div)

Time (5 μs/div)

Figure 34. Half-Scale Settling Time, Falling Edge

AV_DD(2 V/div)

V_OUTA (1 V/div)

V_OUTB (1 V/div)

V_OUTA (50 mV/div)

V_OUTB (50 mV/div)

V_REFINshorted to AV_DD

Time (1 ms/div)

Figure 35. Power-On Glitch, Reset to Zero Scale

Figure 36. Power-On Glitch, Reset to Midscale

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

Typical Characteristics: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

LDAC Trigger (5 V/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

V_OUT(100 μV/div)

LDAC Feedthrough

Glitch Impulse » 0.12 nV-s

From Code: 7FFFh

To Code: 8000h

From Code: 8000h

To Code: 7FFFh

Time (5 μs/div)

Figure 37. Glitch Impulse, Rising Edge, 1-LSB Step

Figure 38. Glitch Impulse, Falling Edge, 1-LSB Step

LDAC Trigger (5 V/div)

Glitch Impulse » 0.1 nV-s

LDAC Feedthrough

V_OUT(100 μV/div)

LDAC Feedthrough

Glitch Impulse » 0.14 nV-s

From Code: 8000h

To Code: 7FFCh

From Code: 7FFCh

To Code: 8000h

Time (5 μs/div)

Figure 39. Glitch Impulse, Rising Edge, 4-LSB Step

Figure 40. Glitch Impulse, Falling Edge, 4-LSB Step

LDAC Trigger (5 V/div)

Glitch Impulse » 0.1 nV-s

V_OUT(500 μV/div)

LDAC Feedthrough

V_OUT(500 μV/div)

Glitch Impulse » 0.1 nV-s

From Code: 7FF0h

To Code: 8000h

From Code: 8000h

To Code: 7FF0h

Time (5 μs/div)

Figure 41. Glitch Impulse, Rising Edge, 16-LSB Step

Figure 42. Glitch Impulse, Falling Edge, 16-LSB Step

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Typical Characteristics: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

LDAC Trigger (5 V/div)

V_OUTB (1 V/div)

LDAC Trigger (5 V/div)

Glitch Area (Between Cursors) = 2 nV-s

V_OUTA (500 μV/div)

6.4 μs

V_OUTA (500 μV/div)

V_OUTA at Midscale Code

Glitch Area (Between Cursors) = 1.6 nV-s

V_OUTA at Midscale Code

Internal Reference Enabled

Gain = 2

7.3 μs

V_OUTB (1 V/div)

Internal Reference Enabled

Gain = 2

Time (5 μs/div)

Figure 43. Channel-to-Channel Crosstalk, 5-V Rising Edge

Figure 44. Channel-to-Channel Crosstalk, 5-V Falling Edge

1400

Internal reference disabled

V_REFIN= 5 V, Gain = 1

Full Scale

Mid Scale

Zero Scale

Internal reference enabled

Gain = 2

Full Scale

Mid Scale

Zero Scale

1200

1000

800

600

400

200

0

1200

1000

800

600

400

200

0

10

100

1k

Frequency (Hz)

10k

100k

10

100

1k

10k

100k

Frequency (Hz)

Figure 45. DAC Output Noise Density vs Frequency

Figure 46. DAC Output Noise Density vs Frequency

SCLK (5 V/div)

V_OUT(500 μV/div)

» 2.5 μV_PP

Clock Feedthrough Impulse » 0.06 nV-s

DAC = Midscale

Time (500 ns/div)

Figure 48. Clock Feedthrough, 500 kHz, Midscale

Figure 47. DAC Output Noise, 0.1 Hz to 10 Hz

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ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

7.7.3 Typical Characteristics: DAC at AV_DD= 3.6 V

At T_A= 25°C, 3.3-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

Internal reference enabled

DACs at midscale code, Gain = 1

DACs at midscale code

−40 −25 −10 20 35 50 65 80 95 110 125

Temperature (°C)

5

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 49. Power-Supply Current vs Temperature

Figure 50. Power-Supply Current vs Temperature

0.50

1.3

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

Internal reference enabled, Gain = 1

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 51. Power-Supply Current vs Digital Input Code

Figure 52. Power-Supply Current vs Digital Input Code

30

Internal reference enabled

Gain = 1

25

20

15

10

5

0

Power Supply Current (mA)

Figure 53. Power-Supply Current Histogram

Figure 54. Power-Supply Current Histogram

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7.7.4 Typical Characteristics: DAC at AV_DD= 2.7 V

At T_A= 25°C, 2.5-V external reference used, gain = 1, and DAC output not loaded, unless otherwise noted.

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

−40°C

Typical channel shown

−40°C

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 55. Linearity Error vs Digital Input Code (–40°C)

Figure 56. Differential Linearity Error vs Digital Input Code

(–40°C)

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−3

−6

−9

Typical channel shown

25°C

Typical channel shown

−0.8

25°C

−1.0

−12

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 57. Linearity Error vs Digital Input Code (25°C)

Figure 58. Differential Linearity Error vs Digital Input Code

(25°C)

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−3

−6

−9

Typical channel shown

125°C

Typical channel shown

−0.8

125°C

−1.0

−12

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 59. Linearity Error vs Digital Input Code (125°C)

Figure 60. Differential Linearity Error vs Digital Input Code

(125°C)

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Typical Characteristics: DAC at AV_DD= 2.7 V (continued)

At T_A= 25°C, 2.5-V external reference used, gain = 1, and DAC output not loaded, unless otherwise noted.

12

1.0

INL Max

INL Min

DNL Max

DNL Min

0.8

9

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

−40 −25 −10

Typical channel shown

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 61. Linearity Error vs Temperature

Figure 62. Differential Linearity Error vs Temperature

0.20

0.15

Ch A

Ch B

Ch A

Ch B

0.10

0.05

0.10

0.05

0.00

−0.05

−0.10

−0.15

−0.20

−0.05

−0.10

−0.15

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 63. Full-Scale Error vs Temperature

Figure 64. Gain Error vs Temperature

4

3

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Ch A

Ch B

Ch A

Ch B

2

1

0

−1

−2

−3

−4

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 65. Offset Error vs Temperature

Figure 66. Zero-Code Error vs Temperature

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Typical Characteristics: DAC at AV_DD= 2.7 V (continued)

At T_A= 25°C, 2.5-V external reference used, gain = 1, and DAC output not loaded, unless otherwise noted.

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

Internal reference enabled

DACs at midscale code, Gain = 1

DACs at midscale code

−40 −25 −10 20 35 50 65 80 95 110 125

Temperature (°C)

5

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 67. Power-Supply Current vs Temperature

Figure 68. Power-Supply Current vs Temperature

0.40

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

Internal reference enabled, Gain = 1

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 69. Power-Supply Current vs Digital Input Code

Figure 70. Power-Supply Current vs Digital Input Code

30

Internal reference enabled

Gain = 1

25

20

15

10

5

0

Power Supply Current (mA)

Figure 71. Power-Supply Current Histogram

Figure 72. Power-Supply Current Histogram

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Typical Characteristics: DAC at AV_DD= 2.7 V (continued)

At T_A= 25°C, 2.5-V external reference used, gain = 1, and DAC output not loaded, unless otherwise noted.

3.0

2.5

2.0

1.5

1.0

0.5

0.0

4

Typical channel shown

Full scale

Mid scale

Zero scale

3

2

1

0

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

−1

−20

−15

−10

−5

0

5

10

15

20

G073

I_LOAD(mA)

Figure 74. DAC Output Voltage vs Load Current

Figure 73. Power-Down Current vs Temperature

LDAC Trigger (5 V/div)

Large Signal V_OUT(1 V/div)

Small Signal Settling (0.61 mV/div = 0.024% FSR)

From Code: 0h

To Code: FFFFh

From Code: FFFFh

To Code: 0h

Time (5 μs/div)

Figure 75. Full-Scale Settling Time, Rising Edge

Figure 76. Full-Scale Settling Time, Falling Edge

LDAC Trigger (5 V/div)

Large Signal V_OUT(1 V/div)

Small Signal Settling (0.61 mV/div = 0.024% FSR)

From Code: 4000h

To Code: C000h

From Code: C000h

To Code: 4000h

Time (5 μs/div)

Figure 77. Half-Scale Settling Time, Rising Edge

Figure 78. Half-Scale Settling Time, Falling Edge

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Typical Characteristics: DAC at AV_DD= 2.7 V (continued)

At T_A= 25°C, 2.5-V external reference used, gain = 1, and DAC output not loaded, unless otherwise noted.

LDAC Trigger (5 V/div)

V_OUT(100 μV/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

V_OUT(100 μV/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

From Code: 7FFFh

To Code: 8000h

From Code: 8000h

To Code: 7FFFh

Time (5 μs/div)

Figure 79. Glitch Impulse, Rising Edge, 1-LSB Step

Figure 80. Glitch Impulse, Falling Edge, 1-LSB Step

LDAC Trigger (5 V/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

V_OUT(100 μV/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

From Code: 7FFCh

To Code: 8000h

From Code: 8000h

To Code: 7FFCh

Time (5 μs/div)

Figure 81. Glitch Impulse, Rising Edge, 4-LSB Step

LDAC Trigger (5 V/div)

Figure 82. Glitch Impulse, Falling Edge, 4-LSB Step

LDAC Trigger (5 V/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

V_OUT(200 μV/div)

LDAC Feedthrough

V_OUT(200 μV/div)

Glitch Impulse » 0.1 nV-s

From Code: 7FF0h

To Code: 8000h

From Code: 8000h

To Code: 7FF0h

Time (5 μs/div)

Figure 83. Glitch Impulse, Rising Edge, 16-LSB Step

Figure 84. Glitch Impulse, Falling Edge, 16-LSB Step

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Typical Characteristics: DAC at AV_DD= 2.7 V (continued)

At T_A= 25°C, 2.5-V external reference used, gain = 1, and DAC output not loaded, unless otherwise noted.

AV_DD(2 V/div)

V_OUTA (500 mV/div)

V_OUTB (500 mV/div)

V_OUTA (50 mV/div)

V_OUTB (50 mV/div)

V_REFINshorted to AV_DD

Time (1 ms/div)

Figure 85. Power-On Glitch, Reset to Zero Scale

Figure 86. Power-On Glitch, Reset to Midscale

SCLK (2 V/div)

Clock Feedthrough Impulse » 0.02 nV-s

V_OUT(500 μV/div)

Time (500 ns/div)

Figure 87. Clock Feedthrough, 500 kHz, Midscale

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8 Detailed Description

8.1 Overview

The DAC756xT, DAC816xT, and DAC856xT devices are low-power, voltage-output, dual-channel, 16-, 14-, and

12-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 4-ppm/°C internal

reference, giving a full-scale output voltage range of 2.5 V or 5 V. The internal reference has an initial accuracy

of ±5 mV and can source or sink up to 20 mA at the V_REFIN/V_REFOUTpin.

8.2 Functional Block Diagram

GND

AVDD

LDAC

CLR

V_REFIN/V_REFOUT

Power-

Down

Control

Logic

D_IN

Buffer Control

Register Control

2.5-V

Reference

Input Control Logic

SCLK

SYNC

Control Logic

DAC Register B

DAC Register A

V_OUT

B

Data Buffer B

Data Buffer A

DAC

DAC756xT (12-Bit)

DAC816xT (14-Bit)

DAC856xT (16-Bit)

V_OUTA

DAC

8.3 Feature Description

8.3.1 Digital-to-Analog Converter (DAC)

The DAC756xT, DAC816xT, and DAC856xT architecture consists of two string DACs, each followed by an

output buffer amplifier. The devices include an internal 2.5-V reference with 4-ppm/°C temperature drift

performance. Figure 88 shows a principal block diagram of the DAC architecture.

V_REFIN

/

V_REFOUT

150 kW

Gain

Register

V_OUT

REF(+)

Resistor String

REF(-)

DAC

Register

D_IN

n

GND

Figure 88. DAC Architecture

The input coding to the DAC756xT, DAC816xT, and DAC856xT devices is straight binary, so the ideal output

voltage is given by Equation 1:

D

æ

ç

è

_INö

V_OUT

=

´ V_REF´ Gain

÷

2ⁿ

ø

(1)

where:

n = resolution in bits; either 12 (DAC756xT), 14 (DAC816xT) or 16 (DAC856xT)

D_IN= decimal equivalent of the binary code that is loaded to the DAC register. D_INranges from 0 to 2ⁿ– 1.

V_REF= DAC reference voltage; either V_REFOUTfrom the internal 2.5-V reference or V_REFINfrom an

aaa external reference.

Gain = 1 by default when internal reference is disabled (using external reference), and gain = 2 by default

aaa when using internal reference. Gain can also be manually set to either 1 or 2 using the gain register.

aaa See the Gain Function section for more information.

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Feature Description (continued)

8.3.1.1 Resistor String

The resistor string section is shown in Figure 89. It is simply a string of resistors, each of value R. The code

loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the

output amplifier by closing one of the switches connecting the string to the amplifier. The resistor string

architecture results in monotonicity. The R_DIVIDERswitch is controlled by the gain registers (see the Gain Function

section). Because the output amplifier has a gain of 2, R_DIVIDERis not shorted when the DAC-n gain is set to 1

(default if internal reference is disabled), and is shorted when the DAC-n gain is set to 2 (default if internal

reference is enabled).

V_REFIN/V_REFOUT

R_DIVIDER

V_REF

2

R

To Output Amplifier

R

Figure 89. Resistor String

8.3.1.2 Output Amplifier

The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a maximum output

range of 0 V to AV_DD. It is capable of driving a load of 2 kΩ in parallel with 3 nF to GND. The typical slew rate is

0.75 V/µs, with a typical full-scale settling time of 14 µs as shown in Figure 31, Figure 32, Figure 75 and

Figure 76.

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Feature Description (continued)

8.3.2 Internal Reference

The DAC756xT, DAC816xT, and DAC856xT devices include a 2.5-V internal reference that is disabled by

default. The internal reference is externally available at the V_REFIN/V_REFOUTpin. The internal reference output

voltage is 2.5 V and can sink and source up to 20 mA.

A minimum 150-nF capacitor is recommended between the reference output and GND for noise filtering.

The internal reference of the DAC756xT, DAC816xT, and DAC856xT devices is a bipolar transistor-based

precision band-gap voltage reference. Figure 90 shows the basic band-gap topology. Transistors Q₁and Q₂are

biased such that the current density of Q₁is greater than that of Q₂. The difference of the two base-emitter

voltages (V_BE1– V_BE2) has a positive temperature coefficient and is forced across resistor R₁. This voltage is

amplified and added to the base-emitter voltage of Q₂, which has a negative temperature coefficient. The

resulting output voltage is virtually independent of temperature. The short-circuit current is limited by design to

approximately 100 mA.

V_REFIN/V_REFOUT

Reference

Enable

Q₁

Q₂

R₁

R₂

Figure 90. Band-Gap Reference Simplified Schematic

8.3.3 Power-On Reset

8.3.3.1 Power-On Reset to Zero-Scale

The DAC7562T, DAC8162T, and DAC8562T devices contain a power-on-reset circuit that controls the output

voltage during power up. All device registers are reset as shown in Table 4. At power up, all DAC registers are

filled with zeros and the output voltages of all DAC channels are set to zero volts. Each DAC channel remains

that way until a valid load command is written to it. The power-on reset is useful in applications where it is

important to know the state of the output of each DAC while the device is in the process of powering up. No

device pin should be brought high before applying power to the device. The internal reference is disabled by

default and remains that way until a valid reference-change command is executed.

8.3.3.2 Power-On Reset to Mid-Scale

The DAC7563T, DAC8163T, and DAC8563T devices contain a power-on reset circuit that controls the output

voltage during power up. At power up, all DAC registers are reset to mid-scale code and the output voltages of

all DAC channels are set to V_REFIN/ 2 volts. Each DAC channel remains that way until a valid load command is

written to it. The power-on reset is useful in applications where it is important to know the state of the output of

each DAC while the device is in the process of powering up. No device pin should be brought high before

applying power to the device. The internal reference is powered off or down by default and remains that way until

a valid reference-change command is executed. If using an external reference, it is acceptable to power on the

V_REFINpin either at the same time as or after applying AV_DD

.

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Table 4. DACxx62T and DACxx63T Power-On Reset Values

REGISTER

DEFAULT SETTING

Zero-scale

DACxx62T

DACxx63T

DAC and input registers

Mid-scale

LDAC registers

LDAC pin enabled for both channels

DACs powered up

Power-down registers

Internal reference register

Gain registers

Internal reference disabled

Gain = 1 for both channels

8.3.3.3 Power-On Reset (POR) Levels

When the device powers up, a POR circuit sets the device in default mode as shown in Table 4. The POR circuit

requires specific AV_DDlevels, as indicated in Figure 91, to ensure discharging of internal capacitors and to reset

the device on power up. In order to ensure a power-on reset, AV_DDmust be below 0.7 V for at least 1 ms. When

AV_DDdrops below 2.2 V but remains above 0.7 V (shown as the undefined region), the device may or may not

reset under all specified temperature and power-supply conditions. In this case, TI recommends a power-on

reset. When AV_DDremains above 2.2 V, a power-on reset does not occur.

AV_DD(V)

5.50

Specified Supply

Voltage Range

No Power-On Reset

2.70

2.20

Undefined

0.70

Power-On Reset

0.00

Figure 91. Relevant Voltage Levels for POR Circuit

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8.4 Device Functional Modes

8.4.1 Power-Down Modes

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The DAC756xT, DAC816xT, and DAC856xT devices have two separate sets of power-down commands. One set

is for the DAC channels and the other set is for the internal reference. The internal reference is forced to a

powered-down state while both DAC channels are powered down, and is only enabled if any DAC channel is

also in the normal mode of operation. For more information on the internal reference control, see the Internal

Reference Enable Register section.

8.4.1.1 DAC Power-Down Commands

The DAC756xT, DAC816xT, and DAC856xT DACs use four modes of operation. These modes are accessed by

setting the serial interface command bits to 100. Once the command bits are set correctly, the four different

power-down modes are software programmable by setting bits DB5 and DB4 in the shift register. Table 5 and

Table 6 show the different power-down options. For more information on how to set the DAC operating mode see

Table 17.

Table 5. DAC-n Operating Modes

DB5

DB4

DAC Modes of Operation

0

1

0

1

0

1

Selected DACs power up (normal mode, default)

Selected DACs power down, output 1 kΩ to GND

Selected DACs power down, output 100 kΩ to GND

Selected DACs power down, output Hi-Z to GND

Table 6. DAC-n Selection for Operating Modes

DAC-B (DB1), DAC-A (DB0)

Operating Mode

DAC-n does not change operating mode

DAC-n operating mode set to value on PD1 and PD0

0

1

It is possible to write to the DAC register or buffer of the DAC channel that is powered down. When the DAC

channel is then powered up, it powers up to this new value.

The advantage of the available power-down modes is that the output impedance of the device is known while it is

in power-down mode. As described in Table 5, there are three different power-down options. V_OUTcan be

connected internally to GND through a 1-kΩ resistor, a 100-kΩ resistor, or open-circuited (Hi-Z). The DAC

power-down circuitry is shown in Figure 92.

Resistor

String

DAC

Amplifier

V_OUTX

Power-Down

Circuitry

Resistor

Network

Figure 92. Output Stage

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8.4.2 Gain Function

The gain register controls the GAIN setting in the DAC transfer function:

D

æ

ç

è

_INö

V_OUT

=

´ V_REF´ Gain

÷

2ⁿ

ø

(2)

The DAC756xT, DAC816xT, and DAC856xT devices have a gain register for each channel. The gain for each

channel, in Equation 2, is either 1 or 2. This gain is automatically set to 2 when using the internal reference, and

is automatically set to 1 when the internal reference is disabled (default). However, each channel can have either

gain by setting the registers appropriately. The gain registers are accessible by setting the serial interface

command bits to 000, address bits to 010, and using DB1 for DAC-B and DB0 for DAC-A. See Table 7 and

Table 17 for the full command structure. The gain registers are automatically reset to provide either gain of 1 or 2

when the internal reference is powered off or on, respectively. After the reference is powered off or on, the gain

register is again accessible to change the gain.

Table 7. DAC-n Selection for Gain Register Command

DB1, DB0

Value

Gain

DB0

0

1

0

1

DAC-A uses gain = 2 (default with internal reference)

DAC-A uses gain = 1 (default with external reference)

DAC-B uses gain = 2 (default with internal reference)

DAC-B uses gain = 1 (default with external reference)

DB1

8.4.3 Software Reset Function

The DAC756xT, DAC816xT, and DAC856xT devices contain a software reset feature. The software reset

function is accessed by setting the serial interface command bits to 101. The software reset command contains

two reset modes which are software-programmable by setting bit DB0 in the shift register. Table 8 and Table 17

show the available software reset commands.

Table 8. Software Reset

DB0

Registers Reset to Default Values

0

DAC registers

Input registers

1

DAC registers

Input registers

LDAC registers

Power-down registers

Internal reference register

Gain registers

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8.4.4 Internal Reference Enable Register

The internal reference in the DAC756xT, DAC816xT, and DAC856xT devices is disabled by default for

debugging, evaluation purposes, or when using an external reference. The internal reference can be powered up

and powered down by setting the serial interface command bits to 111 and configuring DB0 (see Table 9). The

internal reference is forced to a powered down state while both DAC channels are powered down, and can only

be enabled if any DAC channel is in normal mode of operation. During the time that the internal reference is

disabled, the DAC functions normally using an external reference. At this point, the internal reference is

disconnected from the V_REFIN/V_REFOUTpin (Hi-Z output).

Table 9. Internal Reference

DB0

Internal Reference Configuration

Disable internal reference and reset DACs to gain = 1

Enable internal reference and reset DACs to gain = 2

0

1

8.4.4.1 Enabling Internal Reference

To enable the internal reference, refer to the command structure in Table 17. When performing a power cycle to

reset the device, the internal reference is switched off (default mode). In the default mode, the internal reference

is powered down until a valid write sequence powers up the internal reference. However, the internal reference is

forced to a disabled state while both DAC channels are powered down, and remains disabled until either DAC

channel is returned to the normal mode of operation. See DAC Power-Down Commands for more information on

DAC channel modes of operation.

8.4.4.2 Disabling Internal Reference

To disable the internal reference, refer to the command structure in Table 17. When performing a power cycle to

reset the device, the internal reference is disabled (default mode).

8.4.5 CLR Functionality

The edge-triggered CLR pin can be used to set the input and DAC registers immediately according to Table 10.

When the CLR pin receives a falling edge signal the clear mode is activated and changes the DAC output

voltages accordingly. The device exits clear mode on the 24^thfalling edge of the next write to the device. If the

CLR pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated

and changes the input and DAC registers immediately according to Table 10.

Table 10. Clear Mode Reset Values

DEVICE

DAC Output Entering Clear Mode

Zero-scale

DAC8562T, DAC8162T, DAC7562T

DAC8563T, DAC8163T, DAC7563T

Mid-scale

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8.4.6 LDAC Functionality

The DAC756xT, DAC816xT, and DAC856xT devices offer both a software and hardware simultaneous update

and control function. The DAC double-buffered architecture has been designed so that new data can be entered

for each DAC without disturbing the analog outputs.

DAC756xT, DAC816xT, and DAC856xT data updates can be performed either in synchronous or in

asynchronous mode.

In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC

updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values

and then make a falling edge on LDAC pin to simultaneously update the DAC output registers. Data buffers of all

channels must be loaded with desired data before an LDAC falling edge. After a high-to-low LDAC transition, all

DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a

data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is triggered.

LDAC must be returned high before the next serial command is initiated.

In synchronous mode, data are updated with the falling edge of the 24^thSCLK cycle, which follows a falling edge

of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND

permanently or asserted and held low before sending commands to the device.

Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The

LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be

updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 2-bit word

(DB1 and DB0) using command bits C2, C1, and C0 (see Table 17). The default value for each bit, and therefore

for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is

internally tied low for that particular DAC channel) and this DAC channel updates synchronously after the falling

edge of the 24^thSCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the

LDAC pin.

The combination of software and hardware simultaneous update functions is particularly useful in applications

when updating a DAC channel, while keeping the other channel unaffected; see Table 11 and Table 17 for more

information.

Table 11. DAC-n Selection for LDAC Register Command

DB1, DB0

Value

LDAC Pin Functionality

DB0

0

1

0

1

DAC-A uses LDAC pin

DAC-A operates in synchronous mode

DAC-B uses LDAC pin

DB1

DAC-B operates in synchronous mode

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8.5 Programming

The DAC756xT, DAC816xT, and DAC856xT devices have a three-wire serial interface (SYNC, SCLK, and D_IN;

see the table) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the

Serial Write Operation timing diagram (Figure 1) for an example of a typical write sequence.

The DAC756xT, DAC816xT, or DAC856xT input shift register is 24 bits wide, consisting of two don’t care bits

(DB23 to DB22), three command bits (DB21 to DB19), three address bits (DB18 to DB16), and 16 data bits

(DB15 to DB0). All 24 bits of data are loaded into the DAC under the control of the serial clock input, SCLK.

DB23 (MSB) is the first bit that is loaded into the DAC shift register. DB23 is followed by the rest of the 24-bit

word pattern, left-aligned. This configuration means that the first 24 bits of data are latched into the shift register,

and any further clocking of data is ignored.

The write sequence begins by bringing the SYNC line low. Data from the D_INline are clocked into the 24-bit shift

register on each falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the

DAC756xT, DAC816xT, and DAC856xT devices compatible with high-speed DSPs. On the 24^thfalling edge of

the serial clock, the last data bit is clocked into the shift register and the shift register locks. Further clocking does

not change the shift register data.

After receiving the 24^thfalling clock edge, the DAC756xT, DAC816xT, and DAC856xT devices decode the three

command bits, three address bits and 16 data bits to perform the required function, without waiting for a SYNC

rising edge. After the 24^thfalling edge of SCLK is received, the SYNC line may be kept low or brought high. In

either case, the minimum delay time from the 24^thfalling SCLK edge to the next falling SYNC edge must be met

in order to begin the next cycle properly; see the Serial Write Operation timing diagram (Figure 1).

A rising edge of SYNC before the 24-bit sequence is complete resets the SPI interface; no data transfer occurs.

A new write sequence starts at the next falling edge of SYNC. To assure the lowest power consumption of the

device, care should be taken that the levels are as close to each rail as possible.

8.5.1 SYNC Interrupt

In a normal write sequence, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed

DAC register updates on the 24^thfalling edge. However, if SYNC is brought high before the 23^rdfalling edge, it

acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither

an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as

shown in Figure 93).

24th Falling Edge

CLK

SYNC

D_IN

DB23

DB0

DB23

DB0

Invalid/Interrupted Write Sequence:

Output/Mode Does Not Update on the Falling Edge

Valid Write Sequence:

Output/Mode Updates on the Falling Edge

Figure 93. SYNC Interrupt Facility

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Programming (continued)

8.5.2 DAC Register Configuration

When the DAC registers are being written to, the DAC756xT, DAC816xT, and DAC856xT devices receive all 24

bits of data, ignore DB23 and DB22, and decode the next three bits (DB21 to DB19) in order to determine the

DAC operating or control mode (see Table 12). Bits DB18 to DB16 are used to address the DAC channels (see

Table 13).

Table 12. Commands for the DAC756xT, DAC816xT, and DAC856xT Devices

C2

(DB21)

C1

(DB20)

C0

(DB19)

Command

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write to input register n (Table 13)

Software LDAC, update DAC register n (Table 13)

Write to input register n (Table 13) and update all DAC registers

Write to input register n and update DAC register n (Table 13)

Set DAC power up or -down mode

Software reset

Set LDAC registers

Enable or disable the internal reference

Table 13. Address Select for the DAC756xT, DAC816xT, and DAC856xT Devices

A2

(DB18)

A1

(DB17)

A0

(DB16)

Channel (n)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DAC-A

DAC-B

Gain (only use with command 000)

Reserved

DAC-A and DAC-B

When writing to the DAC input registers the next 16, 14, or 12 bits of data that follow are decoded by the DAC to

determine the equivalent analog output (see Table 14 through Table 16) . The data format is straight binary, with

all 0s corresponding to 0-V output and all 1s corresponding to full-scale output. For all documentation purposes,

the data format and representation used here is a true 16-bit pattern (that is, FFFFh data word for full scale) that

the DAC756xT, DAC816xT, and DAC856xT devices require.

Table 14. DAC856xT Data Input Register Format

COMMAND

ADDRESS

DATA

X⁽¹⁾

X

C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DB0

DB23

(1) X' denotes don't care bits.

Table 15. DAC816xT Data Input Register Format

COMMAND

ADDRESS

DATA

X

C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

DB23

DB0

Table 16. DAC756xT Data Input Register Format

COMMAND

ADDRESS

DATA

X

C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

DB23

DB0

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In additon to DAC input register updates, the DAC756xT, DAC816xT, and DAC856xT devices support a number

of functional mode commands (such as write to LDAC register, power down DACs and so on). The complete set

of functional mode commands is shown in Table 17.

Table 17. Command Matrix for the DAC756xT, DAC816xT, and DAC856xT Devices

Command

Address

Data

DB23-

DB22

DESCRIPTION

DB15-

DB6

DB3-

C2

C1

C0

A2

A1

A0

DB5

DB4

DB1

DB0

DB2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16-, 14-, or 12-bit DAC data

X

Write to DAC-A input register

X⁽¹⁾

0

1

0

Write to DAC-B input register

Write to DAC-A and DAC-B input registers

Write to DAC-A input register and update all DACs

Write to DAC-B input register and update all DACs

Write to DAC-A and DAC-B input register and update all DACs

Write to DAC-A input register and update DAC-A

Write to DAC-B input register and update DAC-B

Write to DAC-A and DAC-B input register and update all DACs

Update DAC-A

X

0

1

X

Update DAC-B

X

Update all DACs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Gain: DAC-B gain = 2, DAC-A gain = 2 (default with internal V_REF

Gain: DAC-B gain = 2, DAC-A gain = 1

Gain: DAC-B gain = 1, DAC-A gain = 2

Gain: DAC-B gain = 1, DAC-A gain = 1 (power-on default)

Power up DAC-A

)

0

X

0

1

0

X

1

0

X

1

0

X

0

1

0

1

0

1

X

1

0

1

0

1

0

1

X

0

1

X

Power up DAC-B

Power up DAC-A and DAC-B

Power down DAC-A; 1 kΩ to GND

Power down DAC-B; 1 kΩ to GND

Power down DAC-A and DAC-B; 1 kΩ to GND

Power down DAC-A; 100 kΩ to GND

Power down DAC-B; 100 kΩ to GND

Power down DAC-A and DAC-B; 100 kΩ to GND

Power down DAC-A; Hi-Z

X

1

0

1

X

Power down DAC-B; Hi-Z

Power down DAC-A and DAC-B; Hi-Z

Reset DAC-A and DAC-B input register and update all DACs

Reset all registers and update all DACs (Power-on-reset update)

LDAC pin active for DAC-B and DAC-A

LDAC pin active for DAC-B; inactive for DAC-A

LDAC pin inactive for DAC-B; active for DAC-A

LDAC pin inactive for DAC-B and DAC-A

Disable internal reference and reset DACs to gain = 1

Enable internal reference and reset DACs to gain = 2

X

1

0

1

X

(1) X denotes don't care bits.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 DAC Internal Reference

The internal reference of the DAC756xT, DAC816xT, and DAC856xT devices does not require an external load

capacitor for stability because it is stable without any capacitive load. However, for improved noise performance,

an external load capacitor of 150 nF or larger connected to the V_REFIN/V_REFOUToutput is recommended. Figure 94

shows the typical connections required for operation of the DAC756xT, DAC816xT, and DAC856xT internal

reference. A supply bypass capacitor at the AV_DDinput is also recommended.

DGS

DSC

150 nF

AV_DD

V_REFIN

V_REFOUT

AV_DD

/

1

2

3

4

5

10

9

V_OUT

GND

A

1

2

3

4

5

10

9

V_OUT

GND

A

V_REFIN/V_REFOUT

AV_DD

B

AV_DD

B

1 mF

8

D_IN

SCLK

SYNC

7

LDAC

CLR

SCLK

7

LDAC

CLR

6

SYNC

6

Figure 94. Typical Connections for Operating the DAC756xT, DAC816xT, and DAC856xT Internal

Reference

9.1.1.1 Supply Voltage

The internal reference features an extremely low dropout voltage. It can be operated with a supply of only 5 mV

above the reference output voltage in an unloaded condition. For loaded conditions, see the Load Regulation

section. The stability of the internal reference with variations in supply voltage (line regulation, dc PSRR) is also

exceptional. Within the specified supply voltage range of 2.7 V to 5.5 V, the variation at V_REFIN/V_REFOUTis

typically 50 μV/V; see Figure 7.

9.1.1.2 Temperature Drift

The internal reference is designed to exhibit minimal drift error, defined as the change in reference output voltage

over varying temperature. The drift is calculated using the box method described by Equation 3:

V

- V_{REF _MIN}

æ

ö

REF _MAX

Drift Error =

´10⁶ppm/°C

(

)

ç

÷

V_REF´ T_RANGE

è

ø

(3)

where:

V_{REF_MAX}= maximum reference voltage observed within temperature range T_RANGE

.

V_{REF_MIN}= minimum reference voltage observed within temperature range T_RANGE

.

V_REF= 2.5 V, target value for reference output voltage.

T_RANGE= the characterized range from –40°C to 125°C (165°C range)

The internal reference features an exceptional typical drift coefficient of 4 ppm/°C from –40°C to 125°C.

Characterizing a large number of units, a maximum drift coefficient of 10 ppm/°C is observed. Temperature drift

results are summarized in Figure 3.

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Application Information (continued)

9.1.1.3 Noise Performance

Typical 0.1-Hz to 10-Hz voltage noise and noise spectral density performance are listed in the Electrical

Characteristics. Additional filtering can be used to improve output noise levels, although care should be taken to

ensure the output impedance does not degrade the ac performance. The output noise spectrum at the

V_REFIN/V_REFOUTpin, both unloaded and with an external 4.7-µF load capacitor, is shown in Figure 6. Internal

reference noise impacts the DAC output noise when the internal reference is used.

9.1.1.4 Load Regulation

Load regulation is defined as the change in reference output voltage as a result of changes in load current. The

load regulation of the internal reference is measured using force and sense contacts as shown in Figure 95. The

force and sense lines reduce the impact of contact and trace resistance, resulting in accurate measurement of

the load regulation contributed solely by the internal reference. Measurement results are shown in Figure 4.

Force and sense lines should be used for applications that require improved load regulation.

Output Pin

Contact and

Trace Resistance

V_OUT

Force Line

I_L

Sense Line

Load

Meter

Figure 95. Accurate Load Regulation of the DAC756xT, DAC816xT, and DAC856xT Internal Reference

9.1.1.4.1 Long-Term Stability

Long-term stability or aging refers to the change of the output voltage of a reference over a period of months or

years. This effect lessens as time progresses. The typical drift value for the internal reference is listed in the

Electrical Charateristics and measurement results are shown in Figure 5. This parameter is characterized by

powering up multiple devices and measuring them at regular intervals.

9.1.1.5 Thermal Hysteresis

Thermal hysteresis for a reference is defined as the change in output voltage after operating the device at 25°C,

cycling the device through the operating temperature range, and returning to 25°C. Hysteresis is expressed by

Equation 4:

é

ê

ë

ù

ú

û

V

- V

REF_PRE

REF_POST

6

V

=

´ 10 (ppm/°C)

HYST

V

REF_NOM

(4)

where:

V_HYST= thermal hysteresis.

V_{REF_PRE}= output voltage measured at 25°C pre-temperature cycling.

V_{REF_POST}= output voltage measured after the device cycles through the temperature range of –40°C to

aaa 125°C, and returns to 25°C.

V_{REF_NOM}= 2.5 V, target value for reference output voltage.

9.1.2 DAC Noise Performance

Output noise spectral density at the V_OUT-n pin versus frequency is depicted in Figure 45 and Figure 46 for full-

scale, mid-scale, and zero-scale input codes. The typical noise density for mid-scale code is 90 nV/√Hz at 1 kHz.

High-frequency noise can be improved by filtering the reference noise. Integrated output noise between 0.1 Hz

and 10 Hz is close to 2.5 µV_PP(mid-scale), as shown in Figure 47.

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9.2 Typical Applications

9.2.1 Combined Voltage and Current Analog Output Module Using the XTR300

The design features two independent outputs that can source and sink voltage and current over the standard

industrial output ranges. The possible outputs of the design include: –24 mA to 24 mA, 4 mA–20 mA, 0 mA to 24

mA, 0 V to 5 V, 0 V to 10 V, –5 V to5 V, and –10 V to 10 V.

V_REF

C_COMP

R_SET

5.5 V

0.1 µF

15 V

–15 V

0.1 µF

4.7 µF

XTR300 V+

V–

R_IMON

AV_DD

I_MON

Current

Copy

I_COPY

LDAC

SCLK

D_IN

DRV

IA_IN+

VDAC

CH2

I_DRV

V or I OUTA

R_IN

V_IN

DAC8563T

V_OUT

A

0 V to 5 V, 0 V to 10 V, –5 to 5 V,

–10 V to 10 V, –24 mA to 24 mA,

0 mA to 24 mA, 4mA to 20 mA

OPA

SET

SYNC

+

V_OUT

B

I_IA

RG1

RG2

R_IA

V_REFIN

/

IA_OUT

IA

R_G

V_REFOUT

GND

V_REF

0.022 µF

IA_IN–

DGND

Figure 96. DAC8563T and XTR300 Discrete Analog Output Module

9.2.1.1 Design Requirements

The design uses a DAC and a current-or-voltage output driver to create a discrete analog output design that can

output either voltage or current from the same pin while focusing on high-accuracy specifications. The choice of

the DAC8563T device takes advantage of its 16-bit resolution as well as its low typical offset error of 1 mV and

gain error of 0.01% FSR. The choice of the XTR300 device is based on its strong dc performance, having a

typical error of 400 µV and 0.04% FSR gain error. The XTR300 device allows a variety of both current and

voltage outputs on the same pin while providing load monitoring and error status pins.

The power-on reset-to-midscale feature of the DAC8563T makes the bipolar output of the XTR300 power up at 0

V or 0 A. If using a unipolar output, the recommended device to achieve a system power-on output of 0 V, 0 A or

4 mA is the DAC8562T device.

A recommendation for minimizing the introduction of errors into the system is to use ±0.01% tolerance RG and

RSET resistors. The bypass capacitors on AV_DD, VREF, V+ and V– should have values between 100 nF and

10 µF. Smaller capacitors filter fast low-energy transients, whereas the large capacitors filter the slow high-

energy transients. If there is an expectation of both types of signals in the system, the recommendation is to use

a pair of small and large values as shown on the AV_DDpin of the DAC8563T device in Figure 96.

9.2.1.2 Detailed Design Procedure

When configured for voltage mode, the output of the instrumentation amplifier (IA), internal to the XTR300

device, is routed to the SET pin. The SET output provides feedback for the IA based on the IA input voltage. The

feedback from the IA provides high-impedance remote sensing of the voltage at the output load. Using the output

voltage can overcome errors from PCB traces and protection component impedances. The DAC provides a

unipolar input voltage to the VIN pin of the XTR300 device. The XTR300 device offsets the V_DACrange by a

negative V_REFand amplifies the difference by a value set by the R_Gand R_SETresistors, as shown in Equation 5.

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Typical Applications (continued)

æ

ö

÷

ø

R_G

2

V_DAC- V_REF

V_OUT

=

´ ç

ç

R_SET

è

(5)

When configured for current mode, the XTR300 routes the internal output of its current copy circuitry to the SET

pin. This provides feedback for the internal OPA driver based on 1 / 10th of the output current, resulting in a

voltage-to-current transfer function. Generating bipolar current outputs from the single-ended DAC output

voltage, VDAC, requires the application of an offset to the XTR300 SET pin. Connect the R_SETresistor from the

SET pin to V_REFto apply the offset and obtain the transfer function shown in Equation 6.

æ

ö

÷

ø

V_DAC- V_REF

I_OUT= 10´ ç

ç

è

R _SET

(6)

The desired output ranges for VDAC and V_REFvoltages determine the R_SETand R_Gresistor values, calculated

using Equation 7 and Equation 8. The system design requires a V_DACvoltage range of 0.04 V to 4.96 V in order

to operate the DAC8563T in the specified linear output range from codes 512 to 65 024.

æ

ö

V_DAC- V_REF

4.96 V - 2.5 V

æ

ö

R_SET= 10´ ç

÷ = 10´

= 1025 Ω

ç

÷

ç

è

÷

ø

I_OUT

0.024 A

è

ø

(7)

(8)

2´ V_{OUT_MAX}´ R_SET

2´10 V ´1020 Ω

4.96 V - 2.5 V

R_G

=

= 8292 Ω

V_DAC- V_REF

I_MONand IA_OUTaccomplish load monitoring. The sizing of R_IMONand R_IAdetermine the monitoring output voltage

across the resistors. Size the resistors according to Equation 9 and Equation 10 and the expected output load

current I_DRV

.

10´ V_IMON

R_IMON

=

I_DRV

(9)

10´ V_IA

R_IA

=

I_IA

(10)

For more detailed information about the design procedure of this circuit and how to isolate it, see Two-Channel

Source/Sink Combined Voltage & Current Output, Isolated, EMC/EMI Tested Reference Design (TIDU434).

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Typical Applications (continued)

9.2.1.3 Application Curves

Figure 97 shows the transfer function for the bipolar ±10 V voltage range. This design also supports output

voltage ranges of 0–5 V, 0–10 V and ±5 V. Figure 98 shows the transfer function for the unipolar 0–24 mA

current range. This design also supports output current ranges of ±24 mA and 4 mA–20 mA.

10

8

24

20

16

12

8

6

4

2

4

0

-4

-2

-4

-6

-8

-10

-8

-12

-16

-20

-24

0

10k

20k

30k

40k

50k

60k65535

0

10k

20k

30k

40k

50k

60k65535

Input Code

D001

D002

Figure 97. Output Voltage vs Input Code

Figure 98. Output Current vs Input Code

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Typical Applications (continued)

9.2.2 Up to ±15-V Bipolar Output Using the DAC8562T

The DAC8562T is designed to be operate from a single power supply providing a maximum output range of

AV_DDvolts. However, the DAC can be placed in the configuration shown in Figure 99 in order to be designed into

bipolar systems. Depending on the ratio of the resistor values, the output of the circuit can range anywhere from

±5 V to ±15 V. The design example below shows that the DAC is configured to have its internal reference

enabled and the DAC8562T internal gain set to 2, however, an external 2.5-V reference could also be used (with

DAC8562T internal gain set to 2).

R

G ´ R

5.5 V

18 V

V_OUT

–

+

R

V_REFOUT

OPA140

G ´ R

DAC8562T

–18 V

Figure 99. Bipolar Output Range Circuit Using DAC8562T

The transfer function shown in Equation 11 can be used to calculate the output voltage as a function of the DAC

code, reference voltage and resistor ratio:

D_IN

æ

ç

ö

V_OUT= G × V_REFOUT2 ×

è

-1

÷

65,536

ø

(11)

where:

D_IN= decimal equivalent of the binary code that is loaded to the DAC register, ranging from 0 to 65,535 for

DAC8562T (16 bit).

V_REFOUT= reference output voltage with the internal reference enabled from the DAC V_REFIN/V_REFOUTpin

G = ratio of the resistors

An example configuration to generate a ±10-V output range is shown below in Equation 6 with G = 4 and

V_REFOUT= 2.5 V:

D_IN

V_OUT= 20 ×

-10 V

65,536

(12)

In this example, the range is set to ±10 V by using a resistor ratio of four, V_REFOUTof 2.5 V, and DAC8562T

internal gain of 2. The resistor sizes must be selected keeping in mind the current sink or source capability of the

DAC8562T internal reference. Using larger resistor values, for example, R = 10 kΩ or larger, is recommended.

The operational amplifier is selectable depending on the requirements of the system.

The DAC8562TEVM and DAC7562TEVM boards have the option to evaluate the bipolar output application by

installing the components on the pre-placed footprints. For more information see either the DAC8562EVM or

DAC7562EVM product folder.

44

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Product Folder Links: DAC7562T DAC7563T DAC8162T DAC8163T DAC8562T DAC8563T

DAC7562T, DAC7563T, DAC8162T

DAC8163T, DAC8562T, DAC8563T

www.ti.com

ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

9.3 System Examples

9.3.1 MSP430 Microprocessor Interfacing

Figure 100 shows a serial interface between the DAC756xT, DAC816xT, or DAC856xT device and a typical

MSP430 USI port such as the one found on the MSP430F2013. The port is configured in SPI master mode by

setting bits 3, 5, 6, and 7 in USICTL0. The USI counter interrupt is set in USICTL1 to provide an efficient means

of SPI communication with minimal software overhead. The serial clock polarity, source, and speed are

controlled by settings in the USI clock control register (USICKCTL). The SYNC signal is derived from a bit-

programmable pin on port 1; in this case, port line P1.4 is used. When data are to be transmitted to the

DAC756xT, DAC816xT, or DAC856xT device, P1.4 is taken low. The USI transmits data in 8-bit bytes; thus, only

eight falling clock edges occur in the transmit cycle. To load data to the DAC, P1.4 is left low after the first eight

bits are transmitted; then, a second write cycle is initiated to transmit the second byte of data. P1.4 is taken high

following the completion of the third write cycle.

MSP430F2013

DAC

SYNC

P1.4/GPIO

P1.5/SCLK

P1.6/SDO

SCLK

D_IN

NOTE: Additional pins omitted for clarity.

Figure 100. DAC756xT, DAC816xT, or DAC856xT Device to MSP430 Interface

9.3.2 TMS320 McBSP Microprocessor Interfacing

Figure 101 shows an interface between the DAC756xT, DAC816xT, or DAC856xT device and any TMS320

series DSP from Texas Instruments with a multi-channel buffered serial port (McBSP). Serial data are shifted out

on the rising edge of the serial clock and are clocked into the DAC756xT, DAC816xT, or DAC856xT device on

the falling edge of the SCLK signal.

TMS320F28062

DAC

SYNC

MFSxA

MCLKxA

MDxA

SCLK

D_IN

NOTE: Additional pins omitted for clarity.

Figure 101. DAC756xT, DAC816xT, or DAC856xT Device to TMS320 McBSP Interface

9.3.3 OMAP-L1x Processor Interfacing

Figure 102 shows a serial interface between the DAC756xT, DAC816xT, or DAC856xT device and the OMAP-

L138 processor. The transmit clock CLKx0 of the L138 drives SCLK of the DAC756xT, DAC816xT, or DAC856xT

device, and the data transmit (Dx0) output drives the serial data line of the DAC. The SYNC signal is derived

from the frame sync transmit (FSx0) line, similar to the TMS320 interface.

OMAP-L138

FSx0

DAC

SYNC

CLKx0

Dx0

SCLK

D_IN

NOTE: Additional pins omitted for clarity.

Figure 102. DAC756xT, DAC816xT, or DAC856xT Device to OMAP-L1x Processor

提交文档反馈意见

45

Product Folder Links: DAC7562T DAC7563T DAC8162T DAC8163T DAC8562T DAC8563T

DAC7562T, DAC7563T, DAC8162T

DAC8163T, DAC8562T, DAC8563T

ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

www.ti.com

10 Power Supply Recommendations

These devices can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to

AV_DDshould be well-regulated and low-noise. In order to further minimize noise from the power supplies, a

strong recommendation is to include a pair of 100-pF and 1-nF capacitors and a 0.1-μF to 1-μF bypass

capacitor. The current consumption of the AV_DDpin, the short-circuit current limit, and the load current for these

devices are listed in the Electrical Characteristics table. Choose the power supplies for these devices to meet the

aforementioned current requirements.

11 Layout

11.1 Layout Guidelines

A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power

supplies. The DAC756xT, DAC816xT, and DAC856xT devices offer single-supply operation, and are often used

in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more

digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise

from appearing at the output. As a result of the single ground pin of the DAC756xT, DAC816xT, and DAC856xT

devices, all return currents (including digital and analog return currents for the DAC) must flow through a single

point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from

the ground connection for the digital components until they were connected at the power-entry point of the

system. The power applied to AV_DDshould be well-regulated and low noise. Switching power supplies and dc-dc

converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital

components can create similar high-frequency spikes as their internal logic switches states. This noise can easily

couple into the DAC output voltage through various paths between the power connections and analog output. As

with the GND connection, AV_DDshould be connected to a power-supply plane or trace that is separate from the

connection for digital logic until they are connected at the power-entry point. In addition, a pair of 100-pF to 1-nF

capacitors and a 0.1-µF to 1-µF bypass capacitor are strongly recommended. In some situations, additional

bypassing may be required, such as a 100-µF electrolytic capacitor or even a pi filter made up of inductors and

capacitors – all designed essentially to provide low-pass filtering for the supply and remove the high-frequency

noise.

46

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Product Folder Links: DAC7562T DAC7563T DAC8162T DAC8163T DAC8562T DAC8563T

DAC7562T, DAC7563T, DAC8162T

DAC8163T, DAC8562T, DAC8563T

www.ti.com

ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

11.2 Layout Example

0.1 µF

Bypass Capacitors

100 pF

AV_DD

DIN

SCLK

Digital Lines

V_REFIN/V_REFOUT

SYNC

GND

Digital Lines

LDAC

V_OUT

A

B

Analog Lines

V_OUT

CLK

Figure 103. DACxx6xT Layout Example

提交文档反馈意见

47

Product Folder Links: DAC7562T DAC7563T DAC8162T DAC8163T DAC8562T DAC8563T

DAC7562T, DAC7563T, DAC8162T

DAC8163T, DAC8562T, DAC8563T

www.ti.com

ZHCSE89A –SEPTEMBER 2015–REVISED OCTOBER 2015

12 器件和文档支持

12.1 相关链接

下面的表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，以及样片或购买的快速访

问。

Table 18. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持与社区

请单击此处

DAC7562T

DAC7563T

DAC8162T

DAC8163T

DAC8562T

DAC8563T

12.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 Trademarks

SPI, QSPI are trademarks of Motorola, Inc.

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。本数据随时可能发生变更

并且不对本文档进行修订，恕不另行通知。要获得这份数据表的浏览器版本，请查阅左侧的导航窗格。

提交文档反馈意见

49

Product Folder Links: DAC7562T DAC7563T DAC8162T DAC8163T DAC8562T DAC8563T

PACKAGE OUTLINE

DGS0010A

VSSOP - 1.1 mm max height

S

C

A

L

E

3

.

2

0

SMALL OUTLINE PACKAGE

C

SEATING PLANE

0.1 C

5.05

4.75

TYP

PIN 1 ID

AREA

A

8X 0.5

10

1

3.1

2.9

NOTE 3

2X

2

5

6

0.27

0.17

10X

3.1

2.9

1.1 MAX

0.1

C A

B

NOTE 4

0.23

0.13

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.7

0.4

0 - 8

DETAIL A

TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

www.ti.com

EXAMPLE BOARD LAYOUT

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

(R0.05)

TYP

SYMM

10X (0.3)

1

5

10

SYMM

6

8X (0.5)

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

SYMM

(R0.05) TYP

10X (0.3)

8X (0.5)

1

5

10

SYMM

6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221984/A 05/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DAC7562TDSCR
厂家：	TEXAS INSTRUMENTS
描述：	DAC7562T 双通道、12 位、低功耗、电压输出 DAC，具有 2.5V、4ppm/°C、内部基准电压和 5V TTL I/O \| DSC \| 10 \| -40 to 125
文件：	总63页 (文件大小：2322K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC7562TDSCR [TI]

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