DAC7562_15_技术文档

DAC8562, DAC8563

DAC8162, DAC8163

DAC7562, DAC7563

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DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT

DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM QFN

Check for Samples: DAC8562, DAC8563, DAC8162, DAC8163, DAC7562, DAC7563

1

FEATURES

DESCRIPTION

The DAC856x, DAC816x, and DAC756x are

low-power, voltage-output, dual-channel, 16-, 14-,

and 12-bit digital-to-analog converters (DACs),

23

•

Relative Accuracy:

–

DAC856x (16-Bit): 4 LSB INL

DAC816x (14-Bit): 1 LSB INL

DAC756x (12-Bit): 0.3 LSB INL

respectively. These devices include

a

2.5-V,

4-ppm/°C internal reference, giving a full-scale output

voltage range of 2.5 V or 5 V. The internal reference

has an initial accuracy of ±5 mV and can source or

sink up to 20 mA at the V_REFIN/V_REFOUTpin.

•

Glitch Energy: 0.1 nV-s

Bidirectional Reference: Input or 2.5-V Output

–

Output Disabled by Default

These devices are monotonic, providing excellent

linearity and minimizing undesired code-to-code

transient voltages (glitch). They use a versatile

three-wire serial interface that operates at clock rates

up to 50 MHz. The interface is compatible with

standard SPI™, QSPI™, Microwire™, and digital

signal processor (DSP) interfaces. The DACxx62

devices incorporate a power-on-reset circuit that

ensures the DAC output powers up at zero scale until

a valid code is written to the device, whereas the

DACxx63s similarly power up at mid-scale. These

devices contain a power-down feature that reduces

current consumption to typically 10 nA at 5 V. The

low power consumption, internal reference, and small

footprint make these devices ideal for portable,

battery-operated equipment.

±5-mV Initial Accuracy (Max)

4-ppm/°C Temperature Drift (Typ)

10-ppm/°C Temperature Drift (Max)

20-mA Sink/Source Capability

•

Power-On Reset to Zero Scale or Mid-Scale

Low-Power: 4 mW (Typ, 5-V AV_DD, Including

Internal Reference Current)

Wide Power-Supply Range: 2.7 V to 5.5 V

50-MHz SPI With Schmitt-Triggered Inputs

LDAC and CLR Functions

Output Buffer With Rail-to-Rail Operation

Packages: QFN-10 (3x3 mm), MSOP-10

Temperature Range: –40°C to 125°C

•

The

DACxx62

devices

are

drop-in

and

APPLICATIONS

function-compatible with each other, as are the

DACxx63s. The entire family is available in MSOP-10

and QFN-10 packages.

•

Portable Instrumentation

Bipolar Outputs (reference design)

PLC Analog Output Module (reference design)

Closed-Loop Servo Control

Voltage Controlled Oscillator Tuning

Data Acquisition Systems

Table 1. RELATED DEVICES

16-BIT

14-BIT

12-BIT

Reset to zero

DAC8562

DAC8563

DAC8162

DAC8163

DAC7562

DAC7563

Reset to mid-scale

Programmable Gain and Offset Adjustment

GND

AV_DD

LDAC

CLR

V_REFIN/V_REFOUT

Power-

Down

Control

Logic

D_IN

Buffer Control

Register Control

2.5-V

Reference

Input Control Logic

SCLK

SYNC

Control Logic

DAC Register B

DAC Register A

V_OUTB

Data Buffer B

Data Buffer A

DAC

DAC756x (12-Bit)

DAC816x (14-Bit)

DAC856x (16-Bit)

V_OUTA

DAC

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

SPI, QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC8562, DAC8563

DAC8162, DAC8163

DAC7562, DAC7563

SLAS719C –AUGUST 2010–REVISED JUNE 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DEVICE INFORMATION⁽¹⁾

MAXIMUM

RELATIVE

ACCURACY

(LSB)

MAXIMUM

DIFFERENTIAL

NONLINEARITY

(LSB)

MAXIMUM

REFERENCE

DRIFT

SPECIFIED

TEMPER-

ATURE RANGE

RESET

TO

PACKAGE-

LEAD

PACKAGE

DESIGNATOR

PACKAGE

MARKING

PRODUCT

(ppm/°C)

QFN-10

MSOP-10

QFN-10

DSC

DGS

DSC

DGS

DSC

DGS

DSC

DGS

DSC

DGS

DSC

DGS

DAC8562

DAC8563

DAC8162

DAC8163

DAC7562

DAC7563

Zero

Mid-scale

Zero

8562

8563

8162

8163

7562

7563

±12

±3

±1

10

–40°C to 125°C

MSOP-10

QFN-10

MSOP-10

QFN-10

±0.5

±0.25

Mid-scale

Zero

MSOP-10

QFN-10

MSOP-10

QFN-10

±0.75

Mid-scale

MSOP-10

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI

Web site at www.ti.com.

2

DAC8562, DAC8563

DAC8162, DAC8163

DAC7562, DAC7563

www.ti.com

SLAS719C –AUGUST 2010–REVISED JUNE 2011

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range (unless otherwise noted).

VALUE

–0.3 to 6

UNIT

V

AV_DDto GND

CLR, D_IN, LDAC, SCLK and SYNC input voltage to GND

V_OUTto GND

–0.3 to AV_DD+ 0.3

–40 to 125

V

V_REFIN/V_REFOUTto GND

V

Operating temperature range

°C

Junction temperature, maximum (T_{J max}

)

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION

DAC856x, DAC816x, DAC756x

THERMAL METRIC

DSC

10 PINS

62.8

DGS

10 PINS

173.8

48.5

UNIT

θ_JA

Junction-to-ambient thermal resistance⁽¹⁾

Junction-to-case (top) thermal resistance⁽²⁾

Junction-to-board thermal resistance⁽³⁾

Junction-to-top characterization parameter⁽⁴⁾

Junction-to-board characterization parameter⁽⁵⁾

Junction-to-case (bottom) thermal resistance⁽⁶⁾

°C/W

θ_JCtop

θ_JB

44.3

26.5

79.9

ψ_JT

0.4

1.7

ψ_JB

25.5

68.4

θ_JCbot

46.2

N/A

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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ELECTRICAL CHARACTERISTICS

At AV_DD= 2.7 V to 5.5 V and T_A= –40°C to 125°C (unless otherwise noted).

PARAMETER

STATIC PERFORMANCE⁽¹⁾

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

16

Bits

LSB

DAC856x

DAC816x

DAC756x

Relative accuracy

Using line passing through codes 512 and 65,024

±4

±12

±1

Differential nonlinearity 16-bit monotonic

±0.2

LSB

Resolution

14

12

Bits

Relative accuracy

Using line passing through codes 128 and 16,256

±1

±3

LSB

Differential nonlinearity 14-bit monotonic

Resolution

±0.1

±0.5

LSB

Bits

Relative accuracy

Using line passing through codes 32 and 4,064

±0.3

±0.05

±1

±0.75

±0.25

±4

LSB

Differential nonlinearity 12-bit monotonic

LSB

Offset error

Extrapolated from two-point line⁽¹⁾, unloaded

mV

Offset error drift

Full-scale error

Zero-code error

Zero-code error drift

Gain error

±2

µV/°C

% FSR

mV

DAC register loaded with all 1s

DAC register loaded with all 0s

±0.03

1

±0.2

4

±2

µV/°C

% FSR

Extrapolated from two-point line⁽¹⁾, unloaded

±0.01

±0.15

ppm

FSR/°C

Gain temperature coefficient

±1

OUTPUT CHARACTERISTICS⁽²⁾

Output voltage range

0

AV_DD

V

µs

DACs unloaded

7

10

Output voltage settling time⁽³⁾

Slew rate

R_L= 1 MΩ

Measured between 20% - 80% of a full-scale transition

R_L= ∞

0.75

1

V/µs

nF

Capacitive load stability

R_L= 2 kΩ

3

Code-change glitch impulse

Digital feedthrough

1-LSB change around major carry

SCLK toggling, SYNC high

R_L= 2 kΩ, C_L= 470 pF, AV_DD= 5.5 V

0.1

40

nV-s

mV

Power-on glitch impulse

Full-scale swing on adjacent channel,

External reference

5

Channel-to-channel dc crosstalk

µV

Full-scale swing on adjacent channel,

Internal reference

15

5

DC output impedance

Short-circuit current

At mid-scale input

Ω

mA

µs

DAC outputs at full-scale, DAC outputs shorted to

GND

40

50

Power-up time, including settling time

AC PERFORMANCE⁽²⁾

DAC output noise density

DAC output noise

Coming out of power-down mode

T_A= 25°C, at mid-scale input, f_OUT= 1 kHz

T_A= 25°C, at mid-scale input, 0.1 Hz to 10 Hz

90

nV/√Hz

µV_PP

2.6

LOGIC INPUTS⁽²⁾

Input pin Leakage current

–1

±0.1

1

µA

Logic input LOW voltage V_IN

L

0

0.8

V

0.7 ×

AV_DD

Logic input HIGH voltage V_IN

H

AV_DD

3

V

Pin capacitance

pF

(1) 16-bit: codes 512 and 65,024; 14-bit: codes 128 and 16,256; 12-bit: codes 32 and 4,064

(2) Specified by design or characterization

(3) Transition time between 1/4 scale and 3/4 scale including settling to within ±0.024% FSR

4

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SLAS719C –AUGUST 2010–REVISED JUNE 2011

ELECTRICAL CHARACTERISTICS (continued)

At AV_DD= 2.7 V to 5.5 V and T_A= –40°C to 125°C (unless otherwise noted).

PARAMETER

REFERENCE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

External V_REF= 2.5 V (when internal reference is

disabled), all channels active using gain = 1

External reference current

V_REFINreference input range

15

µA

0

AV_DD

V

Internal reference disabled, gain = 1

Internal reference disabled, gain = 2

170

85

Reference input impedance

kΩ

REFERENCE OUTPUT

Output voltage

T_A= 25°C

2.495

2.5

±0.1

4

2.505

5

V

Initial accuracy

Output voltage temperature drift⁽⁴⁾

–5

mV

10

ppm/°C

µV_PP

Output voltage noise

f = 0.1 Hz to 10 Hz

12

T_A= 25°C, f = 1 kHz, C_L= 0 µF

T_A= 25°C, f = 1 MHz, C_L= 0 µF

T_A= 25°C, f = 1 MHz, C_L= 4.7 µF

T_A= 25°C

250

30

Output voltage noise density

(high-frequency noise)

nV/√Hz

10

Load regulation, sourcing⁽⁵⁾

Load regulation, sinking⁽⁵⁾

Output current load capability⁽⁶⁾

Line regulation

20

µV/mA

mA

T_A= 25°C

185

±20

50

T_A= 25°C

µV/V

ppm

Long-term stability/drift (aging)⁽⁵⁾

T_A= 25°C, time = 0 to 1900 hours

First cycle

100

200

50

Thermal hysteresis⁽⁵⁾

ppm

Additional cycles

POWER REQUIREMENTS⁽⁷⁾

Power supply voltage

2.7

5.5

0.5

1.3

1

V

Normal mode, internal reference off

Normal mode, internal reference on

Power-down modes⁽⁸⁾

0.25

0.8

mA

AV_DD= 3.6 V to 5.5 V

0.01

0.2

µA

mA

µA

Power-down modes⁽⁹⁾

3

I_DD

Normal mode, internal reference off

Normal mode, internal reference on

Power-down modes⁽⁸⁾

0.4

1.3

1

0.73

0.008

0.9

AV_DD= 2.7 V to 3.6 V

Power-down modes⁽⁹⁾

3

Normal mode, internal reference off

Normal mode, internal reference on

Power-down modes⁽⁸⁾

2.75

7.15

5.5

16.5

1.44

4.68

3.6

10.8

mW

µW

mW

µW

2.9

AV_DD= 3.6 V to 5.5 V

0.04

0.54

1.97

0.02

Power-down modes⁽⁹⁾

Power

dissipation

Normal mode, internal reference off

Normal mode, internal reference on

Power-down modes⁽⁸⁾

AV_DD= 2.7 V to 3.6 V

Power-down modes⁽⁹⁾

TEMPERATURE RANGE

Specified performance

–40

125

°C

(4) Internal reference output voltage temperature drift is characterized from –40°C to 125°C.

(5) Explained in more detail in the Application Information section of this data sheet.

(6) Specified by design or characterization

(7) Input code = mid-scale, no load, V_INH = AV_DD, and V_INL = GND

(8) Temperature range –40°C to 105°C

(9) Temperature range –40°C to 125°C

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PIN CONFIGURATIONS

DGS

(Top View)

DSC

(Top View)

1

2

3

4

5

10

9

V_OUT

A

V_REFIN/V_REFOUT

AV_DD

1

2

3

4

5

10

9

V_OUT

A

V_REFIN/V_REFOUT

AV_DD

V_OUT

B

V_OUT

B

8

D_IN

GND

LDAC

CLR

D_IN

GND

LDAC

CLR

7

SCLK

7

SCLK

Thermal Pad⁽¹⁾

QFN Package

6

SYNC

6

SYNC

MSOP Package

(1) It is recommended to connect the thermal pad to the ground plane for better thermal dissipation.

Table 2. PIN DESCRIPTIONS

DESCRIPTION

NAME

NO.

AV_DD

CLR

9

Power-supply input, 2.7 V to 5.5 V

Asynchronous clear input. The CLR input is falling-edge sensitive. When CLR is activated, zero scale

(DACxx62) or mid-scale (DACxx63) is loaded to all input and DAC registers. This sets the DAC output

voltages accordingly. The part exits clear code mode on the 24^thfalling edge of the next write to the part. If

CLR is activated during a write sequence, the write is aborted.

5

Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock

input. Schmitt-trigger logic input

D_IN

8

3

GND

Ground reference point for all circuitry on the device

In synchronous mode, data are updated with the falling edge of the 24^thSCLK cycle, which follows a falling

edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to

GND permanently or asserted and held low before sending commands to the device.

In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous

DAC updates. Multiple single-channel commands can be written in order to set different channel buffers to

desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output

registers.

LDAC

4

SCLK

SYNC

7

6

Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input

Level-triggered control input (active-low). This input is the frame synchronization signal for the input data.

When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock

edges. The DAC output updates following the 24^thclock falling edge. If SYNC is taken high before the 23^rd

clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the

DAC756x/DAC816x/DAC856x. Schmitt-trigger logic input

V_OUT

A

1

2

Analog output voltage from DAC-A

B

Analog output voltage from DAC-B

V_REFIN/ V_REFOUT

10

Bidirectional voltage reference pin. If internal reference is used, 2.5-V output.

6

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SLAS719C –AUGUST 2010–REVISED JUNE 2011

TIMING DIAGRAM

t₁

t₂

SCLK

t₆

t₇

t₃

t₄

t₅

t₈

SYNC

t₁₀

t₉

DIN

DB23

DB0

t₁₁

t₁₂

LDAC⁽¹⁾

LDAC⁽²⁾

t₁₃

CLR

t₁₄

VOUT

(1) Asynchronous LDAC update mode. For more information, see the LDAC Functionality section.

(2) Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section.

Figure 1. Serial Write Operation

TIMING REQUIREMENTS⁽¹⁾⁽²⁾

At AV_DD= 2.7 V to 5.5 V and over –40°C to 125°C (unless otherwise noted).

DAC756x/DAC816x/DAC856x

PARAMETER

UNIT

MIN

10

20

13

80

13

8

TYP

MAX

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

SCLK falling edge to SYNC falling edge (for successful write operation)

SCLK cycle time

SYNC rising edge to 23^rdSCLK falling edge (for successful SYNC interrupt)

ns

(3)

Minimum SYNC HIGH time

SYNC to SCLK falling edge setup time

SCLK LOW time

SCLK HIGH time

8

SCLK falling edge to SYNC rising edge

Data setup time

10

6

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

Data hold time

5

SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode

LDAC pulse duration, LOW time

5

10

80

CLR pulse duration, LOW time

CLR falling edge to start of VOUT transition

100

(1) All input signals are specified with t_R= t_F= 3 ns (10% to 90% of AV_DD) and timed from a voltage level of (V_INL + V_INH)/2.

(2) See the Serial Write Operation timing diagram (Figure 1).

(3) Maximum SCLK frequency is 50 MHz at AV_DD= 2.7 V to 5.5 V.

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TABLES OF GRAPHS

Table 3. Typical Characteristics: Internal Reference Performance

POWER-SUPPLY

MEASUREMENT

VOLTAGE

FIGURE NUMBER

Internal Reference Voltage vs Temperature

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Internal Reference Voltage Temperature Drift Histogram

Internal Reference Voltage vs Load Current

Internal Reference Voltage vs Time

5.5 V

Internal Reference Noise Density vs Frequency

Internal Reference Voltage vs Supply Voltage

2.7 V – 5.5 V

Table 4. Typical Characteristics: DAC Static Performance

POWER-SUPPLY

MEASUREMENT

VOLTAGE

FIGURE NUMBER

FULL-SCALE, GAIN, OFFSET AND ZERO-CODE ERRORS

Full-Scale Error vs Temperature

Gain Error vs Temperature

Offset Error vs Temperature

Zero-Code Error vs Temperature

Full-Scale Error vs Temperature

Gain Error vs Temperature

Offset Error vs Temperature

Zero-Code Error vs Temperature

LOAD REGULATION

Figure 16

Figure 17

Figure 18

Figure 19

Figure 63

Figure 64

Figure 65

Figure 66

5.5 V

2.7 V

5.5 V

2.7 V

Figure 30

Figure 74

DAC Output Voltage vs Load Current

DIFFERENTIAL NONLINEARITY ERROR

T = –40°C

T = 25°C

T = 125°C

Figure 9

Figure 11

Figure 13

Figure 15

Figure 56

Figure 58

Figure 60

Figure 62

Differential Linearity Error vs Digital Input Code

Differential Linearity Error vs Temperature

Differential Linearity Error vs Digital Input Code

Differential Linearity Error vs Temperature

5.5 V

2.7 V

T = –40°C

T = 25°C

T = 125°C

INTEGRAL NONLINEARITY ERROR (RELATIVE ACCURACY)

T = –40°C

Figure 8

Figure 10

Figure 12

Figure 14

Figure 55

Figure 57

Figure 59

Figure 61

Linearity Error vs Digital Input Code

Linearity Error vs Temperature

Linearity Error vs Digital Input Code

Linearity Error vs Temperature

T = 25°C

5.5 V

2.7 V

T = 125°C

T = –40°C

T = 25°C

T = 125°C

8

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SLAS719C –AUGUST 2010–REVISED JUNE 2011

Table 4. Typical Characteristics: DAC Static Performance (continued)

POWER-SUPPLY

VOLTAGE

MEASUREMENT

FIGURE NUMBER

POWER-DOWN CURRENT

Power-Down Current vs Temperature

Power-Down Current vs Power-Supply Voltage

Power-Down Current vs Temperature

POWER-SUPPLY CURRENT

5.5 V

2.7 V – 5.5 V

2.7 V

Figure 28

Figure 29

Figure 73

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

External V_REF

Internal V_REF

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 49

Figure 50

Figure 51

Figure 52

Figure 53

Figure 54

Figure 67

Figure 68

Figure 69

Figure 70

Figure 71

Figure 72

Power-Supply Current vs Temperature

Power-Supply Current vs Digital Input Code

Power-Supply Current Histogram

5.5 V

2.7 V – 5.5 V

3.6 V

Power-Supply Current vs Power-Supply Voltage

Power-Supply Current vs Temperature

Power-Supply Current vs Digital Input Code

Power-Supply Current Histogram

Power-Supply Current vs Temperature

Power-Supply Current vs Digital Input Code

Power-Supply Current Histogram

2.7 V

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Table 5. Typical Characteristics: DAC Dynamic Performance

POWER-SUPPLY

VOLTAGE

MEASUREMENT

FIGURE NUMBER

CHANNEL-TO-CHANNEL CROSSTALK

5-V Rising Edge

Figure 43

Figure 44

Channel-to-Channel Crosstalk

CLOCK FEEDTHROUGH

Clock Feedthrough

5.5 V

5-V Falling Edge

5.5 V

2.7 V

Figure 48

Figure 87

500 kHz, Midscale

GLITCH ENERGY

Rising Edge, Code 7FFFh to 8000h

Falling Edge, Code 8000h to 7FFFh

Rising Edge, Code 7FFCh to 8000h

Falling Edge, Code 8000h to 7FFCh

Rising Edge, Code 7FF0h to 8000h

Falling Edge, Code 8000h to 7FF0h

Rising Edge, Code 7FFFh to 8000h

Falling Edge, Code 8000h to 7FFFh

Rising Edge, Code 7FFCh to 8000h

Falling Edge, Code 8000h to 7FFCh

Rising Edge, Code 7FF0h to 8000h

Falling Edge, Code 8000h to 7FF0h

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

Figure 42

Figure 79

Figure 80

Figure 81

Figure 82

Figure 83

Figure 84

Glitch Energy, 1-LSB Step

Glitch Energy, 4-LSB Step

Glitch Energy, 16-LSB Step

Glitch Energy, 1-LSB Step

Glitch Energy, 4-LSB Step

5.5 V

2.7 V

Glitch Energy, 16-LSB Step

NOISE

External V_REF

Internal V_REF

External V_REF

Figure 45

Figure 46

Figure 47

DAC Output Noise Density vs

Frequency

5.5 V

DAC Output Noise 0.1 Hz to 10 Hz

POWER-ON GLITCH

Reset to Zero Scale

Reset to Midscale

Reset to Zero Scale

Reset to Midscale

Figure 35

Figure 36

Figure 85

Figure 86

5.5 V

2.7 V

Power-on Glitch

SETTLING TIME

Rising Edge, Code 0h to FFFFh

Falling Edge, Code FFFFh to 0h

Rising Edge, Code 4000h to C000h

Falling Edge, Code C000h to 4000h

Rising Edge, Code 0h to FFFFh

Falling Edge, Code FFFFh to 0h

Rising Edge, Code 4000h to C000h

Falling Edge, Code C000h to 4000h

Figure 31

Figure 32

Figure 33

Figure 34

Figure 75

Figure 76

Figure 77

Figure 78

Full-Scale Settling Time

5.5 V

2.7 V

Half-Scale Settling Time

Full-Scale Settling Time

Half-Scale Settling Time

10

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SLAS719C –AUGUST 2010–REVISED JUNE 2011

TYPICAL CHARACTERISTICS: Internal Reference

At T_A= 25°C, AV_DD= 5.5 V, gain = 2 and V_REFOUT, unloaded unless otherwise noted.

INTERNAL REFERENCE VOLTAGE

vs TEMPERATURE

INTERNAL REFERENCE VOLTAGE

TEMPERATURE DRIFT HISTOGRAM

30

25

20

15

10

5

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

60 units shown

(30 MSOP, 30 QFN−10)

0

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Temperature Drift (ppm/°C)

Figure 2.

Figure 3.

INTERNAL REFERENCE VOLTAGE

vs LOAD CURRENT

INTERNAL REFERENCE VOLTAGE

vs TIME

2.510

2.505

2.500

2.495

2.490

400

300

200

100

0

−100

−200

−300

−400

16 units shown (8 MSOP, 8 QFN−10)

Average shown in dashed line

−20

−15

−10

−5

0

5

10

15

20

0

250

500

750

1000

1250

1500

Load Current (mA)

Elapsed Time (Hours)

Figure 4.

Figure 5.

INTERNAL REFERENCE NOISE DENSITY

vs FREQUENCY

INTERNAL REFERENCE VOLTAGE

vs SUPPLY VOLTAGE

400

350

300

250

200

150

100

50

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

No Load

4.7 µF Load

−40°C

+25°C

+125°C

0

10

100

1k

10k

100k

1M

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

Frequency (Hz)

AV_DD(V)

Figure 6.

Figure 7.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

LINEARITY ERROR

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

−40°C

Typical channel shown

−40°C

0

8192 16384 24576 32768 40960 49152 57344 65536

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 8.

Figure 9.

LINEARITY ERROR

vs DIGITAL INPUT CODE (25°C)

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (25°C)

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

25°C

Typical channel shown

25°C

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 10.

Figure 11.

LINEARITY ERROR

vs DIGITAL INPUT CODE (125°C)

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (125°C)

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

125°C

Typical channel shown

125°C

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 12.

Figure 13.

12

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SLAS719C –AUGUST 2010–REVISED JUNE 2011

TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

LINEARITY ERROR

vs TEMPERATURE

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

12

9

1.0

0.8

INL Max

INL Min

DNL Max

DNL Min

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

−40 −25 −10

Typical channel shown

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 14.

Figure 15.

FULL-SCALE ERROR

vs TEMPERATURE

GAIN ERROR

vs TEMPERATURE

0.20

0.15

0.10

Ch A

Ch B

Ch A

Ch B

0.10

0.05

0.00

−0.05

−0.10

−0.15

−0.20

−0.05

−0.10

−0.15

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 16.

Figure 17.

OFFSET ERROR

vs TEMPERATURE

ZERO-CODE ERROR

vs TEMPERATURE

4

3

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Ch A

Ch B

Ch A

Ch B

2

1

0

−1

−2

−3

−4

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 18.

Figure 19.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

POWER-SUPPLY CURRENT

vs TEMPERATURE

POWER-SUPPLY CURRENT

vs TEMPERATURE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

Internal reference enabled

DACs at midscale code, Gain = 2

DACs at midscale code

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10 20 35 50 65 80 95 110 125

5

Temperature (°C)

Figure 20.

Figure 21.

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

Internal reference enabled, Gain = 2

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 22.

Figure 23.

POWER-SUPPLY CURRENT

HISTOGRAM

POWER-SUPPLY CURRENT

HISTOGRAM

30

25

20

15

10

5

30

25

20

15

10

5

Internal reference enabled

Gain = 2

0

Power Supply Current (mA)

Figure 24.

Figure 25.

14

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SLAS719C –AUGUST 2010–REVISED JUNE 2011

TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

POWER-SUPPLY CURRENT

vs POWER-SUPPLY VOLTAGE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

V_REFIN= 2.5 V

DACs at midscale code, Gain = 1

Internal reference enabled

DACs at midscale code, Gain = 1

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

AV_DD(V)

Figure 26.

Figure 27.

POWER-DOWN CURRENT

vs TEMPERATURE

vs POWER-SUPPLY VOLTAGE

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0.040

0.035

0.030

0.025

0.020

0.015

0.010

0.005

0.000

I_DD(µA)

I_REFIN(µA)

Both channels and internal reference

in power−down mode; V_REFIN= A_VDD

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

AV_DD(V)

Figure 28.

Figure 29.

DAC OUTPUT VOLTAGE

vs LOAD CURRENT

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

−1.0

Typical channel shown

Full scale

Mid scale

Zero scale

−20

−15

−10

−5

0

5

10

15

20

I_LOAD(mA)

Figure 30.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

FULL-SCALE SETTLING TIME:

RISING EDGE

FULL-SCALE SETTLING TIME:

FALLING EDGE

LDAC Trigger (5 V/div)

Large Signal V_OUT(2 V/div)

Small Signal Settling

(1.22 mV/div = 0.024% FSR)

Small Signal Settling (1.22 mV/div = 0.024% FSR)

From Code: 0h

To Code: FFFFh

From Code: FFFFh

To Code: 0h

Time (5 μs/div)

Figure 31.

Figure 32.

HALF-SCALE SETTLING TIME:

RISING EDGE

HALF-SCALE SETTLING TIME:

FALLING EDGE

LDAC Trigger (5 V/div)

Large Signal V_OUT(2 V/div)

Small Signal Settling (1.22 mV/div = 0.024% FSR)

From Code: 4000h

To Code: C000h

From Code: C000h

To Code: 4000h

Time (5 μs/div)

Figure 33.

Figure 34.

POWER-ON GLITCH

RESET TO ZERO SCALE

POWER-ON GLITCH

RESET TO MIDSCALE

AV_DD(2 V/div)

V_OUTA (1 V/div)

V_OUTB (1 V/div)

V_OUTA (50 mV/div)

V_OUTB (50 mV/div)

V_REFINshorted to AV_DD

Time (1 ms/div)

Figure 35.

Figure 36.

16

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SLAS719C –AUGUST 2010–REVISED JUNE 2011

TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

GLITCH ENERGY

RISING EDGE, 1-LSB STEP

FALLING EDGE, 1-LSB STEP

LDAC Trigger (5 V/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

V_OUT(100 μV/div)

LDAC Feedthrough

Glitch Impulse » 0.12 nV-s

From Code: 7FFFh

To Code: 8000h

From Code: 8000h

To Code: 7FFFh

Time (5 μs/div)

Figure 37.

Figure 38.

GLITCH ENERGY

RISING EDGE, 4-LSB STEP

FALLING EDGE, 4-LSB STEP

LDAC Trigger (5 V/div)

Glitch Impulse » 0.1 nV-s

LDAC Feedthrough

V_OUT(100 μV/div)

LDAC Feedthrough

Glitch Impulse » 0.14 nV-s

From Code: 8000h

To Code: 7FFCh

From Code: 7FFCh

To Code: 8000h

Time (5 μs/div)

Figure 39.

Figure 40.

GLITCH ENERGY

RISING EDGE, 16-LSB STEP

FALLING EDGE, 16-LSB STEP

LDAC Trigger (5 V/div)

Glitch Impulse » 0.1 nV-s

V_OUT(500 μV/div)

LDAC Feedthrough

V_OUT(500 μV/div)

Glitch Impulse » 0.1 nV-s

From Code: 7FF0h

To Code: 8000h

From Code: 8000h

To Code: 7FF0h

Time (5 μs/div)

Figure 41.

Figure 42.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

CHANNEL-TO-CHANNEL CROSSTALK

5-V RISING EDGE

CHANNEL-TO-CHANNEL CROSSTALK

5-V FALLING EDGE

LDAC Trigger (5 V/div)

V_OUTB (1 V/div)

LDAC Trigger (5 V/div)

Glitch Area (Between Cursors) = 2 nV-s

V_OUTA (500 μV/div)

6.4 μs

V_OUTA (500 μV/div)

V_OUTA at Midscale Code

Glitch Area (Between Cursors) = 1.6 nV-s

Internal Reference Enabled

Gain = 2

7.3 μs

V_OUTB (1 V/div)

V_OUTA at Midscale Code

Internal Reference Enabled

Gain = 2

Time (5 μs/div)

Figure 43.

Figure 44.

DAC OUTPUT NOISE DENSITY

vs FREQUENCY

DAC OUTPUT NOISE DENSITY

vs FREQUENCY

1400

1200

1000

800

600

400

200

0

1400

1200

1000

800

600

400

200

0

Internal reference disabled

V_REFIN= 5 V, Gain = 1

Full Scale

Mid Scale

Zero Scale

Internal reference enabled

Gain = 2

Full Scale

Mid Scale

Zero Scale

10

100

1k

10k

100k

10

100

1k

10k

100k

Frequency (Hz)

Figure 45.

Figure 46.

DAC OUTPUT NOISE

0.1 Hz TO 10 Hz

CLOCK FEEDTHROUGH

500 kHz, MIDSCALE

SCLK (5 V/div)

V_OUT(500 μV/div)

» 2.5 μV_PP

Clock Feedthrough Impulse » 0.06 nV-s

DAC = Midscale

Time (500 ns/div)

Figure 47.

Figure 48.

18

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SLAS719C –AUGUST 2010–REVISED JUNE 2011

TYPICAL CHARACTERISTICS: DAC at AV_DD= 3.6 V

At T_A= 25°C, 3.3-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

POWER-SUPPLY CURRENT

vs TEMPERATURE

POWER-SUPPLY CURRENT

vs TEMPERATURE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

Internal reference enabled

DACs at midscale code, Gain = 1

DACs at midscale code

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 49.

Figure 50.

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

Internal reference enabled, Gain = 1

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 51.

Figure 52.

POWER-SUPPLY CURRENT

HISTOGRAM

POWER-SUPPLY CURRENT

HISTOGRAM

30

25

20

15

10

5

30

25

20

15

10

5

Internal reference enabled

Gain = 1

0

Power Supply Current (mA)

Figure 53.

Figure 54.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7 V

At T_A= 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

LINEARITY ERROR

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

−40°C

Typical channel shown

−40°C

0

8192 16384 24576 32768 40960 49152 57344 65536

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 55.

Figure 56.

LINEARITY ERROR

vs DIGITAL INPUT CODE (25°C)

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (25°C)

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

25°C

Typical channel shown

25°C

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 57.

Figure 58.

LINEARITY ERROR

vs DIGITAL INPUT CODE (125°C)

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (125°C)

12

9

1.0

0.8

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

125°C

Typical channel shown

125°C

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 59.

Figure 60.

20

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SLAS719C –AUGUST 2010–REVISED JUNE 2011

TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7 V (continued)

At T_A= 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

LINEARITY ERROR

vs TEMPERATURE

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

12

9

1.0

0.8

INL Max

INL Min

DNL Max

DNL Min

0.6

6

0.4

3

0.2

0

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

−3

−6

−9

−12

Typical channel shown

−40 −25 −10

Typical channel shown

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 61.

Figure 62.

FULL-SCALE ERROR

vs TEMPERATURE

GAIN ERROR

vs TEMPERATURE

0.20

0.15

0.10

Ch A

Ch B

Ch A

Ch B

0.10

0.05

0.00

−0.05

−0.10

−0.15

−0.20

−0.05

−0.10

−0.15

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 63.

Figure 64.

OFFSET ERROR

vs TEMPERATURE

ZERO-CODE ERROR

vs TEMPERATURE

4

3

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Ch A

Ch B

Ch A

Ch B

2

1

0

−1

−2

−3

−4

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 65.

Figure 66.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7 V (continued)

At T_A= 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

POWER-SUPPLY CURRENT

vs TEMPERATURE

POWER-SUPPLY CURRENT

vs TEMPERATURE

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

Internal reference enabled

DACs at midscale code, Gain = 1

DACs at midscale code

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 67.

Figure 68.

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

Internal reference enabled, Gain = 1

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 69.

Figure 70.

POWER-SUPPLY CURRENT

HISTOGRAM

POWER-SUPPLY CURRENT

HISTOGRAM

30

25

20

15

10

5

30

25

20

15

10

5

Internal reference enabled

Gain = 1

0

Power Supply Current (mA)

Figure 71.

Figure 72.

22

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7 V (continued)

At T_A= 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

POWER-DOWN CURRENT

vs TEMPERATURE

DAC OUTPUT VOLTAGE

vs LOAD CURRENT

3.0

2.5

2.0

1.5

1.0

0.5

0.0

4

3

Typical channel shown

Full scale

Mid scale

Zero scale

2

1

0

−1

−20

−40 −25 −10

5

20 35 50 65 80 95 110 125

−15

−10

−5

0

5

10

15

20

Temperature (°C)

I_LOAD(mA)

Figure 73.

Figure 74.

FULL-SCALE SETTLING TIME:

RISING EDGE

FULL-SCALE SETTLING TIME:

FALLING EDGE

LDAC Trigger (5 V/div)

Large Signal V_OUT(1 V/div)

Small Signal Settling (0.61 mV/div = 0.024% FSR)

From Code: 0h

To Code: FFFFh

From Code: FFFFh

To Code: 0h

Time (5 μs/div)

Figure 75.

Figure 76.

HALF-SCALE SETTLING TIME:

RISING EDGE

HALF-SCALE SETTLING TIME:

FALLING EDGE

LDAC Trigger (5 V/div)

Large Signal V_OUT(1 V/div)

Small Signal Settling (0.61 mV/div = 0.024% FSR)

From Code: 4000h

To Code: C000h

From Code: C000h

To Code: 4000h

Time (5 μs/div)

Figure 77.

Figure 78.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7 V (continued)

At T_A= 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

GLITCH ENERGY

RISING EDGE, 1-LSB STEP

FALLING EDGE, 1-LSB STEP

LDAC Trigger (5 V/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

V_OUT(100 μV/div)

LDAC Feedthrough

V_OUT(100 μV/div)

Glitch Impulse » 0.1 nV-s

From Code: 7FFFh

To Code: 8000h

From Code: 8000h

To Code: 7FFFh

Time (5 μs/div)

Figure 79.

Figure 80.

GLITCH ENERGY

RISING EDGE, 4-LSB STEP

FALLING EDGE, 4-LSB STEP

LDAC Trigger (5 V/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

V_OUT(100 μV/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

From Code: 7FFCh

To Code: 8000h

From Code: 8000h

To Code: 7FFCh

Time (5 μs/div)

Figure 81.

Figure 82.

GLITCH ENERGY

RISING EDGE, 16-LSB STEP

FALLING EDGE, 16-LSB STEP

LDAC Trigger (5 V/div)

LDAC Feedthrough

Glitch Impulse » 0.1 nV-s

V_OUT(200 μV/div)

LDAC Feedthrough

V_OUT(200 μV/div)

Glitch Impulse » 0.1 nV-s

From Code: 7FF0h

To Code: 8000h

From Code: 8000h

To Code: 7FF0h

Time (5 μs/div)

Figure 83.

Figure 84.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7 V (continued)

At T_A= 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

POWER-ON GLITCH

RESET TO ZERO SCALE

POWER-ON GLITCH

RESET TO MIDSCALE

AV_DD(2 V/div)

V_OUTA (500 mV/div)

V_OUTB (500 mV/div)

V_OUTA (50 mV/div)

V_OUTB (50 mV/div)

V_REFINshorted to AV_DD

Time (1 ms/div)

Figure 85.

Figure 86.

CLOCK FEEDTHROUGH

500 kHz, MIDSCALE

SCLK (2 V/div)

Clock Feedthrough Impulse » 0.02 nV-s

V_OUT(500 μV/div)

Time (500 ns/div)

Figure 87.

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THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER (DAC)

The DAC756x, DAC816x, and DAC856x architecture consists of two string DACs, each followed by an output

buffer amplifier. The devices include an internal 2.5-V reference with 4-ppm/°C temperature drift performance.

Figure 88 shows a principal block diagram of the DAC architecture.

V_REFIN

/

V_REFOUT

150 kW

Gain

Register

V_OUT

REF(+)

Resistor String

REF(-)

DAC

Register

D_IN

n

GND

Figure 88. DAC Architecture

The input coding to the DAC756x, DAC816x, and DAC856x is straight binary, so the ideal output voltage is given

by Equation 1:

D

æ

_INö

V_OUT

=

´ V_REF´ Gain

÷

ø

ç

2ⁿ

è

(1)

where:

n = resolution in bits; either 12 (DAC756x), 14 (DAC816x) or 16 (DAC856x)

D_IN= decimal equivalent of the binary code that is loaded to the DAC register. D_INranges from 0 to 2ⁿ– 1.

V_REF= DAC reference voltage; either V_REFOUTfrom the internal 2.5-V reference or V_REFINfrom an

aaa external reference.

Gain = 1 by default when internal reference is disabled (using external reference), and gain = 2 by default

aaa when using internal reference. Gain can also be manually set to either 1 or 2 using the gain register.

aaa See the GAIN REGISTERS section for more information.

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Resistor String

The resistor string section is shown in Figure 89. It is simply a string of resistors, each of value R. The code

loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the

output amplifier by closing one of the switches connecting the string to the amplifier. The resistor string

architecture guarantees monotonicity. The R_DIVIDERswitch is controlled by the gain registers (see the GAIN

REGISTERS section). Because the output amplifier has a gain of two, R_DIVIDERis not shorted when the DAC-n

gain is set to one (default if internal reference is disabled), and is shorted when the DAC-n gain is set to two

(default if internal reference is enabled).

V_REFIN/V_REFOUT

R_DIVIDER

V_REF

2

R

To Output Amplifier

R

Figure 89. Resistor String

Output Amplifier

The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a maximum output

range of 0 V to AV_DD. It is capable of driving a load of 2 kΩ in parallel with 3 nF to GND. The typical slew rate is

0.75 V/µs, with a typical full-scale settling time of 14 µs as shown in Figure 31, Figure 32, Figure 75 and

Figure 76.

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INTERNAL REFERENCE

The DAC756x, DAC816x, and DAC856x include a 2.5-V internal reference that is disabled by default. The

internal reference is externally available at the V_REFIN/V_REFOUTpin. The internal reference output voltage is 2.5 V

and can sink and source up to 20 mA.

A minimum 150-nF capacitor is recommended between the reference output and GND for noise filtering.

The internal reference of the DAC756x, DAC816x, and DAC856x is a bipolar transistor based precision bandgap

voltage reference. Figure 90 shows the basic bandgap topology. Transistors Q₁and Q₂are biased such that the

current density of Q₁is greater than that of Q₂. The difference of the two base-emitter voltages (V_BE1– V_BE2) has

a positive temperature coefficient and is forced across resistor R₁. This voltage is amplified and added to the

base-emitter voltage of Q₂, which has a negative temperature coefficient. The resulting output voltage is virtually

independent of temperature. The short-circuit current is limited by design to approximately 100 mA.

V_REFIN/V_REFOUT

Reference

Enable

Q₁

Q₂

R₁

R₂

Figure 90. Bandgap Reference Simplified Schematic

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POWER-ON RESET

Power-On Reset to Zero-scale

The DAC7562, DAC8162, and DAC8562 contain a power-on-reset circuit that controls the output voltage during

power up. All device registers are reset as shown in Table 6. At power up all DAC registers are filled with zeros

and the output voltages of all DAC channels are set to zero volts. Each DAC channel remains that way until a

valid load command is written to it. The power-on reset is useful in applications where it is important to know the

state of the output of each DAC while the device is in the process of powering up. No device pin should be

brought high before power is applied to the device. The internal reference is disabled by default and remains that

way until a valid reference-change command is executed.

Power-On Reset to Mid-scale

The DAC7563, DAC8163, and DAC8563 contain a power-on reset circuit that controls the output voltage during

power up. At power up, all DAC registers are reset to mid-scale code and the output voltages of all DAC

channels are set to V_REFIN/2 volts. Each DAC channel remains that way until a valid load command is written to

it. The power-on reset is useful in applications where it is important to know the state of the output of each DAC

while the device is in the process of powering up. No device pin should be brought high before power is applied

to the device. The internal reference is powered off/down by default and remains that way until a valid

reference-change command is executed. If using an external reference, it is acceptable to power on the V_REFIN

either at the same time as or after AV_DDis applied.

Table 6. DACxx62 and DACxx63 Power-On Reset Values

REGISTER

DEFAULT SETTING

Zero-scale

DACxx62

DACxx63

DAC and Input registers

Mid-scale

LDAC registers

LDAC pin enabled for both channels

DACs powered up

Power-down registers

Internal reference register

Gain registers

Internal reference disabled

Gain = 1 for both channels

CLR FUNCTIONALITY

The edge-triggered CLR pin can be used to set the input and DAC registers immediately according to Table 7.

When the CLR pin receives a falling edge signal the clear mode is activated and changes the DAC output

voltages accordingly. The part exits clear mode on the 24^thfalling edge of the next write to the part. If the CLR

pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated and

changes the input and DAC registers immediately according to Table 7.

Table 7. Clear Mode Reset Values

DEVICE

DAC Output Entering Clear Mode

Zero-scale

DAC8562, DAC8162, DAC7562

DAC8563, DAC8163, DAC7563

Mid-scale

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SERIAL INTERFACE

The DAC756x, DAC816x, and DAC856x have a 3-wire serial interface (SYNC, SCLK, and D_IN; see the Pin

Descriptions) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the

Serial Write Operation timing diagram (Figure 1) for an example of a typical write sequence.

The DAC756x, DAC816x, or DAC856x input shift register is 24-bits wide, consisting of two don’t care bits (DB23

to DB22), three command bits (DB21 to DB19), three address bits (DB18 to DB16), and 16 data bits (DB15 to

DB0). The 16 data bits comprise the 16-, 14-, or 12-bit input code. All 24 bits of data are loaded into the DAC

under the control of the serial clock input, SCLK. DB23 (MSB) is the first bit that is loaded into the DAC shift

register. It is followed by the rest of the 24-bit word pattern, left-aligned. This configuration means that the first 24

bits of data are latched into the shift register, and any further clocking of data is ignored. When the DAC registers

are being written to, the DAC756x, DAC816x, and DAC856x receive all 24 bits of data, ignore DB23 and DB22,

and decode the next three bits (DB21 to DB19) in order to determine the DAC operating/control mode (see

Table 8 through Table 10). Bits DB18 to DB16 are used to address DAC channels. The next 16/14/12 bits of

data that follow are decoded by the DAC to determine the equivalent analog output. For more details on these

and other commands (such as write to LDAC register, power down DACs, etc.), see their respective sections.

The data format is straight binary, with all 0s corresponding to 0-V output and all 1s corresponding to full-scale

output. For all documentation purposes, the data format and representation used here is a true 16-bit pattern

(that is, FFFFh data word for full scale) that the DAC756x, DAC816x, and DAC856x require.

The write sequence begins by bringing the SYNC line low. Data from the D_INline are clocked into the 24-bit shift

register on each falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the

DAC756x, DAC816x, and DAC856x compatible with high-speed DSPs. On the 24^thfalling edge of the serial

clock, the last data bit is clocked into the shift register and the shift register locks. Further clocking does not

change the shift register data.

After receiving the 24^thfalling clock edge, the DAC756x, DAC816x, and DAC856x decode the three command

bits and three address bits and 16/14/12 data bits to perform the required function, without waiting for a SYNC

rising edge. After the 24^thfalling edge of SCLK is received, the SYNC line may be kept low or brought high. In

either case, the minimum delay time from the 24^thfalling SCLK edge to the next falling SYNC edge must be met

in order to begin the next cycle properly; see the Serial Write Operation timing diagram (Figure 1).

A rising edge of SYNC before the 24-bit sequence is complete resets the SPI interface; no data transfer occurs.

A new write sequence starts at the next falling edge of SYNC. To assure the lowest power consumption of the

device, care should be taken that the levels are as close to each rail as possible.

SYNC Interrupt

In a normal write sequence, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed

DAC register updates on the 24^thfalling edge. However, if SYNC is brought high before the 23^rdfalling edge, it

acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither

an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as

shown in Figure 91).

24th Falling Edge

CLK

SYNC

D_IN

DB23

DB0

DB23

DB0

Invalid/Interrupted Write Sequence:

Output/Mode Does Not Update on the Falling Edge

Valid Write Sequence:

Output/Mode Updates on the Falling Edge

Figure 91. SYNC Interrupt Facility

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Input Shift Register

The input shift register (SR) of the DAC856x, DAC816x, and DAC756x is 24 bits wide (as shown in Table 8,

Table 9, and Table 10, respectively), and consists of two don’t care bits (DB23 to DB22), three command bits

(DB21 to DB19), three address bits (DB18 to DB16), and 16 data bits (DB15 to DB0). The 16 data bits comprise

the 16-, 14-, or 12-bit input code.

Table 8. DAC856x Data Input Register Format

Command

Address

Data

X⁽¹⁾

X

C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DB0

DB23

(1) X' denotes don't care bits.

Table 9. DAC816x Data Input Register Format

Command

Address

Data

X

C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

DB23

DB0

Table 10. DAC756x Data Input Register Format

Command

Address

Data

X

C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

DB23

DB0

The DAC856x, DAC816x, and DAC756x support a number of different load commands. The load commands are

summarized in Table 11 and Table 12, and fully exhausted in Table 13.

Table 11. Commands for the DAC856x, DAC816x, and DAC756x

C2

(DB21)

C1

(DB20)

C0

(DB19)

Command

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write to input register n (Table 12)

Software LDAC, update DAC register n (Table 12)

Write to input register n (Table 12) and update all DAC registers

Write to input register n and update DAC register n (Table 12)

Set DAC power up/down mode

Software reset

Set LDAC registers

Enable/disable internal reference

Table 12. Address Select for the DAC856x, DAC816x, and DAC756x

A2

(DB18)

A1

(DB17)

A0

(DB16)

Channel (n)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DAC-A

DAC-B

Gain (only use with command 000)

Reserved

DAC-A and DAC-B

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Table 13. Command Matrix for the DAC856x, DAC816x, and DAC756x

Command

C1

Address

Data

DB23-

DB22

DESCRIPTION

DB15-

DB6

DB3-

C2

C0

A2

A1

A0

DB5

DB4

DB1

DB0

DB2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16/14/12 bit DAC data

X

Write to DAC-A input register

X⁽¹⁾

0

1

0

Write to DAC-B input register

Write to DAC-A and DAC-B input registers

Write to DAC-A input register and update all DACs

Write to DAC-B input register and update all DACs

X

0

1

Write to DAC-A and DAC-B input register and update all DACs

Write to DAC-A input register and update DAC-A

Write to DAC-B input register and update DAC-B

Write to DAC-A and DAC-B input register and update all DACs

Update DAC-A

X

Update DAC-B

X

Update all DACs

0

1

0

1

0

1

0

1

0

1

X

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Gain: DAC-B gain = 2, DAC-A gain = 2 (default with internal V_REF

Gain: DAC-B gain = 2, DAC-A gain = 1

Gain: DAC-B gain = 1, DAC-A gain = 2

Gain: DAC-B gain = 1, DAC-A gain = 1 (power-on default)

Power up DAC-A

)

X

0

1

0

X

1

0

X

0

1

0

1

0

1

X

Power up DAC-B

Power up DAC-A and DAC-B

Power down DAC-A; 1 kΩ to GND

Power down DAC-B; 1 kΩ to GND

Power down DAC-A and DAC-B; 1 kΩ to GND

Power down DAC-A; 100 kΩ to GND

Power down DAC-B; 100 kΩ to GND

Power down DAC-A and DAC-B; 100 kΩ to GND

Power down DAC-A; Hi-Z

X

1

0

1

X

Power down DAC-B; Hi-Z

Power down DAC-A and DAC-B; Hi-Z

Reset DAC-A and DAC-B input register and update all DACs

Reset all registers and update all DACs (Power-on-reset update)

LDAC pin active for DAC-B and DAC-A

LDAC pin active for DAC-B; inactive for DAC-A

LDAC pin inactive for DAC-B; active for DAC-A

LDAC pin inactive for DAC-B and DAC-A

Disable internal reference and reset DACs to gain = 1

Enable Internal Reference & reset DACs to gain = 2

X

1

0

1

X

(1) X' denotes don't care bits.

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GAIN REGISTERS

The gain register controls the GAIN setting in the DAC transfer function:

D

æ

_INö

V_OUT

=

´ V_REF´ Gain

÷

ø

ç

2ⁿ

è

(2)

The DAC756x, DAC816x, and DAC856x have a gain register for each channel. The gain for each channel, in

Equation 2, is either 1 or 2. This gain is automatically set to 2 when using the internal reference, and is

automatically set to 1 when the internal reference is disabled (default). However, each channel can have either

gain by setting the registers appropriately. The gain registers are accessible by using command bits = 000 and

address bits = 010, and using DB1 for DAC-B and DB0 for DAC-A. See Table 13 or Table 14 and Table 15 for

the full command structure. The gain registers are automatically reset to provide either gain of 1 or 2 when the

internal reference is powered off or on, respectively. After the reference is powered off or on, the gain register is

again accessible to change the gain.

Table 14. Gain Register Command Structure

Command

Address

1

Data

X

0

X

DAC-B

DAC-A

DB0

DB23

Table 15. DAC-n Selection for Gain Register Command

DB1/DB0

Value

Gain

DB0

0

1

0

1

DAC-A uses gain = 2 (default with internal reference)

DAC-A uses gain = 1 (default with external reference)

DAC-B uses gain = 2 (default with internal reference)

DAC-B uses gain = 1 (default with external reference)

DB1

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POWER-DOWN MODES

The DAC756x, DAC816x, and DAC856x have two separate sets of power-down commands. One set is for the

DAC channels and the other set is for the internal reference. The internal reference is forced to a powered down

state while both DAC channels are powered down, and is only enabled if any DAC channel is also in normal

mode of operation. For more information on the internal reference control, see the INTERNAL REFERENCE

ENABLE REGISTER section.

DAC Power-Down Commands

The DAC756x, DAC816x, and DAC856x DACs use four modes of operation. These modes are accessed by

setting command bits C2, C1, and C0, and power-down register bits DB5 and DB4. The command bits must be

set to 100. Once the command bits are set correctly, the four different power down modes are software

programmable by setting bits DB5 and DB4 in the shift register. Table 13 or Table 16 through Table 18 shows

how to control the operating mode with data bits PD1 (DB5), PD0 (DB4), DB1, and DB0.

Table 16. DAC Power Mode Register Command Structure

Command

Address

X

Data

X

1

0

X

PD1 PD0

X

DAC-B

DAC-A

DB0

DB23

Table 17. DAC-n Operating Modes

PD1 (DB5)

PD0 (DB4)

DAC OPERATING MODES

Power up selected DACs (normal mode, default)

Power down selected DACs 1 kΩ to GND

Power down selected DACs 100 kΩ to GND

Power down selected DACs Hi-Z to GND

0

1

0

1

0

1

Table 18. DAC-n Selection for Operating Modes

DB1/DB0

Operating Mode

0

1

DAC-n does not change operating mode

DAC-n operating mode set to value on PD1 and PD0

It is possible to write to the DAC register/buffer of the DAC channel that is powered down. When the DAC

channel is then powered up, it powers up to this new value.

The advantage of the available power-down modes is that the output impedance of the device is known while it is

in power-down mode. As described in Table 17, there are three different power-down options. V_OUTcan be

connected internally to GND through a 1-kΩ resistor, a 100-kΩ resistor, or open-circuited (Hi-Z). The DAC

powerdown circuitry is shown in Figure 92.

Resistor

String

DAC

Amplifier

V_OUTX

Power-Down

Circuitry

Resistor

Network

Figure 92. Output Stage

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SOFTWARE RESET FUNCTION

The DAC756x, DAC816x, and DAC856x contain a software reset feature. The software reset function uses

command 101. The software reset command contains two reset modes which are software-programmable by

setting bit DB0 in the shift register. Table 13 and/or Table 19 and Table 20 show the available software reset

commands.

Table 19. Software Reset Command Structure

Command

0

Address

X

Data

X

1

X

RST

DB0

DB23

Table 20. Software Reset

RST (DB0)

Registers Reset to Default Values

0

DAC registers

Input registers

1

DAC registers

Input registers

LDAC registers

Power-down registers

Internal reference register

Gain registers

LDAC FUNCTIONALITY

The DAC756x, DAC816x, and DAC856x offer both a software and hardware simultaneous update and control

function. The DAC double-buffered architecture has been designed so that new data can be entered for each

DAC without disturbing the analog outputs.

DAC756x, DAC816x, and DAC856x data updates can be performed either in synchronous or in asynchronous

mode.

In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC

updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values

and then make a falling edge on LDAC pin to simultaneously update the DAC output registers. Data buffers of all

channels must be loaded with desired data before an LDAC falling edge. After a high-to-low LDAC transition, all

DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a

data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is triggered.

LDAC must be returned high before the next serial command is initiated.

In synchronous mode, data are updated with the falling edge of the 24^thSCLK cycle, which follows a falling edge

of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND

permanently or asserted and held low before sending commands to the device.

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Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The

LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be

updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 2-bit word

(DB1 and DB0) using command bits C2, C1, and C0 (see Table 13 or Table 21). The default value for each bit,

and therefore for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the

LDAC pin is internally tied low for that particular DAC channel) and this DAC channel updates synchronously

after the falling edge of the 24^thSCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is

controlled by the LDAC pin.

The combination of software and hardware simultaneous update functions is particularly useful in applications

when updating a DAC channel, while keeping the other channel unaffected; see Table 13 or Table 21 and

Table 22 for more information.

Table 21. LDAC Register Command Structure

Command

Address

X

Data

X

1

0

X

DAC-B

DAC-A

DB0

DB23

Table 22. DAC-n Selection for LDAC Register Command

DB1/DB0

Value

LDAC Pin Functionality

DB0

0

1

0

1

DAC-A uses LDAC pin

DAC-A operates in synchronous mode

DAC-B uses LDAC pin

DB1

DAC-B operates in synchronous mode

INTERNAL REFERENCE ENABLE REGISTER

The internal reference in the DAC756x, DAC816x, and DAC856x is disabled by default for debugging, evaluation

purposes, or when using an external reference. The internal reference can be powered up and powered down

using a serial command that requires a 24-bit write sequence, as shown in Table 23 and Table 24. The internal

reference is forced to a powered down state while both DAC channels are powered down, and is only enabled if

any DAC channel is in normal mode of operation in addition to using the command in Table 23. During the time

that the internal reference is disabled, the DAC functions normally using an external reference. At this point, the

internal reference is disconnected from the V_REFIN/V_REFOUTpin (Hi-Z output).

Enabling Internal Reference

To enable the internal reference, write the 24-bit serial command shown in Table 23. When performing a power

cycle to reset the device, the internal reference is switched off (default mode). In the default mode, the internal

reference is powered down until a valid write sequence is applied to power up the internal reference. However,

the internal reference is forced to a disabled state while both DAC channels are powered down, and remains

disabled until either DAC channel is returned to the normal mode of operation. See DAC Power-Down

Commands for more information on DAC channel modes of operation.

Table 23. Write Sequence for Enabling Internal Reference

Command

1

Address

X

Data

X

1

X

1

DB23

DB0

Disabling Internal Reference

To disable the internal reference, write the 24-bit serial command shown in Table 24. When performing a power

cycle to reset the device, the internal reference is disabled (default mode).

Table 24. Write Sequence for Disabling Internal Reference

Command

1

Address

X

Data

X

1

X

0

DB23

DB0

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APPLICATION INFORMATION

INTERNAL REFERENCE

The internal reference of the DAC756x, DAC816x, and DAC856x does not require an external load capacitor for

stability because it is stable without any capacitive load. However, for improved noise performance, an external

load capacitor of 150 nF or larger connected to the V_REFIN/V_REFOUToutput is recommended. Figure 93 shows the

typical connections required for operation of the DAC756x, DAC816x, and DAC856x internal reference. A supply

bypass capacitor at the AV_DDinput is also recommended.

DGS

DSC

150 nF

AV_DD

150 nF

AV_DD

V_REFIN

V_REFOUT

AV_DD

/

1

2

3

4

5

10

9

V_OUT

GND

A

1

2

3

4

5

10

9

V_OUT

GND

A

V_REFIN/V_REFOUT

AV_DD

B

1 mF

8

D_IN

SCLK

SYNC

7

LDAC

CLR

SCLK

7

LDAC

CLR

6

SYNC

6

Figure 93. Typical Connections for Operating the DAC756x/DAC816x/DAC856x Internal Reference

Supply Voltage

The internal reference features an extremely low dropout voltage. It can be operated with a supply of only 5 mV

above the reference output voltage in an unloaded condition. For loaded conditions, refer to the Load Regulation

section. The stability of the internal reference with variations in supply voltage (line regulation, DC PSRR) is also

exceptional. Within the specified supply voltage range of 2.7 V to 5.5 V, the variation at V_REFIN/V_REFOUTis

typically 50 µV/V; see Figure 7.

Temperature Drift

The internal reference is designed to exhibit minimal drift error, defined as the change in reference output voltage

over varying temperature. The drift is calculated using the box method described by Equation 3:

V

- V_{REF _MIN}

æ

ö

REF _MAX

Drift Error =

´10⁶ppm/°C

(

)

ç

÷

V_REF´ T_RANGE

è

ø

(3)

where:

V_{REF_MAX}= maximum reference voltage observed within temperature range T_RANGE

.

V_{REF_MIN}= minimum reference voltage observed within temperature range T_RANGE

.

V_REF= 2.5 V, target value for reference output voltage.

T_RANGE= the characterized range from –40°C to 125°C (165°C range)

The internal reference features an exceptional typical drift coefficient of 4 ppm/°C from –40°C to 125°C.

Characterizing a large number of units, a maximum drift coefficient of 10 ppm/°C is observed. Temperature drift

results are summarized in Figure 3.

Noise Performance

Typical 0.1-Hz to 10-Hz voltage noise and noise spectral density performance are listed in the Electrical

Characteristics. Additional filtering can be used to improve output noise levels, although care should be taken to

ensure the output impedance does not degrade the AC performance. The output noise spectrum at the

V_REFIN/V_REFOUTpin, both unloaded and with an external 4.7-µF load capacitor, is shown in Figure 6. Internal

reference noise impacts the DAC output noise when the internal reference is used.

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Load Regulation

Load regulation is defined as the change in reference output voltage as a result of changes in load current. The

load regulation of the internal reference is measured using force and sense contacts as shown in Figure 94. The

force and sense lines reduce the impact of contact and trace resistance, resulting in accurate measurement of

the load regulation contributed solely by the internal reference. Measurement results are shown in Figure 4.

Force and sense lines should be used for applications that require improved load regulation.

Output Pin

Contact and

Trace Resistance

V_OUT

Force Line

I_L

Sense Line

Load

Meter

Figure 94. Accurate Load Regulation of the DAC756x/DAC816x/DAC856x Internal Reference

Long-Term Stability

Long-term stability/aging refers to the change of the output voltage of a reference over a period of months or

years. This effect lessens as time progresses. The typical drift value for the internal reference is listed in the

Electrical Charateristics and measurement results are shown in Figure 5. This parameter is characterized by

powering up multiple devices and measuring them at regular intervals.

Thermal Hysteresis

Thermal hysteresis for a reference is defined as the change in output voltage after operating the device at 25°C,

cycling the device through the operating temperature range, and returning to 25°C. Hysteresis is expressed by

Equation 4:

é

ê

ù

ú

V

- V

REF_PRE

REF_POST

6

V

=

´ 10 (ppm/°C)

HYST

V

ê

ë

REF_NOM

ú

û

(4)

Where:

V_HYST= thermal hysteresis.

V_{REF_PRE}= output voltage measured at 25°C pre-temperature cycling.

V_{REF_POST}= output voltage measured after the device cycles through the temperature range of –40°C to

aaa 125°C, and returns to 25°C.

V_{REF_NOM}= 2.5 V, target value for reference output voltage.

DAC NOISE PERFORMANCE

Output noise spectral density at the V_OUT-n pin versus frequency is depicted in Figure 45 and Figure 46 for

full-scale, mid-scale, and zero-scale input codes. The typical noise density for mid-scale code is 90 nV/√Hz at

1 kHz. High-frequency noise can be improved by filtering the reference noise. Integrated output noise between

0.1 Hz and 10 Hz is close to 2.5 µV_PP(mid-scale), as shown in Figure 47.

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UP TO ±15-V BIPOLAR OUTPUT USING THE DAC8562

The DAC8562 is designed to be operate from a single power supply providing a maximum output range of AV_DD

volts. However, the DAC can be placed in the configuration shown in Figure 95 in order to be designed into

bipolar systems. Depending on the ratio of the resistor values, the output of the circuit can range anywhere from

±5 V to ±15 V. The design example below shows that the DAC is configured to have its internal reference

enabled and the DAC8562 internal gain set to two, however, an external 2.5-V reference could also be used

(with DAC8562 internal gain set to two).

R

G ´ R

5.5 V

18 V

V_OUT

–

+

R

V_REFOUT

OPA140

G ´ R

DAC8562

–18 V

Figure 95. Bipolar Output Range Circuit Using DAC8562

The transfer function shown in Equation 5 can be used to calculate the output voltage as a function of the DAC

code, reference voltage and resistor ratio:

D_IN

æ

ç

ö

V_OUT= G × V_REFOUT2 ×

è

-1

÷

65,536

ø

(5)

where:

D_IN= decimal equivalent of the binary code that is loaded to the DAC register, ranging from 0 to 65,535 for

aaa DAC8562 (16 bit).

V_REFOUT= reference output voltage with the internal reference enabled from the DAC V_REFIN/V_REFOUTpin

G = ratio of the resistors

An example configuration to generate a ±10-V output range is shown below in Equation 6 with G = 4 and

V_REFOUT= 2.5 V:

D_IN

V_OUT= 20 ×

-10 V

65,536

(6)

In this example, the range is set to ±10 V by using a resistor ratio of four, V_REFOUTof 2.5 V, and DAC8562

internal gain of two. The resistor sizes must be selected keeping in mind the current sink/source capability of the

DAC8562 internal reference. Using larger resistor values, for example R = 10 kΩ or larger is recommended. The

op amp is selectable depending on the requirements of the system.

The DAC8562EVM and DAC7562EVM boards have the option to evaluate the bipolar output application by

installing the components on the pre-placed footprints. For more information see either the DAC8562EVM or

DAC7562EVM product folder.

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PLC ANALOG OUTPUT MODULE USING THE DAC8562

The DAC8562 can be mated with one of TI's 0- to 20-mA voltage-to-current transmitters to create a low-cost,

programmable current source for use in PLC applications. One specific example includes combining the

DAC8562 with the XTR111 to create a voltage-to-current solution. The DAC output voltage generates a current,

I_SET, which is determined by the value of the external resistor, R_SET. This current is internally amplified by 10 and

output at the IS node. A p-channel MOSFET Q1 can be added in an application where a wide compliance

voltage is required, for example, when using a high impedance load. The optional PNP transistor, Q2, along with

the R4 resistor provides external current limiting in a case where the external FET is forced to low impedance.

Additionally, resistors R2 and R3 can be used to scale the 3-V internal regulator to a desired voltage to power

the DAC. Figure 96 shows a working 0- to 20-mA solution using one DAC8562 channel and a ±10-V voltage

output using the other DAC8562 channel. For more information on the ±10-V voltage output circuit see the UP

TO ±15-V BIPOLAR OUTPUT USING THE DAC8562 application.

24 V

5.5 V

VSP

REGF

REGS

IS

R4

15 Ω

C1

470 nF

R2

2.5 kΩ

Q2

XTR111

R3

3 kΩ

Q1

VG

R1

2.5 kΩ

A_VDD

0 to 5 V

V_OUT

A

VIN

R5

15 Ω

C2

10 nF

SET

DAC8562

R_SET

2.5 kΩ

V_OUT

B

V_REFOUT

GND

I_OUT

0- to 20-mA Output

18 V

R6

10 kΩ

+

OPA140

–

V_OUT

10-V Output

R7

40 kΩ

–18 V

R8

10 kΩ

R9

40 kΩ

Figure 96. 0- to 20-mA and ±10-V Outputs Using DAC8562

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MICROPROCESSOR INTERFACING

DAC756x/DAC816x/DAC856x to an MSP430 USI Interface

Figure 97 shows a serial interface between the DAC756x, DAC816x, or DAC856x and a typical MSP430 USI port

such as the one found on the MSP430F2013. The port is configured in SPI master mode by setting bits 3, 5, 6,

and 7 in USICTL0. The USI counter interrupt is set in USICTL1 to provide an efficient means of SPI

communication with minimal software overhead. The serial clock polarity, source, and speed are controlled by

settings in the USI clock control register (USICKCTL). The SYNC signal is derived from a bit-programmable pin

on port 1; in this case, port line P1.4 is used. When data are to be transmitted to the DAC756x, DAC816x, or

DAC856x, P1.4 is taken low. The USI transmits data in 8-bit bytes; thus, only eight falling clock edges occur in

the transmit cycle. To load data to the DAC, P1.4 is left low after the first eight bits are transmitted; then, a

second write cycle is initiated to transmit the second byte of data. P1.4 is taken high following the completion of

the third write cycle.

MSP430F2013

DAC

SYNC

P1.4/GPIO

P1.5/SCLK

P1.6/SDO

SCLK

D_IN

NOTE: Additional pins omitted for clarity.

Figure 97. DAC756x/DAC816x/DAC856x to MSP430 Interface

DAC756x/DAC816x/DAC856x to a TMS320 McBSP Interface

Figure 98 shows an interface between the DAC756x, DAC816x, or DAC856x and any TMS320 series DSP from

Texas Instruments with a multi-channel buffered serial port (McBSP). Serial data are shifted out on the rising

edge of the serial clock and are clocked into the DAC756x, DAC816x, or DAC856x on the falling edge of the

SCLK signal.

TMS320F28062

DAC

SYNC

MFSxA

MCLKxA

MDxA

SCLK

D_IN

NOTE: Additional pins omitted for clarity.

Figure 98. DAC756x/DAC816x/DAC856x to TMS320 McBSP Interface

DAC756x/DAC816x/DAC856x to an OMAP-L1x Processor

Figure 99 shows a serial interface between the DAC756x/DAC816x/DAC856x and the OMAP-L138. The transmit

clock CLKx0 of the L138 drives SCLK of the DAC756x, DAC816x, or DAC856x, and the data transmit (Dx0)

output drives the serial data line of the DAC. The SYNC signal is derived from the frame sync transmit (FSx0)

line, similar to the TMS320 interface.

OMAP-L138

FSx0

DAC

SYNC

CLKx0

Dx0

SCLK

D_IN

NOTE: Additional pins omitted for clarity.

Figure 99. DAC756x/DAC816x/DAC856x to OMAP-L1x Processor

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LAYOUT

A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power

supplies. The DAC756x, DAC816x, and DAC856x offer single-supply operation, and are often used in close

proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic

present in the design and the higher the switching speed, the more difficult it is to keep digital noise from

appearing at the output. As a result of the single ground pin of the DAC756x, DAC816x, and DAC856x, all return

currents (including digital and analog return currents for the DAC) must flow through a single point. Ideally, GND

would be connected directly to an analog ground plane. This plane would be separate from the ground

connection for the digital components until they were connected at the power-entry point of the system. The

power applied to AV_DDshould be well-regulated and low noise. Switching power supplies and dc/dc converters

often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can

create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the

DAC output voltage through various paths between the power connections and analog output. As with the GND

connection, AV_DDshould be connected to a power-supply plane or trace that is separate from the connection for

digital logic until they are connected at the power-entry point. In addition, a 1-µF to 10-µF capacitor and 0.1-µF

bypass capacitor are strongly recommended. In some situations, additional bypassing may be required, such as

a 100-µF electrolytic capacitor or even a pi filter made up of inductors and capacitors – all designed to essentially

low-pass filter the supply and remove the high-frequency noise.

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PARAMETER DEFINITIONS

With the increased complexity of many different specifications listed in product data sheets, this section

summarizes selected specifications related to digital-to-analog converters.

STATIC PERFORMANCE

Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity

(INL). These are dc specifications and provide information on the accuracy of the DAC. They are most important

in applications where the signal changes slowly and accuracy is required.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is defined as the maximum deviation of the real LSB step from the ideal 1 LSB

step. Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart.

If the DNL is less than 1 LSB, the DAC is said to be monotonic.

Full-Scale Error

Full-scale error is defined as the deviation of the real full-scale output voltage from the ideal output voltage while

the DAC register is loaded with the full-scale code (0xFFFF). Ideally, the output should be V_REF– 1 LSB or

2 × V_REF– 1 LSB, depending on the DAC voltage gain. The full-scale error is expressed in percent of full-scale

range (% FSR).

Full-Scale Error Drift

Full-scale error drift is defined as the change in full-scale error with a change in temperature. Full-scale error drift

is expressed in units of ppm of FSR/°C.

Full-Scale Range (FSR)

Full-scale range (FSR) is the difference between the maximum and minimum analog output values that the DAC

is specified to provide; typically, the maximum and minimum values are also specified. For an n-bit DAC, these

values are usually given as the values matching with code 0 and 2ⁿ– 1.

Gain Error

Gain error is defined as the deviation in the slope of the real DAC transfer characteristic from the ideal transfer

function. Gain error is expressed as a percentage of full-scale range (% FSR).

Gain Temperature Coefficient

The gain temperature coefficient is defined as the change in gain error with changes in temperature. The gain

temperature coefficient is expressed in ppm of FSR/°C.

Least-Significant Bit (LSB)

The least significant bit (LSB) is defined as the smallest value in a binary coded system. The value of the LSB

can be calculated by dividing the full-scale output voltage by 2ⁿ, where n is the resolution of the converter.

Monotonicity

Monotonicity is defined as a slope whose sign does not change. If a DAC is monotonic, the output changes in

the same direction or remains constant for each step increase (or decrease) in the input code.

Most-Significant Bit (MSB)

The most significant bit (MSB) is defined as the largest value in a binary coded system. The value of the MSB

can be calculated by dividing the full-scale output voltage by 2. Its value is one-half of full-scale.

Offset Error

The offset error is defined as the difference between actual output voltage and the ideal output voltage in the

linear region of the transfer function. This difference is calculated by using a straight line defined by two codes

(code 512 and code 65,024). Because the offset error is defined by a straight line, it can have a negative or

positive value. Offset error is measured in mV.

Offset Error Drift

Offset error drift is defined as the change in offset error with a change in temperature. Offset error drift is

expressed in µV/°C.

Power-Supply Rejection Ratio (PSRR)

Power-supply rejection ratio (PSRR) is defined as the ratio of change in output voltage to a change in supply

voltage for a full-scale output of the DAC. The PSRR of a device indicates how the output of the DAC is affected

by changes in the supply voltage. PSRR is measured in decibels (dB).

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Relative Accuracy or Integral Nonlinearity (INL)

Relative accuracy or integral nonlinearity (INL) is defined as the maximum deviation between the real transfer

function and a straight line passing through the endpoints of the ideal DAC transfer function. INL is measured in

LSBs.

Resolution

Generally, the DAC resolution can be expressed in different forms. Specifications such as IEC 60748-4

recognize the numerical, analog, and relative resolution. The numerical resolution is defined as the number of

digits in the chosen numbering system necessary to express the total number of steps of the transfer

characteristic, where a step represents both a digital input code and the corresponding discrete analogue output

value. The most commonly-used definition of resolution provided in data sheets is the numerical resolution

expressed in bits.

Zero-Code Error

The zero-code error is defined as the DAC output voltage, when all 0s are loaded into the DAC register.

Zero-code error is a measure of the difference between actual output voltage and ideal output voltage (0 V). It is

expressed in mV. It is primarily caused by offsets in the output amplifier.

Zero-Code Error Drift

Zero-code error drift is defined as the change in zero-code error with a change in temperature. Zero-code error

drift is expressed in µV/°C.

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DYNAMIC PERFORMANCE

Dynamic performance parameters are specifications such as settling time or slew rate, which are important in

applications where the signal rapidly changes and/or high frequency signals are present.

Channel-to-Channel Crosstalk

Crosstalk in a multi-channel DAC is defined as a glitch coupled onto the output of a channel (victim) when the

output of an adjacent channel (agressor) has a full-scale transition. It is calculated as the total area under the

measured glitch on the victim channel at mid-scale code. It is expressed in nV-s.

Channel-to-Channel DC Crosstalk

Channel-to-channel dc crosstalk is defined as the dc change in the output level of one DAC channel in response

to a change in the output of another DAC channel. It is measured with a full-scale output change on one DAC

channel while monitoring another DAC channel at mid-scale. It is expressed in LSB.

Code Change/Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC

register changes state. It is normally specified as the area of the glitch in nanovolt-seconds (nV-s), and is

measured when the digital input code is changed by 1 LSB at the major carry transition.

DAC Output Noise

DAC output noise is defined as any voltage deviation of DAC output from the desired value (within a particular

frequency band). It is measured with a DAC channel kept at mid-scale while filtering the output voltage within a

band of 0.1 Hz to 10 Hz and measuring its amplitude peaks. It is expressed in terms of peak-to-peak voltage

(V_PP).

DAC Output Noise Density

Output noise density is defined as internally-generated random noise. Random noise is characterized as a

spectral density (nV/√Hz). It is measured by setting the DAC to mid-scale and measuring noise at the output.

Digital Feedthrough

Digital feedthrough is defined as the impulse seen at the output of the DAC from the digital inputs of the DAC. It

is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code

change on the data bus; that is, from all 0s to all 1s and vice versa.

Output Voltage Settling Time

Settling time is the total time (including slew time) for the DAC output to settle within an error band around its

final value after a change in input. Settling times are specified to within ±0.024% FSR (or whatever value is

stated) of full-scale range.

Slew Rate

The output slew rate (SR) of an amplifier or other electronic circuit is defined as the maximum rate of change of

the output voltage for all possible input signals.

DV

(t)

OUT

SR = max

Dt

(7)

Where ΔV_OUT(t) is the output produced by the amplifier as a function of time t.

Submit Documentation Feedback

45

Product Folder Link(s): DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Jun-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC7562SDGSR

DAC7562SDSCR

DAC7563SDGSR

DAC7563SDGST

DAC7563SDSCR

DAC8162SDGSR

DAC8162SDGST

DAC8162SDSCR

DAC8162SDSCT

DAC8163SDGSR

DAC8163SDSCR

DAC8163SDSCT

DAC8562SDGSR

DAC8562SDGST

DAC8562SDSCR

DAC8562SDSCT

DAC8563SDGSR

DAC8563SDSCR

MSOP

SON

DGS

DSC

DGS

DSC

DGS

DSC

DGS

DSC

DGS

DSC

DGS

DSC

10

2500

3000

2500

250

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

12.4

5.3

3.3

5.3

3.3

5.3

3.3

5.3

3.3

5.3

3.3

5.3

3.3

1.3

1.1

1.3

1.1

1.3

1.1

1.3

1.1

1.3

1.1

1.3

1.1

8.0

12.0

Q1

Q2

Q1

Q2

Q1

Q2

Q1

Q2

Q1

Q2

Q1

Q2

MSOP

SON

3000

2500

250

MSOP

SON

3000

250

SON

MSOP

SON

2500

3000

250

SON

MSOP

SON

2500

250

3000

250

SON

MSOP

SON

2500

3000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Jun-2011

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC8563SDSCT

SON

DSC

10

250

180.0

12.4

3.3

1.1

8.0

12.0

Q2

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC7562SDGSR

DAC7562SDSCR

DAC7563SDGSR

DAC7563SDGST

DAC7563SDSCR

DAC8162SDGSR

DAC8162SDGST

DAC8162SDSCR

DAC8162SDSCT

DAC8163SDGSR

DAC8163SDSCR

DAC8163SDSCT

DAC8562SDGSR

DAC8562SDGST

DAC8562SDSCR

DAC8562SDSCT

MSOP

SON

DGS

DSC

DGS

DSC

DGS

DSC

DGS

DSC

DGS

DSC

10

2500

3000

2500

250

346.0

203.0

346.0

203.0

346.0

190.5

346.0

190.5

346.0

203.0

346.0

190.5

346.0

203.0

346.0

203.0

346.0

212.7

346.0

212.7

346.0

203.0

346.0

212.7

35.0

29.0

35.0

29.0

35.0

29.0

31.8

35.0

29.0

31.8

35.0

29.0

31.8

MSOP

SON

3000

2500

250

MSOP

SON

3000

250

SON

MSOP

SON

2500

3000

250

SON

MSOP

SON

2500

250

3000

250

SON

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Jun-2011

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC8563SDGSR

DAC8563SDSCR

DAC8563SDSCT

MSOP

SON

DGS

DSC

10

2500

3000

250

346.0

190.5

346.0

212.7

35.0

29.0

31.8

SON

Pack Materials-Page 3

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型号：	DAC7562_15
厂家：	TEXAS INSTRUMENTS
描述：	Internal Reference
文件：	总56页 (文件大小：1315K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC7562_15 [TI]

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