DAC7612UBG4 [TI]
Dual, 12-Bit Serial Input Digital-To-Analog Converter 8-SOIC -40 to 85;
| 型号： | DAC7612UBG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual, 12-Bit Serial Input Digital-To-Analog Converter 8-SOIC -40 to 85 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DAC7612
DAC7612
Dual, 12-Bit Serial Input
DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
FEATURES
The DAC7612 is a dual, 12-bit digital-to-analog con-
verter (DAC) with guaranteed 12-bit monotonicity
performance over the industrial temperature range. It
requires a single +5V supply and contains an input
shift register, latch, 2.435V reference, a dual DAC, and
high speed rail-to-rail output amplifiers. For a full-
scale step, each output will settle to 1 LSB within 7µs
while only consuming 3.7mW.
● LOW POWER: 3.7mW
● FAST SETTLING: 7µs to 1 LSB
● 1mV LSB WITH 4.095V FULL-SCALE
RANGE
● COMPLETE WITH REFERENCE
● 12-BIT LINEARITY AND MONOTONICITY
OVER INDUSTRIAL TEMP RANGE
The synchronous serial interface is compatible with a
wide variety of DSPs and microcontrollers. Clock
(CLK), Serial Data In (SDI), Chip Select (CS) and
Load DACs (LOADDACS) comprise the serial inter-
face.
● 3-WIRE INTERFACE: Up to 20MHz Clock
● SMALL PACKAGE: 8-Lead SOIC
APPLICATIONS
● PROCESS CONTROL
The DAC7612 is available in an 8-lead SOIC package
and is fully specified over the industrial temperature
range of –40°C to +85°C.
● DATA ACQUISITION SYSTEMS
● CLOSED-LOOP SERVO-CONTROL
● PC PERIPHERALS
● PORTABLE INSTRUMENTATION
VDD
12-Bit DAC A
VOUTA
12
LOADDACS
DAC Register A
12
CS
CLK
14-Bit Serial Shift Register
SDI
12
Ref
DAC Register B
12
12-Bit DAC B
VOUTB
DAC7612
GND
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
• Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
•
© 1999 Burr-Brown Corporation
PDS-1501A
Printed in U.S.A. June, 1999
SBAS106
SPECIFICATIONS
At TA = –40°C to +85°C, and VDD = +5V, unless otherwise noted.
DAC7612U
TYP
DAC7612UB
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
12
✻
Bits
ACCURACY
Relative Accuracy(1)
Differential Nonlinearity
Zero-Scale Error
Zero Scale Match
Full-Scale Voltage
Full-Scale Match
–2
–1
–1
±1/2
±1/2
+1
1/2
4.095
1/2
+2
+1
+3
–1
–1
✻
±1/4
±1/4
✻
1/2
4.095
1/2
+1
+1
✻
LSB
LSB
LSB
LSB
V
Guaranteed Monotonic
Code 000H
Code 000H
Code FFFH
Code FFFH
2
4.079
4.111
4.087
4.103
2
LSB
ANALOG OUTPUT
Output Current
Load Regulation
Capacitive Load
Short-Circuit Current
Short-Circuit Duration
Code 800H
RLOAD ≥ 402Ω, Code 800H
No Oscillation
±5
±7
1
500
±15
Indefinite
✻
✻
✻
✻
✻
✻
mA
LSB
pF
3
✻
mA
GND or VDD
DIGITAL INPUT
Data Format
Data Coding
Logic Family
Logic Levels
VIH
VIL
IIH
IIL
Serial
Straight Binary
CMOS
✻
✻
✻
0.7 • VDD
✻
V
V
µA
µA
0.3 • VDD
±10
✻
✻
✻
±10
DYNAMIC PERFORMANCE
Settling Time(2) (tS)
DAC Glitch
To ±1 LSB of Final Value
7
2.5
0.5
✻
✻
✻
µs
nV-s
nV-s
Digital Feedthrough
POWER SUPPLY
VDD
IDD
Power Dissipation
Power Supply Sensitivity
+4.75
–40
+5.0
0.75
3.5
+5.25
1.5
7.5
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
mA
mW
%/%
VIH = 5V, VIL = 0V, No Load, at Code 000H
VIH = 5V, VIL = 0V, No Load
∆VDD = ±5%
0.0025
0.002
TEMPERATURE RANGE
Specified Performance
+85
✻
°C
✻ Same specification as for DAC7612U.
NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where
the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
DAC7612
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
Top View
SO-8
1
SDI
Serial Data Input. Data is clocked into the internal
serial register on the rising edge of CLK.
2
3
CLK
Synchronous Clock for the Serial Data Input.
LOADDACS Loads the internal DAC registers. All DAC registers
are transparent latches and are transparent when
LOADDACS is LOW (regardless of the state of CS
or CLK).
1
8
7
6
5
VOUTA
VDD
SDI
2
CLK
DAC7612U
3
GND
VOUTB
LOADDACS
4
5
6
7
8
CS
Chip Select. Active LOW.
DAC B Output Voltage
Ground
4
CS
VOUTB
GND
VDD
Positive Power Supply
DAC A Output Voltage
VOUTA
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
VDD to GND .......................................................................... –0.3V to 6V
Digital Inputs to GND ..............................................–0.3V to VDD + 0.3V
VOUT to GND ...........................................................–0.3V to VDD + 0.3V
Power Dissipation ........................................................................ 325mW
Thermal Resistance, θJA ........................................................... 150°C/W
Maximum Junction Temperature .................................................. +150°C
Operating Temperature Range ...................................... –40°C to +85°C
Storage Temperature Range ....................................... –65°C to +150°C
Lead Temperature (soldering, 10s).............................................. +300°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
DRAWING
NUMBER(1)
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DAC7612U
±2
"
±1
"
±1
"
±1
"
–40°C to +85°C
SO-8
182
"
182
"
DAC7612U
DAC7612U/2K5
DAC7612UB
Rails
Tape and Reel
Rails
"
"
"
SO-8
"
DAC7612UB
–40°C to +85°C
"
"
DAC7612UB/2K5
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7612U/2K5” will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
3
DAC7612
EQUIVALENT INPUT LOGIC
ESD protection
diodes to VDD
and GND
DAC Switches
12
DAC B Register
LOADDACS
12
Data
SDI
Serial Shift Register
CS
12
CLK
DAC A Register
12
DAC Switches
®
4
DAC7612
TIMING DIAGRAMS
(MSB)
D11
(LSB)
D0
SDI
CLK
CS
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
tCSS
tCSH
tLD1
tLD2
LOADDACS
tDS
tDH
SDI
tCL
tCH
CLK
tLDW
LOADDACS
tS
FS
±1 LSB
Error Band
VOUT
ZS
LOGIC TRUTH TABLE
TIMING SPECIFICATIONS
TA = –40°C to +85°C and VDD = +5V.
SERIAL SHIFT
A0 CLK CS LOADDACS REGISTER
DAC
DAC
A1
REGISTER A REGISTER B
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
X
X
L
X
X
X
X
↑
X
H
L
H(1)
H
H
L
No Change
Shifts One Bit
No Change
No Change
No Change
No Change
No Change
tCH
tCL
tLDW
tDS
Clock Width HIGH
Clock Width LOW
Load Pulse Width
Data Setup
30
30
20
15
15
15
10
30
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Loads Serial
Data Word
Loads Serial
Data Word
H
H
L
X
X
H
H
L
L
No Change
No Change
Loads Serial
Data Word
No Change
tDH
Data Hold
H
No Change
Loads Serial
Data Word
tLD1
tLD2
tCSS
tCSH
Load Setup
Load Hold
↑ Positive Logic Transition; X = Don’t Care.
Select
NOTE: (1) A HIGH value is suggested in order to avoid to “false clock” from
advancing the shift register and changing the DAC voltage.
Deselect
NOTE: All input control signals are specified with tR = tF = 5ns (10% to 90%
of +5V) and timed from a voltage level of 2.5V. These parameters are
guaranteed by design and are not subject to production testing.
DATA INPUT TABLE
B0
A1
B1 B2 B3
B4 B5 B6
B7 B8 B9 B10 B11 B12 B13
D6 D5 D4 D3 D2 D1 D0
A0 D11 D10 D9 D8 D7
®
5
DAC7612
TYPICAL PERFORMANCE CURVES
At TA = +25°, and VDD = 5V, unless otherwise specified.
OUTPUT SWING vs LOAD
5
PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT
1k
100
10
+85°C
4
RL tied to GND
Data = FFFH
3
+25°C
2
1
–40°C
1
0
0.1
RL tied to VDD
Data = 000H
Data = 000H
0.01
10
100
1k
Load Resistance (Ω)
10k
100k
0.001
0.01
0.1
1
10
100
Current (mA)
BROADBAND NOISE
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
1
2
3
4
5
Time (2ms/div)
Code = FFFH, BW = 1MHz
Logic Voltage (V)
POWER SUPPLY REJECTION vs FREQUENCY
MINIMUM SUPPLY VOLTAGE vs LOAD
70
60
50
40
30
20
10
0
5.0
4.8
4.6
4.4
4.2
4.0
Data = FFFH
VDD = 5V
±200mV AC
10
100
1k
10k
100k
1M
0.01
0.1
1
10
Frequency (Hz)
Output Load Current (mA)
®
6
DAC7612
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE
SUPPLY CURRENT vs TEMPERATURE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
20
15
VDD = 5.0V
VLOGIC = 3.5V
Data = FFFH
No Load
Positive
Current
Limit
VDD = 5.25V
10
Data = 800H
Output tied to ISOURCE
5
0
VDD = 4.75V
–5
–10
–15
–20
Negative
Current
Limit
At worst-case digital inputs.
0
1
2
3
4
5
6
–50 –30 –10
10
30
50
70
90
110 130
Output Voltage (V)
Temperature (°C)
MIDSCALE GLITCH PERFORMANCE
LOADDACS
MIDSCALE GLITCH PERFORMANCE
LOADDACS
7FFH to 800H
800H to 7FFH
Time (500ns/div)
Time (500ns/div)
RISE TIME DETAIL
LARGE-SIGNAL SETTLING TIME
LOADDACS
CL = 100pF
L = No Load
R
CL = 100pF
L = No Load
R
LOADDACS
Time (10µs/div)
Time (20µs/div)
®
7
DAC7612
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
FALL TIME DETAIL
OUTPUT VOLTAGE NOISE vs FREQUENCY
Data = FFFH
10.000
CL = 100pF
RL = No Load
1.000
0.100
LOADDACS
0.010
Time (10µs/div)
10
100
1k
10k
100k
Frequency (Hz)
TOTAL UNADJUSTED ERROR HISTOGRAM
LONG-TERM DRIFT ACCELERATED BY BURN-IN
35
5
4
T.U.E = Σ (INL + ZSE + FSE)
Sample Size = 200 Units
30
25
20
15
10
5
Max
Avg
3
T
A = +25°C
2
1
0
–1
–2
–3
–4
–5
Min
0
0
168
336
504
672
840
1008
–12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12
Hours of Operation at +150°C
FULL-SCALE VOLTAGE vs TEMPERATURE
ZERO-SCALE VOLTAGE vs TEMPERATURE
4.111
4.103
4.095
4.087
4.079
3
2
1
0
Avg + 3σ
Avg + 3σ
Avg
Avg
Avg – 3σ
Avg – 3σ
–1
–40
–15
10
35
60
85
–40
–15
10
35
60
85
Temperature (°C)
Temperature (°C)
®
8
DAC7612
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
LINEARITY ERROR vs DIGITAL CODE
LINEARITY ERROR vs DIGITAL CODE
(DAC A at +85°C)
(DAC B at +85°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0
0
0
512
512
512
1024 1536
2048
2560 3072
3584
3584
3584
4096
4096
4096
0
512
1024 1536
2048
2560 3072
3584
4096
Code
Code
LINEARITY ERROR vs DIGITAL CODE
LINEARITY ERROR vs DIGITAL CODE
(DAC B at +25°C)
(DAC A at +25°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0
512
1024 1536
2048
2560 3072
3584
4096
1024 1536
2048
2560 3072
Code
Code
LINEARITY ERROR vs DIGITAL CODE
LINEARITY ERROR vs DIGITAL CODE
(DAC A at –40°C)
(DAC B at –40°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
1024 1536
2048
2560 3072
0
512
1024 1536
2048
2560 3072
3584
4096
Code
Code
®
9
DAC7612
next 12 bits are the code (MSB-first) sent to the DAC. The
data format is Straight Binary and is loaded MSB-first into
the shift registers after loading the address bits. Table I shows
the relationship between input code and output voltage.
OPERATION
The DAC7612 is a dual, 12-bit digital-to-analog converter
(DAC) complete with a serial-to-parallel shift register, DAC
registers, laser-trimmed 12-bit DACs, on-board reference,
and rail-to-rail output amplifiers. Figure 1 shows the basic
operation of the DAC7612.
The digital data into the DAC7612 is double-buffered. This
means that new data can be entered into the chosen DAC
without disturbing the old data and the analog output of the
converter. At some point after the data has been entered into
the serial shift register, this data can be transferred into the
DAC registers. This transfer is accomplished with a HIGH
to LOW transition of the LOADDACS pin. The LOADDACS
pin makes the DAC registers transparent. If new data is
shifted into the shift register while LOADDACS is LOW,
the DAC output voltages will change as each new bit is
entered. To prevent this, LOADDACS must be returned
HIGH prior to shifting in new serial data.
INTERFACE
Figure 1 shows the basic connection between a
microcontroller and the DAC7612. The interface consists of
a Serial Clock (CLK), Serial Data (SDI), and a Load DAC
signal (LOADDACS). In addition, a chip select (CS) input is
available to enable serial communication when there are
multiple serial devices. Loading either DAC A or DAC B is
done by shifting 14 serial bits in via the SDI input. The first
2 bits represent the address of the DAC to be updated and the
DIGITAL-TO-ANALOG CONVERTER
The internal DAC section is a 12-bit voltage output
device that swings between ground and the internal ref-
erence voltage. The DAC is realized by a laser-trimmed
R-2R ladder network which is switched by N-channel
MOSFETs. Each DAC output is internally connected to a
rail-to-rail output operational amplifier.
DAC7612 Full-Scale Range = 4.095V
Least Significant Bit = 1mV
DIGITAL INPUT CODE
STRAIGHT OFFSETBINARY
ANALOG OUTPUT
(V)
DESCRIPTION
FFFH
801H
800H
7FFH
000H
+4.095
+2.049
+2.048
+2.047
0
Full Scale
Midscale + 1 LSB
Midscale
OUTPUT AMPLIFIER
Midscale – 1 LSB
Zero Scale
A precision, low-power amplifier buffers the output of each
DAC section and provides additional gain to achieve a 0V to
4.095V range. Each amplifier has low offset voltage, low
TABLE I. Digital Input Code and Corresponding Ideal
Analog Output.
DAC7612U
Serial Data
Serial Clock
Load DACs
Chip Select
SDI
1
2
3
4
VOUTA
VDD
8
7
6
5
0V to +4.095V
+
CLK
0.1µF
10µF
LOADDACS
CS
GND
VOUTB
0V to +4.095V
FIGURE 1. Basic Operation of the DAC7612.
®
10
DAC7612
noise, and a set gain of 1.682V/V (4.095/2.435). See Figure
2 for an equivalent circuit schematic of the analog portion of
the DAC7612.
If power consumption is critical, it is important to keep the
logic levels on the digital inputs (SDI, CLK, CS,
LOADDACS) as close as possible to either VDD or ground.
This will keep the CMOS inputs (see “Supply Current vs
Logic Input Voltages” in the Typical Performance Curves)
from shunting current between VDD and ground.
The output amplifier has a 7µs typical settling time to ±1
LSB of the final value. Note that there are differences in the
settling time for negative-going signals versus positive-
going signals.
The DAC7612 power supply should be bypassed as shown
in Figure 1. The bypass capacitors should be placed as close
to the device as possible, with the 0.1µF capacitor taking
priority in this regard. The “Power Supply Rejection vs
Frequency” graph in the Typical Performance Curves sec-
tion shows the PSRR performance of the DAC7612. This
should be taken into account when using switching power
supplies or DC/DC converters.
The rail-to-rail output stage of the amplifier provides the full-
scale range of 0V to 4.095V while operating on a supply voltage
as low as 4.75V. In addition to its ability to drive resistive loads,
the amplifier will remain stable while driving capacitive loads
of up to 500pF. See Figure 3 for an equivalent circuit schematic
of the amplifier’s output driver and the Typical Performance
Curves section for more information regarding settling time,
load driving capability, and output noise.
In addition to offering guaranteed performance with VDD in
the 4.75V to 5.25V range, the DAC7612 will operate with
reduced performance down to 4.5V. Operation between
4.5V and 4.75V will result in longer settling time, reduced
performance, and current sourcing capability. Consult the
“VDD vs Load Current” graph in the Typical Performance
Curves section for more information.
POWER SUPPLY
A BiCMOS process and careful design of the bipolar and
CMOS sections of the DAC7612 result in a very low power
device. Bipolar transistors are used where tight matching
and low noise are needed to achieve analog accuracy, and
CMOS transistors are used for logic, switching functions
and for other low power stages.
R-2R DAC
Output Amplifier
2R
2R
2R
R
Buffer
R2
Bandgap
2.435V
Reference
R
R
R1
2R
Typical of DAC A or DAC B
2R
FIGURE 2. Simplified Schematic of Analog Portion.
VDD
P-Channel
N-Channel
VOUT
GND
FIGURE 3. Simplified Driver Section of Output Amplifier.
®
11
DAC7612
reference point for the internal bandgap reference. Ideally,
GND would be connected directly to an analog ground
plane. This plane would be separate from the ground con-
nection for the digital components until they are connected
at the power entry point of the system (see Figure 4).
APPLICATIONS
POWER AND GROUNDING
The DAC7612 can be used in a wide variety of situations—
from low power, battery operated systems to large-scale
industrial process control systems. In addition, some appli-
cations require better performance than others, or are par-
ticularly sensitive to one or two specific parameters. This
diversity makes it difficult to define definite rules to follow
concerning the power supply, bypassing, and grounding.
The following discussion must be considered in relation to
the desired performance and needs of the particular system.
The power applied to VDD should be well regulated and low-
noise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between VDD and VOUT
.
A precision analog component requires careful layout, ad-
equate bypassing, and a clean, well-regulated power supply.
As the DAC7612 is a single-supply, +5V component, it will
often be used in conjunction with digital logic,
microcontrollers, microprocessors, and digital signal proces-
sors. The more digital logic present in the design and the
higher the switching speed, the more difficult it will be to
achieve good performance.
As with the GND connection, VDD should be connected to
a +5V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 10µF and 0.1µF capaci-
tors shown in Figure 4 are strongly recommended and
should be installed as close to VDD and ground as possible.
In some situations, additional bypassing may be required
such as a 100µF electrolytic capacitor or even a “Pi” filter
made up of inductors and capacitors—all designed to essen-
tially lowpass filter the +5V supply, removing the high
frequency noise (see Figure 4).
Because the DAC7612 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through this pin. The GND pin is also the ground
Digital Circuits
+5V
Power
Supply
+5V
+5V
GND
DAC7612
VDD
GND
+
+
100µF
10µF
0.1µF
GND
Optional
Other
Analog
Components
FIGURE 4. Suggested Power and Ground Connections for a DAC7612 Sharing a +5V Supply with a Digital System.
®
12
DAC7612
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2009
PACKAGING INFORMATION
Orderable Device
DAC7612U
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
DAC7612U/2K5
DAC7612U/2K5G4
DAC7612UB
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
DAC7612UB/2K5
DAC7612UB/2K5G4
DAC7612UBG4
DAC7612UG4
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
DAC7612U/2K5
DAC7612UB/2K5
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC7612U/2K5
DAC7612UB/2K5
SOIC
SOIC
D
D
8
8
2500
2500
346.0
346.0
346.0
346.0
29.0
29.0
Pack Materials-Page 2
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