DAC7621EBG4 [TI]
12 位、并行输入数模转换器 | DB | 20 | -40 to 85;
| 型号： | DAC7621EBG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 位、并行输入数模转换器 | DB | 20 | -40 to 85 光电二极管 转换器 数模转换器 |
| 文件： | 总17页 (文件大小：625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DAC7621
®
DAC7621
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit, Parallel Input
DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
FEATURES
The DAC7621 is a 12-bit digital-to-analog converter
(DAC) with guaranteed 12-bit monotonicity perfor-
mance over the industrial temperature range. It re-
quires a single +5V supply and contains an input
register, latch, 2.435V reference, DAC, and high speed
rail-to-rail output amplifier. For a full-scale step, the
output will settle to 1 LSB within 7µs. The device
consumes 2.5mW (0.5mA at 5V).
● LOW POWER: 2.5mW
● FAST SETTLING: 7µs to 1 LSB
● 1mV LSB WITH 4.095V FULL-SCALE
RANGE
● COMPLETE WITH REFERENCE
● 12-BIT LINEARITY AND MONOTONICITY
OVER INDUSTRIAL TEMP RANGE
The parallel interface is compatible with a wide variety
of microcontrollers. The DAC7621 accepts a 12-bit
parallel word, has a double-buffered input logic struc-
ture and provides data readback. In addition, two
control pins provide a chip select (CS) function and
asynchronous clear (CLR) input. The CLR input can
be used to ensure that the DAC7621 output is 0V on
power-up or as required by the application.
● ASYNCHRONOUS RESET TO 0V
APPLICATIONS
● PROCESS CONTROL
● DATA ACQUISITION SYSTEMS
● CLOSED-LOOP SERVO-CONTROL
● PC PERIPHERALS
The DAC7621 is available in a 20-lead SSOP package
and is fully specified over the industrial temperature
range of –40°C to +85°C.
● PORTABLE INSTRUMENTATION
VDD
Ref
12-Bit DAC
12
VOUT
CLR
DAC Register
12
LOADDAC
Input Register
12
CS
I/O Buffer
R/W
DAC7621
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
DGND
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
• Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
•
© 1998 Burr-Brown Corporation
PDS-1502B
Printed in U.S.A. March, 1999
SBAS107
SPECIFICATIONS
ELECTRICAL
At TA = –40°C to +85°C, and VDD = +5V, unless otherwise noted.
DAC7621E
TYP
DAC7621EB
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
12
✻
Bits
ACCURACY
Relative Accuracy(1)
Differential Nonlinearity
Zero-Scale Error
Full Scale Voltage
–2
–1
–1
±1/2
±1/2
+1
+2
+1
+3
–1
–1
✻
±1/4
±1/4
✻
+1
+1
✻
LSB
LSB
LSB
V
Guaranteed Monotonic
Code 000H
Code FFFH
4.079
4.095
4.111
4.087
4.095
4.103
ANALOG OUTPUT
Output Current
Load Regulation
Capacitive Load
Short-Circuit Current
Short-Circuit Duration
Code 800H
RLOAD ≥ 402Ω, Code 800H
No Oscillation
±5
±7
1
500
±20
Indefinite
✻
✻
✻
✻
✻
✻
mA
LSB
pF
3
✻
mA
GND or VDD
DIGITAL INPUT
Data Format
Data Coding
Logic Family
Logic Levels
VIH
VIL
IIH
IIL
Parallel
Straight Binary
CMOS
✻
✻
✻
0.7 • VDD
✻
V
V
µA
µA
0.3 • VDD
±10
✻
✻
✻
±10
DYNAMIC PERFORMANCE
Settling Time(2) (tS)
DAC Glitch
To ±1 LSB of Final Value
7
5
2
✻
✻
✻
µs
nV-s
nV-s
Digital Feedthrough
POWER SUPPLY
VDD
IDD
Power Dissipation
Power Supply Sensitivity
+4.75
–40
+5.0
0.5
2.5
+5.25
1
5
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
mA
mW
%/%
VIH = 5V, VIL = 0V, No Load, at Code 000H
VIH = 5V, VIL = 0V, No Load
∆VDD = ±5%
0.001
0.004
TEMPERATURE RANGE
Specified Performance
+85
✻
°C
✻ Same specification as for DAC7621E.
NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where
the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
DAC7621
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
Top View
SSOP
1
CLR
Reset. Resets the DAC register to zero. Active
LOW. Asynchronous input.
2
VDD
VOUT
AGND
DGND
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R/W
CS
Postive Power Supply
DAC Output Voltage
Analog Ground
Digital Ground
Data Bit 11, MSB
Data Bit 10
3
4
1
20 LOADDAC
19 CS
CLR
5
2
VDD
6
3
18 R/W
7
VOUT
8
Data Bit 9
4
17 DB0 (LSB)
16 DB1
AGND
9
Data Bit 8
5
DGND
10
11
12
13
14
15
16
17
18
19
20
Data Bit 7
DAC7621E
6
15 DB2
Data Bit 6
DB11 (MSB)
Data Bit 5
7
14 DB3
DB10
Data Bit 4
8
13 DB4
DB9
Data Bit 3
9
12 DB5
Data Bit 2
DB8
Data Bit 1
10
11 DB6
DB7
Data Bit 0, LSB
Read and Write Control
Chip Select. Active LOW.
LOADDAC Loads the internal DAC register. The DAC register
is a transparent latch and is transparent when
LOADDAC is LOW (regardless of the state of CS or
CLK).
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
VDD to GND .......................................................................... –0.3V to 6V
Digital Inputs to GND ..............................................–0.3V to VDD + 0.3V
VOUT to GND ...........................................................–0.3V to VDD + 0.3V
Power Dissipation ........................................................................ 325mW
Thermal Resistance, θJA ........................................................... 150°C/W
Maximum Junction Temperature .................................................. +150°C
Operating Temperature Range ...................................... –40°C to +85°C
Storage Temperature Range ....................................... –65°C to +150°C
Lead Temperature (soldering, 10s).............................................. +300°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
DRAWING
NUMBER(1)
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DAC7621E
±2
"
±1
"
±1
"
±1
"
–40°C to +85°C
20-Lead SSOP
334
"
334
"
DAC7621E
DAC7621E/1K
DAC7621EB
Rails
Tape and Reel
Rails
"
"
"
DAC7621EB
–40°C to +85°C
20-Lead SSOP
"
"
"
DAC7621EB/1K
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7621E/1K” will get a single
1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
3
DAC7621
TIMING DIAGRAMS
tWCS
CS
tWS
tWH
R/W
tRCS
CS
tRDS
R/W
tLWD
tRDH
LOADDAC
Data In
tDH
tDS
tDZ
Data Out
Data Valid
tCSD
Data Output Timing
Digital Input Timing
TIMING SPECIFICATIONS
LOGIC TRUTH TABLE
TA = –40°C to +85°C
INPUT
DAC
R/W
CS
LOADDAC
REGISTER
REGISTER
MODE
SYMBOL
tRCS
DESCRIPTION
CS LOW for Read
MIN TYP MAX UNITS
L
L
L
L
L
H
H
L
Write
Write
Read
Hold
Hold
Write
Hold
Write
Write Input
Read Input
Update
200
10
0
ns
ns
ns
ns
tRDS
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
H
X
X
L
Hold
tRDH
H
H
Update
Hold
tDZ
CS HIGH to Data Bus
in High Impedance
100
H
Hold
X = Don’t Care.
tCSD
tWCS
tWS
CS LOW to Data Bus Valid
CS LOW for Write
100 160
ns
50
0
R/W LOW to CS LOW
R/W LOW after CS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LOADDAC LOW
ns
ns
ns
ns
ns
tWH
tDS
5
0
tDH
5
tLWD
50
®
4
DAC7621
TYPICAL PERFORMANCE CURVES
At TA = +25°, and VDD = 5V, unless otherwise specified.
PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT
OUTPUT SWING vs LOAD
4.5
1k
100
10
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
85°C (mV)
25°C
1
–40°C
0.1
Data = 000H
0.01
0.001
0.01
0.1
1
10
100
10
100
1k
10k
100k
Current (mA)
Load Resistance (Ω)
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
BROADBAND NOISE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5
4.5
4.0
3.5
3.0
2.5 2.0
1.5
1.0
0.5
Time (2µs/div)
Logic Voltage (V)
POWER SUPPLY REJECTION vs FREQUENCY
Data = FFFH
MINIMUM SUPPLY VOLTAGE vs LOAD
70
60
50
40
30
20
10
0
5.0
4.8
4.6
4.4
4.2
4.0
∆VFS = 1 LSB
Data = FFFH
VDD = 5V
±200mV AC
10
100
1k
10k
100k
1M
0.010
0.100
1.000
10.000
Frequency (Hz)
Output Load Current (mA)
®
5
DAC7621
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
SUPPLY CURRENT vs TEMPERATURE
VLOGIC = 3.5V
Data = FFFH
No Load
SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
80
60
Positive
Current
Limit
40
Data = 800H
Output tied to ISOURCE
20
0
VDD = 5.0V
VDD = 5.25V
–20
–40
–60
–80
Negative
Current
Limit
VDD = 4.75V
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (V)
Temperature (°C)
MID-SCALE GLITCH PERFORMANCE
LOADDAC
MID-SCALE GLITCH PERFORMANCE
LOADDAC
VOUT
7FFH to 800H
800H to 7FFH
Time (500ns/div)
Time (500ns/div)
RISE TIME DETAIL
LARGE-SIGNAL SETTLING TIME
CL = 110pF
LD
RL = No Load
VOUT
VOUT
LD
Time (10µs/div)
Time (20µs/div)
®
6
DAC7621
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
OUTPUT VOLTAGE NOISE vs FREQUENCY
Data = FFFH
FALL TIME DETAIL
10.000
1.000
0.100
LD
0.010
Time (10µs/div)
10
100
1k
10k
100k
Frequency (Hz)
LONG-TERM DRIFT ACCELERATED BY BURN-IN
144 Units
TOTAL UNADJUSTED ERROR HISTOGRAM
60
50
40
30
20
10
0
8
6
T.U.E = ΣINL = ZS + FS
Sample Size = 300 Units
T
A = +25°C
4
2
0
min
–2
–4
–6
–8
avg
max
0
200
400
600
800
1000
1200
–12
–8
–4
0
4
8
12
Hours of Operation at +150°C
FULL-SCALE VOLTAGE vs TEMPERATURE
ZERO-SCALE VOLTAGE vs TEMPERATURE
4.115
4.110
4.105
4.100
4.095
4.090
4.085
4.080
4.075
3
2
No Load
Avg + 3σ
Sample Size = 300
1
Avg
0
Avg – 3σ
–1
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
®
7
DAC7621
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE
LINEARITY ERROR vs DIGITAL CODE
(at +25°C)
(at +25°C)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0
512 1024 1536 2048 2560 3072 3584 4096
Code
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
Code
DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE
LINEARITY ERROR vs DIGITAL CODE
(at +85°C)
(at +85°C)
1
0.5
1
0.5
0
0
–0.5
–1.0
–0.5
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
Code
512 1024 1536 2048 2560 3072 3584 4096
Code
LINEARITY ERROR vs DIGITAL CODE
DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE
(at –40°C)
(at –40°C)
1
0.5
1
0.5
0
0
–0.5
–1.0
–0.5
–1.0
512 1024 1536 2048 2560 3072 3584 4096
Code
0
512 1024 1536 2048 2560 3072 3584 4096
Code
®
8
DAC7621
The digital data into the DAC7621 is double-buffered. This
means that new data can be entered into the DAC without
disturbing the old data and the analog output of the con-
verter. At some point after the data has been entered into the
serial shift register, this data can be transferred into the DAC
register. This transfer is accomplished with a HIGH to LOW
transition of the LOADDAC pin. However, the LOADDAC
pin makes the DAC register transparent. If new data be-
comes available on the bus register while LOADDAC is
LOW, the DAC output voltage will change as the data
changes. To prevent this, CS must be returned HIGH prior
to changing data on the bus.
OPERATION
The DAC7621 is a 12-bit digital-to-analog converter (DAC)
complete with an input shift register, DAC register, laser-
trimmed 12-bit DAC, on-board reference, and a rail-to-rail
output amplifier. Figure 1 shows the basic operation of the
DAC7621.
INTERFACE
Figure 1 shows the basic connection between a
microcontroller and the DAC7621. The interface consists of
a Read/Write (R/W), data, and a load DAC signal
(LOADDAC). In addition, a chip select (CS) input is avail-
able to enable the DAC7621 when there are multiple de-
vices. The data format is Straight Binary. An asynchronous
clear input (CLR) is provided to simplify start-up or periodic
resets. Table I shows the relationship between input code
and output voltage.
At any time, the contents of the DAC register can be set to
000H (analog output equals 0V) by taking the CLR input
LOW. The DAC register will remain at this value until CLR
is returned HIGH and LOADDAC is taken LOW to allow
the contents of the input register to be transferred to the
DAC register. If LOADDAC is LOW when CLR is taken
LOW, the DAC register will be set to 000H and the analog
output driven to 0V. When CLR is returned HIGH, the DAC
register and the analog output will respond accordingly.
DAC7621 Full-Scale Range = 4.095V
Least Significant Bit = 1mV
DIGITAL INPUT CODE
STRAIGHT OFFSET BINARY
ANALOG OUTPUT
(V)
DESCRIPTION
DIGITAL-TO-ANALOG CONVERTER
FFFH
801H
800H
7FFH
000H
+4.095
+2.049
+2.048
+2.047
0
Full Scale
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
Zero Scale
The internal DAC section is a 12-bit voltage output
device that swings between ground and the internal ref-
erence voltage. The DAC is realized by a laser-trimmed
R-2R ladder network which is switched by N-channel
MOSFETs. The DAC output is internally connected to
the rail-to-rail output operational amplifier.
TABLE I. Digital Input Code and Corresponding Ideal
Analog Output.
DAC7621E
Clear
1
2
LOADDAC 20
CS 19
Load DAC
Chip Select
Read/Write
CLR
+5V
VDD
+
10µF
0.1µF
0V to
+4.095V
3
R/W 18
DB0 17
DB1 16
DB2 15
DB3 14
DB4 13
DB5 12
DB6 11
VOUT
AGND
DGND
DB11
DB10
DB9
4
5
6
Data Bus
7
8
Data Bus
9
DB8
10
DB7
FIGURE 1. Basic Operation of the DAC7621.
®
9
DAC7621
R-2R DAC
2R
Output Amplifier
R
Buffer
2R
2R
R2
2.435V
Bandgap
Reference
R
R
R1
2R
2R
FIGURE 2. Simplified Schematic of Analog Portion.
OUTPUT AMPLIFIER
POWER SUPPLY
A precision, low-power amplifier buffers the output of the
DAC section and provides additional gain to achieve a 0V
to 4.095V range. The amplifier has low offset voltage, low
noise, and a set gain of 1.682V/V (4.095/2.435). See Figure
2 for an equivalent circuit schematic of the analog portion
of the DAC7621.
A BiCMOS process and careful design of the bipolar and
CMOS sections of the DAC7621 result in a very low power
device. Bipolar transistors are used where tight matching
and low noise are needed to achieve analog accuracy, and
CMOS transistors are used for logic, switching functions
and for other low power stages.
The output amplifier has a 7µs typical settling time to ±1
LSB of the final value. Note that there are differences in the
settling time for negative-going signals versus positive-
going signals.
If power consumption is critical, it is important to keep the
logic levels on the digital inputs (R/W, CLK, CS, LOADDAC,
CLR) as close as possible to either VDD or ground. This will
keep the CMOS inputs (see “Supply Current vs Logic Input
Voltages” in the Typical Performance Curves) from shunt-
ing current between VDD and ground.
The rail-to-rail output stage of the amplifier provides the
full-scale range of 0V to 4.095V while operating on a
supply voltage as low as 4.75V. In addition to its ability to
drive resistive loads, the amplifier will remain stable while
driving capacitive loads of up to 500pF. See Figure 3 for an
equivalent circuit schematic of the amplifier’s output driver
and the Typical Performance Curves section for more infor-
mation regarding settling time, load driving capability, and
output noise.
The DAC7621 power supply should be bypassed as shown
in Figure 1. The bypass capacitors should be placed as close
to the device as possible, with the 0.1µF capacitor taking
priority in this regard. The “Power Supply Rejection vs
Frequency” graph in the Typical Performance Curves sec-
tion shows the PSRR performance of the DAC7621. This
should be taken into account when using switching power
supplies or DC/DC converters.
In addition to offering guaranteed performance with VDD in
the 4.75V to 5.25V range, the DAC7621 will operate with
reduced performance down to 4.5V. Operation between
4.5V and 4.75V will result in longer settling time, reduced
performance, and current sourcing capability. Consult the
“VDD vs Load Current” graph in the Typical Performance
Curves section for more information.
VDD
P-Channel
VOUT
N-Channel
AGND
FIGURE 3. Simplified Driver Section of Output Amplifier.
®
10
DAC7621
signals and should cross them at right angles. A solid analog
ground plane around the D/A package, as well as under it in
the vicinity of the analog and power supply pins, will isolate
the D/A from switching currents. It is recommended that
DGND and AGND be connected directly to the ground
planes under the package.
APPLICATIONS
POWER AND GROUNDING
The DAC7621 can be used in a wide variety of situations—
from low power, battery operated systems to large-scale
industrial process control systems. In addition, some appli-
cations require better performance than others, or are par-
ticularly sensitive to one or two specific parameters. This
diversity makes it difficult to define definite rules to follow
concerning the power supply, bypassing, and grounding.
The following discussion must be considered in relation to
the desired performance and needs of the particular system.
If several DAC7621s are used, or if sharing supplies with
other components, connecting the AGND and DGND lines
together at the power supplies once, rather than at each chip,
may produce better results.
The power applied to VDD should be well regulated and low-
noise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
A precision analog component requires careful layout, ad-
equate bypassing, and a clean, well-regulated power supply.
As the DAC7621 is a single-supply, +5V component, it will
often be used in conjunction with digital logic,
microcontrollers, microprocessors, and digital signal proces-
sors. The more digital logic present in the design and the
higher the switching speed, the more difficult it will be to
achieve good performance.
voltage through various paths between VDD and VOUT
.
As with the GND connection, VDD should be connected to
a +5V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 10µF and 0.1µF capaci-
tors shown in Figure 4 are strongly recommended and
should be installed as close to VDD and ground as possible.
In some situations, additional bypassing may be required
such as a 100µF electrolytic capacitor or even a “Pi” filter
made up of inductors and capacitors—all designed to essen-
tially lowpass filter the +5V supply, removing the high
frequency noise (see Figure 4).
The DAC7621 has separate analog ground and digital ground
pins. The current through DGND is mostly switching tran-
sients and are up to 4mA peak in amplitude. The current
through AGND is typically 0.5mA.
For best performance, separate analog and digital ground
planes with a single interconnection point to minimize
ground loops. The analog pins are located adjacent to each
other to help isolate analog from digital signals. Analog
signals should be routed as far as possible from digital
Digital Circuits
+5V
Power
Supply
+5V
+5V
GND
DAC7621
VDD
GND
+
+
100µF
10µF
0.1µF
AGND
DGND
Optional
Other
Analog
Components
FIGURE 4. Suggested Power and Ground Connections for a DAC7621 Sharing a +5V Supply with a Digital System with a
Single Ground Plane.
®
11
DAC7621
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC7621E
DAC7621E/1K
DAC7621EB
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
DB
DB
DB
20
20
20
70
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
DAC7621E
Samples
Samples
Samples
1000 RoHS & Green
Call TI
Call TI
DAC7621E
70
70
RoHS & Green
RoHS & Green
DAC7621E
B
DAC7621EBG4
ACTIVE
SSOP
DB
20
Call TI
Level-3-260C-168 HR
-40 to 85
DAC7621E
B
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC7621E/1K
SSOP
DB
20
1000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DB 20
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
DAC7621E/1K
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DAC7621E
DAC7621EB
DAC7621EBG4
DB
DB
DB
SSOP
SSOP
SSOP
20
20
20
70
70
70
530
530
530
10.2
10.2
10.2
4000
4000
4000
NA
NA
NA
Pack Materials-Page 3
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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