DAC7664YBTG4 [TI]
PARALLEL, WORD INPUT LOADING, 12us SETTLING TIME, 16-BIT DAC, PQFP64, GREEN, PLASTIC, LQFP-64;
| 型号： | DAC7664YBTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PARALLEL, WORD INPUT LOADING, 12us SETTLING TIME, 16-BIT DAC, PQFP64, GREEN, PLASTIC, LQFP-64 输入元件 转换器 |
| 文件： | 总32页 (文件大小：1040K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBAS271 − MARCH 2004
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢊ ꢋꢌꢍ ꢅ ꢉꢎꢏ ꢐ ꢈꢅ ꢑꢈꢅ
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FEATURES
DESCRIPTION
D
D
D
D
D
Low Glitch: 1nV-s (typ)
The DAC7664 is
a
16-bit, quad voltage output
digital-to-analog converter (DAC) with 16-bit monotonic
performance over the specified temperature range. It
accepts 16-bit parallel input data, has double-buffered
DAC input logic (allowing simultaneous update of all
DACs), and provides a readback mode of the internal input
registers. Programmable asynchronous reset clears all
registers to a mid-scale code of 8000h or to a zero-scale
of 0000h. The DAC7664 can operate from a single +5V
supply or from +5V and −5V supplies.
Low Power: 18mW
Unipolar or Bipolar Operation
Settling Time: 12µs to 0.003%
16-Bit Linearity and Monotonicity:
–40°C to +85°C
Programmable Reset to Mid-Scale or
Zero-Scale
D
D
D
D
D
D
Data Readback
Low power and small size per DAC make the DAC7664
ideal for automatic test equipment, DAC-per-pin
programmers, data acquisition systems, and closed-loop
servo control. The DAC7664 is available in an LQFP-64
package and is specified for operation over the −40°C to
+85°C temperature range.
Double-Buffered Data Inputs
Internal Bandgap Voltage Reference
Power-On Reset
3V to 5V Logic Interface
VD
VS
VC
D
S
C
APPLICATIONS
D
D
D
D
D
Process Control
V
REFH A and B
Closed-Loop Servo Control
Motor Control
DAC7664
V
REFL A and B
Bandgap
Voltage Reference
Data Acquisition Systems
DAC-per-Pin Programmers
V
O UTA Sense 2
O UTA Sense 1
O UTA
Input
DAC
V
DAC A
DAC B
DAC C
Data
Register A
Register A
V
DB0−DB15
Latch
VREF
VREF
VREF
VREF
OFSR2A
OFSR1A
V
O UTB Sense 2
O UTB Sense 1
O UTB
Input
Register B
DAC
V
Register B
V
OFSR2B
OFSR1B
V
O UTC Sense 2
O UTC Sense 1
O UTC
Input
Register C
DAC
V
A0
A1
Register C
V
OFSR2C
OFSR1C
CS
Control
Logic
RST
RSTSEL
LDAC
R/W
V
O UTD Sense 2
O UTD Sense 1
O UTD
Input
Register D
DAC
V
DAC D
Register D
V
OFSR2D
OFSR1D
VREFL C
and D
V
REFH C
and D
AGND
DGND
This device has ESD-CDM sensitivity and special handling precautions must be taken.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢛꢜ ꢐ ꢒꢝ ꢖ ꢞꢟ ꢐꢠ ꢒ ꢓꢞꢓ ꢄꢔ ꢡꢌ ꢘ ꢢꢉ ꢅꢄꢌꢔ ꢄꢣ ꢤꢈ ꢘ ꢘ ꢏꢔꢅ ꢉꢣ ꢌꢡ ꢑꢈꢥ ꢍꢄꢤ ꢉꢅꢄ ꢌꢔ ꢊꢉ ꢅꢏꢦ ꢛꢘ ꢌꢊꢈ ꢤꢅꢣ
ꢤ ꢌꢔ ꢡꢌꢘ ꢢ ꢅꢌ ꢣ ꢑꢏ ꢤ ꢄ ꢡꢄ ꢤ ꢉ ꢅꢄ ꢌꢔꢣ ꢑ ꢏꢘ ꢅꢧꢏ ꢅꢏ ꢘ ꢢꢣ ꢌꢡ ꢞꢏꢨ ꢉꢣ ꢟꢔꢣ ꢅꢘ ꢈꢢ ꢏꢔꢅ ꢣ ꢣꢅ ꢉꢔꢊ ꢉꢘ ꢊ ꢩ ꢉꢘ ꢘ ꢉ ꢔꢅꢪꢦ
ꢛꢘ ꢌ ꢊꢈꢤ ꢅ ꢄꢌ ꢔ ꢑꢘ ꢌ ꢤ ꢏ ꢣ ꢣ ꢄꢔ ꢎ ꢊꢌ ꢏ ꢣ ꢔꢌꢅ ꢔꢏ ꢤꢏ ꢣꢣ ꢉꢘ ꢄꢍ ꢪ ꢄꢔꢤ ꢍꢈꢊ ꢏ ꢅꢏ ꢣꢅꢄ ꢔꢎ ꢌꢡ ꢉꢍ ꢍ ꢑꢉ ꢘ ꢉꢢ ꢏꢅꢏ ꢘ ꢣꢦ
Copyright 2004, Texas Instruments Incorporated
www.ti.com
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www.ti.com
SBAS271 − MARCH 2004
(1)
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE−LEAD
DAC7664YT
DAC7664YR
DAC7664YBT
DAC7664YBR
DAC7664YCT
DAC7664YCR
Tape and Reel, 250
Tape and Reel, 1500
Tape and Reel, 250
Tape and Reel, 1500
Tape and Reel, 250
Tape and Reel, 1500
DAC7664Y
DAC7664YB
DAC7664YC
LQFP−64
LQFP−64
LQFP−64
PM
PM
PM
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
DAC7664Y
DAC7664YB
DAC7664YC
(1)
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
proper handling and installation procedures can cause damage.
DAC7664
−0.3 to 11
−0.3 to 5.5
UNIT
IOV , V
DD CC
and V
and V
to V
SS
V
V
V
V
V
DD
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
IOV , V
DD CC
to GND
DD
Digital Input Voltage to GND
Digital Output Voltage to GND
ESD-CDM
−0.3 to V
+ 0.3
DD
−0.3 to V
+ 0.3
DD
200
+150
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10s)
°C
°C
°C
°C
−40 to +85
−65 to +125
+300
(1)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional
operationof the device at these or any other conditions beyond
those specified is not implied.
2
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SBAS271 − MARCH 2004
ELECTRICAL CHARACTERISTICS: V
= 0V
SS
All specifications at T = T
A
to T
, IOV
DD
= V
DD
= V
CC
= +5V, and V
= 0V, unless otherwise noted.
MIN
MAX
SS
DAC7664Y
TYP
DAC7664YB
DAC7664YC
MIN TYP MAX
PARAMETER
Accuracy
TEST CONDITIONS
MIN
MAX
MIN
TYP MAX
UNIT
Linearity error
3
4
2
4
3
2
2
1
3
2
[
[
[
LSB
LSB
Linearity match
Differential linearity error
−1
16
+2
LSB
Monotonicity, T
to T
MAX
14
15
Bit
MIN
Unipolar zero error
1
5
5
10
20
15
7
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
mV
Unipolar zero error drift
Full-scale error
[
[
12.5
[
ppm/°C
mV
6
4
Full-scale error drift
Unipolar zero matching
Full-scale matching
7
[
ppm/°C
mV
Channel-to-channel matching
Channel-to-channel matching
3
2
5
4
10
100
2
8
mV
Power-supply rejection ratio (PSRR) At full-scale
10
[
[
ppm/V
Analog Output
Voltage output
R
= 10kΩ
0
2.5
[
[
[
[
[
[
[
[
V
L
Output current
−1.25
+1.25
mA
pF
Maximum load capacitance
Short-circuit current
Short-circuit duration
Dynamic Performance
Settling time
No oscillation
500
20
[
[
[
[
[
[
mA
GND or V
CC
Indefinite
To 0.003%, 2.5V output step
12
0.5
2
15
[
[
[
[
[
[
[
[
[
[
µs
LSB
Channel-to-channel crosstalk
Digital feedthrough
Output noise voltage
nV-s
f = 10kHz
130
nV/√Hz
7FFFh to 8000h or
8000h to 7FFFh
DAC glitch
1
5
[
[
[
[
nV-s
Digital Input
V
[
[
V
V
0.7 × IOV
IH
DD
V
[
[
[
[
[
[
0.3 × IOV
DD
IL
I
I
10
µA
µA
IH
10
IL
Digital Output
V
V
V
V
I
I
I
I
= −0.8mA, IOV
= 5V
3.6
2.4
4.5
0.3
2.6
0.3
[
[
[
[
[
[
[
[
[
[
[
[
V
V
V
V
OH
OL
OH
OL
OH
OL
OH
OL
DD
= 1.6mA, IOV
= 5V
0.4
0.4
[
[
[
[
DD
= −0.4mA, IOV
= 0.8mA, IOV
= 3V
DD
= 3V
DD
Power Supply
V
+4.75
+2.7
+4.75
0
+5.0
+5.0
+5.0
0
+5.25
+5.25
+5.25
0
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
V
V
DD
IOV
DD
CC
V
V
V
V
SS
CC
DD
I
I
3.5
50
5
mA
µA
µA
mW
I(IOV
)
50
DD
Power
18
25
[
[
Temperature Range
Specified performance
−40
+85
[
[
[
°C
[ specifications same as the grade to the left
3
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SBAS271 − MARCH 2004
ELECTRICAL CHARACTERISTICS: V
= −5V
SS
All specifications at T = T
A
to T
, IOV
DD
= V
DD
= V
CC
= +5V, and V = −5V, unless otherwise noted.
SS
MIN
MAX
DAC7664Y
TYP
DAC7664YB
DAC7664YC
PARAMETER
Accuracy
TEST CONDITIONS
MIN
MAX
MIN
TYP MAX MIN TYP MAX
UNIT
Linearity error
3
4
2
4
3
2
2
1
3
2
[
[
[
LSB
LSB
Linearity match
Differential linearity error
−1
16
+2
LSB
Monotonicity, T
to T
MAX
14
15
Bit
MIN
Bipolar zero error
1
5
5
10
20
15
7
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
mV
Bipolar zero error drift
Full-scale error
[
[
12.5
[
ppm/°C
mV
6
4
Full-scale error drift
Bipolar zero matching
Full-scale matching
7
[
ppm/°C
mV
Channel-to-channel matching
Channel-to-channel matching
3
2
5
4
10
100
2
8
mV
Power-supply rejection ratio (PSRR) At full-scale
10
[
[
ppm/V
Analog Output
Voltage output
R
= 10kΩ
−2.5
+2.5
[
[
[
[
[
[
[
[
V
L
Output current
−1.25
+1.25
mA
pF
Maximum load capacitance
Short-circuit current
Short-circuit duration
Dynamic Performance
Settling time
No oscillation
500
[
[
[
[
[
[
−15, +30
Indefinite
mA
GND or V
CC
or V
SS
To 0.003%, 5V output step
12
0.5
2
15
[
[
[
[
[
[
[
[
[
[
µs
LSB
Channel-to-channel crosstalk
Digital feedthrough
Output noise voltage
nV-s
f = 10kHz
200
nV/√Hz
7FFFh to 8000h or
8000h to 7FFFh
DAC glitch
2
7
[
[
[
[
nV-s
Digital Input
V
[
[
V
V
0.7 × IOV
IH
DD
V
[
[
[
[
[
[
0.3 × IOV
DD
IL
I
I
10
µA
µA
IH
10
IL
Digital Output
V
V
V
V
I
I
I
I
= −0.8mA, IOV
= 5V
3.6
2.4
4.5
0.3
2.6
0.3
[
[
[
[
[
[
[
[
[
[
[
[
V
V
V
V
OH
OL
OH
OL
OH
OL
OH
OL
DD
= 1.6mA, IOV
= 5V
0.4
0.4
[
[
[
[
DD
= −0.4mA, IOV
= 0.8mA, IOV
= 3V
DD
= 3V
DD
Power Supply
V
+4.75
+2.7
+5.0
+5.0
+5.0
−5.0
4
+5.25
+5.25
+5.25
−4.75
5.5
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
V
V
DD
IOV
DD
CC
V
V
+4.75
−5.25
V
V
SS
CC
DD
I
I
mA
µA
µA
mA
mW
50
I(IOV
)
50
DD
I
−3.5
−40
−2.0
30
[
[
[
[
SS
Power
45
[
[
Temperature Range
Specified performance
+85
[
°C
[ specifications same as the grade to the left
4
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SBAS271 − MARCH 2004
PIN ASSIGNMENTS
LQFP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Offset D Range 1 49
32 LDAC
50
51
52
31
30
29
Offset D Range 2
Offset C Range 2
Offset C Range 1
R/W
CS
DB0
V
V
OUTC Sense 2 53
28 DB1
54
55
56
27
26
OUTC Sense 1
OUTC
REF GND
DB2
DB3
V
25 DB4
24 DB5
23 DB6
DAC7664
REF GND 57
VOUT
B
58
59
60
61
62
22
21
20
19
V
OUTB Sense 1
DB7
DB8
DB9
DB10
VOUTB Sense 2
Offset B Range 1
Offset B Range 2
Offset A Range 2 63
64
18 DB11
17
Offset A Range 1
DB12
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
5
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SBAS271 − MARCH 2004
Terminal Functions
PIN
NAME
DESCRIPTION
PIN
NAME
DESCRIPTION
1
2
3
4
5
6
NC
NC
No Connection
No Connection
38
RSTSEL Reset select. Determines the action of RST.
If high, an RST command sets the DAC
registers to mid-scale (8000h). If low, an RST
command sets the DAC registers to zero
(0000h).
V
Analog –5V power supply or 0V single supply
Analog +5V power supply
SS
CC
V
V
V
A
DAC A output voltage
OUT
39
40
41
42
43
44
NC
NC
NC
NC
NC
No connection
No connection
No connection
No connection
No connection
A
Connect to V
A for unipolar mode
OUT
Sense 1
OUT
7
V
A
Connect to V
A for bipolar mode
OUT
OUT
Sense 2
AGND
DGND
8
Analog ground
Digital ground
V
D
Connect to V
D for bipolar mode
D for unipolar mode
OUT
OUT
9
Sense 2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
V
Digital +5V power supply
Interface power supply
Data bit 15 (MSB)
Data bit 14
DD
IOV
45
V
D
Connect to V
OUT
Sense 1
OUT
DD
DB15
DB14
DB13
NC
46
47
48
49
V
D
DAC D output
No connection
No connection
OUT
NC
Data bit 13
NC
No connection
No connection
Data bit 12
Offset D
Range 1
Connect to Offset D Range 2 for unipolar
mode
NC
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CS
50
51
52
53
54
Offset D
Range 2
Connect to Offset D Range 1 for unipolar
mode
Data bit 11
Offset C
Range 2
Connect to Offset C Range 1 for unipolar
mode
Data bit 10
Data bit 9
Offset C
Range 1
Connect to Offset C Range 2 for unipolar
mode
Data bit 8
Data bit 7
V
C
Connect to V C for bipolar mode
OUT
OUT
Sense 2
Data bit 6
Data bit 5
V
C
Connect to V C for unipolar mode
OUT
OUT
Sense 1
Data bit 4
Data bit 3
55
56
57
58
59
V C
OUT
DAC C output
Data bit 2
REF GND Reference ground
REF GND Reference ground
Data bit 1
Data bit 0
V
B
DAC B output
OUT
OUT
Chip select, active low
V
B
Connect to V
B for unipolar mode
B for bipolar mode
OUT
R/W
Enabled by CS; controls the data read and
data write.
Sense 1
60
61
62
63
64
V
B
Connect to V
OUT
OUT
32
LDAC
DAC register load control, rising edge
triggered.
Sense 2
Offset B
Range 1
Connect to Offset B Range 2 for unipolar
mode
33
34
35
NC
NC
A1
No connection
No connection
Offset B
Range 2
Connect to Offset B Range 1 for unipolar
mode
Enabled by CS; in combination with A0,
selects the individual DAC input registers.
Offset A
Range 2
Connect to Offset A Range 1 for unipolar
mode
36
37
A0
Enabled by CS; in combination with A1,
selects the individual DAC input registers.
Offset A
Range 1
Connect to Offset A Range 2 for unipolar
mode
RST
Reset, rising edge triggered. Depending on
the state of RSTSEL, the DAC registers are
set to either mid-scale or zero.
6
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= 0V (+25°C)
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V
SS
= 0V, representative unit, unless otherwise noted.
A
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
_
(DAC A, +25 C)
_
(DAC B, +25 C)
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
0.5
1.0
1.5
2.0
−
−
−
−
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
0.5
1.0
1.5
2.0
−
−
−
−
0.5
1.0
1.5
2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 1
Figure 2
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
_
_
(DAC D, +25 C)
(DAC C, +25 C)
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Figure 3
Figure 4
7
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= 0V (+85°C)
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V
SS
= 0V, representative unit, unless otherwise noted.
A
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
_
_
(DAC A, +85 C)
(DAC B, +85 C)
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 5
Figure 6
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
_
_
(DAC C, +85 C)
(DAC D, +85 C)
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
−
−
−
−
−
−
−
−
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 7
Figure 8
8
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= 0V (−40°C)
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V
SS
= 0V, representative unit, unless otherwise noted.
A
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
−
_
−
_
(DAC A, 40 C)
(DAC B, 40 C)
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
−
−
−
−
−
−
−
−
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 9
Figure 10
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
−
_
−
_
(DAC C, 40 C)
(DAC D, 40 C)
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 11
Figure 12
9
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= 0V
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V = 0V, representative unit, unless otherwise noted.
SS
A
SUPPLY CURRENT vs TEMPERATURE
SUPPLY CURRENT vs DIGITAL INPUT CODE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
All DACs at Midscale
No Load
All DACs
No Load
ICC
ICC
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
−
−
15
40
10
35
60
85
Digital Input Code
_
Temperature ( C)
Figure 13
Figure 14
ZERO−SCALE ERROR vs TEMPERATURE
(Code 0000h)
POSITIVE FULL−SCALE ERROR vs TEMPERATURE
10
8
10
(Code FFFFh)
8
6
4
2
0
2
4
6
8
6
DAC D
4
DAC B
DAC C
DAC B
DAC C
DAC A
2
0
−
−
−
−
−
−
−
−
2
4
6
8
DAC D
DAC A
−
−
10
10
−
−
−
−
15
40
15
10
35
60
85
40
10
35
60
85
_
Temperature ( C)
_
Temperature ( C)
Figure 15
Figure 16
BROADBAND NOISE
(Code = 8000h, BW = 10kHz)
OUTPUT NOISE VOLTAGE vs FREQUENCY
1000
100
10
Time (10ms/div)
10
100
1k
10k
100k
1M
Frequency (Hz)
Figure 17
Figure 18
10
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= 0V (continued)
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V
SS
= 0V, representative unit, unless otherwise noted.
A
SETTLING TIME
(0V to +2.5V)
SETTLING TIME
(+2.5V to 39mV)
Large Signal: 1.0V/div
µ
Small Signal: 100 V/div
Large Signal: 1.0V/div
µ
Small Signal: 100 V/div
µ
µ
Time (5 s/div)
Time (5 s/div)
Figure 19
Figure 20
MIDSCALE GLITCH PERFORMANCE
CODE 7FFFh to 8000h
MIDSCALE GLITCH PERFORMANCE
CODE 8000h to 7FFFh
Unfiltered DAC Output
Unfiltered DAC Output
DAC Output after
DAC Output After
2K, 470pF Low−Pass Filter
2K, 470pF Low−Pass Filter
µ
µ
Time (0.5 s/div)
Time (0.5 s/div)
Figure 21
Figure 22
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32750 to 32850
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32850 to 32750
Unfiltered DAC Output
DAC Output After
2K, 470pF Low−Pass Filter
DAC Output After
2K, 470pF Low−Pass Filter
100
Codes
Unfiltered DAC Output
µ
µ
Time (1.0 s/div)
Time (1.0 s/div)
Figure 23
Figure 24
11
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= 0V (continued)
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V
SS
= 0V, representative unit, unless otherwise noted.
A
IOVDD SUPPLY CURRENT
vs LOGIC INPUT LEVEL FOR DIGITAL INPUTS
VOUT vs RLOAD
0.8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Typical of One
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Digital Input
IOVDD = 5V
Source
Sink
10
0
1
2
3
4
5
0.01
0.1
1
100
Logic Input Level for Digital Inputs (V)
Ω
RLOAD (k
)
Figure 26
Figure 25
12
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= −5V (+25°C)
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V
SS
= −5V, representative unit, unless otherwise noted.
A
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
_
_
(DAC A, +25 C)
(DAC B, +25 C)
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 27
Figure 28
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
_
_
(DAC C, +25 C)
(DAC D, +25 C)
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
−
−
−
−
−
−
−
−
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 29
Figure 30
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= −5V (+85°C)
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V
SS
= −5V, representative unit, unless otherwise noted.
A
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
_
_
(DAC A, +85 C)
(DAC B, +85 C)
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 31
Figure 32
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
_
_
(DAC C, +85 C)
(DAC D, +85 C)
2.0
2.0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 33
Figure 34
14
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= −5V (−40°C)
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V
SS
= −5V, representative unit, unless otherwise noted.
A
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
−
_
−
_
(DAC A, 40 C)
(DAC B, 40 C)
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 35
Figure 36
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
−
_
−
_
(DAC C, 40 C)
(DAC D, 40 C)
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
−
−
−
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 37
Figure 38
15
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= −5V
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V = −5V, representative unit, unless otherwise noted.
SS
A
SUPPLY CURRENT vs TEMPERATURE
ICC
SUPPLY CURRENT vs DIGITAL INPUT CODE
ICC
5
4
3
2
1
0
5
4
3
2
1
0
1
2
3
4
5
−
1
2
3
4
5
−
−
−
−
−
ISS
ISS
−
−
−
−
All DACs
No Load
All DACs at Midscale
No Load
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
−
−
15
40
10
35
60
85
Digital Input Code
_
Temperature ( C)
Figure 39
Figure 40
BIPOLAR ZERO ERROR vs TEMPERATURE
(Code 8000h)
POSITIVE FULL− SCALE ERROR vs TEMPERATURE
10
8
10
8
(Code FFFFh)
6
6
DAC C
DAC B
4
4
DAC C
DAC D
DAC D
DAC B
2
2
0
0
−
−
−
−
−
−
−
−
2
4
6
8
2
4
6
8
DAC A
DAC A
−
−
10
10
−
−
−
−
15
40
15
10
35
60
85
40
10
35
60
85
_
_
Temperature ( C)
Temperature ( C)
Figure 41
Figure 42
NEGATIVE FULL−SCALE ERROR vs TEMPERATURE
(Code 0000h)
10
8
6
DAC B
4
2
DAC A
0
−
−
−
−
2
4
6
8
DAC C
DAC D
−
10
−
−
15
40
10
35
60
85
_
Temperature ( C)
Figure 43
16
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= −5V (continued)
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V = −5V, representative unit, unless otherwise noted.
SS
A
BROADBAND NOISE
(Code = 8000h, BW = 10kHz)
OUTPUT NOISE VOLTAGE vs FREQUENCY
1000
100
10
10
100
1k
10k
100k
1M
Time (10ms/div)
Frequency (Hz)
Figure 44
Figure 45
SETTLING TIME
SETTLING TIME
−
−
(+2.5V to 2.5V)
( 2.5V to +2.5V)
Large Signal: 1.0V/div
µ
Small Signal: 100 V/div
µ
Small Signal: 100 V/div
Large Signal: 1.0V/div
µ
µ
Time (5 s/div)
Time (5 s/div)
Figure 46
Figure 47
MIDSCALE GLITCH PERFORMANCE
CODE 7FFFh to 8000h
MIDSCALE GLITCH PERFORMANCE
CODE 8000h to 7FFFh
Unfiltered DAC Output
Unfiltered DAC Output
DAC Output after
DAC Output After
2K, 470pF Low−Pass Filter
2K, 470pF Low−Pass Filter
µ
µ
Time (0.5 s/div)
Time (0.5 s/div)
Figure 48
Figure 49
17
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SBAS271 − MARCH 2004
TYPICAL CHARACTERISTICS: V
= −5V (continued)
SS
All specifications at T = 25°C, IOV
DD
= V
DD
= V
CC
= +5V, V = −5V, representative unit, unless otherwise noted.
SS
A
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32750 to 32850
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32850 to 32750
Unfiltered DAC Output
DAC Output After
2K, 470pF Low−Pass Filter
DAC Output After
2K, 470pF Low−Pass Filter
100
Codes
Unfiltered DAC Output
µ
µ
Time (1.0 s/div)
Time (1.0 s/div)
Figure 50
Figure 51
VOUT vs RLOAD
5
4
3
2
1
0
Source
−
1
2
3
4
5
Sink
−
−
−
−
0.01
0.1
1
10
100
Ω
RLOAD (k
)
Figure 52
18
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SBAS271 − MARCH 2004
THEORY OF OPERATION
The DAC7664 is a quad voltage output 16-bit DAC. The
architecture is an R−2R ladder configuration with the three
most significant bits (MSBs) segmented, followed by an
operational amplifier that serves as a buffer. Each DAC
has its own R−2R ladder network, segmented MSBs, and
output op amp, as shown in Figure 53. The minimum
voltage output (zero-scale) and maximum voltage output
(full-scale) are set by the internal voltage references and
the resistors associated with the output operational
amplifier.
The digital input is a 16-bit parallel word and the DAC input
registers offer readback capability. The converters can be
powered from either a single +5V supply or a dual 5V
supply. The device offers a reset function that immediately
sets all DAC output voltages and DAC registers to
mid-scale (code 8000h) or to zero-scale, code 0000h. See
Figure 54 and Figure 55 for the basic operation of the
DAC7664.
VOUTS1
Ω
13K
Ω
13K
VOUTS2
Ω
100
R
VOUT
2R
2R
2R
2R
2R
2R
2R
2R
2R
OFSR2
Ω
Ω
13K
11K
12K
OFSR1
Ω
VREF
H
L
VREF
Figure 53. DAC7664 Architecture
19
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SBAS271 − MARCH 2004
0V to +2.5V
NC NC
NC NC NC NC NC NC
NC NC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
32
31
30
Offset D Range 1
LDAC
R/W
CS
Load DAC Registers
Read/Write
Offset D Range 2
Offset C Range 2
Chip Select
52 Offset C Range 1
(LSB) DB0 29
NC
53
54
55
28
27
26
V
V
V
OUTC Sense 2
OUTC Sense 1
OUTC
DB1
DB2
DB3
0V to +2.5V
DAC7664
56 Reference GND
DB4 25
Single Supply
NC = No Connection
57
58
59
24
23
Reference GND
DB5
DB6
DAC
Input
Data
V
V
OUTB
DB7 22
DB8 21
DB9 20
0V to +2.5V
OUTB Sense 1
NC 60 VOUTB Sense 2
61 Offset B Range 1
62
63
64
19
18
17
Offset B Range 2
Offset A Range 2
Offset A Range 1
DB10
DB11
DB12
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
NC NC
NC NC
NC
DAC
Input Data
0V to +2.5V
+5V
+3V to +5V
+
+
µ
1 F
µ
µ
µ
1 F
0.1 F
0.1 F
Figure 54. Basic Single-Supply Operation of the DAC7664
20
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SBAS271 − MARCH 2004
−
2.5V to +2.5V
+5V
NC NC
NC
NC NC NC NC NC
NC NC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
LDAC 32
R/W 31
Load DAC Registers
Read/Write
NC
NC
Offset D Range 1
Offset D Range 2
Offset C Range 2
NC 51
CS 30
Chip Select
NC 52 Offset C Range 1
53 VOUTC Sense 2
(LSB) DB0 29
DB1 28
NC 54 VOUTC Sense 1
DB2 27
−
−
55
V
OUTC
DB3 26
2.5V to +2.5V
2.5V to +2.5V
DAC7664
Dual Supply
NC = No Connection
56 Reference GND
57 Reference GND
DB4 25
DB5 24
DAC
Input
Data
58 VOUT
B
DB6 23
DB7
NC 59 VOUTB Sense 1
22
60
61
62
63
64
DB8 21
DB9 20
VOUTB Sense 2
NC
NC
NC
NC
Offset B Range 1
Offset B Range 2
Offset A Range 2
Offset A Range 1
DB10 19
DB11 18
DB12 17
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
NC NC
NC NC
NC
−
5V
DAC
Input Data
µ
1 F
µ
0.1 F
+
−
2.5V to +2.5V
+5V
+3V to +5V
+
+
µ
1 F
µ
0.1 F
µ
µ
1 F
0.1 F
Figure 55. Basic Dual-Supply Operation of the DAC7664
21
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SBAS271 − MARCH 2004
The DAC7664 offers
a
force and sense output
ANALOG OUTPUTS
configuration for the high open-loop gain output amplifier.
This feature allows the loop around the output amplifier to
be closed at the load (as shown in Figure 56), thus
ensuring an accurate output voltage.
When VSS = –5V (dual-supply operation), the output
amplifier can swing to within 2.25V of the supply rails over
a range of –40°C to +85°C. When VSS = 0V (single-supply
operation), and with RLOAD also connected to ground, the
output can swing to within 5mV of ground. Care must be
taken when measuring the zero-scale error when
VSS = 0V. Since the output voltage cannot swing below
ground, the output voltage may not change for the first few
digital input codes (0000h, 0001h, 0002h, etc.) if the output
amplifier has a negative offset.
DIGITAL INTERFACE
Table 1 shows the basic control logic for the DAC7664.
Note that each internal register is edge-triggered and not
level-triggered. When the LDAC signal is transitioned to
high, the digital word currently in the register is latched.
The first set of registers (the input registers) are triggered
via the A0, A1, R/W, and CS inputs. Only one of these
registers is transparent at any given time.
Due to the high accuracy of these DACs, system design
problems such as grounding and contact resistance are
very important. A 16-bit converter with a 2.5V full-scale
range has a 1LSB value of 38µV. With a load current of
1mA, series wiring and connector resistance of only 40mΩ
(RW2) will cause a voltage drop of 40µV, as shown in
Figure 56. To understand what this means in terms of
system layout, the resistivity of a typical 1-ounce
copper-clad printed circuit board is 1/2 mΩ per square. For
a 1mA load, a 0.01-inch-wide printed circuit conductor 0.6
inches long will result in a voltage drop of 30µV.
The double-buffered architecture is designed mainly so
each DAC input register can be written to at any time and
then all DAC voltages updated simultaneously by the
rising edge of LDAC. It also allows a DAC input register to
be written to at any point and the DAC voltages to be
synchronously changed via a trigger signal connected to
LDAC.
RW1
VOUTA Sense1
6
5
8
RW2
VOUTA
VOUT
DAC7664
AGND
RW1
V
OUTB Sense1 59
58
RW2
VOUT
V
OUTB
Figure 56. Analog Output Closed-Loop Configuration (1/2 DAC7664). R represents wiring resistances.
W
Table 1. DAC7664 Logic Truth Table
A1
L
L
A0
L
R/W
L
CS
L
RST
H
RSTSEL LDAC INPUT REGISTER DAC REGISTER
MODE
Write input
Write input
Write input
Write input
Read input
Read input
Read input
Read input
Update
DAC
A
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
↑
Write
Write
Hold
Hold
H
L
L
L
H
B
H
H
L
L
L
L
H
Write
Hold
C
H
L
L
L
H
Write
Hold
D
H
H
H
H
X
L
H
Read
Hold
A
H
L
L
H
Read
Hold
B
H
H
X
X
X
X
L
H
Read
Hold
C
H
X
X
X
X
L
H
Read
Hold
D
H
H
X
X
H
Hold
Write
All
All
All
All
X
H
H
X
X
Hold
Hold
Hold
X
↑
Reset to zero
Reset to zero
Reset to zero
X
↑
H
Reset to mid-scale Reset to mid-scale Reset to mid-scale
22
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SBAS271 − MARCH 2004
3V TO 5V LOGIC INTERFACE
DIGITAL TIMING
All of the digital input and output pins are compatible with
any logic supply voltage between 3V and 5V. Connect the
interface logic supply voltage to the IOVDD pin. Note that
the internal digital logic operates from 5V, so the VDD pin
must connect to a 5V supply.
Figure 57 and Table 2 provide detailed timing information
for the digital interface of the DAC7664.
DIGITAL INPUT CODING
The DAC7664 input data is in straight binary format. The
output voltage for single-supply operation is given by
Equation 1:
GLITCH SUPPRESSION CIRCUIT
Figure 21, Figure 22, Figure 48, and Figure 49 show the
typical DAC output when switching between codes 7FFFh
and 8000h. For R-2R ladder DACs, this is potentially the
worst-case glitch condition, since every switch in the DAC
changes state. To minimize the glitch energy at this and
other code pairs with possible high-glitch outputs, an
internal track-and-hold circuit is used to maintain the DAC
ouput voltage at a nearly constant level during the internal
switching interval. This track-and-hold circuit is activated
only when the transition is at, or close to, one of the code
pairs with the high-glitch possibility.
2.5 N
VOUT
+
65, 536
(1)
where N is the digital input code.
This equation does not include the effects of offset
(zero-scale) or gain (full-scale) errors.
The output for the dual supply operation is given by
Equation 2:
5 N
VOUT
+
* 2.5
It is advisable to avoid digital transitions within 1µs of the
rising edge of the LDAC signal. These signals can affect
the charge on the track-and-hold capacitor, thus
increasing the glitch energy.
65, 536
(2)
23
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SBAS271 − MARCH 2004
tWCS
tWS
CS
tWH
R/W
tRCS
tRDS
tAH
CS
tAS
tRDH
A0/A1
tLH
tLX
R/W
tLS
tLWD
tAH
tAS
0.003% of FSR
Error Band
LDAC
A0/A1
tDS
tDH
tDZ
Data In
tS
Data Out
Data Valid
tCSD
VOUT
Data Read Timing
Data Write Timing
tSS
0.003% of FSR
Error Band
tSH
RESET SEL
tRSH
tRSS
RST
+FS
VOUT, RESET SEL LOW
−
FS
+FS
MS
VOUT, RESET SEL HIGH
−
FS
DAC7664 Reset Timing
Figure 57. Digital Input and Output Timing
24
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SBAS271 − MARCH 2004
Table 2. Timing Specifications for Figure 57
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
t
CS low for read
150
ns
RCS
RDS
RDH
R/W high to CS low
R/W high after CS high
CS high to data bus in high impedance
CS low to data bus valid
CS low for write
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
t
t
100
150
DZ
CSD
t
100
t
40
0
WCS
t
R/W low to CS low
WS
t
R/W low after CS high
Address valid to CS low
Address valid after CS high
CS low to LDAC high
CS low after LDAC high
LDAC high
10
0
WH
t
AS
t
10
30
100
100
0
AH
t
LS
t
LH
t
LX
t
Data valid to CS low
DS
DH
t
Data valid after CS low
LDAC low
10
100
0
t
LWD
t
RSTSEL valid before RST high
RSTSEL valid after RST high
RSTSEL low before RST high
RSTSEL low after RST high
Settling time
SS
t
200
10
10
SH
t
RSS
t
RSH
t
S
12
25
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
DAC7664YBT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PM
64
64
64
64
64
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
DAC7664Y
B
DAC7664YBTG4
DAC7664YCT
DAC7664YCTG4
DAC7664YT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PM
PM
PM
PM
PM
250
250
250
250
250
Green (RoHS
& no Sb/Br)
DAC7664Y
B
Green (RoHS
& no Sb/Br)
DAC7664Y
C
Green (RoHS
& no Sb/Br)
DAC7664Y
C
Green (RoHS
& no Sb/Br)
DAC7664Y
DAC7664YTG4
Green (RoHS
& no Sb/Br)
DAC7664Y
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC7664YBT
DAC7664YCT
DAC7664YT
LQFP
LQFP
LQFP
PM
PM
PM
64
64
64
250
250
250
330.0
330.0
330.0
24.4
24.4
24.4
13.0
13.0
13.0
13.0
13.0
13.0
2.1
2.1
2.1
16.0
16.0
16.0
24.0
24.0
24.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC7664YBT
DAC7664YCT
DAC7664YT
LQFP
LQFP
LQFP
PM
PM
PM
64
64
64
250
250
250
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
0°–7°
11,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040152/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
1
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