DAC7678SPWR [TI]

12-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output, Two-Wire Interface Digital-to-Analog Converter with 2.5V Internal Reference; 12位，八通道，超低短时脉冲波形干扰，电压输出，两线接口数字 - 模拟转换器具有2.5V内部参考


型号：	DAC7678SPWR
厂家：	TEXAS INSTRUMENTS
描述：	12-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output, Two-Wire Interface Digital-to-Analog Converter with 2.5V Internal Reference 12位，八通道，超低短时脉冲波形干扰，电压输出，两线接口数字 - 模拟转换器具有2.5V内部参考转换器数模转换器脉冲光电二极管 PC
文件：	总52页 (文件大小：1793K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC7678

www.ti.com

SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

12-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output, Two-Wire Interface

Digital-to-Analog Converter with 2.5V Internal Reference

Check for Samples: DAC7678

FEATURES

APPLICATIONS

•

Portable Instrumentation

Closed-Loop Servo-Control

Process Control

Data Acquisition Systems

Programmable Attenuation

PC Peripherals

•

Relative Accuracy:

–

1 LSB INL

•

Glitch Energy: 0.15nV-s

Internal Reference:

–

2.5V Reference Voltage (disabled by

default)

–

±5mV Initial Accuracy (max)

DESCRIPTION

5ppm/°C Temperature Drift (typ)

25ppm/°C Temperature Drift (max)

20mA Sink/Source Capability

The DAC7678 is a low-power, voltage-output, octal

channel, 12-bit digital-to-analog converter (DAC). The

DAC7678 includes a 2.5V internal reference (disabled

by default), giving a full-scale output voltage range of

5V. The internal reference has an initial accuracy of

±5mV and can source up to 20mA at the

V_REFIN/V_REFOUTpin. The device is monotonic,

provides very good linearity, and minimizes undesired

code-to-code transient voltages (glitch).

•

Power-On Reset to Zero Scale or Midscale

–

Devices in the TSSOP Package Reset to

Zero Scale

–

Devices in the QFN Package Reset to Zero

Scale or Midscale

Ultra-Low Power Operation: 0.13mA/Channel

at 5V (without internal reference current)

The DAC7678 uses a versatile, 2-wire serial interface

that is I²C-compatible and operates at clock rates of

up to 3.4MHz. Multiple devices can share the same

bus.

•

Wide Power-Supply Range: +2.7V to +5.5V

2-Wire Serial Interface ( I²C™ compatible)

The DAC7678 incorporates a power-on-reset circuit

that ensures the DAC output powers up to either

zero-scale or mid-scale until a valid code is written to

the device. These devices contain a power-down

feature, accessed over the serial interface that

reduces the current consumption of the device to

typically 0.42mA at 5V. Power consumption (including

internal reference) is typically 3.56mW at 3V,

reducing to 0.68mW in power-down mode. The low

power consumption, internal reference, and small

footprint make this device ideal for portable,

battery-operated equipment. The DAC7678 is drop-in

On-Chip Output Buffer Amplifier with

Rail-to-Rail Operation

•

Temperature Range: –40°C to +125°C

AV_DD

V_REFIN/V_REFOUT

DAC7678

2.5V

Reference

V_OUT

DAC Register H

DAC Register G

DAC Register F

DAC Register E

DAC Register D

DAC Register C

DAC Register B

DAC Register A

Data Buffer H

Data Buffer G

Data Buffer F

Data Buffer E

Data Buffer D

Data Buffer C

Data Buffer B

Data Buffer A

12-Bit DAC

and

functionally

compatible

with

DAC5578,

DAC6578, and DAC7578. All devices are available in

a 4x4 QFN-24 package and a TSSOP-16 package.

RELATED DEVICES

8-BIT

10-BIT

12-BIT

Pin- and Function-Compatible

(w/internal reference)

—

DAC7678

SCL

SDA

Input Control Logic

Buffer Control

Pin- and Function-Compatible

DAC5578 DAC6578 DAC7578

Power-Down

Control Logic

ADDR0

ADDR1

LDAC

RSTSEL

CLR

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

I²C is a trademark of NXP Semiconductors.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC7678

SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION⁽¹⁾

MAXIMUM

RELATIVE

ACCURACY (LSB)

MAXIMUM

DIFFERENTIAL

NONLINEARITY (LSB)

MAXIMUM

REFERENCE DRIFT

(ppm/°C)

SPECIFIED

TEMPERATURE

RANGE

PACKAGE-

LEAD

PACKAGE

DESIGNATOR

PACKAGE

MARKING

PRODUCT

TSSOP-16

QFN-24

DAC7678

±1

±0.25

–40°C to +125°C

DAC7678

RGE

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

DAC7678

–0.3 to +6

UNIT

AV_DDto GND

Digital input voltage to GND

V_OUTto GND

–0.3 to +AV_DD+ 0.3

–40 to +125

V_REFIN/V_REFOUTto GND

Operating temperature range

Storage temperature range

Junction temperature range (T_Jmax)

Power dissipation

°C

–65 to +150

+150

(T_Jmax – T_A)/q_JA

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

THERMAL INFORMATION

DAC7678

THERMAL METRIC⁽¹⁾

UNITS

PW (16 PINS)

RGE (24 PINS)

q_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

111.9

33.3

52.4

33.7

16.9

7.4

q_JCtop

q_JB

°C/W

y_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

y_JB

51.2

n/a

7.1

q_JCbot

1.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

ELECTRICAL CHARACTERISTICS

At AV_DD= 2.7V to 5.5V, External Reference Used, and over –40°C to +125°C, unless otherwise noted.

DAC7678

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

STATIC PERFORMANCE⁽¹⁾

Resolution

Bits

LSB

Relative accuracy

Differential nonlinearity

Offset error

Measured by the line passing through codes 30 and 4050

12-bit monotonic

Extrapolated from two-point line⁽²⁾, unloaded

±0.3

±0.1

0.5

±1

±0.25

±4

Offset error drift

Full-scale error

mV/°C

DAC register loaded with all '1's

±0.03

±0.2 % of FSR

Full-scale error drift

Zero-code error

Zero-code error drift

Gain error

mV/°C

DAC register loaded with all '0's

mV/°C

Extrapolated from two-point line⁽²⁾, unloaded

±0.01

±0.15 % of FSR

ppm of

FSR/°C

Gain temperature coefficient

±1

OUTPUT CHARACTERISTICS⁽³⁾

Output voltage range

AV_DD

DACs unloaded, 1/4 scale to 3/4 scale

Output voltage settling time

Slew rate

R_L= 1MΩ, C_L= 470 pF

0.75

470

1000

0.15

1.5

V/ms

R_L= ∞

Capacitive load stability

R_L= 2kΩ

Code change glitch impulse

Digital feedthrough

1LSB change around major carry

SCL toggling

nV-s

LSB

Ω

Power-on glitch

R_L= ∞

Channel-to-channel dc crosstalk

DC output impedance

Full-scale swing on adjacent channel

At midscale input

0.1

4.5

Short-circuit current

DAC outputs shorted to GND

Coming out of power-down mode, AV_DD= 5V

Power-up time (including settling time)

AC PERFORMANCE⁽³⁾

DAC output noise density

T_A= +25°C, at zero-code input, f_OUT= 1kHz

nV/√Hz

mV_PP

T_A= +25°C, at midscale input, 0.1Hz to 10Hz (external

reference used)

DAC output noise

(1) Linearity calculated using a reduced code range; output unloaded.

(2) 12-bit: 30 and 4050

(3) Specified by design or characterization; not production tested.

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ELECTRICAL CHARACTERISTICS (continued)

At AV_DD= 2.7V to 5.5V, External Reference Used, and over –40°C to +125°C, unless otherwise noted.

DAC7678

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

INTERNAL REFERENCE

Output voltage

T_A= +25°C

2.495

–5

2.5

±0.1

2.505

Initial accuracy

Output voltage temperature drift⁽⁴⁾

ppm/°C

mV_PP

Output voltage noise

T_A= +25°C, f = 0.1Hz to 10Hz

T_A= +25°C, f = 1kHz, C_L= 0mF

T_A= +25°C, f = 1MHz, C_L= 0mF

Sourcing, T_A= +25°C

250

Output voltage noise density

(high-frequency noise)

nV/√Hz

500

200

±20

mV/mA

Load regulation⁽⁵⁾

Sinking, T_A= +25°C

Output current load capability⁽⁴⁾

Line regulation

Long-term stability/drift (aging)⁽⁵⁾

T_A= +25°C

mV/V

ppm

T_A= +25°C, time = 0 to 2160 hours

First cycle

100

200

Thermal hysteresis⁽⁵⁾

Additional cycles

AV_DD= 5.5V

420

400

Internal reference current consumption

External reference current

AV_DD= 3.6V

External V_REF= 2.5V (when internal reference is disabled), all

eight channels active

V_REFIN/V_REFOUTpin reference input range

Reference input impedance

LOGIC INPUTS⁽⁴⁾

AV_DD

Reference disabled

±1

kΩ

Input current

V_IN

Logic input LOW voltage

Logic input HIGH voltage

2.7V ≤ AV_DD≤ 5.5V

GND–0.3

0.7×AV_DD

0.3×AV_DD

AV_DD+0.3

V_INH

Pin capacitance

1.5

POWER REQUIREMENTS

AV_DD

2.7

5.5

1.4

1.3

2.2

AV_DD= 3.6V to 5.5V, V_INH = AV_DDand V_INL = GND

AV_DD= 2.7V to 3.6V, V_INH = AV_DDand V_INL = GND

AV_DD= 3.6V to 5.5V, V_INH = AV_DDand V_INL = GND

AV_DD= 2.7V to 3.6V, V_INH = AV_DDand V_INL = GND

AV_DD= 3.6V to 5.5V, V_INH = AV_DDand V_INL = GND

AV_DD= 2.7V to 3.6V, V_INH = AV_DDand V_INL = GND

AV_DD= 3.6V to 5.5V, V_INH = AV_DDand V_INL = GND

AV_DD= 2.7V to 3.6V, V_INH = AV_DDand V_INL = GND

AV_DD= 3.6V to 5.5V, V_INH = AV_DDand V_INL = GND

AV_DD= 2.7V to 3.6V, V_INH = AV_DDand V_INL = GND

AV_DD= 3.6V to 5.5V, V_INH = AV_DDand V_INL = GND

AV_DD= 2.7V to 3.6V, V_INH = AV_DDand V_INL = GND

1.02

0.86

1.49

1.32

0.42

0.25

3.67

2.32

5.36

3.56

1.51

0.68

Normal mode, internal

reference switched off

Normal mode, internal

reference switched on

(6)

I_DD

All power-down modes

4.7

7.7

4.68

12.1

7.2

Normal mode, internal

reference switched off

Power

Normal mode, internal

reference switched on

dissipation⁽⁶⁾

All power-down modes

16.92

TEMPERATURE RANGE

Specified performance

–40

+125

°C

(4) Specified by design or characterization; not production tested.

(5) Explained in more detail in the Application Information section of this data sheet.

(6) Input code = midscale, no load.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

PIN CONFIGURATIONS

PW PACKAGE

TSSOP-16

(TOP VIEW)

RGE PACKAGE

QFN-24

(TOP VIEW)

15 SDA

SCL

LDAC

ADDR0

AV_DD

24 23 22 21 20 19

GND

18 NC

13 V_OUT

12 V_OUT

11 V_OUT

10 V_OUT

V_OUT

V_REFIN/V_REFOUT

17 GND

AV_DD

DAC7678

16 V_OUT

V_OUTA

DAC7678

V_OUT

14 V_OUT

13 V_OUT

(Thermal pad)

CLR

10 11 12

(1) It is recommended to connect the thermal

pad to GND for better thermal dissipation.

PIN DESCRIPTIONS

16-PIN 24-PIN

NAME

DESCRIPTION

LDAC

ADDR0

AV_DD

Load DACs.

Three-state address input 0

Power-supply input, 2.7V to 5.5V

Analog output voltage from DAC A

Analog output voltage from DAC C

Analog output voltage from DAC E

Analog output voltage from DAC G

V_OUT

V_REFIN

V_REFOUT

Positive reference input or reference output of 2.5V, if internal reference used.

CLR

Asynchronous clear input

V_OUT

Analog output voltage from DAC H

Analog output voltage from DAC F

Analog output voltage from DAC D

Analog output voltage from DAC B

Ground reference point for all circuitry on the device

V_OUT

GND

Serial data input. Data are clocked into or out of the input register. This pin is a bidirectional,

open-drain data line that should be connected to the supply voltage with an external pull-up resistor.

SDA

—

SCL

Serial clock input. Data can be transferred at rates up to 3.4MHz. Schmitt-trigger logic input.

Not internally connected.

RSTSEL

ADDR1

Reset select pin. RSTSEL high resets device to mid-scale; RSTSEL low resets device to zero-scale.

Three-state address input 1

Not internally connected.

Twos complement select. If the TWOC pin is pulled high, the DAC registers use twos complement

format; if TWOC is pulled low, the DAC registers use straight binary format.

—

TWOC

—

Not internally connected.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

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TIMING DIAGRAM

t_LOW

Low Byte Ack Cycle

t_R

t_F

t_HD:STA

SCL

t_HIGH

t_HD:STA

t_SU:STA

t_SU:DAT

t_SU:STO

t_HD:DAT

SDA

t_BUF

t₁

LDAC¹

t₃

t₂

LDAC²

t₄

CLR

(1) Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section

(2) Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section

Figure 1. Serial Write Operation

TIMING REQUIREMENTS

At AV_DD= 2.7 V to 5.5 V and –40°C to +125°C range (unless otherwise noted).

STANDARD

FAST

MODE

HIGH SPEED

MODE

MIN MAX

0.1

PARAMETER

UNIT

MIN

MAX

MIN

MAX

3.4

SCL frequency, f_SCL

0.4

MHz

µs

Bus free time between STOP and START conditions, t_BUF

Hold time after repeated start, t_HDSTA

Repeated Start setup time, t_SUSTA

STOP condition setup time, t_SUSTO

Data hold time, t_HDDAT

4.7

1.3

0.6

0.16

4.7

0.6

Data setup time, t_SUDAT

250

4700

4000

300

1000

100

1300

600

SCL clock LOW period, t_LOW

160

SCL clock HIGH period, t_HIGH

Clock/Data fall time, t_F

300

160

Clock/Data rise time, t_R

LDAC pulse width LOW time, t₁

1.2

0.6

SCL falling edge to LDAC falling edge for asynchronous LDAC update, t₂

LDAC falling edge to SCL falling edge for synchronous LDAC update, t₃

CLR pulse width LOW time, t₄

360

10.5

1.2

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS: INTERNAL REFERENCE

At T_A= 25°C, unless otherwise noted

INTERNAL REFERENCE VOLTAGE

vs TEMPERATURE

LONG-TERM STABILITY DRIFT

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

250

200

150

100

19 Devices Shown

22 Devices Shown

-50

-100

-150

-200

-250

-40 -25 -10

110 125

240

480

720

960

1200 1440 1680 1920 2160

T - Temperature - °C

t - Time - Hours

Figure 2.

Figure 3.

INTERNAL REFERENCE VOLTAGE

vs SUPPLY VOLTAGE

INTERNAL REFERENCE VOLTAGE

vs LOAD CURRENT

2.505

2.515

2.510

2.505

2.504

2.503

2.502

2.501

= 125°C

= 25°C

2.500

2.499

2.498

= -40°C

2.500

= -40°C

2.495

2.490

2.497

2.496

2.495

-20

-15

-10

-5

Load Current - mA

3.9

4.3

2.7

3.1

3.5

4.7

5.1

5.5

Supply Voltage - V

Figure 4.

Figure 5.

INTERNAL REFERENCE NOISE DENSITY

vs FREQUENCY

INTERNAL REFERENCE NOISE

0.1 Hz to 10 Hz

350

300

250

200

150

100

Reference Unbuffered

= 0 mF

REF

15 mV

Peak-to-peak

t - Time - 2s/div

100

1000

f - Frequency - Hz

10000

100000

Figure 6.

Figure 7.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

LINEARITY ERROR

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (All 8 channels)

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

1.0

All Eight Channels Shown,

All Eight Channels Shown

AV = 5.5 V,

0.8 AV = 5.5 V,

Internal Reference = 2.5 V

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

CHA

CHE

CHC

CHG

CHB

CHF

CHD

CHH

DNL CHE

DNL CHA

DNL CHB

DNL CHC

DNL CHD

DNL CHF

DNLCHG

DNLCHH

-0.8

-1.0

512

1024

1536 2048

Digital Input Code

2560

3072

3584

4096

512

1024

1536 2048

Digital Input Code

2560

3072

3584

4096

Figure 8.

Figure 9.

LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

1.00

0.80

0.60

0.40

0.20

0.00

-0.20

-0.40

-0.60

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

AV = 5.5 V,

Internal Reference = 2.5 V,

Typical Channel Shown

Internal Reference = 2.5 V,

Typical Channel Shown

-0.80

-1.00

-0.20

-0.25

512

1024

1536 2048

Digital Input Code

2560

3072

3584

4096

512

1024

1536 2048

Digital Input Code

2560

3072

3584

Figure 10.

Figure 11.

LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE(+25°C)

0.25

0.20

1.00

0.80

0.60

0.40

0.20

0.00

-0.20

-0.40

-0.60

-0.80

-1.00

AV = 5.5 V,

Internal Reference = 2.5 V,

Typical Channel Shown

Internal Reference = 2.5 V,

Typical Channel Shown

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

512

1024

1536 2048

Digital Input Code

2560

3072

3584

512

1024

1536 2048

Digital Input Code

2560

3072

3584

4096

Figure 12.

Figure 13.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

LINEARITY ERROR

vs DIGITAL INPUT CODE (+125°C)

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+125°C)

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

1.00

0.80

0.60

0.40

0.20

0.00

-0.20

-0.40

-0.60

-0.80

-1.00

AV = 5.5 V,

Internal Reference = 2.5 V,

Typical Channel Shown

Internal Reference = 2.5 V,

Typical Channel Shown

512

1024

1536

2048

Digital Input Code

2560

3072

3584

4096

512

1024

1536

2048

Digital Input Code

2560

3072

3584

4096

Figure 14.

Figure 15.

LINEARITY ERROR

vs TEMPERATURE

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

1.00

0.80

0.60

0.40

0.20

0.00

-0.20

-0.40

-0.60

AV = 5.5 V,

Internal Reference = 2.5 V

INL MAX

INL MIN

DNL MAX

DNL MIN

-0.80

-1.00

-0.20

-0.25

-40 -25 -10

110 125

-40

-25

-10

T - Temperature -°C

110 125

T - Temperature -°C

Figure 16.

Figure 17.

POWER SUPPLY CURRENT

vs TEMPERATURE

OFFSET ERROR

vs TEMPERATURE

1.40

1.30

AV = 5.5 V,

External Reference = 5 V

Internal Reference = 2.5 V

1.20

1.10

1.00

-1

-2

Ch A Ch B

Ch C Ch D

Ch E Ch F

Ch G Ch H

0.90

0.80

-3

-4

-40 -25 -10

110 125

-40 -25 -10

110 125

T - Temperature -°C

Figure 18.

Figure 19.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

POWER SUPPLY CURRENT

vs TEMPERATURE

FULL-SCALE ERROR

vs TEMPERATURE

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

2.20

2.10

AV = 5.5 V,

Internal Reference = 2.5 V

2.00

1.90

1.80

1.70

1.60

DAC A

DAC C

DAC E

DAC G

DAC B

DAC D

DAC F

DAC H

1.50

-0.15

-0.20

1.40

1.30

-40 -25 -10

110 125

-40 -25 -10

110 125

T - Temperature -°C

Figure 20.

Figure 21.

POWER-DOWN CURRENT

vs TEMPERATURE

GAIN ERROR

vs TEMPERATURE

6.00

5.50

5.00

4.50

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.15

0.10

0.05

0.00

-0.05

AV = 5.5 V,

Internal Reference = 2.5 V

DAC A

DAC C

DAC E

DAC G

DAC B

DAC D

DAC F

DAC H

-0.10

-0.15

0.50

0.00

-40 -25 -10

110 125

-40 -25 -10

110 125

T - Temperature -°C

Figure 22.

Figure 23.

SOURCE CURRENT

AT POSITIVE RAIL

SINK CURRENT

AT NEGATIVE RAIL

5.00

4.95

4.90

0.60

0.50

0.40

0.30

0.20

0.10

0.00

AV = 5.5 V,

Channel C

Internal Reference Enabled,

DAC Loaded with 000h

Channel C

4.85

4.80

AV = 5.5 V,

Internal Reference Enabled,

DAC Loaded with FFFh

- mA

sink

SOURCE

Figure 24.

Figure 25.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

SOURCE CURRENT

AT POSITIVE RAIL

SINK CURRENT

AT NEGATIVE RAIL

5.00

4.95

4.90

0.60

0.50

AV = 5.5 V,

Channel D

Internal Reference Enabled,

DAC Loaded with 000h

Channel D

0.40

0.30

0.20

4.85

4.80

AV = 5.5 V,

0.10

0.00

Internal Reference Enabled,

DAC Loaded with FFFh

- mA

SINK

SOURCE

Figure 26.

Figure 27.

SOURCE CURRENT

AT POSITIVE RAIL

SINK CURRENT

AT NEGATIVE RAIL

5.00

4.95

4.90

0.60

0.50

AV = 5.5 V,

Channel H

Internal Reference Enabled,

DAC Loaded with 000h

Channel H

0.40

0.30

0.20

4.85

4.80

AV = 5.5 V,

0.10

0.00

Internal Reference Enabled,

DAC Loaded with FFFh

- mA

SINK

SOURCE

Figure 28.

Figure 29.

POWER SUPPLY CURRENT

vs DIGITAL INPUT CODE

POWER SUPPLY CURRENT

vs DIGITAL INPUT CODE

2.20

2.10

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

2.00

1.90

1.80

1.70

1.60

1.50

1.40

AV = 5.5 V,

1.30

1.20

1.10

External Reference = 5 V,

Internal Reference Disabled,

Code Loaded to all Eight DAC Channels

Internal Reference Enabled,

Code Loaded to all Eight DAC Channels

512

1024

1536 2048 2560 3072 3584

Digital Input Code

4096

512

1024

1536

2048

2560

3072

3584

4096

Digital Input Code

Figure 30.

Figure 31.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

POWER SUPPLY CURRENT

vs POWER SUPPLY VOLTAGE

2.20

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

AV = 2.7 V to 5.5 V,

Internal Reference Disabled

Internal Reference Enabled

2.00

1.80

1.60

1.40

1.20

1.00

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

AV - Supply Voltage - V

Figure 32.

Figure 33.

POWER DOWN CURRENT

vs POWER SUPPLY VOLTAGE

POWER-SUPPLY CURRENT

HISTOGRAM

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

AV = 5.5 V,

AV = 2.7 V to 5.5 V

Internal Reference = 2.5 V

0.05

0.00

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

AV - Supply Voltage - V

- Supply Current - mA

Figure 34.

Figure 35.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

POWER-SUPPLY CURRENT

HISTOGRAM

AV = 5.5 V,

External Reference = 5 V

- Supply Current - mA

Figure 36.

FULL-SCALE SETTLING TIME:

5V RISING EDGE

FULL-SCALE SETTLING TIME:

5V FALLING EDGE

AV = 5.5 V,

From Code FFFh to 000h

Internal Reference Enabled

Zoomed Rising Edge

100 mV/div

Zoomed Falling Edge

100 mV/div

Falling Edge

2 V/div

Rising Edge

2 V/div

AV = 5.5 V,

Trigger Pulse

5 V/div

From Code 000h to FFFh,

Internal Reference Enabled

Trigger Pulse

5 V/div

t - Time - 5 ms/div

Figure 37.

Figure 38.

HALF-SCALE SETTLING TIME:

5V RISING EDGE

HALF-SCALE SETTLING TIME:

5V FALLING EDGE

AV = 5.5 V,

From Code 400h to C00h

Internal Reference Enabled

From Code C00h to 400h

Internal Reference Enabled

Zoomed Rising Edge

100 mV/div

Zoomed Falling Edge

100 mV/div

Falling Edge

2 V/div

Rising Edge

2 V/div

Trigger Pulse

5 V/div

Trigger Pulse

5 V/div

t - Time - 5 ms/div

Figure 39.

Figure 40.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

CLOCK FEEDTHROUGH

400 kHz, MIDSCALE

POWER-ON GLITCH

RESET TO ZERO SCALE

AV = 5.5 V,

DAC Unloaded,

DAC at Zero Scale

Clock Feedthrough Impulse ~1.5 nV-s

Internal Reference Enabled

- 2 mV/div

OUT

~2 mV

- 5 mV/div

OUT

SCL - 5 V/div

AV - 2 V/div

t - Time - 10 ms/div

t - Time - 1 ms/div

Figure 41.

Figure 42.

POWER-ON GLITCH

RESET-TO-MID SCALE

POWER-OFF GLITCH

AV = 5.5 V,

DAC Unloaded,

DAC at Zero Scale

DAC Unloaded,

DAC at Zero Scale

- 2 V/div

OUT

- 1 mV/div

OUT

AV - 2 V/div

t - Time - 20 ms/div

t - Time - 10 ms/div

Figure 43.

Figure 44.

GLITCH ENERGY:

5V 1LSB STEP, RISING EDGE

5V 1LSB STEP, FALLING EDGE

AV = 5.5 V,

From Code 801h to 800h

From Code 800h to 801h

- 500 mV/div

OUT

LDAC Clock

Feed-Through

- 500 mV/div

OUT

LDAC Clock

Feed-Through

LDAC - Trigger Pulse

5 V/div

LDAC - Trigger Pulse

5 V/div

t - Time - 2 ms/div

Figure 45.

Figure 46.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

DAC OUTPUT NOISE DENSITY vs FREQUENCY

INTERNAL REFERENCE ENABLED

DAC OUTPUT NOISE DENSITY vs FREQUENCY

INTERNAL REFERENCE DISABLED

800

700

600

500

400

300

200

100

300

250

200

150

100

AV = 5.5 V,

DAC Output Unloaded,

Internal Reference = 2.5 V

DAC Output Unloaded,

External Reference = 5 V

Full Scale

Mid Scale

Full Scale

Mid Scale

Zero Scale

100

1000

f - Frequency - Hz

10000

100000

100

1000

f - Frequency - Hz

10000

100000

Figure 47.

Figure 48.

DAC OUTPUT NOISE

0.1 Hz to 10 Hz

~3 mV

t - Time - 2 s/div

Figure 49.

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TYPICAL CHARACTERISTICS: DAC AT AV_DD= 3.6 V

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

POWER SUPPLY CURRENT

vs TEMPERATURE

POWER SUPPLY CURRENT

vs DIGITAL INPUT CODE

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

1.30

1.20

AV = 3.6 V,

External Reference = 3.3 V

1.10

1.00

0.90

AV = 3.6 V,

External Reference = 3.3 V,

Internal Reference Disabled,

Code Loaded to all Eight DAC Channels

0.80

0.70

-40 -25 -10

110 125

512

1024

1536 2048

Digital Input Code

2560

3072

3584

4096

T - Temperature -°C

Figure 50.

Figure 51.

POWER SUPPLY CURRENT

HISTOGRAM

AV = 3.6 V,

External Reference = 3.3 V

0.765

0.7

0.785

0.795

0.805

0.815

0.825

0.835

0.845

0.85

0.865

0.875

0.8

0.895

0.905

0.915

0.925

0.935

0.945

0.95

0.965

0.975

- Supply Current - mA

Figure 52.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS: DAC AT AV_DD= 2.7 V

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

LINEARITY ERROR

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (All 8 Channels)

1.00

0.80

0.60

0.25

0.20

AV = 2.7 V,

External Reference = 2.5 V

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

0.40

0.20

0.00

-0.20

-0.40

-0.60

CHA

CHB

CHC

CHD

CHE

CHF

CHG

CHH

DNL CHA DNL CHE

DNL CHB DNL CHF

DNL CHC DNL CHG

DNL CHD DNL CHH

-0.20

-0.25

-0.80

-1.00

512

1024

1536

2048

Digital Input Code

2560

3072

3584

4096

512

1024

1536

2048

Digital Input Code

2560

3072

3584

4096

Figure 53.

Figure 54.

LINEARITY ERROR

vs DIGITAL INPUT CODE (-40°C)

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (-40°C)

1.00

0.80

0.60

0.40

0.20

0.00

-0.20

-0.40

-0.60

0.25

AV = 2.7 V,

0.20 External Reference = 2.5 V

External Reference = 2.5 V

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

-0.80

-1.00

512

1024

1536

2048

Digital Input Code

2560

3072

3584

512

1024

1536

2048

Digital Input Code

2560

3072

3584

4096

Figure 55.

Figure 56.

LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

1.00

0.80

0.60

0.40

0.20

0.00

-0.20

-0.40

-0.60

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

AV = 2.7 V,

External Reference = 2.5 V

-0.80

-1.00

512

1024

1536

2048 2560

Digital Input Code

3072

3584

512

1024

1536

2048

Digital Input Code

2560

3072

3584

4096

Figure 57.

Figure 58.

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TYPICAL CHARACTERISTICS: DAC AT AV_DD= 2.7 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

LINEARITY ERROR

vs DIGITAL INPUT CODE (+125°C)

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+125°C)

0.25

1.00

0.80

AV = 2.7 V,

0.20 External Reference = 2.5 V

External Reference = 2.5 V

0.60

0.40

0.20

0.00

-0.20

-0.40

-0.60

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

-0.80

-1.00

512

1024

1536

2048

Digital Input Code

2560

3072

3584

4096

512

1024

1536

2048

Digital Input Code

2560

3072

3584

4096

Figure 59.

Figure 60.

LINEARITY ERROR

vs TEMPERATURE

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

1.00

0.80

0.60

0.40

0.20

0.00

-0.20

-0.40

-0.60

-0.80

-1.00

0.25

0.20

AV = 2.7 V,

External Reference = 2.5 V

0.15

0.10

INL MAX

INL MIN

DNL MAX

DNL MIN

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

-40 -25 -10

T - Temperature -°C

110 125

-40 -25 -10

T - Temperature -°C

110 125

Figure 61.

Figure 62.

POWER-SUPPLY CURRENT

vs TEMPERATURE

OFFSET ERROR

vs TEMPERATURE

1.30

1.20

AV = 2.7 V,

External Reference = 2.5 V

1.10

1.00

0.90

0.80

-1

-2

DAC A

DAC C

DAC E

DAC G

DAC B

DAC D

DAC F

DAC H

0.70

0.60

-3

-4

-40 -25 -10

110 125

-40 -25 -10

110 125

T - Temperature -°C

Figure 63.

Figure 64.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS: DAC AT AV_DD= 2.7 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

POWER-DOWN CURRENT

vs TEMPERATURE

FULL-SCALE ERROR

vs TEMPERATURE

4.70

4.50

0.20

0.15

0.10

AV = 2.7 V,

4.20

3.90

3.60

External Reference = 2.5 V

3.30

3.00

2.70

2.40

2.10

1.80

1.50

1.20

0.90

0.60

0.30

0.00

0.05

0.00

-0.05

-0.10

DAC A

DAC C

DAC E

DAC B

DAC D

DAC F

-0.15

-0.20

DAC G DAC H

-40 -25 -10

110 125

-40 -25 -10

110 125

T - Temperature -°C

Figure 65.

Figure 66.

GAIN ERROR

vs TEMPERATURE

0.15

AV = 2.7 V,

External Reference = 2.5 V

0.10

0.05

0.00

-0.05

DAC A

DAC C

DAC E

DAC G

DAC B

DAC D

DAC F

DAC H

-0.10

-0.15

-40 -25 -10

110 125

T - Temperature -°C

Figure 67.

SOURCE CURRENT

AT POSITIVE RAIL

SINK CURRENT

AT NEGATIVE RAIL

2.500

2.495

0.60

AV = 2.7 V,

External Reference = 2.5 V,

DAC Loaded with 000h

External Reference = 2.5 V,

DAC Loaded with FFFh

Channel A

0.50

0.40

0.30

0.20

2.490

2.485

2.480

2.475

2.470

2.465

2.460

2.455

Channel A

0.10

0.00

2.450

2.445

- mA

SINK

SOURCE

Figure 68.

Figure 69.

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TYPICAL CHARACTERISTICS: DAC AT AV_DD= 2.7 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

SOURCE CURRENT

AT POSITIVE RAIL

SINK CURRENT

AT NEGATIVE RAIL

2.500

2.495

2.490

0.60

0.50

AV = 2.7 V,

External Reference = 2.5 V,

DAC Loaded with FFFh

External Reference = 2.5 V,

DAC Loaded with 000h

Channel B

2.485

2.480

0.40

0.30

0.20

2.475

2.470

2.465

2.460

0.10

0.00

2.455

2.450

- mA

SINK

SOURCE

Figure 70.

Figure 71.

SOURCE CURRENT

AT POSITIVE RAIL

SINK CURRENT

AT NEGATIVE RAIL

2.500

2.495

2.490

2.485

2.480

2.475

2.470

2.465

2.460

2.455

2.450

0.60

0.50

AV = 2.7 V,

External Reference = 2.5 V,

DAC Loaded with FFFh

External Reference = 2.5 V,

DAC Loaded with 000h

Channel G

0.40

0.30

0.20

0.10

0.00

- mA

SINK

SOURCE

Figure 72.

Figure 73.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS: DAC AT AV_DD= 2.7 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

POWER SUPPLY CURRENT

vs DIGITAL INPUT CODE

POWER SUPPLY CURRENT

HISTOGRAM

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

AV = 2.7 V,

External Reference = 2.5 V

External Reference = 2.5 V,

Internal Reference Disabled,

Code Loaded to all Eight DAC Channels

512

1024

1536

2048

Digital Input Code

2560

3072

3584

4096

- Supply Current - mA

Figure 74.

Figure 75.

FULL-SCALE SETTLING TIME:

2.7V RISING EDGE

FULL-SCALE SETTLING TIME:

2.7V FALLING EDGE

AV = 2.7 V,

From Code FFFh to 000h

External Reference = 2.5 V

From Code 000h to FFFh

External Reference = 2.5 V

Zoomed Rising Edge

100 mV/div

Zoomed Falling Edge

100 mV/div

Falling Edge

2 V/div

Rising Edge

2 V/div

Trigger Pulse

5 V/div

Trigger Pulse

5 V/div

t - Time - 5 ms/div

Figure 76.

Figure 77.

HALF-SCALE SETTLING TIME:

2.7V RISING EDGE

HALF-SCALE SETTLING TIME:

2.7V FALLING EDGE

AV = 2.7 V,

From Code 400h to C00h

External Reference = 2.5 V

From Code C00h to 400h

External Reference = 2.5 V

Zoomed Falling Edge

100 mV/div

Zoomed Rising Edge

100 mV/div

Falling Edge

2 V/div

Rising Edge

2 V/div

Trigger Pulse

5 V/div

Trigger Pulse

5 V/div

t - Time - 5 ms/div

Figure 78.

Figure 79.

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TYPICAL CHARACTERISTICS: DAC AT AV_DD= 2.7 V (continued)

At T_A= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless

otherwise noted

CLOCK FEEDTHROUGH

400 kHz, MIDSCALE

POWER-ON GLITCH

RESET TO ZERO SCALE

AV = 2.7 V,

External Reference = 2.5 V,

DAC = Zero Scale,

DACs unloaded

Clock Feedthrough Impulse ~ 0.5n V-s

External Reference = 2.5 V

- 2 mV/div

OUT

~ 1.8 mV

- 5 mV/div

OUT

AV - 2 V/div

SCL - 5 V/div

t - Time - 10 ms/div

t - Time - 1 ms/div

Figure 80.

Figure 81.

POWER-ON GLITCH

RESET TO MIDSCALE

POWER-OFF GLITCH

AV = 2.7 V,

External Reference = 2.5 V,

DAC = Mid Scale,

DACs Unloaded

DAC = Zero Scale

- 2 mV/div

OUT

- 1 mV/div

OUT

AV - 2 V/div

t - Time - 10 ms/div

t - Time - 20 ms/div

Figure 82.

Figure 83.

GLITCH ENERGY:

2.7V 1LSB STEP, RISING EDGE

2.7V 1LSB STEP, FALLING EDGE

AV = 2.7 V,

From Code 801h to 800h

External Reference = 2.5 V

From Code 800h to 801h

External Reference = 2.5 V

- 500 mV/div

OUT

LDAC Clock

Feed-Through

LDAC Clock

Feed-Through

- 500 mV/div

OUT

LDAC - Trigger Pulse

5 V/div

LDAC - Trigger Pulse

5 V/div

t - Time - 2 ms/div

Figure 84.

Figure 85.

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

THEORY OF OPERATION

will be un-shorted if external reference is used. Thus

the overall gain will be one and allows the user to

provide an external reference value of 0 to AVDD. If

internal reference is used R_DIVIDERis shorted and the

overall gain will be two.

DIGITAL-TO-ANALOG CONVERTER (DAC)

The DAC7678 architecture consists of eight string

DACs each followed by an output buffer amplifier.

The DAC7678 also includes an internal 2.5V

reference with a maximum 25ppm/°C temperature

drift performance, offering a 5V, full-scale output

voltage. Figure 86 shows a principal block diagram of

the DAC architecture.

V_REF

R_DIVIDER

V_REFIN/V_REFOUT

V_REF

150kW

178kW

V_OUT

REF(+)

Resistor String

REF(-)

DAC

To Output Amplifier

(2x Gain)

Figure 86. Device Architecture

For the TSSOP package, the input coding to the

DAC7678 is straight binary. For the QFN package,

the TWOC pin controls the code format.

When using the internal reference, the ideal output

voltage is given by Equation 1:

D_IN

V_OUT

´ 2 ´ V_REFOUT

4096

(1)

When using an external reference, the ideal output

voltage is given by Equation 2:

D_IN

V_OUT

´ V_REFIN

4096

(2)

Where:

D_IN= decimal equivalent of the binary code that

is loaded to the DAC register. It can range from 0

to 4095.

V_REFOUT= internal reference voltage of 2.5V (typ),

supplied at the V_REFIN/V_REFOUTpin.

Figure 87. Resistor String

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating

rail-to-rail voltages on its output, giving a maximum

output range of 0V to AV_DD. It is capable of driving a

load of 2kΩ in parallel with 1000pF to GND. The

source and sink capabilities of the output amplifier

can be seen in the Typical Characteristics. The

typical slew rate is 0.75V/ms, with a typical full-scale

settling time of 7ms with the output unloaded.

V_REFIN= external reference voltage of 0V to 5V

(typ), supplied at the V_REFIN/V_REFOUTpin.

RESISTOR STRING

The resistor string circuitry is shown in Figure 87. It is

a string of resistors, each of value R. The code

loaded into the DAC register determines at which

node on the string the voltage is tapped off to be fed

into the output amplifier by closing one of the

switches connecting the string to the amplifier. It is

monotonic because it is a string of resistors. R_DIVIDER

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INTERNAL REFERENCE

using an external reference. The internal reference

can be powered up and powered down using a serial

command that requires a 32-bit write sequence,

which consists of 8 bit Address Byte plus 24 bit serial

command as shown in Table 1. During the time that

the internal reference is disabled, the DAC functions

normally using an external reference. However, when

switching to the external reference the internal gain is

dynamically switched to one. Therefore appropriate

value of external reference should be used per the

desired output voltage. At this point, the internal

reference is disconnected from the V_REFIN/V_REFOUTpin

(3-state output). Do not attempt to drive the

V_REFIN/V_REFOUTpin externally and internally at the

same time indefinitely. There are two modes that

allow communication with the internal reference:

Regular/Static and Flexible. In Flexible mode DB14

needs to be set to '1' as shown in Table 17.

The DAC7678 includes a 2.5V internal reference that

is disabled by default. The internal reference is

externally available at the V_REFIN/V_REFOUTpin. A

minimum 100nF capacitor is recommended between

the reference output and GND for noise filtering. The

internal reference of the DAC7678 is

bipolar-transistor based precision bandgap voltage

reference. Figure 88 shows the basic bandgap

topology. Transistors Q₁and Q₂are biased such that

the current density of Q₁is greater than that of Q₂.

The difference of the two base-emitter voltages (V_BE1

– V_BE2) has a positive temperature coefficient and is

forced across resistor R₁. This voltage is gained up

and added to the base-emitter voltage of Q₂, which

has a negative temperature coefficient. The resulting

output voltage is virtually independent of temperature.

The short-circuit current is limited by design to

approximately 100mA.

Regular/Static Mode (see Table 1 and Table 2)

Enabling Internal Reference:

V_REF

To enable the internal reference, write the 24-bit

serial command shown in Table 1 after properly

addressing the device. When performing a power

cycle to reset the device, the internal reference is

switched off (default mode). In the default mode, the

internal reference is powered down until a valid write

sequence is applied to power up the internal

reference. Setting DB4 to '1' turns on the internal

reference.If the internal reference is powered up, it

automatically powers down when all DACs power

down in any of the power-down modes (see Table 17

and Power Down Modes section). The internal

reference automatically powers up when any DAC is

powered up.

Reference

Disable

Q₁

Q₂

R₁

R₂

Disabling Internal Reference:

To disable the internal reference, address the device

by writing the 8-bit address byte and then writing the

24-bit serial command shown in Table 1. When

performing a power cycle to reset the device, the

internal reference is put back into the default mode

(switched off).

Figure 88. Simplified Schematic of the Bandgap

Reference

Enable/Disable Internal Reference

The internal reference in the DAC7678 is disabled by

default for debugging, evaluation purposes, or when

SPACER

Table 1. Write Sequence for Enabling Internal Reference (Static Mode) (Internal Reference Powered On)

COMMAND AND ACCESS BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT BYTE

DB15

DB14

DB13

DB12

DB11

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Table 2. Write Sequence for Disabling Internal Reference (Static Mode) (Internal Reference Powered Off)

COMMAND AND ACCESS BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT BYTE

DB15

DB14

DB13

DB12

DB11

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

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Flexible Mode (see Table 3, Table 4, Table 5 and

Table 6)

internal reference operating mode. When performing

a power cycle to reset the device, the internal

reference is switched off (default mode). In the

default mode, the internal reference remains powered

down until a valid write sequence is applied to power

up the internal reference. When the internal reference

is powered up in flexible mode, it remains powered

up, regardless of the state of the DACs.

Enabling Internal Reference:

Method 1) To enable the internal reference, write the

24-bit serial command shown in Table 3 after

properly addressing the device. When performing a

power cycle to reset the device, the internal reference

is switched off (default mode). In the default mode,

the internal reference is powered down until a valid

write sequence is applied to power up the internal

reference. If the internal reference is powered up, it

automatically powers down when all DACs power

down in any of the power-down modes (see the

Power Down Modes section). The internal reference

powers up automatically when any DAC is powered

up.

Disabling Internal Reference:

To disable the internal reference, write the 24-bit

serial command shown in Table 5 after properly

addressing the device. When performing a power

cycle to reset the device, the internal reference is

switched off (default mode). When the internal

reference is operated in Flexible mode, Static mode

is disabled and does not work. To switch from

Flexible mode to Static mode, use the command

shown in Table 6.

Method 2) To always enable the internal reference,

write the 24-bit serial command shown in Table 4

after properly addressing the device. When the

internal reference is always enabled, any power-down

command to the DAC channels does not change the

Table 3. Write Sequence for Enabling Internal Reference (Flexible Mode)

(Internal Reference Powered On)

COMMAND AND ACCESS BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT BYTE

DB15

DB14

DB13

DB12

DB11

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Table 4. Write Sequence for Enabling Internal Reference (Flexible Mode)

(Internal Reference Always Powered On)

COMMAND AND ACCESS BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT BYTE

DB15

DB14

DB13

DB12

DB11

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Table 5. Write Sequence for Disabling Internal Reference (Flexible Mode)

(Internal Reference Always Powered Down)

COMMAND AND ACCESS BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT BYTE

DB15

DB14

DB13

DB12

DB11

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Table 6. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference

COMMAND AND ACCESS BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT BYTE

DB15

DB14

DB13

DB12

DB11

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

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TWO-WIRE, I²C-COMPATIBLE INTERFACE

and fast modes. The protocol for high-speed mode is

different from the F/S-mode, and it is referred to as

HS-mode. The DAC7678 supports 7-bit addressing.

The 10-bit addressing and general call address are

not supported.

Other than specific timing signals, the I²C interface

works with serial bytes. At the end of each byte, a 9^th

clock cycle is used to generate/detect an

acknowledge signal, Acknowledge is when the SDA

line is pulled low during the high period of the 9^th

clock cycle. A not-acknowledge is when the SDA line

is left high during the high period of the 9^thclock

cycle as shown in Figure 90.

The I²C™ is a 2-wire serial interface developed by

Philips Semiconductor (see I²C™-Bus Specification,

Rev. 03, June 2007). The bus consists of a data line

(SDA) and a clock line (SCL) with pull-up structures.

When the bus is idle, both SDA and SCL lines are

pulled high. All the I²C™ compatible devices connect

to the I²C™ bus through open drain I/O pins, SDA

and SCL.

The I²C specification states that the device that

controls communication is called a master, and the

devices that are controlled by the master are called

slaves. The master device generates the SCL signal.

The master device also generates special timing

conditions (start condition, repeated start condition,

and stop condition) on the bus to indicate the start or

stop of a data transfer. Device addressing is also

done by the master. The master device on an I²C bus

Data Output

by Transmitter

Not Acknowledge

Data Output

by Receiver

Acknowledge

is usually

a microcontroller or a digital signal

SCL from

Master

processor (DSP). The DAC7678 on the other hand,

operates as a slave device on the I²C bus. A slave

devcie acknowledges master's commands and upon

master's control, either receives or transmits data.

Clock Pulse for

START

Acknowledgement

Condition

Figure 90. Acknowledge and Not Acknowledge

on the I²C Bus

SDA

SCL

SDA

SCL

F/S Mode Protocol

•

The master initiates data transfer by generating a

start condition. The start condition is when a

high-to-low transition occcurs on the SDA line

while SCL is high, as shown in Figure 90. All

Start

Stop

Condition

Figure 89. Start and Stop Conditions

I²C-compatible devices recognize

condition.

start

The DAC7678 normally operates as a slave receiver.

A master device writes to the DAC7678, a slave

receiver. However, if a master device inquires the

DAC7678 internal register data, the DAC7678

operates as a slave transmitter. In this case, the

master device reads from the DAC7678, a slave

transmitter. According to I²C™ terminology, read and

write are with respect to the master device.

•

The master then generates the SCL pulses, and

transmits the 7-bit address and the read/write

direction bit (R/W) on the SDA line. During all

transmissions, the master ensures that data is

valid. A valid data condition requires the SDA line

to be stable during the entire high period of the

clock pulse, as shown in Figure 91. All devices

recognize the address sent by the master and

compare it to their internal fixed addresses. Only

The DAC7678 works as a slave and supports the

following data transfer modes, as defined in the I²C™

-Bus Specification:

the slave device with

a matching address

generates an acknowledge by pulling the SDA line

low during the entire high period of the ninth SCL

cycle, as shown in Figure 90 by pulling the SDA

line low during the entire high period of the 9^th

SCL cycle. Upon detecting this acknowledge, the

master knows the communication link with a slave

has been established.

The master generates further SCL cycles to either

transmit data to the slave (R/W bit 0) or receive

data from the slave (R/W bit 1). In either case, the

receiver needs to acknowledge the data sent by

the transmitter. So the acknowledge signal can

either be generated by the master or by the slave,

depending on which one is the receiver. The 9-bit

valid data sequences, consisting of 8-data bits

•

Standard mode (100 kbps)

Fast mode (400 kbps)

Fast mode+ (1.0Mbps) and

High-Speed mode (3.4 Mbps)

The data transfer protocol for standard and fast

modes is exactly the same, therefore they are

referred to as F/S-mode in this document. The fast

mode+ protocol is supported in terms of data transfer

speed but not output current. The low-level output

current would be 3mA similar to the case of standard

•

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and 1-bit acknowledge can continue as long as

necessary.

all devices must recognize it and switch their

internal setting to support 3.4Mbps operation.

•

To signal the end of the data transfer, the master

generates a stop condition by pulling the SDA line

from low to high while the SCL line is high (see

Figure 89). This action releases the bus and stops

the communication link with the addressed slave.

All I²C-compatible devices recognize the stop

condition. Upon receipt of a stop condition, the

bus is released, and all slave devices then wait for

a start condition followed by a matching address.

•

The master then generates a repeated start

condition (a repeated start condition has the same

timing as the start condition). After this repeated

start condition, the protocol is the same as

F/S-mode, except that transmission speeds up to

3.4Mbps are allowed. A stop condition ends HS

mode and switches all the internal settings of the

slave devices to support F/S-mode. Instead of

using a stop condition, repeated start conditions

should be used to secure the bus in H/S-mode.

DAC7678 I²C UPDATE SEQUENCE

SDA

For a single update, the DAC7678 requires a start

condition, a valid I²C address, a command and

access (CA) byte, and two data bytes, the most

significant data byte (MSDB) and least significant

data byte (LSDB), as shown in Table 7.

SCL

Data Line Stable;

Data Valid

Change of Data Allowed

Figure 91. Bit Transfer on the I²C Bus

HS Mode Protocol

After each byte is received, the DAC7678

acknowledges by pulling the SDA line low during the

high period of a single clock pulse, as shown in

Figure 92. These four bytes and acknowledge cycles

make up the 36 clock cycles required for a single

update to occur. A valid I²C address selects the

DAC7678.

•

When the bus is idle, both the SDA and SCL lines

are pulled high by the pull-up resistors.

The master generates a start condition followed

by a valid serial byte containing H/S master code

00001XXX. This transmission is made in F/S

mode at no more than 1.0 Mbps. No device is

allowed to acknowledge the H/S master code, but

•

Recognize START or

REPEATED START

Condition

Recognize STOP or

REPEATED START

Condition

Generate ACKNOWLEDGE

Signal

SDA

MSB

Acknowledgement

Signal From Slave

Address

R/W

SCL

3 - 8

ACK

Clock Line Held Low While

Interrupts are Serviced

START or

REPEATED START

Condition

REPEATED START or

STOP

Condition

Figure 92. I²C Bus Protocol

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Table 7. Update Sequence

MSB

···

LSB

MSB

···

LSB

MSB

···

LSB

MSB

···

LSB

ACK

Address (A) Byte

DB[32:24]

Command/Access Byte

DB[23:16]

MSDB

DB[15:8]

LSDB

DB[7:0]

SPACING

The CA byte sets the operational mode of the

selected DAC7678. When the operational mode is

selected by this byte, the DAC7678 must receive two

data bytes, the most significant data byte (MSDB)

and least significant data byte (LSDB), for data

update to occur. The DAC7678 performs an update

on the falling edge of the acknowledge signal that

follows the LSDB.

maximum DAC update rate is limited to 22.22kSPS.

Using the Fast mode plus (clock = 1MHz), the

maximum DAC update rate is limited to 55.55kSPS.

When a stop condition is received, the DAC7678

releases the I²C bus and awaits a new start condition.

Address (A) Byte

The address byte, as shown in Table 8, is the first

byte received following the START condition from the

master device. The first four bits (MSBs) of the

address are factory preset to 1001. The next 3 bits of

the address are controlled by the ADDR pin(s). The

ADDR pin(s) inputs can be connected to AV_DD, GND,

or left floating. The device address should be

determined before device power up. During power up

the device latches the values of the address pins and

consequently will respond to that particular address

according to Table 9 and Table 10. When using the

QFN package (DAC7678RGE), up to 8 devices can

be connected to the same I²C bus. When using the

TSSOP package (DAC7678PW), up to 3 devices can

be connected to the same I²C bus.

The CA byte does not have to be resent until a

change in operational mode is required. The bits of

the control byte continuously determine the type of

update performed. Thus, for the first update, the

DAC7678 requires a start condition, a valid I²C

address, the CA byte, and two data bytes (MSDB and

LSDB). For all consecutive updates, the DAC7678

needs only an MSDB and LSDB, as long as the CA

byte command remains the same.

When using the I²C HS mode (clock = 3.4MHz), each

12-bit DAC update other than the first update can be

done within 18 clock cycles (MSDB, acknowledge

signal, LSDB, acknowledge signal) at 188.88kSPS.

When using Fast mode (clock = 400kHz), the

Table 8. Address Byte

MSB

AD6

LSB

AD5

AD4

AD3

AD2

AD1

AD0

R/W

See Table 9 or Table 10 Slave Address column

0 or 1

Table 9. Address Format For QFN-24 (RGE) Package

SLAVE ADDRESS

1001 000

ADDR1

ADDR0

1001 001

1001 010

1001 011

1001 100

Float

1001 101

1001 110

Float

1001 111

Not supported

Float

Table 10. Address Format For TSSOP-16 (PW) Package

SLAVE ADDRESS

1001 000

ADDR0

1001 010

1001 100

Float

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Command and Access (CA) Byte

Table 11. Command and Access Byte

The Command and Access Byte, as shown in

Table 11, controls which command is executed and

which register is being accessed when writing to or

reading from the DAC7678. See Table 12 for a list of

write and read commands.

MSB

LSB

Command bits

Access bits

Table 12. Command and Access Byte Format⁽¹⁾

DESCRIPTION

Write Sequences

A0 Write to DAC input register channel n

A0 Select to update DAC register channel n

Write to DAC input register channel n, and update all DAC registers (global

software LDAC)

A0 Write to DAC input register channel n, and update DAC register channel n

Power down/on DAC

Write to clear code register

Write to LDAC register

Software reset

Write to internal reference register

Write to additional internal reference register

Read Sequences

A0 Read from DAC input register channel n

A0 Read from DAC register channel n

Read from DAC power down register

Read from clear code register

Read from LDAC register

Read from internal reference register

Read from additional internal reference register

Access Sequences

DAC channel A

DAC channel B

DAC channel C

DAC channel D

DAC channel E

DAC channel F

DAC channel G

DAC channel H

All DAC channels, broadcast update

(1) Any sequences other than the ones listed are invalid; improper use can cause incorrect device functionality.

shown in Table 13 and Table 14. See Table 17 for a

complete list of write sequences and Table 18 for a

complete list of read sequences. The DAC7678

updates at the falling edge of the acknowledge signal

that follows the LSDB[0] bit.

Most Significant Data Byte (MSDB) and Least

Significant Data Byte (LSDB)

The MSDB and LSDB contain the data that are

passed to the register(s) specified by the CA byte, as

Table 13. MSDB

MSB

LSB

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

Most Significant Data Byte (MSDB)

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Broadcast Address Byte

2. Then send a command byte for the register to be

read. The device will acknowledge this event

again.

Broadcast addressing, see Table 15, is also

supported by DAC7678. Broadcast addressing can

be used for synchronously updating or powering

down multiple DAC7678 devices. DAC7678 is

designed to work with other members of the

DACx578 family to support multichannel synchronous

update. Using the broadcast address, DAC7678

responds regardless of the states of the address pins.

Broadcast is supported only in write mode (Master

writes to DAC7678).

3. Then send a repeated start with the slave

address and the R/W bit set to '1' for reading.

The device will also acknowledge this event.

4. Then the device writes the MSDB byte of the

addressed

The

master

should

acknowledge this byte. Finally, the device writes

out the LSDB of the register as shown in

Table 16.

An alternative reading method allows for reading back

the value of the last register written. The sequence is

a start/repeated start with slave address and the R/W

bit set to '1', and the two bytes of the last register are

read out.

DAC7678 I²C READ SEQUENCE

To read any register other than the power-down

used:

1. Send a start or repeated start command with a

slave address and the R/W bit set to '0' for

writing. The device will acknowledge this event.

Note that it is not possible to use the broadcast

address for reading.

Table 14. LSDB

MSB

LSB

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Least Significant Data Byte (LSDB)

Table 15. Broadcast Address Byte

MSB

LSB

Table 16. Read Sequence

MSB

…

R/W(0)

ACK

MSB

…

LSB

ACK

MSB

Address Byte

From master

…

R/W(1)

ACK

MSB

…

LSB

ACK

MSB

…

LSB

ACK

Address Byte

From master

Command/Access Byte

From master

MSDB

LSDB

Slave

slave

From Slave

Master

From Slave

Master

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Table 17. Control Matrix for Write Commands

COMMAND AND ACCESS BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

DB6 DB5 DB4 DB3 DB2 DB1 DB0

DESCRIPTION

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

Write to DAC Input Register

Data[11:4]

Data[3:0]

Write to DAC input register of channel A

Write to DAC input register of channel B

Write to DAC input register of channel C

Write to DAC input register of channel D

Write to DAC input register of channel E

Write to DAC input register of channel F

Write to DAC input register of channel G

Write to DAC input register of channel H

Invalid code, no action performed

Data[11:4]

Data[3:0]

Data[11:4]

Data[3:0]

Broadcast mode–write to all DAC channels

Select to Update DAC Register

Selects DAC channel A to be updated

Selects DAC channel B to be updated

Selects DAC channel C to be updated

Selects DAC channel D to be updated

Selects DAC channel E to be updated

Selects DAC channel F to be updated

Selects DAC channel G to be updated

Selects DAC channel H to be updated

Invalid code, no action performed

Broadcast mode–selects all DAC channels to be

updated

Write to DAC Input Registers and Update DAC Register (Individual Software LDAC)

Write to DAC input register for channel A and

update channel A DAC register

Data[11:4]

Data[3:0]

Write to DAC input register for channel B and

update channel B DAC register

Data[11:4]

Write to DAC input register for channel C and

update channel C DAC register

Write to DAC input register for channel D and

update channel D DAC register

Write to DAC input register for channel E and

update channel E DAC register

Write to DAC input register for channel F and

update channel F DAC register

Write to DAC input register for channel G and

update channel G DAC register

Write to DAC input register for channel H and

update channel H DAC register

Data[3:0]

Invalid code, no action performed

Broadcast mode–write to all input registers and

update all DAC registers

Data[11:4]

Data[3:0]

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Table 17. Control Matrix for Write Commands (continued)

COMMAND AND ACCESS BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

DESCRIPTION

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6 DB5 DB4 DB3 DB2 DB1 DB0

Write to Select DAC Input Register and Update All DAC Registers (Global Software LDAC)

Write to DAC input register of channel A and

update all DAC registers

Data[11:4]

Data[3:0]

Write to DAC input register of channel B and

update all DAC registers

Data[11:4]

Data[3:0]

Write to DAC input register of channel C and

update all DAC registers

Write to DAC input register of channel D and

update all DAC registers

Write to DAC input register of channel E and

update all DAC registers

Write to DAC input register of channel F and

update all DAC registers

Write to DAC input register of channel G and

update all DAC registers

Write to DAC input register of channel H and

update all DAC registers

Data[3:0]

Invalid code, no action performed

Broadcast mode–write to all input registers and

update all DAC registers

Data[11:4]

Data[3:0]

Power-Down Register

PD1

PD0

DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H

Each DAC bit set to '1' powers on selected DACs

Each DAC bit set to '1' powers down selected

DACs. V_OUTconnected to GND through 1kΩ

pull-down resistor

DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H

Each DAC bit set to '1' powers down selected

DACs. V_OUTconnected to GND through 100kΩ

pull-down resistor

DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H

Each DAC bit set to '1' powers down selected

DACs. V_OUTis High Z

Clear Code Register

CL1

CL0

Write to clear code register, CLR pin will clear to

zero scale

Write to clear code register, CLR pin will clear to

midscale

Write to clear code register, CLR pin will clear to

full scale

Write to clear code register disables CLR pin

LDAC Register

When all DAC bits are set to '1', selected DACs

ignore the LDAC pin.

When all DAC bits are set to '0', selected DAC

registers update according to the LDAC pin.

DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A

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Table 17. Control Matrix for Write Commands (continued)

COMMAND AND ACCESS BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

DESCRIPTION

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4 DB3 DB2 DB1 DB0

Software Reset

Software reset (default). Equivalent to power-on

reset (POR).

Software reset that sets device into High-Speed

mode

Software reset that maintains High-Speed mode

state

Internal Reference in Regular/Static Mode

Disable internal reference (Regular/Static mode)

Enable internal reference (Regular/Static mode). If

any DACs are powered on, the reference is on. If

all DACS are powered down, then reference is off.

Internal Reference in Flexible Mode

TR2

TR1

TR0

Reference powers down when all DACs power

down. Reference powers on when any DACs are

powered on.

Reference is powered on regardless of DAC power

state

Reference is powered down regardless of DAC

power state

Reference follows Regular/Static mode reference

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Table 18. Control Matrix for Read Commands

COMMAND ACCESS BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

DESCRIPTION

DB15

DB14

DB13

DB12

DB11

DB10 DB9 DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Input Register

Data[11:4]

Data[3:0]

Read from DAC input register channel A

Read from DAC input register channel B

Read from DAC input register channel C

Read from DAC input register channel D

Read from DAC input register channel E

Read from DAC input register channel F

Read from DAC input register channel G

Read from DAC input register channel H

Invalid code

Data[3:0]

DAC Register

Data[11:4]

Data[3:0]

Read DAC A DAC register

Read DAC B DAC register

Read DAC C DAC register

Read DAC D DAC register

Read DAC E DAC register

Read DAC F DAC register

Read DAC G DAC register

Read DAC H DAC register

Invalid code

Power Down Register

PD1 PD0 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H Read power down register

Clear Code Register

CL1

CL0

Read clear code register

LDAC Register

DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A Read LDAC register

Internal Reference in Regular/Static Mode

Read reference register

Internal Reference in Flexible Mode

TR2

TR1

TR0

Read additional reference register

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POWER-ON RESET TO ZERO-SCALE OR

MID-SCALE

Alternatively, all DAC outputs can be updated

simultaneously using the built-in LDAC software

function. The LDAC register offers additional flexibility

and control, giving the ability to select which DAC

channel(s) should be updated simultaneously when

the hardware LDAC pin is being brought low. The

LDAC register is loaded with an 8-bit word (DB15 to

DB8) using control bits C3, C2, C1, and C0. The

default value for each bit, and therefore each DAC

channel, is zero and the external LDAC pin operates

in normal mode. If the LDAC register bit for a

selected DAC channel is set to '1', that DAC channel

ignores the external LDAC pin and updates only

through the software LDAC command. If, however,

the LDAC register bit is set to '0', the DAC channel is

controlled by the external LDAC pin.

The DAC7678 contains a power-on reset (POR)

circuit that controls the output voltage during

power-on. For devices housed in the TSSOP

package, at power-on, all DAC registers are filled with

zeros and the output voltages of all DAC channels

are set to zero-scale. For devices housed in the QFN

package, all DAC registers are set to have all DAC

channels power on depending of the state of the

RSTSEL pin.

The RSTSEL pin value is read at power-on and

should be set prior to or simultaneously with AV_DD

For RSTSEL set to AV_DD, the DAC channels are

loaded with midscale code. If RSTSEL is set to

ground, the DAC channels are loaded with zero-scale

code. All DAC channels remain in this state until a

valid write sequence and load command are sent to

the respective DAC channel. The power-on reset

function is useful in applications where it is important

to know the output state of each DAC while the

device is in the process of powering on.

This combination of

a software and hardware

simultaneous update function is particularly useful in

applications where only selective DAC channels are

to be updated simultaneously, while keeping the other

channels unaffected and updating those channels

synchronously.

The internal reference is powered off/down by default,

and remains that way until a valid reference-change

command is executed.

POWER-DOWN MODES

The DAC7678 has two separate sets of power-down

commands. One set is for the DAC channels and the

other set is for the internal reference. For more

information on powering down the reference see the

Enable/Disable Internal Reference section.

LDAC FUNCTIONALITY

The DAC7678 offers both software and hardware

simultaneous updates and control functions. The

DAC double-buffered architecture is designed so that

new data can be entered for each DAC without

disturbing the analog outputs.

DAC Power-Down Commands

The DAC7678 uses four modes of operation. These

modes are accessed by using control bits C3, C2,

C1, and C0. The control bits must be set to '0100'.

When the control bits are set correctly, the four

The DAC7678 data updates can be performed either

in synchronous or asynchronous mode.

different

power-down

modes

are

software

In synchronous mode, data are updated on the falling

edge of the acknowledge signal that follows LSDB.

For synchronous mode updates, the LDAC pin is not

required and must be connected to GND

permanently.

programmable by setting bits PD0 (DB13) and PD1

(DB14) in the control register. Table 19 shows how to

control the operating mode with data bits PD0 (DB13)

and PD1 (DB14). The DAC7678 treats the

power-down condition as data; all the operational

modes are still valid for power down. It is possible to

In asynchronous mode, the LDAC pin is used as a

broadcast

power-down condition to all the

negative-edge-triggered

timing

signal

for

DAC7678s in a system. It is also possible to

power-down a channel and update data on other

channels. Furthermore, it is possible to write to the

DAC register/buffer of the DAC channel that is

powered down. When the DAC channel is then

powered on, it will contain this new value.

asynchronous DAC updates. Multiple single-channel

updates can be performed in order to set different

channel buffers to desired values and then make a

falling edge on the LDAC pin. The data buffers of all

the channels must be loaded with the desired data

before an LDAC falling edge. After a high-to-low

LDAC transition, all DACs are simultaneously

updated with the last contents of the corresponding

data buffers. If the contents of a data buffer are not

changed by the serial interface, the corresponding

DAC output remains unchanged after the LDAC

trigger.

When both the PD0 and PD1 bits are set to '0', the

device works normally with its typical consumption of

1.49 mA at 5.5V. The reference is included with the

operation of all eight channels. However, for the three

power-down modes, the supply current falls to 0.42

µA at 5.5V (0.25 µA at 2.7V). Not only does the

supply current fall, but the output stage also switches

internally from the output amplifier to a resistor

network of known values as shown in Figure 93.

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The advantage of this switching is that the output

impedance of the device is known while it is in

power-down mode. As described in Table 19, there

are three different power-down options. V_OUTcan be

connected internally to GND through a 1kΩ resistor, a

100kΩ resistor, or open-circuited (High-Z). In other

words, C3, C2, C1, and C0 = '0100' and DB14 and

DB13 = '11' represent a power-down condition with

High-Z output impedance for a selected channel.

DB14 and DB13 = '01' represents a power-down

condition with 1kΩ output impedance and '10'

CLEAR CODE REGISTER AND CLR PIN

The DAC7678 contains a clear code register. The

clear code register can be accessed via the serial

interface (I²C) and is user configurable. Bringing the

CLR pin low clears the contents of all DAC registers

and all DAC buffers and replaces the code with the

code determined by the clear code register. The clear

code register can be written to by applying the

commands shown in Table 17. The default setting of

the clear code register sets the output of all DAC

channels to 0V when the CLR pin is brought low. The

CLR pin is falling-edge triggered; therefore, the

device exits clear code mode on the falling edge of

the acknowledge signal that follows LSDB of the next

write sequence. If the CLR pin is executed (brought

low) during a write sequence, this write sequence is

aborted and the DAC registers and DAC buffers are

cleared as described above.

represents

a power-down condition with 100kΩ

output impedance.

Table 19. DAC Operating Modes

PD1

(DB14) (DB13)

PD0

DAC OPERATING MODES

Power on selected DACs

Power down selected DACs, 1kΩ to GND

Power down selected DACs, 100kΩ to GND

Power down selected DACs, High-Z to GND

When performing a software reset of the device, the

clear code register is reset to the default mode (DB5

= '0', DB4 = '0'). Setting the clear code register to

DB4 = '1' and DB5 = '1' ignores any activity on the

external CLR pin.

SPACER

SOFTWARE RESET FUNCTION

Resistor

String

DAC

The DAC7678 contains a software reset feature.

When the software reset feature is executed, the

device (all DAC channels) are reset to the power-on

reset code. All registers inside the device are reset to

the respective default settings. The DAC7678 has an

additional feature of switching straight to high speed

mode after reset. Table 20 shows all the different

modes of the software reset function.

Amplifier

OUT

Power-Down

Circuitry

Resistor

Network

Table 20. Software Reset Modes

DB15

DB14

OPERATING MODES

Figure 93. Output Stage During Power-Down

SPACER

Default Software reset. Equivalent to

Power-on-Reset

Software reset and set part in High Speed

Mode

Software reset and maintain High Speed

Mode state

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OPERATING EXAMPLES: DAC7678

For the following examples X = don’t care; value can be either '0' or '1'.

I²C Standard and Fast mode examples (ADDR0 and LDAC pin tied low) (TSSOP package)

Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output

Command and

Access Byte

Start

Address

MSDB

LSDB

Stop

ACK

1001 0000

0000 0000

1000 0000

0000 XXXX

Channel A updates to Mid Scale after the falling edge of the last ACK cycle

SPACER

Example 2: Power-Down Channel B, C, and H with Hi-Z Output

Command and

Access Byte

Start

Address

MSDB

LSDB

Stop

ACK

1001 0000

0100 XXXX

X111 0000

110X XXXX

SPACER

Example 3: Read-back the value of the input register of Channel G

Command and

Access Byte

Repeated

Start

MSDB (from

DAC7678)

LSDB (from

DAC7678)

Start

Address

ACK

1001 0000

0000 0110

1001 0001

XXXX XXXX

XXXX 0000

SPACER

Example 4: Write multiple bytes of data to Channel F

Write Full Scale and then Quarter Scale to Channel F

Command and

Access Byte

Start

Address

MSDB

LSDB

1111 XXXX

MSDB

0100 0000

LSDB

0000 XXXX

Stop

ACK

ACK*

ACK

ACK**

1001 0000

0000 0101

1111 1111

Channel F updates to Full Scale after the falling edge of the 4th ACK* cycle and then Channel F updates to

quarter scale after falling edge of the last ACK** cycle.

I²C High Speed mode example (ADDR0 and LDAC pin tied low) (TSSOP package)

SPACER

Example 5: Write Mid Scale and then Full Scale to all DAC channels

Master

Code

Command

Address ACK and Access ACK

Byte

NOT Repeated

Start

MSDB

ACK

LSDB

ACK

MSDB

ACK

LSDB

ACK

Stop

ACK

Start

0000 1000

1001 0000

0011 1111

1000 0000

0000 XXXX

1111 1111

1111 XXXX

All Channels update to Mid Scale after the falling edge of the 4th ACK cycle and then all Channels update to Full

scale after falling edge of the last ACK cycle.

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APPLICATION INFORMATION

INTERNAL REFERENCE

Where:

V_{REF_MAX}= maximum reference voltage observed

The internal reference of the DAC7678 does not

require an external load capacitor for stability

because it is stable with any capacitive load.

However, for improved noise performance, an

external load capacitor of 100nF or larger connected

to the V_REFIN/V_REFOUToutput is recommended.

Figure 94 shows the typical connections required for

operation of the DAC7678 internal reference. A

supply bypass capacitor at the AV_DDinput is also

recommended.

within temperature range T_RANGE

V_{REF_MIN}= minimum reference voltage observed

within temperature range T_RANGE

V_REF= 2.5V, target value for reference output

voltage.

The internal reference features an exceptional

maximum drift coefficient of 25ppm/°C from –40°C to

125°C. Temperature drift results are summarized in

the Typical Characteristics.

DAC7678

Noise Performance

SCL

SDA

GND

LDAC

ADDR0

AV_DD

Typical 0.1Hz to 10Hz voltage noise can be seen in

Figure 7, Internal Reference Noise. Additional filtering

can be used to improve output noise levels, although

care should be taken to ensure the output impedance

does not degrade the ac performance. The output

noise spectrum at V_REFIN/V_REFOUTwithout any

external components is depicted in Figure 6, Internal

Reference Noise Density vs Frequency. Internal

reference noise impacts the DAC output noise; see

the DAC Noise Performance section for more details.

AV_DD

1mF

V_OUTB

V_OUT

CLR

V_REFIN/V_REFOUT

100nF

Load Regulation

Load regulation is defined as the change in reference

output voltage as a result of changes in load current.

The load regulation of the internal reference is

measured using force and sense contacts as shown

in Figure 5. The force and sense lines reduce the

impact of contact and trace resistance, resulting in

accurate measurement of the load regulation

contributed solely by the internal reference.

Measurement results are summarized in the Typical

Characteristics. Force and sense lines should be

used for applications that require improved load

regulation.

Figure 94. Typical Connections for Operating the

DAC7678 Internal Reference

Supply Voltage

The internal reference features an extremely low

dropout voltage. It can be operated with a supply of

only 5mV above the reference output voltage in an

unloaded condition. For loaded conditions, refer to

the Load Regulation section. The stability of the

internal reference with variations in supply voltage

(line regulation, dc PSRR) is also exceptional. Within

the specified supply voltage range of 2.7V to 5.5V,

the variation at V_REFIN/V_REFOUTis less than 100 µV/V;

see the Typical Characteristics.

Output Pin

Contact and

Trace Resistance

V_OUT

Force Line

Temperature Drift

I_L

The internal reference is designed to exhibit minimal

drift error, defined as the change in reference output

voltage over varying temperature. The drift is

calculated using the box method described by

Equation 3:

Sense Line

Load

Meter

Figure 95. Accurate Load Regulation of the

DAC7678 Internal Reference

- V_{REF_MIN}

REF_MAX

Drift Error =

´ 10⁶(ppm/°C)

V_REF´ T_RANGE

(3)

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Long-Term Stability

è 2ⁿ

æ R₁+ R₂

V_OUT

REF

´ Gain ´

- V_REF´

R₁

Long-term stability/aging refers to the change of the

output voltage of a reference over a period of months

or years. This effect lessens as time progresses (see

Figure 3, the typical long-term stability curve). The

typical drift value for the internal reference is 100ppm

from 0 hours to 2160 hours. This parameter is

characterized by powering-up 19 units and measuring

them at regular intervals for a period of 2160 hours.

(5)

Where:

D_IN= decimal equivalent of the binary code that

is loaded to the DAC register. It can range from 0

to 4095 (12 bit)

n = resolution in bits

Gain = 1 when External Reference is used and 2

when internal reference is used.

Thermal Hysteresis

Thermal hysteresis for a reference is defined as the

change in output voltage after operating the device at

25°C, cycling the device through the operating

temperature range, and returning to 25°C. Hysteresis

is expressed by Equation 4:

10 ´ D

- 5V

OUT

(6)

This result has an output voltage range of ±5V with

000h corresponding to a -5V output and FFFh

corresponding to a +5V output for the 12 bit

DAC7678.

æ |V_{REF_PRE}- V_{REF_POST}| ö

V_HYST= ç

÷ ´ 10⁶(ppm/°C)

V_{REF_NOM}

R₂

10kW

(4)

_REFEXT

Where:

+6V

R₁

10kW

V_HYST= thermal hysteresis

V_{REF_PRE}= output voltage measured at 25°C

pre-temperature cycling

V_{REF_POST}= output voltage measured after the

device cycles through the temperature range of

–40°C to 125°C, and returns to 25°C.

±5V

OPA703

AV_DD

V_OUT

V_REFIN

DAC7678

V_REFOUT

-6V

10mF

0.1mF

GND

Serial Interface

DAC NOISE PERFORMANCE

Typical noise performance for the DAC7678 with the

internal reference enabled is shown in Figure 47.

Output noise spectral density at the V_OUTXpin versus

frequency is depicted in Figure 47 for full-scale,

midscale, and zero-scale input codes. The typical

noise density for midscale code is 290nV/√Hz at

1kHz and 117nV/√Hz at 100 kHz when internal

reference is enabled. The typical noise density

reduces to 104nV/√Hz at 1kHz for mid scale code

with external reference as shown in Figure 48.

High-frequency noise can be improved by filtering the

reference noise. Integrated output noise between

0.1Hz and 10Hz is close to 3µVPP (midscale), as

shown in Figure 49.

Figure 96. Bipolar Output Range Using External

Reference at 5V

MICROPROCESSOR INTERFACING

A basic connection diagram to the SCL and SDA pins

of the DAC7678 is shown in Figure 97. The DAC7678

interfaces directly to standard mode, fast mode and

high speed mode of 2-Wire compatible serial

interfaces. The DAC7678 does not perform clock

stretching (pulling SCL low), as a result it is not

necessary to provide for this function unless other

devices on the same bus require this function. Pull-up

resistors are required on both the SDA and SCL lines

as the bus-drivers are open-drain. The size of these

pull-up resistors depends on the operating speed and

capacitance of the bus lines. Higher value resistors

consume less power but increase transition time on

the bus limiting the bus speed. Long bus lines have

higher capacitance and require smaller pull-up

resistors to compensate. The resistors should not be

too small; if they are, bus drivers may not be able to

pull the bus lines low.

BIPOLAR OPERATION USING THE DAC7678

The DAC7678 family of products is designed for

single-supply operation, but a bipolar output range is

also possible using the circuit in Figure 96. Rail-to-rail

operation at the amplifier output is achievable using

an OPA703 as the output amplifier.

The output voltage for any input code can be

calculated with Equation 5.

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CONNECTING MULTIPLE DEVICES

VDD

Pull-Up Resistors

1kW to 10kW (typ)

Multiple devices of DAC7678 family can be

connected on the same bus. Using the address pin,

the DAC7678 can be set to one of three different I²C

addresses for the TSSOP package and one of eight

addresses for the QFN package. An example

showing three DAC7678 devices in TSSOP package

is shown if Figure 98. Note that only one set of

pull-up resistors is needed per bus. The pull-up

resistor values may need to be lowered slightly to

compensate for the additional bus capacitance due to

multiple devices and increased bus length.

Microcontroller or

Microprocessor

with I²C Port

SCL

SDA

SCL

SDA

GND

LDAC

ADDR0

AV_DD

DAC7678

Top

View

V_OUTB

V_OUT

CLR

SCL

SDA

GND

LDAC

ADDR0

AV_DD

Leave

Floating

DAC7678

Top

View

V_OUTB

V_OUTA

V_OUTC

V_OUTE

V_OUTG

VDD

V_REFIN/V_REFOUT

V_OUT

Pull-Up Resistors

1kW to 10kW (typ)

Microcontroller or

Microprocessor

with I²C Port

CLR

V_REFIN/V_REFOUT

Figure 97. Typical Connections of the DAC7678

SCL

SDA

VDD

SCL

SDA

GND

SCL

SDA

GND

LDAC

ADDR0

AV_DD

LDAC

ADDR0

AV_DD

DAC7678

Top

View

DAC7678

Top

View

V_OUTB

V_OUTA

V_OUTC

V_OUTE

V_OUTG

V_OUTA

V_OUTC

V_OUTE

V_OUTG

V_OUT

CLR

V_OUT

CLR

V_REFIN/V_REFOUT

Figure 98. Typical Connections of the Multiple

DAC7678 on the Same Bus

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PARAMETER DEFINITIONS

With the increased complexity of many different

specifications listed in product data sheets, this

section summarizes selected specifications related to

digital-to-analog converters.

Full-Scale Error

Full-scale error is defined as the deviation of the real

full-scale output voltage from the ideal output voltage

while the DAC register is loaded with the full-scale

code (0xFFF). Ideally, the output should be AVDD – 1

LSB. The full-scale error is expressed in percent of

full-scale range (%FSR).

STATIC PERFORMANCE

Static performance parameters are specifications

such as differential nonlinearity (DNL) or integral

nonlinearity (INL). These are dc specifications and

provide information on the accuracy of the DAC. They

are most important in applications where the signal

changes slowly and accuracy is required.

Offset Error

The offset error is defined as the difference between

actual output voltage and the ideal output voltage in

the linear region of the transfer function. This

difference is calculated by using a straight line

defined by two codes (code 30 and 4050). Since the

offset error is defined by a straight line, it can have a

negative or positive value. Offset error is measured in

mV.

Resolution

Generally, the DAC resolution can be expressed in

different forms. Specifications such as IEC 60748-4

recognize the numerical, analog, and relative

resolution. The numerical resolution is defined as the

number of digits in the chosen numbering system

necessary to express the total number of steps of the

transfer characteristic, where a step represents both

a digital input code and the corresponding discrete

analogue output value. The most commonly-used

definition of resolution provided in data sheets is the

numerical resolution expressed in bits.

Zero-Code Error

The zero-code error is defined as the DAC output

voltage, when all '0's are loaded into the DAC

a measure of the

difference between actual output voltage and ideal

output voltage (0V). It is expressed in mV. It is

primarily caused by offsets in the output amplifier.

Gain Error

Least Significant Bit (LSB)

Gain error is defined as the deviation in the slope of

the real DAC transfer characteristic from the ideal

transfer function. Gain error is expressed as a

percentage of full-scale range (%FSR).

The least significant bit (LSB) is defined as the

smallest value in a binary coded system. The value of

the LSB can be calculated by dividing the full-scale

output voltage by 2ⁿ, where n is the resolution of the

converter.

Full-Scale Error Drift

Full-scale error drift is defined as the change in

full-scale error with

Most Significant Bit (MSB)

a change in temperature.

The most significant bit (MSB) is defined as the

largest value in a binary coded system. The value of

the MSB can be calculated by dividing the full-scale

output voltage by 2. Its value is one-half of full-scale.

Full-scale error drift is expressed in units of µV/°C.

Offset Error Drift

Offset error drift is defined as the change in offset

error with a change in temperature. Offset error drift

is expressed in µV/°C.

Relative Accuracy or Integral Nonlinearity (INL)

Relative accuracy or integral nonlinearity (INL) is

defined as the maximum deviation between the real

transfer function and a straight line passing through

the endpoints of the ideal DAC transfer function. INL

is measured in LSBs.

Zero-Code Error Drift

Zero-code error drift is defined as the change in

zero-code error with

a change in temperature.

Zero-code error drift is expressed in µV/°C.

Gain Temperature Coefficient

Differential Nonlinearity (DNL)

The gain temperature coefficient is defined as the

change in gain error with changes in temperature.

The gain temperature coefficient is expressed in ppm

of FSR/°C.

Differential nonlinearity (DNL) is defined as the

maximum deviation of the real LSB step from the

ideal 1LSB step. Ideally, any two adjacent digital

codes correspond to output analog voltages that are

exactly one LSB apart. If the DNL is less than 1LSB,

the DAC is said to be monotonic.

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Power-Supply Rejection Ratio (PSRR)

Channel-to-Channel DC Crosstalk

Power-supply rejection ratio (PSRR) is defined as the

ratio of change in output voltage to a change in

supply voltage for a full-scale output of the DAC. The

PSRR of a device indicates how the output of the

DAC is affected by changes in the supply voltage.

PSRR is measured in decibels (dB).

Channel-to-channel dc crosstalk is defined as the dc

change in the output level of one DAC channel in

response to a change in the output of another DAC

channel. It is measured with a full-scale output

change on one DAC channel while monitoring

another DAC channel remains at midscale. It is

expressed in LSB.

Monotonicity

DAC Output Noise Density

Monotonicity is defined as a slope whose sign does

not change. If a DAC is monotonic, the output

changes in the same direction or remains at least

constant for each step increase (or decrease) in the

input code.

Output noise density is defined as internally-

generated random noise. Random noise is

characterized as a spectral density (nV/√Hz). It is

measured by loading the DAC to midscale and

measuring noise at the output.

DYNAMIC PERFORMANCE

DAC Output Noise

Dynamic performance parameters are specifications

such as settling time or slew rate, which are important

in applications where the signal rapidly changes

and/or high frequency signals are present.

DAC output noise is defined as any voltage deviation

of DAC output from the desired value (within a

particular frequency band). It is measured with a DAC

channel kept at midscale while filtering the output

voltage within

measuring its amplitude peaks. It is expressed in

terms of peak-to-peak voltage (Vpp).

a band of 0.1Hz to 10Hz and

Slew Rate

The output slew rate (SR) of an amplifier or other

electronic circuit is defined as the maximum rate of

change of the output voltage for all possible input

signals.

Full-Scale Range (FSR)

Full-scale range (FSR) is the difference between the

maximum and minimum analog output values that the

DAC is specified to provide; typically, the maximum

and minimum values are also specified. For an n-bit

DAC, these values are usually given as the values

matching with code 0 and 2ⁿ–1.

DV_OUT(t)

SR = max

Where ΔV_OUT(t) is the output produced by the

amplifier as a function of time t.

LAYOUT

Output Voltage Settling Time

Settling time is the total time (including slew time) for

the DAC output to settle within an error band around

its final value after a change in input. Settling times

are specified to within ±0.003% (or whatever value is

specified) of full-scale range (FSR).

A precision analog component requires careful layout,

adequate bypassing, and clean, well-regulated power

supplies. The DAC7678 offers single-supply

operation, and is often used in close proximity with

digital logic, microcontrollers, microprocessors, and

digital signal processors. The more digital logic

present in the design and the higher the switching

speed, the more difficult it is to keep digital noise

from appearing at the output. As a result of the single

Code Change/Digital-to-Analog Glitch Energy

Digital-to-analog glitch impulse is the impulse injected

into the analog output when the input code in the

DAC register changes state. It is normally specified

as the area of the glitch in nanovolt-seconds (nV-s),

and is measured when the digital input code is

changed by 1LSB at the major carry transition.

ground

the

DAC7678,

all

return

currents(including digital and analog return currents

for the DAC) must flow through a single point. Ideally,

GND would be connected directly to an analog

ground plane. This plane would be separate from the

ground connection for the digital components until

they were connected at the power-entry point of the

system.

Digital Feed-through

Digital feed-through is defined as impulse seen at the

output of the DAC from the digital inputs of the DAC.

It is measured when the DAC output is not updated. It

is specified in nV-s, and measured with a full-scale

code change on the data bus; that is, from all '0's to

all '1's and vice versa.

The power applied to AVDD should be well-regulated

and low noise. Switching power supplies and dc/dc

converters often have high-frequency glitches or

spikes riding on the output voltage. In addition, digital

components can create similar high-frequency spikes

as their internal logic switches states. This noise can

easily couple into the DAC output voltage through

various paths between the power connections and

analog output. As with the GND connection, AVDD

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DAC7678

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SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

should be connected to a power-supply plane or trace

that is separate from the connection for digital logic

until they are connected at the power-entry point. In

addition, a 1µF to 10µF capacitor and 0.1µF bypass

capacitor are strongly recommended. In some

situations, additional bypassing may be required,

such as a 100µF electrolytic capacitor or even a Pi

filter made up of inductors and capacitors – all

designed to essentially low-pass filter the supply and

remove the high-frequency noise.

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Product Folder Link(s): DAC7678

DAC7678

SBAS493A –FEBRUARY 2010–REVISED AUGUST 2010

www.ti.com

REVISION HISTORY

Changes from Original (February 2010) to Revision A

Page

•

Changed the data sheet From: Product Preview status To : Production ............................................................................. 1

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Product Folder Link(s): DAC7678

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

0,10

0,65

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

16-Aug-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

DAC7678SPW

DAC7678SPWR

DAC7678SRGER

DAC7678SRGET

ACTIVE

TSSOP

VQFN

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Request Free Samples

2000

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Purchase Samples

RGE

Green (RoHS

& no Sb/Br)

VQFN

Green (RoHS

& no Sb/Br)

Request Free Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Aug-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC7678SPWR

DAC7678SRGER

DAC7678SRGET

TSSOP

VQFN

RGE

2000

3000

250

330.0

180.0

12.4

6.9

4.3

5.6

4.3

1.6

1.5

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Aug-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC7678SPWR

DAC7678SRGER

DAC7678SRGET

TSSOP

VQFN

RGE

2000

3000

250

346.0

190.5

346.0

212.7

29.0

31.8

Pack Materials-Page 2

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DAC7678SPWR [TI]

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