DAC7731 [TI]

具有内部 +10V 基准和串行 I/F 的 16 位单通道数模转换器;


型号：	DAC7731
厂家：	TEXAS INSTRUMENTS
描述：	具有内部 +10V 基准和串行 I/F 的 16 位单通道数模转换器转换器数模转换器
文件：	总23页 (文件大小：527K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC7731

SBAS249B – DECEMBER 2001 – REVISED NOVEMBER 2007

16-Bit, Voltage Output, Serial Input

DIGITAL-TO-ANALOG CONVERTER

DESCRIPTION

FEATURES

ꢀ LOW POWER: 150mW MAXIMUM

The DAC7731 is a 16-bit Digital-to-Analog Converter (DAC)

which provides 16 bits of monotonic performance over the

specified operating temperature range and offers a +10V

internal reference. Designed for automatic test equipment

and industrial process control applications, the DAC7731

output swing can be configured in a ±10V, ±5V, or +10V

range. The flexibility of the output configuration allows the

DAC7731 to provide both unipolar and bipolar operation by

pin strapping. The DAC7731 includes a high-speed output

amplifier with a maximum settling time of 5µs to ±0.003%

FSR for a 20V full-scale change and only consumes 100mW

(typical) of power.

ꢀ +10V INTERNAL REFERENCE

ꢀ UNIPOLAR OR BIPOLAR OPERATION

ꢀ SETTLING TIME: 5µs to ±0.003% FSR

ꢀ 16-BIT MONOTONICITY, –40°C TO +85°C

ꢀ ±10V, ±5V, OR +10V CONFIGURABLE VOLTAGE

OUTPUT

ꢀ RESET TO ZERO OR MID-SCALE

ꢀ DOUBLE-BUFFERED DATA INPUT

ꢀ DAISY-CHAIN FEATURE FOR MULTIPLE

DAC7731s ON A SINGLE BUS

The DAC7731 features a standard 3-wire, SPI-compatible

serial interface with double buffering to allow asynchronous

updates of the analog output as well as a serial data output

line for daisy-chaining multiple DAC7731s. A user program-

mable reset control forces the DAC output to either min-scale

(0000_h) or mid-scale (8000_h), overriding both the input and

DAC register values. The DAC7731 is available in a

SSOP-24 package and three performance grades specified

to operate from –40°C to +85°C.

ꢀ SMALL SSOP-24 PACKAGE

APPLICATIONS

ꢀ PROCESS CONTROL

ꢀ ATE PIN ELECTRONICS

ꢀ CLOSED-LOOP SERVO CONTROL

ꢀꢀMOTOR CONTROL

ꢀꢀDATA ACQUISITION SYSTEMS

REF_OUTREF_IN

V_REF

V_DDV_SSV_CC

REFADJ

R_OFFSET

Buffer

RFB2

REFEN

RSTSEL

RST

+10V

Reference

Control

Logic

LDAC

RFB1

SCLK

SDO

SDI

Enable

Input

DAC

V_OUT

AGND

DGND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

V_CCto V_SS........................................................................... –0.3V to +32V

_CCto AGND ...................................................................... –0.3V to +16V

_SSto AGND ...................................................................... –16V to +0.3V

AGND to DGND ................................................................... –0.3V to 0.3V

REF_INto AGND ..............................................................0V to V_CC– 1.4V

_DDto DGND ........................................................................ –0.3V to +6V

Digital Input Voltage to DGND ................................. –0.3V to V_DD+ 0.3V

Digital Output Voltage to DGND .............................. –0.3V to V_DD+ 0.3V

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range .........................................–65°C to +150°C

Junction Temperature (TJ Max) .................................................... +150°C

ESD damage can range from subtle performance degradation

tocompletedevicefailure. Precisionintegratedcircuitsmaybe

more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION⁽¹⁾

SPECIFIED

PACKAGE

DESIGNATOR

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER⁽²⁾

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE-LEAD

DAC7731E

SSOP-24

–40°C to +85°C

DAC7731E

Rails, 60

DAC7731E/1K

Tape and Reel,1000

DAC7731EB

SSOP-24

–40°C to +85°C

DAC7731EB

Rails, 60

DAC7731EB/1K

Tape and Reel, 1000

DAC7731EC

SSOP-24

–40°C to +85°C

DAC7731EC

Rails, 60

DAC7731EC/1K

Tape and Reel, 1000

NOTE: (1) For the most current package ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com.

PIN CONFIGURATION

PIN DESCRIPTIONS

NAME

DESCRIPTION

Top View

SSOP

V_CC

REF_OUT

REF_IN

Positive Analog Power Supply

Internal Reference Output

Reference Input

Internal Reference Trim. (Acts as a gain adjustment

input when the internal reference is used.)

Buffered Output from REF_IN, can be used to drive

external devices. Internally, this pin directly drives the

DAC's circuitry.

REFADJ

V_REF

V_CC

REF_OUT

REF_IN

REFADJ

V_REF

V_SS

R_OFFSET

AGND

RFB2

Offsetting Resistor

Analog ground

Feedback Resistor 2, used to configure DAC output

range.

Feedback Resistor 1, used to configure DAC output

range.

Summing Junction of the Output Amplifier

DAC Voltage Output

Digital Power Supply

Digital Ground

Reserved, Connect to DGND

No Connection

V_OUTreset; active LOW, depending on the state of

RSTSEL, the DAC register is either reset to mid-

scale or min-scale.

DAC register load control, rising dege triggered. Data

is loaded from the input register to the DAC register.

Serial Data Input. Data is latched into the input

Serial Data Output, delayed 16 SCLK clock cycles.

Chip Select, Active LOW

REFEN

RSTSEL

SCLK

RFB1

V_OUT

V_DD

DGND

TEST

R_OFFSET

AGND

RFB2

RFB1

SDO

SDI

DAC7731

LDAC

RST

LDAC

SDI

V_OUT

TEST

DGND

V_DD

SDO

SCLK

RSTSEL

Serial Clock Input

Reset Select; determines the action of RST. If HIGH,

RST will reset the DAC register to mid-scale. If LOW,

RST will reset the DAC register to min-scale.

Enables internal +10V reference (REF_OUT), active

LOW.

REFEN

V_SS

NOTE: RST, LDAC, SDI, CS and SCK are Schmitt-triggered inputs.

Negative Analog Power Supply

DAC7731

SBAS249B

www.ti.com

ELECTRICAL CHARACTERISTICS

All specifications at T_A= T_MINto T_MAX, V_CC= +15V, V_SS= –15V, V_DD= +5V, Internal refi⁄ence enabled, unless otherwise noted.

DAC7731E

TYP

DAC7731EB

TYP

DAC7731EC

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

ACCURACY

Linearity Error (INL)

±6

±5

±4

±3

±2

±3

±2

±1

LSB

_A= 25°C

Differential Linearity Error (DNL)

Monotonicity

Bits

Offset Error

Offset Error Drift

Gain Error

±0.1

ꢀ

% of FSR

ppm/°C

% of FSR

ppm/°C

ppm/V

±2

ꢀ

With Internal REF

With External REF

With Internal REF

At Full-Scale

±0.4

±0.25

±0.1

±0.15

ꢀ

Gain Error Drift

PSRR (V_CCor V_SS

±15

±10

ꢀ

±7

ꢀ

)

200

ꢀ

ANALOG OUTPUT⁽¹⁾

Voltage Output⁽²⁾

+11.4/–4.75

+11.4/–11.4

+11.4/–6.4

0 to 10

±10

±5

ꢀ

Output Current

±5

ꢀ

Ω

Output Impeadance

Maximum Load Capacitance

Short-Circuit Current

Short-Circuit Duration

0.1

200

±15

ꢀ

AGND

Indefinite

REFERENCE

Reference Output

9.96

400

±15

10.04

9.975

ꢀ

±10

10.025

ꢀ

±7

ꢀ

Ω

REF_OUTImpedance

REF_OUTVoltage Drift

REF_OUTVoltage Adjustment⁽³⁾

REF_INInput Range⁽⁴⁾

REF_INInput Current

REFADJ Input Range

ppm/°C

±25

4.75

ꢀ

V_CC– 1.4

ꢀ

Absolute Max Value that

can be applied is V_CC

ꢀ

REFADJ Input Impedance

ꢀ

kΩ

Ω

_REFOutput Current

_REFImpedance

–2

ꢀ

DYNAMIC PERFORMANCE

Settling Time to ±0.003%

20V Output Step

R_L= 5kΩ, C_L= 200pF,

with external REF_OUT

to REF_INfilter⁽⁵⁾

ꢀ

µs

Digital Feedthrough

Output Noise Voltage

100

ꢀ

nV-s

nV/√Hz

at 10kHz

DIGITAL INPUT

V_IH

V_IL

|I_H| < 10µA

|I_L| < 10µA

0.7 • V_DD

ꢀ

0.3 • V_DD

ꢀ

DIGITAL OUTPUT

V_OH

V_OL

I_OH= –0.8mA

I_OL= 1.6mA

3.6

0.4

POWER SUPPLY

V_DD

V_CC

V_SS

+4.75

+11.4

–15.75

+5.0

+5.25

+15.75

–11.4

–4.75

ꢀ

Bipolar Operation

Unipolar Opeation

I_DD

I_CC

I_SS

Power

100

–2.5

ꢀ

µA

Unloaded

No Load, Ext. Reference

No Load, Int. Reference

ꢀ

–4

ꢀ

100

150

+85

ꢀ

TEMPERATURE RANGE

Specified Performance

–40

°C

ꢀ Specifications same as grade to the left.

NOTES: (1) With minimum V_CC/V_SSrequirements, internal reference enabled.

(2) Please refer to the Theory of Operation section for more information with respect to output voltage configurations.

(3) See Figure 11 for gain and offset adjustment connection diagrams when using the internal reference.

(4) The minimum value for REF_INmust be equal to the greater of V_SS+14V and +4.75V, where +4.75V is the minimum voltage allowed.

(5) Reference low-pass filter values: 100kΩ, 1.0µF (see Figure 14).

DAC7731

SBAS249B

www.ti.com

TIMING CHARACTERISTICS

V_CC= +15V, V_SS= –15V, V_DD= 5V; R_L= 2kΩ to AGND; C_L= 200pF to AGND; all specifications –40°C to +85°C, unless otherwise noted.

DAC7731

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

t_WH

t_WL

SCLK HIGH Time

SCLK LOW Time

t_SDI

Setup Time: Data in valid before rising SCLK

Hold Time: Data in valid after rising SCLK

Setup Time: CS falling edge before first rising SCLK

Hold Time: CS rising edge after 16th rising SCLK

Delay Time: CS Falling Edge to Data Out valid, C_L= 20pF on SDO

Hold Time: Data Out valid after SCLK rising edge, C_L20pF on SDO

Delay Time: CS rising edge to SDO = High Impedance

CS HIGH Time

t_HDI

t_SCS

t_HSC

t_DDO

t_HDO

t_DDOZ

t_WCSH

t_WLDL

LDAC LOW Time

t_WLDH

t_SLD

LDAC HIGH Time

Setup Time: 16th Rising SCLK Before LDAC Rising Edge

Delay Time: LDAC rising edge to first SCLK rising edge of next

transfer cycle.

t_DLD

t_SCLK

Setup Time: CS High before falling SCLK edge following 16th

rising SCLK edge

t_SRS

t_HRS

t_WRL

t_S

Setup Time: RSTSEL Valid Before RST LOW

Hold Time: RSTSEL valid after RST HIGH

RST LOW Time

DAC V_OUTSettling Time

µs

INTERFACE TIMING

t_SCS

t_HCS

t_WCSH

t_WH

SCLK

t_WL

t_SCLK

t_HDI

t_SDI

B15

B14

B13

C15

B15

C14

C13

B13

C12

B12

SDI

t_DDO

Word B

A13

Word C

B14

t_HDO

A14

t_DDOZ

A15

SDO

t_DLD

Word B

t_WLDL

Word A

t_WLDH

LDAC

V_OUT

t_SLD

t_S

±0.003% of FSR

Error Bands

RESET TIMING

t_SRS

RSTSEL

t_HRS

t_WRL

RST

V_OUT

t_S

+FS

(RSTSEL = LOW)

–FS

Min-Scale

Mid-Scale

+FS

(RSTSEL = HIGH)

V_OUT

–FS

DAC7731

SBAS249B

www.ti.com

TYPICAL CHARACTERISTICS

T_A= +25°C (unless otherwise noted).

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

–2

–4

–6

Bipolar Configuration: V_OUT= –10V to +10V

–4

Bipolar Configuration: V_OUT= –10V to +10V

_A= 85°C, Internal Reference Enabled

_A= 25°C, Internal Reference Enabled

–6

2.0

1.5

2.0

1.5

1.0

0.5

0.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

OFFSET ERROR vs TEMPERATURE

1.00

0.75

0.50

_OUT= –10 to +10V

–2

–4

–6

V_OUT= 0 to +10V

Bipolar Configuration: V_OUT= –10V to +10V

_A= –40°C, Internal Reference Enabled

0.25

0.00

2.0

1.5

–0.25

–0.50

–0.75

–1.00

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

–40

–15

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Temperature (°C)

Digital Input Code

V_CCSUPPLY CURRENT vs DIGITAL INPUT CODE

GAIN ERROR vs TEMPERATURE

0.000

4.4

4.3

4.2

4.1

4.0

3.9

3.8

3.7

Bipolar Configuration: V_OUT= –10V to +10V

Internal Reference Enabled, T_A= 25°C

–0.010

–0.020

–0.030

–0.040

–0.050

–0.060

–0.070

–0.080

–0.090

–0.100

Ext. Ref, Unipolar Mode: V_OUT= 0 to +10V

Ext. Ref, Bipolar Mode: V_OUT= –10 to +10V

Int. Ref, Unipolar Mode: V_OUT= 0 to +10V

Int. Ref, Bipolar Mode: V_OUT= –10 to +10V

Load = 200pF, 2kΩ

–40

–15

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Temperature (°C)

Digital Input Code

DAC7731

SBAS249B

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

T_A= +25°C (unless otherwise noted).

V_CCSUPPLY CURRENT vs DIGITAL INPUT CODE

V_SSSUPPLY CURRENT vs DIGITAL INPUT CODE

3.4

–1.50

–1.75

–2.00

–2.25

–2.50

–2.75

Bipolar Configuration: V_OUT= –10V to +10V

External Reference, REFEN = 5V, T_A= 25°C

3.3

3.2

3.1

3.0

2.9

2.8

Bipolar Configuration: V_OUT= –10V to +10V

_A= 25°C

2.7

0000_H2000_H4000_H6000_H8000_HA000_HC000_HE000_HFFFF_H

Digital Input Code

SUPPLY CURRENT vs LOGIC INPUT VOLTAGE

SUPPLY CURRENT vs TEMPERATURE

1800

Load Current Excluded

T_A= 25°C, Transition

Shown for a Single

Input (Applies to CS,

SCLK,D_INand LDAC

inputs)

1600

1400

1200

1000

800

600

400

200

_CC= +15V, V_SS= –15V

Bipolar V_OUTConfiguration: –10V to +10V

I_CC

–1

–2

–3

I_SS

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

–40

–15

V_LOGIC(V)

Temperature (°C)

HISTOGRAM OF V_SSCURRENT CONSUMPTION

HISTOGRAM OF V_CCCURRENT CONSUMPTION

100

Bipolar Output Configuration

Internal Reference Enabled

Code = 5555_H

Bipolar Output Configuration

Internal Reference Enabled

Code = 5555_H

–3.50

–3.00

–2.50

–2.00

–1.50

3.000

3.500

4.000

4.500

5.000

I_SS(mA)

I_CC(mA)

DAC7731

SBAS249B

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

T_A= +25°C (unless otherwise noted).

POWER-SUPPY REJECTION RATIO vs FREQUENCY

(Measured at V_OUT

POWER-SUPPY REJECTION RATIO vs FREQUENCY

)

(Measured at V_OUT

)

Bipolar Configuration: ±10V V_OUT, Code FFFF_H

–V_SS, V_CC= 15V + 1Vp-p, V_DD= 5V + 0.5Vp-p

Bipolar Configuration: ±10V V_OUT

Code 8000_H

–10

–20

–30

–40

–50

–60

–70

–80

–V_SS, V_CC= 15V + 1Vp-p

–10

–20

–30

–40

–50

–60

–70

–80

_DD= 5V + 0.5Vp-p

V_SS

V_CC

V_SS

V_DD

V_CC

V_DD

0.01K

0.1K

10K

100K

10M

0.1K

10K

100K

10M

Frequency (Hz)

INTERNAL REFERENCE OUTPUT vs TEMPERATURE

INTERNAL REFERENCE START-UP

10.015

10.010

10.005

10.000

9.995

15V

10V

9.990

9.985

–40

–15

Time (2ms/div)

Temperature (°C)

OUTPUT VOLTAGE vs R_LOAD

Source

REF_OUTVOLTAGE vs LOAD

11.0

Loaded to V_CC

V_CC= +15V

10.5

10.0

9.5

–4

–8

–12

Sink

9.0

Loaded to AGND

8.5

0.0

0.1

1.0

10.0

100.0

100

R_LOAD(kΩ)

REF_OUTLOAD(kΩ)

DAC7731

SBAS249B

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

T_A= +25°C (unless otherwise noted).

POWER-SUPPY REJECTION RATIO vs FREQUENCY

(Measured at REF_OUT

)

OUTPUT NOISE vs FREQUENCY

900

800

700

600

500

400

300

200

100

Internal Reference Enabled

–V_SS, V_CC= 15V + 1Vp-p,

_DD= 5V + 0.5Vp-p

Unipolar Configuration, Internal Reference Enabled

–10

–20

–30

–40

–50

–60

–70

–80

V_CC

Code FFFF_H

V_DD

V_SS

Code 0000_H

100

10K

100K

10M

0.01K

0.1K

10K

100K

10M

Frequency (Hz)

BROADBAND NOISE

OUTPUT NOISE vs FREQUENCY

800

700

600

500

400

300

200

100

Bipolar Configuration: ±10V, Internal Reference Enabled

Code 0000_H

Code FFFF_H

Internal Reference Enabled

Filtered with 1.6Hz Low-Pass

Code FFFF_H, Bipolar ±10V Configuration

10kHz Measurement BW

Code 8000_H

0.01K

0.1K

10K

100K

10M

Time (100µs/div)

Frequency (Hz)

BIPOLAR FULL-SCALE SETTLING TIME

Large-Signal Output (5V/div)

UNIPOLAR FULL-SCALE SETTLING TIME

Large-Signal Output (5V/div)

Small-Signal Error (150µV/div)

Small-Signal Error (300µV/div)

Bipolar Configuration: V_OUT= –10 to +10V

–Full-Scale to +Full-Scale

Unipolar Configuration: V_OUT= 0 to +10V

Zero-Scale to +Full-Scale Change

5kΩ, 200pF Load

Time (2µs/div)

DAC7731

SBAS249B

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

T_A= +25°C (unless otherwise noted).

BIPOLAR FULL-SCALE SETTLING TIME

UNIPOLAR FULL-SCALE SETTLING TIME

Small-Signal Error (150µV/div)

Small-Signal Error (300µV/div)

Large-Signal Output (5V/div)

Unipolar Configuration: V_OUT= 0V to +10V

+Full-Scale to Zero-Scale Change

5kΩ, 200pF Load

Bipolar Configuration: V_OUT= –10 to +10V

+Full-Scale to –Full-Scale

5kΩ, 200pF Load

Time (2µs/div)

MID-SCALE GLITCH

Code 8000_Hto 7FFF_H

Code 7FFF_Hto 8000_H

Bipolar Configuration: ±10V V_OUT

Time (1µs/div)

DAC7731

SBAS249B

www.ti.com

The digital input is a serial word made up of the DAC code

(MSB first) and is loaded into the DAC register using the

LDAC input pin. The converter can be powered from ±12V

to ±15V dual analog supplies and a +5V logic supply. The

device offers a reset function, which immediately sets the

DAC output voltage and DAC register to min-scale (code

0000_H) or mid-scale (code 8000_H). The data I/O and reset

functions are discussed in more detail in the following sec-

tions.

THEORY OF OPERATION

The DAC7731 is a voltage output, 16-bit DAC with a +10V

built-in internal reference. The architecture is an R-2R ladder

configuration with the three MSBs segmented, followed by

an operational amplifier that serves as a buffer, as shown in

Figure 1. The output buffer is designed to allow user-

configurable output adjustments giving the DAC7731 output

voltage ranges of 0V to +10V, –5V to +5V, or –10V to +10V.

Please refer to Figures 2, 3, and 4 for pin configuration

information.

R_OFFSET

RFB2

REF_IN

V_REF

REF_ADJ

REF_OUT

R/4

Buffer

RFB1

+10V Internal

Reference

R/2

R/4

V_OUT

V_REF

AGND

FIGURE 1. DAC7731 Architecture.

V_CC

DAC7731

V_SS

0.1µF

1µF

0.1µF

1µF

V_CC

V_SS

REFEN

RSTSEL

SCLK

V_CC

V_SS

REFEN

RSTSEL

SCLK

1µF

0.1µF

REF_OUT

REF_IN

REFADJ

V_REF

1µF

0.1µF

REF_OUT

REF_IN

REFADJ

V_REF

Control/Data

Bus

Control/Data

Bus

R_OFFSET

AGND

RFB2

RFB1

SDO

R_OFFSET

AGND

RFB2

RFB1

SDO

SDI

LDAC

RST

LDAC

RST

V_OUT

TEST

DGND

(–5V to +5V)

V_OUT

TEST

DGND

(0V to +10V)

V_DD

0.1µF

1µF

0.1µF

1µF

FIGURE 3. Basic Operation: V_OUT= –5V to +5V.

FIGURE 2. Basic Operation: V_OUT= 0V to +10V.

DAC7731

SBAS249B

www.ti.com

DAC7731 output amplifier into one of three voltage output

modes as discussed earlier. V_REFcan also be used to drive

other system components requiring an external reference.

V_CC

DAC7731

V_SS

0.1µF

1µF

V_CC

V_SS

REFEN

RSTSEL

SCLK

1µF

0.1µF

REF_OUT

REF_IN

REFADJ

V_REF

REFEN

ACTION

Internal Reference disabled;

REF_OUT= High Impedance

Internal Reference enabled;

REF_OUT= +10V

Control/Data

Bus

R_OFFSET

AGND

RFB2

RFB1

SDO

TABLE I. REFEN Action.

SDI

LDAC

RST

The internal reference of the DAC7731 can be disabled when

use of an external reference is desired. When using an

external reference, the reference input, REF_IN, can be any

voltage between 4.75V (or V_SS+ 14V, whichever is greater)

and V_CC– 1.4V.

V_OUT

TEST

DGND

(–10V to +10V)

V_DD

0.1µF

1µF

DIGITAL INTERFACE

Table II shows the input data format for the DAC7731 and

Table III illustrates the basic control logic of the device. The

serial interface consists of a chip select input (CS), serial data

clock input (SCLK), serial data input (SDI), serial data output

(SDO), and load control input (LDAC). An asynchronous reset

input (RST), which is active LOW, is provided to simplify start-

up conditions, periodic resets, or emergency resets to a known

state, depending on the status of the reset select (RSTSEL)

signal. Please refer to the DAC Reset section for additional

information regarding the reset operation.

FIGURE 4. Basic Operation: V_OUT= –10V to +10V.

ANALOG OUTPUTS

The output amplifier can swing to within 1.4V of the supply

rails, specified over the –40°C to +85°C temperature range.

This allows for a ±10V DAC voltage output operation from

±12V supplies with a typical 5% tolerance.

When the DAC7731 is configured for a unipolar, 0V to 10V

output, a negative voltage supply is required. This is due to

internal biasing of the output stage. Please refer to the

Electrical Characteristics table (see page 3) for more infor-

mation.

ANALOG OUTPUT

DIGITAL INPUT

Unipolar Configuration

Bipolar Configuration

Unipolar Straight Binary

Bipolar Offset Binary

0x0000

0x0001

Zero (0V)

–Full-Scale (–V_REFor –V_REF/2)

The minimum and maximum voltage output values are de-

pendent upon the output configuration implemented and

reference voltage applied to the DAC7731. Please note that

V_SS(the negative power supply) must be in the range of

–4.75V to –15.75V for unipolar operation. The voltage on V_SS

sets several bias points within the converter and is required

in all modes of operation. If V_SSis not in one of these two

configurations, the bias values may be in error and proper

operation of the device is not ensured.

Zero + 1LSB

–Full-Scale + 1LSB

1/2 Full-Scale

1/2 Full-Scale + 1LSB

Bipolar Zero

Bipolar Zero + 1LSB

0x8000

0x8001

0xFFFF

Full-Scale (V_REF– 1LSB) +Full-Scale (+V_REF– 1LSB

or +V_REF/2 – 1LSB)

TABLE II. DAC7731 Data Format.

Supply sequence is important in establishing the correct

startup of the DAC. The following supply sequence must be

followed: V_SS(device substrate) first, then V_DDfollowed by

CONTROL STATUS

COMMAND

CS RST RSTSEL LDAC SCLK

ACTION

Shift Register is disabled on the serial bus.

V_CC. In addition, each supply must reach the values specified

Enable SDO pin from High Impedance;

enables shift operation and I/O bus

(SCLK, SDI, SDO).

in the Electrical Characteristics table (see page 3) within

100ms of its ramp start.

↑

Serial Data Shifted into Input Register

Serial Data Shifted into Input Register⁽¹⁾

Data in Input Register is Loaded into DAC Register.

Resets Input and DAC Registers to mid-scale.

Resets Input and DAC Registers to min-scale.

REFERENCE INPUTS

The DAC7731 provides a built-in +10V voltage reference and

on-chip buffer to allow external component reference drive. To

use the internal reference, REFEN must be LOW, enabling the

reference circuitry of the DAC7731 (as shown in Table I) and

the REF_OUTpin must be connected to REF_IN. This is the input

to the on-chip reference buffer. The buffer output is provided

at the V_REFpin. In this configuration, V_REFis used to setup the

NOTE: (1) In order to avoid unwanted shifting of the input register by an

additional bit, care must be taken that a rising edge on CS only occurs

when SCLK is HIGH.

TABLE III. DAC7731 Logic Truth Table.

DAC7731

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The DAC code is provided via a 16-bit serial interface, as shown

in Table II. The digital input word makes up the digital code to

be loaded into the data input register of the device. A typical

data transfer and DAC output update take place as follows:

Once CS is active (LOW), the DAC7731 is enabled on the serial

bus and the 16-bit serial data transfer can begin. The serial data

is shifted into the device on each rising SCLK edge until all 16

bits are transferred (1 bit per 1 rising SCLK edge). Once

received, the data in the input register is loaded into the DAC

command). This action updates the analog output, V_OUT, to the

desired voltage specified by the digital input word. A rising edge

on LDAC is completely asynchronous to the serial interface of

the device and can occur at any time. Care must be taken to

ensure that the entire 16 bits of data are loaded into the input

commands will have no effect on the DAC output if the data in

the input register is unchanged between rising LDAC edges.

When CS is returned HIGH, the rising edge on CS must

occur when SCLK is HIGH. Application of a rising CS edge

when SCLK is LOW will cause one additional shift in the

serial input shift register, corrupting the desired input data.

TIMING CONSIDERATIONS

The flexible interface of the DAC7731 can operate under a

number of different scenarios as is required by a host

controller. Critical timing for a 16-bit data transfer cycle is

shown in the Interface Timing section of the Timing Charac-

teristics. While this is the most common method of writing to

the DAC7731, the device accepts two additional modes of

data transfer from the host. These are byte transfer mode

and continuous transfer mode.

Byte transfer mode is especially useful when an 8-bit host is

communicating with the DAC. Data transfer can occur with-

out requiring an additional general purpose I/O pin to control

the CS input of the DAC in cycles of 16 clocks. A HIGH state

on CS stops data from coming into and out of the internal

shift register. This provides byte-wide support for 8-bit host

processors. Figure 5 is an example of the timing cycle of

such a data transfer.

The remaining data transfer mode accepted by the DAC7731

is continuous transfer. The CS of the DAC7731 can be tied

LOW or held LOW by the controller for an indefinite number of

serial clock cycles. Each clock cycle will transfer data into the

16-Bit Data Word

Most Significant Byte

Least Significant Byte

SCLK

SDI

B15

B14

B13

Byte 1, Word N

A13

Byte 2, Word N

A15

A14

SDO

Byte 2, Word N – 1

Byte 1, Word N – 1

LDAC

FIGURE 5. Byte-Wide Data Write Cycle.

SCLK

SDI

B15

B14

C15

C14

D15

D14

Word N

Word N + 1

Word N

Word N + 2

C14

A15

A14

B15

B14

C15

SDO

Word N – 1

Word N + 1

LDAC

FIGURE 6. Continuous Transfer Control.

DAC7731

SBAS249B

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DAC via SDI and out of the DAC on SDO. Care must be taken

that the LDAC signal to the DAC(s) is timed correctly so that

valid data is transferred into the DAC register on each rising

LDAC edge. (Valid data refers to the serial data latched on

each of the 16 rising SCLK edges prior to the occurrence of a

rising LDAC signal.) The rising edge of LDAC must occur

before the first rising SCLK edge of the following 16-bit

transfer. Figure 6 shows continuous transfer timing.

cycle written into the chain will arrive at the last DAC7731 on

the final cycle of the data transfer. Upon completion of the

required number of data transfer cycles (one cycle per

device), each DAC voltage output is updated with a rising

edge on the LDAC inputs. Figure 7 shows the required timing

to properly update two DAC7731s in a daisy-chained con-

figuration, as shown in Figure 8.

DAC RESET

DAISY-CHAINING USING SDO

The RST and RSTSEL inputs control the reset of the analog

output. The reset command is level triggered by a low signal on

RST. Once RST is LOW, the DAC output will begin settling to

the mid-scale or min-scale code depending on the state of the

RSTSEL input. A HIGH value on RSTSEL will cause V_OUTto

reset to the mid-scale code (8000_H) and a LOW value will reset

Multiple DAC7731s can be connected to a single serial port

by attaching each of their control inputs in parallel and daisy-

chaining the SDO and SDI I/Os of each device. The SDO

output of the DAC7731 is active when CS is LOW and can

be left unconnected when not required for use in a daisy-

chain configuration.

V_OUTto min-scale (8000_H). A change in the state of the RSTSEL

Once a data transfer cycle begins, new data is shifted into

SDI and data currently residing in the shift register (from

previous cycle, power-up, or reset command) is presented

on SDO, MSB first. One data transfer cycle for each DAC7731

is required to update all devices in the chain. The first data

input while RST is LOW will cause a corresponding change in

the reset command selected internally and consequently change

the output value of V_OUTof the DAC. Note that a valid reset

signal also resets the input register of the DAC to the value

specified by the state of RSTSEL.

Both DAC V_OUT's

are updated

LSBs latched

SCLK

LDAC

First Data Transfer Cycle

A15 A14

SDI

B15

A15

B14

A14

Previous cycle word from host

(to DAC7731 B SDI)

SDO

FIGURE 7. DAC7731 Daisy-Chain Timing for Figure 7.

From Host

Controller

To next

DAC7731

V_CC

V_SS

REFEN

RSTSEL

SCLK

V_CC

V_SS

REFEN

REF_OUT

REF_IN

REFADJ

V_REF

REF_OUT

REF_IN

REFADJ

V_REF

RSTSEL

SCLK

R_OFFSET

AGND

RFB2

RFB1

SDO

R_OFFSET

AGND

RFB2

RFB1

SDO

SDI

LDAC

RST

LDAC

RST

V_OUT

TEST

DGND

V_OUT

TEST

DGND

V_DD

First Device in Chain

Second Device in Chain

FIGURE 8. DAC7731 Daisy-Chain Schematic.

DAC7731

SBAS249B

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at +10V – 1LSB for the 0V to +10V or ±10V output range and

+5V – 1LSB for the ±5V output range. Figure 11 shows the

generalized external offset and gain adjustment circuitry

using potentiometers.

APPLICATIONS

GAIN AND OFFSET CALIBRATION

The architecture of the DAC7731 is designed in such a way

as to allow for easily configurable offset and gain calibration

using a minimum of external components. The DAC7731

has built-in feedback resistors and output amplifier summing

points brought out of the package in order to make the

absolute calibration possible. Figures 9 and 10 illustrate the

relationship of offset and gain adjustments for the DAC7731

in a unipolar configuration and in a bipolar configuration,

DAC7731

Optional Gain

Adjust

respectively.

R_POT1

Optional Offset

(+V_REF

)

I_SJ

Adjust

+ Full Scale

Gain Adjust

Rotates

(Other Connections Omitted

for Clarity)

R₁

1LSB

the Line

R_S

R_POT2

V_OADJ

–

Input =

0000_H

Input =

FFFF_H

FIGURE 11. Generalized External Calibration Circuitry for

Gain and Symmetrical Offset Adjustment.

Zero Scale

(AGND)

Digital Input

OFFSET ADJUSTMENT

Offset Adjust Translates the Line

Offset adjustment is accomplished by introducing a small

current into the summing junction (SJ) of the DAC7731. The

voltage at SJ, or V_SJ, is dependent on the output configura-

tion of the DAC7731. See Table IV for the required pin

strapping for a given configuration and the nominal values of

FIGURE 9. Relationship of Offset and Gain Adjustments for

V_OUT= 0V to +10V Output Configuration.

(+V_REFor +V_REF/2)

V_SJfor each output range.

+ Full

Scale

(1)

REFERENCE

OUTPUT

PIN STRAPPING

V_SJ

1LSB

CONFIGURATION CONFIGURATION R_OFFSETRFB1 RFB2

Input =

0000_H

Internal

Reference

0V to +10V

–10V to +10V

–5V to +5V

to V_REFto V_OUTto V_OUT

NC NC

to AGND to V_OUTto V_OUT+1.666V

+5V

Gain

Adjust

Rotates

to V_OUT+3.333V

External

Reference

0V to V_REF

–V_REFto V_REF

–V_REF/2 to V_REF/2 to AGND to V_OUTto V_OUTV_REF/6

to V_REFto V_OUTto V_OUTV_REF/2

the Line

Offset

to V_OUTV_REF/3

Adjust

Translates

the Line

NOTE: (1) Voltage measured at V_SJfor a given configuration.

TABLE IV. Nominal V_SJversus V_OUTand Reference Configu-

ration.

Input =

FFFF_H

Input = 8000_H

– Full-Scale

(–V_REFOR –V_REF/2)

The current level required to adjust the DAC7731’s offset can

be created by using a potentiometer divider as shown in

Figure 11 Another alternative is to use a unipolar DAC in order

to apply a voltage, V_OADJ, to the resistor R_S. A ±2uA current

range applied to SJ will ensure offset adjustment coverage of

the ±0.1% maximum offset specification of the DAC7731.

Digital Input

FIGURE 10. Relationship of Offset and Gain Adjustments for

_OUT=–10Vto+10VOutputConfiguration.(Same

Theory Applies for V_OUT= –5V to +5V.)

When in a unipolar configuration (V_SJ= 5V), only a single

resistor, R_S, is needed for symmetrical offset adjustment with

a 0V to 10V V_OADJrange. When in one of the two bipolar

configurations, V_SJis either +3.333V (±10V range) or +1.666V

(±5V range), and circuit values chosen to match those given

in Table V will provide symmetrical offset adjust. Please refer

When calibrating the DAC output, offset should be adjusted

first to avoid first order interaction of adjustments. In unipolar

mode, the DAC7731 offset is adjusted from code 0000_Hand

for either bipolar mode, offset adjustments are made at code

8000_H. Gain adjustment can then be made at code FFFF_Hfor

each configuration, where the output of the DAC should be

to Figure 11 for component configuration.

DAC7731

SBAS249B

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OUTPUT

CONFIGURATION

R_POT2

R₁

R_S

I_SJ

RANGE

NOMINAL

OFFSET

REF_OUTADJUST RANGE

ADJUSTMENT

0V to +10V

–10V to +10V

–5V to +5V

10K

20K

2.5M

1.5M

±2µA

±2.2µA

±1.7µA

±25mV

±55mV

±21mV

Typical REF_OUT

Adjustment Range

TABLE V. Recommended External Component Values for

Symmetrical Offset Adjustment (V_REF= 10V).

Minimum REF_OUT

Adjustment Range

–10

–20

–30

–40

Figure 12 illustrates the typical minimum offset adjustment

ranges provided by forcing a current at SJ for a given output

voltage configuration.

REFADJ (V)

OFFSET ADJUST RANGE

FIGURE 13. Internal Reference Adjustment Transfer Charac-

teristic.

–10V to +10V V_OUT

typ

Configuration

min (75% of typ)

VOLTAGE AT REFADJ

REF_OUTVOLTAGE

typ

REFADJ = 0V

REFADJ = 5V or NC⁽¹⁾

REFADJ = 10V

10V + 25mV (min)

10V

10V – 25mV (max)

min (75% of typ)

0V to 10V and –5V to +5V

V_OUTConfiguration

NOTE: NC = Not Connected.

–25

–50

TABLE VI. Minimum Internal Reference Adjustment Range.

NOISE PERFORMANCE

–2

–1

Increased noise performance of the DAC output can be

achieved by filtering the voltage reference input to the DAC7731.

Figure 14 shows a typical internal reference filter schematic. A

low-pass filter applied between the REF_OUTand REF_INpins can

increase noise immunity at the DAC and output amplifier. The

REF_OUTpin can source a maximum of 50µA so care should be

taken in order to avoid overloading the internal reference output.

I_SJ(µA)

FIGURE 12. Offset Adjustment Transfer Characteristic.

GAIN ADJUSTMENT

When using the internal reference of the DAC7731, gain

adjustment is performed by adjusting the device’s internal

reference voltage via the reference adjust pin, REFADJ. The

effect of a reference voltage change on the gain of the DAC

output can be seen in the generic equation (for unipolar

configuration):

DAC7731

V_CC

V_SS

REFEN

RSTSEL

SCLK

Low-Pass Reference Filter

REF_OUT

REF_IN

REFADJ

V_REF

_OUT= V_REFIN• (N/65536)

1.0µF

100kΩ

Where N is represented in decimal format and ranges from

0 to 65535.

REFADJ can be driven by a low impedance voltage source

such as a unipolar, 0V to +10V DAC or a potentiometer (less

than 100kΩ), see Figure 11. Since the input impedance of

REFADJ is typically 50kΩ, the smaller the resistance of the

potentiometer, the more linear the adjustment will be. A 10kΩ

potentiometer is suggested if linearity of the reference adjust-

ment is of concern.

R_OFFSET

AGND

RFB2

RFB1

SDO

SDI

LDAC

RST

When the DAC7731’s internal reference is not used, gain

adjustments can be made via trimming the external refer-

ence applied to the DAC at REF_IN. This can be accomplished

through using a potentiometer, unipolar DAC, or other means

of precision voltage adjustment to control the voltage pre-

sented to the DAC7731 by the external reference. Figure 13

and Table VI summarize the range of adjustment of the

internal reference via REFADJ.

V_OUT

TEST

DGND

V_DD

(Other connections omitted for clarity.)

FIGURE 14. Filtering the Internal Reference.

DAC7731

SBAS249B

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The voltages applied to V_CCand V_SSshould be well regulated

and low noise. Switching power supplies and DC/DC convert-

ers will often have high-frequency glitches or spikes riding on

the output voltage. In addition, digital components can create

similar high-frequency spikes as their internal logic switches

states. This noise can easily couple into the DAC output

voltage through various paths between the power connec-

tions and analog output.

LAYOUT

A precision analog component requires careful layout, adequate

bypassing, and clean, well-regulated power supplies. The

DAC7731 offers separate digital and analog supplies, as it will

often be used in close proximity with digital logic, microcontrollers,

microprocessors, and digital signal processors. The more digital

logic present in the design and the higher the switching speed,

the more important it will become to separate the analog and

digital ground and supply planes at the device.

In addition, a 1µF to 10µF bypass capacitor in parallel with a

0.1µF bypass capacitor is strongly recommended for each

supply input. In some situations, additional bypassing may be

required, such as a 100µF electrolytic capacitor or even a Pi

filter made up of inductors and capacitors–all designed to

essentially low-pass filter the analog supplies, removing any

high frequency noise components.

Since the DAC7731 has both analog and digital ground pins,

return currents can be better controlled and have less effect

on the DAC output error. Ideally, AGND would be connected

directly to an analog ground plane and DGND to the digital

ground plane. The analog ground plane would be separate

from the ground connection for the digital components until

they were connected at the power-entry point of the system.

DAC7731

SBAS249B

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PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DAC7731E

DAC7731E/1K

DAC7731EB

ACTIVE

SSOP

RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 85

DAC7731E

1000 RoHS & Green

60 RoHS & Green

1000 RoHS & Green

60 RoHS & Green

1000 RoHS & Green

60 RoHS & Green

NIPDAU

Call TI

DAC7731E

DAC7731EB/1K

DAC7731EC

ACTIVE

SSOP

Call TI

Level-3-260C-168 HR

-40 to 85

DAC7731E

DAC7731EC/1K

DAC7731ECG4

DAC7731E

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC7731E/1K

DAC7731EB/1K

DAC7731EC/1K

SSOP

1000

330.0

16.4

8.2

8.8

2.5

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC7731E/1K

DAC7731EB/1K

DAC7731EC/1K

SSOP

1000

356.0

35.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2023

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

DAC7731E

DAC7731EB

DAC7731EC

DAC7731ECG4

SSOP

530

10.5

4000

4.1

Pack Materials-Page 3

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

0,15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

0,25

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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