DAC7822 [TI]
12 位双通道并行输入乘法数模转换器;
| 型号： | DAC7822 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 位双通道并行输入乘法数模转换器 转换器 数模转换器 |
| 文件： | 总24页 (文件大小：1177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC7822
SBAS374A–JUNE 2006–REVISED JULY 2007
Dual, 12-Bit, Parallel Input, Multiplying
Digital-to-Analog Converter
FEATURES
DESCRIPTION
•
•
•
±1LSB INL
The DAC7822 is a dual, CMOS, 12-bit, current
output digital-to-analog converter (DAC). This device
operates from a 2.5V to 5.5V power supply, making it
suitable for battery-powered and many other
applications.
2.5V to 5.5V Supply Operation
Fast Parallel Interface:
17ns Write Cycle
•
•
•
•
Update Rate of 20.4MSPS
10MHz Multiplying Bandwidth
±15V Reference Input
The DAC7822 operates with a fast parallel interface.
Data readback allows the user to read the contents
of the DAC register via the DB pins. On power-up,
the internal register and latches are filled with zeroes
and the DAC outputs are at zero scale.
Extended Temperature Range:
–40°C to +125°C
The
DAC7822
offers
excellent
4-quadrant
•
•
•
•
•
•
•
40-Lead QFN
multiplication characteristics, with large signal
multiplying bandwidth of 10MHz. The applied
external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback
resistor (RFB) provides temperature tracking and
full-scale voltage output when combined with an
external current-to-voltage precision amplifier. The
DAC7822 also includes the resistors necessary for
4-quadrant multiplication and other configuration
modes.
12-Bit Monotonic
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Readback Function
Industry-Standard Pin Configuration
Pin-Compatible with the AD5405
APPLICATIONS
•
•
•
•
•
•
•
Portable Battery-Powered Instruments
Waveform Generators
Analog Processing
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Ultrasound
The DAC7822 is available in
package.
a 40-lead QFN
R3A
R2_3A
R2A VREF
A
R1A
R3
R2
R1
RFB
2R
2R
2R
2R
RFBA
VDD
DB0
DATA
IOUT1A
IOUT2A
INPUT
12-Bit
INPUTS
LATCH
BUFFER
R-2R DAC A
DB11
DAC A/B
CS
CONTROL
LOGIC
IOUT1B
IOUT2B
12-Bit
R/W
LATCH
R-2R DAC B
LDAC
CLR
R3
R2
2R
R1
RFB
2R
2R
2R
POWER-ON
RESET
GND
RFB
B
R3B
R2_3B
R2B VREF
B
R1B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
DAC7822
www.ti.com
SBAS374A–JUNE 2006–REVISED JULY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
DAC7822
–0.3 to +7.0
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–40 to +125
–65 to +150
+150
UNIT
V
VDD to GND
Digital input voltage to GND
VOUT to GND
V
V
Operating temperature range
Storage temperature range
Junction temperature (TJ max)
ESD Rating, HBM
°C
°C
°C
V
2000
ESD Rating, CDM
1000
V
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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SBAS374A–JUNE 2006–REVISED JULY 2007
ELECTRICAL CHARACTERISTICS
VDD = +2.5V to +5.5V; IOUT1 = Virtual GND; IOUT2 = 0V; VREF = 10V; TA = full operating temperature. All specifications –40°C
to +125°C, unless otherwise noted.
DAC7822
PARAMETER
STATIC PERFORMANCE
Resolution
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
LSB
nA
Relative accuracy
±1
±1
Differential nonlinearity
Output leakage current
Output leakage current
Full-scale gain error
Full-scale tempco(1)
Data = 000h, TA = +25°C
±1
Data = 000h, TA = TMAX
±15
±25
nA
All ones loaded to DAC register
±10
±5
mV
ppm/°C
mV
Bipolar zero-code error
Output capacitance
Circuit configuration as shown in Figure 41
DAC latches leaded with all 1s
±25
25
30
pF
REFERENCE INPUT
VREF range
–15
8
15
12
V
VREFA, VREFB, Input resistance
R1, RFB resistance
10
20
kΩ
kΩ
kΩ
%
17
17
25
R2, R3 resistance
20
25
VREFA to VREFB Input Mismatch
R2 to R3 Mismatch
1.6
0.06
2.5
0.18
%
LOGIC INPUTS AND OUTPUT(1)
VDD = +2.5V
VDD = +5V
VDD = +2.5V
VDD = +5V
0.6
0.8
V
V
Input low voltage
Input high voltage
VIL
VIH
2.1
2.4
V
V
Input leakage current
Input capacitance
IIL
1
µA
pF
CIL
10
POWER REQUIREMENTS
VDD
2.5
5.5
5
V
IDD (normal operation)
VDD = +4.5V to +5.5V
VDD = +2.5V to +3.6V
AC CHARACTERISTICS(1)
Output voltage settling time
Reference multiplying BW
Logic inputs = 0V
µA
µA
µA
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
0.8
0.4
5
2.5
0.2
µs
VREF = 7VPP, Data = FFFh
10
10
MHz
VREF = 0V to 10V,
Data = 7FFh to 800h to 7FFh
DAC glitch impulse
nV-s
Feedthrough error VOUT/VREF
Digital feedthrough
Data = 000h, VREF = 100kHz
–70
2
dB
nV-s
dB
Total harmonic distortion
Output spot noise voltage
–105
25
nV/√Hz
(1) Specified by design and characterization; not production tested.
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SBAS374A–JUNE 2006–REVISED JULY 2007
TIMING INFORMATION
t8
t1
t2
t2
R/W
CS
t9
t3
t5
t4
t10
t11
DACA/DACB
t6
t12
t13
t7
DATA
DATA VALID
DATA VALID
TIMING REQUIREMENTS: 2.5V to 5.5V
At tr = tf = 1ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = 2.5V to 5.5V, VREF = 10V,
IOUT2 = 0V. All specifications –40°C to +125°C, unless otherwise noted.
DAC7822
PARAMETER(1)
TEST CONDITIONS
R/W to CS setup time
MIN
0
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1
t2
R/W to CS hold time
CS low time (write cycle)
Address setup time
0
t3
10
10
0
t4
t5
Address hold time
t6
Data setup time
6
t7
Data hold time
0
t8
R/W high to CS low
CS minimum high time
Address setup time (Read Cycle)
Address hold time (Read Cycle)
Data access time
5
t9
7
t10
t11
t12
t13
0
0
5
5
35
10
Bus relinquish time
(1) Ensured by design; not production tested.
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SBAS374A–JUNE 2006–REVISED JULY 2007
DEVICE INFORMATION
RTA PACKAGE
QFN-40
(TOP VIEW)
30
R1B
R2B
R2_3
R3B
VREF
VDD
CLR
R/W
CS
1
2
R1A
R2A
29
28
27
26
25
24
23
22
21
3
B
B
R2_3A
4
R3A
5
VREF
A
DGND
LDAC
DAC A/B
NC
DAC7822
6
7
8
9
10
DB0
DB11
TERMINAL FUNCTIONS
PIN NO.
PIN NAME
R1A, R2A, R2_3A, R3A
DESCRIPTION
DAC A 4-Quadrant Resistors. Allows a number of configuration modes, including bipolar operation with
minimum of external components.
1-4
5, 26
6
VREFA, VREF
DGND
B
DAC Reference Voltage Input Terminals.
Digital Ground Pin.
Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or
synchronous update mode is selected whereby the DAC is updated on the rising edge of CS.
7
LDAC
8
DAC A/B
NC
Selects DAC A or B. Low selects DAC A, and high selects DAC B.
Not internally connected.
9, 34-37
10-21
DB11 to DB0
CS
Parallel Data Bits 11 through 0.
Chip Select Input; active low. Used in conjuction with R/W to load parallel data to the input latch or to read data
from the DAC register. Edge sensitive; when pulled high, the DAC data is latched.
22
23
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
CS to read back contents of DAC register.
R/W
24
25
CLR
VDD
Active Low Control Input. Clears DAC output and input and DAC registers.
Positive Power Supply Input. These parts can be operated from a supply of 2.5V to 5.5V.
DAC B 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with a
minimum of external components.
27-30
31, 40
32
R3B, R2_3B, R2B, R1B
RFBB, RFB
IOUT2B
A
External Amplifier Output.
DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but can be biased
to achieve single-supply operation.
33
38
IOUT1B
IOUT1A
DAC B Current Output.
DAC A Current Output.
DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but can be biased
to achieve single-supply operation.
39
IOUT2A
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TYPICAL CHARACTERISTICS: VDD = +5V
At TA = +25°C, +VDD = +5V, unless otherwise noted.
Channel A
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
TA = +25°C
VREF = +10V
TA = +25°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Digital Input Code
Figure 1.
Figure 2.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
TA = -40°C
VREF = +10V
TA = -40°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
512 1024 1536 2048 2560 3072 3584 4096
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Digital Input Code
Figure 3.
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
TA = +125°C
VREF = +10V
TA = +125°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
512 1024 1536 2048 2560 3072 3584 4096
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Digital Input Code
Figure 5.
Figure 6.
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SBAS374A–JUNE 2006–REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, +VDD = +5V, unless otherwise noted.
Channel B
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
TA = +25°C
TA = +25°C
VREF = +10V
0.8
V
= +10V
REF
0.6
0.4
0.6
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Figure 7.
Figure 8.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
TA = -40°C
TA = -40°C
VREF = +10V
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
512 1024 1536 2048 2560 3072 3584 4096
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Digital Input Code
Figure 9.
Figure 10.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
TA = +125°C
VREF = +10V
TA = +125°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
512 1024 1536 2048 2560 3072 3584 4096
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Digital Input Code
Figure 11.
Figure 12.
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SBAS374A–JUNE 2006–REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, +VDD = +5V, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE MULTIPLYING BANDWIDTH
6
0
-6
2.0
0xFFF
VDD = 5.0V
0x800
0x400
0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002
0x001
1.8
-12
-18
-24
-30
-36
-42
-48
-56
-60
-66
-72
-78
-84
-90
-96
-102
1.6
1.4
Applied to the CS pin.
R/W and LDAC held at 0V.
All other digital inputs
1.2
1.0
held at supply voltage.
0.8
0.6
VDD = 3.0V
0.4
VDD = 2.5V
0.2
0
0x000
10
100
1k
10k
100k
1M
10M
100M
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Logic Input Voltage (V)
Bandwidth (Hz)
Figure 13.
Figure 14.
MIDSCALE DAC GLITCH
MIDSCALE DAC GLITCH
Code 2048 to 2047
Code 2047 to 2048
DAC Update
DAC Update
Time (50ns/div)
Time (50ns/div)
Figure 15.
Figure 16.
GAIN ERROR
vs TEMPERATURE
DAC SETTLING TIME
10
VREF = +10V
8
6
Small Signal Settling
4
2
0
Channel B
Channel A
-2
-4
-6
-8
-10
DAC Update
Time (20ns/div)
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, +VDD = +5V, unless otherwise noted.
SUPPLY CURRENT
vs TEMPERATURE
OUTPUT LEAKAGE
vs TEMPERATURE
2.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VREF = +10V
VREF = +10V
1.8
1.6
1.4
1.2
1.0
VDD = +5.0V
0.8
0.6
0.4
VDD = +2.5V
0.2
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS: VDD = +2.5V
At TA = +25°C, +VDD = +2.5V, unless otherwise noted.
Channel A
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
TA = +25°C
VREF = +10V
TA = +25°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-0.2
-0.4
-0.6
-0.8
-1.0
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Digital Input Code
Figure 21.
Figure 22.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
TA = -40°C
VREF = +10V
TA = -40°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-0.2
-0.4
-0.6
-0.8
-1.0
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Digital Input Code
Figure 23.
Figure 24.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
TA = +125°C
VREF = +10V
TA = +125°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-0.2
-0.4
-0.6
-0.8
-1.0
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Digital Input Code
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS: VDD = +2.5V (continued)
At TA = +25°C, +VDD = +2.5V, unless otherwise noted.
Channel B
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
TA = +25°C
TA = +25°C
VREF = +10V
0.8
VREF = +10V
0.6
0.4
0.6
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Figure 27.
Figure 28.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
TA = -40°C
VREF = +10V
TA = -40°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
512 1024 1536 2048 2560 3072 3584 4096
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Digital Input Code
Figure 29.
Figure 30.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
TA = +125°C
VREF = +10V
TA = +125°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
512 1024 1536 2048 2560 3072 3584 4096
512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Digital Input Code
Figure 31.
Figure 32.
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SBAS374A–JUNE 2006–REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +2.5V (continued)
At TA = +25°C, +VDD = +2.5V, unless otherwise noted.
MIDSCALE DAC GLITCH
MIDSCALE DAC GLITCH
Code 2048 to 2047
Code 2047 to 2048
DAC Update
DAC Update
Time (50ns/div)
Time (50ns/div)
Figure 33.
Figure 34.
GAIN ERROR
vs TEMPERATURE
OUTPUT LEAKAGE
vs TEMPERATURE
10
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VREF = +10V
8
VREF = +10V
6
4
2
0
Channel B
-2
-4
-6
Channel A
-8
-10
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 35.
Figure 36.
12
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THEORY OF OPERATION
The DAC7822 is a dual channel, current output, 12-bit, digital-to-analog converter (DAC). The architecture,
illustrated in Figure 37, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to IOUT1 or the IOUT2 terminal. The IOUT1 terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input VREF that determines the DAC full-scale current. The R-2R ladder presents a code-independent load
impedance to the external reference of 10kΩ ±20%. The external reference voltage can vary over a range of
–15V to +15V, thus providing bipolar IOUT current operation. By using an external I/V converter and the
DAC7822 RFB resistor, output voltage ranges of –VREF to VREF can be generated.
R
R
R
R
VREF
R1
2R
2R
2R
2R
2R
RFB
IOUT
1
2
IOUT
DB11
(MSB)
DB10
DB9
DB0
(LSB)
Figure 37. Equivalent R-2R DAC Circuit
When using an external I/V converter and the DAC7822 RFB and R1 resistors, the DAC output voltage is given
by Equation 1:
CODE
4096
VOUT + * VREF
(1)
Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output
impedance as seen looking into the IOUT1 terminal changes versus code, the external I/V converter noise gain
also changes. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such
that the amplifier offset is not modulated by the DAC IOUT1 terminal impedance change. External op amps with
large offset voltages can produce INL errors in the transfer function of the DAC7822 as a result of offset
modulation versus DAC code.
For best linearity performance of the DAC7822, a low input offset voltage op amp (such as the OPA277) is
recommended (see Figure 38). This circuit allows VREF swinging from –10V to +10V.
VDD
15V
VDD R1 RFB
R2
V+
IOUT
1
R2/R3
R3
DAC7822
GND
VOUT
OPA277
IOUT2
V-
-15V
VREF
Figure 38. Voltage Output Configuration
13
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APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design (see Figure 39), the DAC7822 current output (IOUT) and the connection with the
inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)
layout design practices. For each code change, there is a step function. If the gain bandwidth product (GBP) of
the op amp is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible.
Therefore, for circuit stability, a compensation capacitor C1 (1pF to 5pF typ) can be added to the design, as
shown in Figure 39.
VDD
VDD
VREF
RFB
C1
IOUT1
VREF
DAC7822
U1
VOUT
IOUT2
GND
Figure 39. Gain Peaking Prevention Circuit with Compensation Capacitor
Amplifier Selection
There are many choices and many differences in selecting the proper operational amplifier for a multiplying DAC
(MDAC). Making the analog signal out of the MDAC is one critical aspect. However, there are also other issues
to take into account such as amplifier noise, input bias current, and offset voltage, as well as MDAC resolution
and glitch energy. Table 1 and Table 2 suggest some suitable operational amplifiers for low power, fast settling,
and high-speed applications. A greater selection of operational amplifiers can be found at www.ti.com/amplifer.
Table 1. Suitable Precision Operational Amplifiers from Texas Instruments
IQ
TOTAL
SUPPLY
VOLTAGE
(V) (min)
TOTAL
SUPPLY
VOLTAGE
(V) (max)
PER
SLEW
OFFSET
DRIFT
(typ)
CHANNEL GBW RATE
(max)
(mA)
IIB
CMRR
(typ)
(typ)
(MHz) (V/μs)
(max) (min)
PACKAGE/
LEAD
PRODUCT
Low Power
(μV/°C)
(pA)
10
(dB)
DESCRIPTION
SOT5-23,
PDIP-8,
SOIC-8
12V, CMOS, Rail-to-Rail I/O,
Operational Amplifier
OPA703
OPA735
4
12
12
0.2
1
0.6
1.5
4
70
0.05μV/°C (max),
Single-Supply CMOS
Zero-Drift Series Operational
Amplifier
SOT5-23,
SOIC-8
2.7
0.75
1.6
0.01
200
115
Low Power, Single-Supply,
Rail-To-Rail Operational
Amplifiers MicroAmplifier
Series
SOT5-23,
PDIP-8,
SOIC-8
OPA344
OPA348
2.7
5.5
0.25
1
1
2.5
10
80
SC5-70,
SOT5-23,
SOIC-8
1MHz, 45μA, Rail-to-Rail I/O,
Single Op Amp
2.1
4
5.5
36
0.065
0.825
1
1
0.5
0.8
2
10
70
PDIP-8,
SOIC-8,
SON-8
High Precision Operational
Amplifiers
OPA277
0.1
1000
130
Fast Settling
High-Speed, Single-Supply,
Rail-to-Rail Operational
Amplifiers MicroAmplifier
Series
MSOP-8,
PDIP-8,
SOIC-8
OPA350
2.7
5.5
7.5
38
22
4
10
76
e-trim 20MHz, High
Precision CMOS Operational
Amplifier
MSOP-8,
SON-8
OPA727
OPA227
4
5
12
36
6.5
3.8
20
8
30
0.6
0.1
500
86
PDIP-8,
SOIC-8
High Precision, Low Noise
Operational Amplifiers
2.3
10000
120
14
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SBAS374A–JUNE 2006–REVISED JULY 2007
Table 2. Suitable High Speed Operational Amplifiers from Texas Instruments (Multiple Channel Options)
SUPPLY
VOLTAGE
(V)
GBW
PRODUCT
(MHz)
VOLTAGE
NOISE
nV/√Hz
GBW
(typ)
(MHz)
SLEW
RATE
(V/μs)
VOS
(typ)
(μV)
VOS
(max)
(μV)
CMRR
(min)
(dB)
PACKAGE/
LEAD
PRODUCT
DESCRIPTION
Single Channel
Very Low-Power High Speed
Rail-To-Rail Input/Output
Voltage Feedback
SOT5-23,
MSOP-8,
SOIC-8
THS4281
±2.7 to ±15
38
12.5
35
500
3500
500
1000
Operational Amplifier
CDIP-8,
MSOP-8,
SOIC-8
100-MHz Low Noise
Voltage-Feedback Amplifier
THS4031
THS4631
OPA656
±4.5 to ±16.5
±4.5 to ±16.5
±4 to ±6
200
210
230
1.6
7
100
900
290
500
260
250
3000
2000
2600
3000
50pA
2pA
8000
2
SOIC-8,
MSOP-8
High Speed FET-Input
Operational Amplifier
Wideband, Unity Gain Stable
FET-Input Operational
Amplifier
SOIC-8,
SOT5-23
7
5pA
Unity Gain Stable, Low
Noise, Voltage Feedback
Operational Amplifier
SOIC-8,
SOT5-23
OPA820
Dual Channel
THS4032
±2.5 to ±6
280
2.5
240
200
1200
900
23,000
100-MHz Low Noise
Voltage-Feedback Amplifier,
Dual
SOIC-8,
MSOP-8
±4.5 to ±16.5
±2 to ±6.3
200
220
1.6
2
100
170
500
200
3000
1200
3000
9600
8000
SpeedPlus Dual Wideband,
Low-Noise Operational
Amplifier
SOIC-8,
MSOP-8
OPA2822
12000
Positive Voltage Output Circuit
As Figure 40 illustrates, in order to generate a positive voltage output, a negative reference is input to the
DAC7822. This design is suggested instead of using an inverting amp to invert the output as a result of resistor
tolerance errors. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual ground
and a –2.5V input to the DAC7822 with an op amp.
+2.5V Reference
VDD
VOUT
GND
VIN
VDD
RFB
C1
VREF
IOUT1
DAC7822
OPA277
-2.5V
VOUT
OPA277
IOUT2
GND
0 < VOUT < +2.5V
Figure 40. Positive Voltage Output Circuit
Bipolar Output Section
The DAC7822, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 41,
external op amp U2 is added as a summing amp and has a gain of 2X that widens the output span to 5V. A
4-quadrant multiplying circuit is implemented by using a 2.5V offset of the reference voltage to bias U2.
According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full-scale produce
output voltages of VOUT = –2.5V to VOUT = +2.5V.
D
+ ǒ
*1Ǔ
VREF
VOUT
0.5 2N
(2)
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SBAS374A–JUNE 2006–REVISED JULY 2007
External resistance mismatching is the significant error in Figure 41.
VDD
R1A
R1
RFB
2R
2R
RFBA
(2)
C1
R2A
VIN
IOUT1A
IOUT2A
R2
(1)
2R
DAC7822
VOUT = -VIN to +VIN
U2
R2_3A
R3
2R
R3A
U1
AGND
GND
AGND
VREFA
AGND
NOTES: (1) Similar configuration for DAC B.
(2) C1 phase compensation (1pF to 5pF) may be
required if U2 is a high-speed amplifier.
Figure 41. Bipolar Output Circuit
Parallel Interface
Data are loaded to the DAC7822 as a 12-bit parallel word. The bi-directional bus is controlled with CS and R/W,
allowing data to be written to or read from the DAC register. To write to the device, CS and R/W are brought
low, and data available on the data lines fills the input register. The rising edge of CS latches the data and
transfers the latched data-word to the DAC register. The DAC latches are not transparent; therefore, a write
sequence must consist of a falling and rising edge on CS in order to ensure that data are loaded to the DAC
register and its analog equivalent is reflected on the DAC output.
To read data stored in the device, R/W is held high and CS is brought low. Data are loaded from the DAC
register back to the input register and out onto the data line, where it can be read back to the controller.
Cross-Reference
The DAC7822 has an industry-standard pinout. Table 3 provides the cross-reference information.
Table 3. Cross-Reference
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
PACKAGE
OPTION
CROSS-
REFERENCE PART
PRODUCT
INL (LSB) DNL (LSB)
±1 ±1
DAC7822
–40°C to +125°C
40-Lead QFN
QFN-40
AD5405
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
DAC7822IRTAR
DAC7822IRTARG4
DAC7822IRTAT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
WQFN
WQFN
WQFN
WQFN
RTA
40
40
40
40
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
DAC7822
ACTIVE
ACTIVE
ACTIVE
RTA
RTA
RTA
2000
250
Green (RoHS
& no Sb/Br)
DAC7822
DAC7822
DAC7822
Green (RoHS
& no Sb/Br)
DAC7822IRTATG4
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Mar-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC7822IRTAR
DAC7822IRTAT
WQFN
WQFN
RTA
RTA
40
40
2000
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Mar-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC7822IRTAR
DAC7822IRTAT
WQFN
WQFN
RTA
RTA
40
40
2000
250
336.6
213.0
336.6
191.0
28.6
55.0
Pack Materials-Page 2
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相关型号：
DAC7822IRTATG4
12-bit, Dual Channel, Parallel Input, Multiplying Digital-to-Analog Converter 40-WQFN -40 to 125
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