DAC80-CBI-I [TI]
Monolithic 12-Bit DIGITAL-TO-ANALOG CONVERTERS; 单片12位数字 - 模拟转换器
| 型号： | DAC80-CBI-I |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Monolithic 12-Bit DIGITAL-TO-ANALOG CONVERTERS |
| 文件： | 总10页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DAC80
DAC80P
Monolithic 12-Bit
DIGITAL-TO-ANALOG CONVERTERS
resistors, as well as low integral and differential lin-
FEATURES
● INDUSTRY STANDARD PINOUT
earity errors. Innovative circuit design enables the
DAC80 to operate at supply voltages as low as ±11.4V
with no loss in performance or accuracy over any
range of output voltage. The lower power dissipation
of this 118-mil by 121-mil chip results in higher
reliability and greater long term stability.
● FULL ±10V SWING WITH VCC = ±12VDC
● DIGITAL INPUTS ARE TTL- AND
CMOS-COMPATIBLE
● GUARANTEED SPECIFICATIONS WITH
±12V AND ±15V SUPPLIES
Burr-Brown has further enhanced the reliability of the
monolithic DAC80 by offering a hermetic, side-brazed,
ceramic package. In addition, ease of use has been
enhanced by eliminating the need for a +5V logic
power supply.
● ±1/2LSB MAXIMUM NONLINEARITY:
0°C to +70°C
● SETTLING TIME: 4µs max to ±0.01% of
Full Scale
For applications requiring both reliability and low
cost, the DAC80P in a molded plastic package offers
the same electrical performance over temperature as
the ceramic model. The DAC80P is available with
voltage output only.
● GUARANTEED MONOTONICITY:
0°C to +70°C
● TWO PACKAGE OPTIONS: Hermetic side-
brazed ceramic and low-cost molded
plastic
For designs that require a wider temperature range, see
Burr-Brown models DAC85H and DAC87H.
DESCRIPTION
Reference
This monolithic digital-to-analog converter is pin-for-
pin equivalent to the industry standard DAC80 first
introduced by Burr-Brown. Its single-chip design in-
cludes the output amplifier and provides a highly
stable reference capable of supplying up to 2.5mA to
an external load without degradation of D/A perfor-
mance.
12-Bit
Resistor
Ladder
Network
and
Reference
Control
Circuit
Gain
Adjustment
Scaling
Network
Current
Switches
This converter uses proven circuit techniques to pro-
vide accurate and reliable performance over tempera-
ture and power supply variations. The use of a buried
zener diode as the basis for the internal reference
contributes to the high stability and low noise of the
device. Advanced methods of laser trimming result in
precision output current and output amplifier feedback
Analog
Output
Offset
Adjustment
+ Supply
– Supply
International Airport Industrial Park
•
Mailing Address: PO Box 11400
Cable: BBRCORP
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
•
Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111
•
•
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1986 Burr-Brown Corporation
PDS-643F
Printed in U.S.A. July, 1993
SBAS148
SPECIFICATIONS
ELECTRICAL
Typical at +25°C and ±VCC = 12V or 15V unless otherwise noted.
DAC80
TYP
PARAMETER
MIN
MAX
UNITS
DIGITAL INPUT
Resolution
Logic Levels (0°C to +70°C)(1)
12
Bits
:
V
V
IH (Logic “1”)
IL (Logic “0”)
+2
0
+16.5
+0.8
+20
VDC
VDC
µA
IIH (VIN = +2.4V)
IL (VIN = +0.4V)
I
–180
µA
ACCURACY (at +25°C)
Linearity Error
Differential Linearity Error
Gain Error(2)
Offset Error(2)
±1/4
±1/2
±0.1
±1/2
±3/4
±0.3
LSB
LSB
%
±0.05
±0.15
% of FSR(3)
DRIFT (0°C to +70°C)(4)
Total Bipolar Drift (includes gain, offset, and linearity drifts)
Total Error Over 0°C to +70°C(5)
Unipolar
±10
±25
ppm of FSR/°C
±0.06
±0.06
±10
±5
±1
±7
±0.15
±0.12
±30
±10
±3
% of FSR
% of FSR
ppm/°C
Bipolar
Gain: Including Internal Reference
Excluding Internal Reference
Unipolar Offset
ppm/°C
ppm of FSR/°C
ppm of FSR/°C
LSB
Bipolar Offset
±15
Differential Linearity 0°C to +70°C
Linearity Error 0°C to +70°C
Monotonicity Guaranteed
±1/2
±1/4
±3/4
±1/2
+70
LSB
°C
0
CONVERSION SPEED, VOUT Models
Settling Time to ±0.01% of FSR
For FSR Change (2kΩ || 500pF Load)
with 10kΩ Feedback
with 5kΩ Feedback
For 1LSB Change
3
2
1
4
3
µs
µs
µs
Slew Rate
10
V/µs
CONVERSION SPEED, IOUT Models
Settling Time to ±0.01% of FSR
For FSR change: 10Ω to 100Ω Load
1kΩ Load
300
1
ns
µs
ANALOG OUTPUT, VOUT Models
Ranges
±2.5, ±5, ±10, +5, +10
V
mA
Ω
Output Current(6)
±5
Output Impedance (DC)
Short Circuit to Common, Duration(7)
0.05
Indefinite
ANALOG OUTPUT, IOUT Models
Ranges: Bipolar
Unipolar
Output Impendance: Bipolar
Unipolar
±0.96
–1.96
2.6
4.6
–2.5
±1.0
–2.0
3.2
±1.04
–2.04
3.7
8.6
+2.5
mA
mA
kΩ
kΩ
V
6.6
Compliance
REFERENCE VOLTAGE OUTPUT
External Current (constant load)
Drift vs Temperature
+6.23
+6.30
+6.37
2.5
±20
V
mA
ppm/°C
Ω
±10
1
Output Impedance
POWER SUPPLY SENSITIVITY
VCC = ±12VDC or ±15VDC
±0.002
±0.006
% FSR/ % VCC
POWER SUPPLY REQUIREMENTS
±VCC
Supply Drain (no load): +VCC
–VCC
±11.4
±16.5
12
20
VDC
mA
mA
8
15
Power Dissipation (VCC = ±15VDC)
345
480
mW
TEMPERATURE RANGE
Specification
Operating
Storage: Plastic DIP
Ceramic DIP
0
+70
+85
+100
+150
°C
°C
°C
°C
–25
–60
–65
NOTES:(1)Referto“LogicInputCompatibility”section. (2)Adjustabletozerowithexternaltrimpotentiometer. (3)FSRmeansfullscalerangeandis20Vfor±10Vrange,
10V for ±5V range for VOUT models; 2mA for IOUT models. (4) To maintain drift spec, internal feedback resistors must be used. (5) Includes the effects of gain, offset
and linearity drift. Gain and offset errors externally adjusted to zero at +25°C. (6) For ±VCC less than ±12VDC, limit output current load to ±2.5mA to maintain ±10V full
scale output voltage swing. For output range of ±5V or less, the output current is ±5mA over entire ±VCC range. (7) Short circuit current is 40mA, max.
®
2
DAC80/80P
FUNCTIONAL DIAGRAM AND PIN ASSIGNMENTS
Voltage Models
Current Models
(MSB) Bit 1
Bit 2
1
2
3
4
5
6
7
8
9
24 6.3V Ref Out
23 Gain Adjust
22 +VCC
(MSB) Bit 1
Bit 2
1
2
3
4
5
6
7
8
9
24 6.3V Ref Out
23 Gain Adjust
22 +VCC
Reference
Control
Circuit
Reference
Control
Circuit
Bit 3
Bit 3
Bit 4
21 Common
Bit 4
21 Common
20 Scaling Network
19 Scaling Network
18 Scaling Network
17 Bipolar Offset
16 Ref Input
15 IOUT
12-Bit
Resistor
Ladder
Network
and
12-Bit
Resistor
Ladder
Network
and
Bit 5
20 Summing Junction
19 20V Range
18 10V Range
17 Bipolar Offset
16 Ref Input
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
5kΩ
2kΩ
Bit 6
3kΩ
5kΩ
5kΩ
6.3kΩ
Bit 7
Current
Switches
Current
Switches
Bit 8
6.3kΩ
Bit 9
Bit 10 10
Bit 11 11
15 VOUT
Bit 10 10
Bit 11 11
14 –VCC
14 –VCC
(LSB) Bit 12 12
13 NC(1)
(LSB) Bit 12 12
13 NC(1)
NOTE: (1) Logic supply applied to this pin has no effect.
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
+VCC to Common ...................................................................... 0V to +18V
–VCC to Common ......................................................................... 0V to –18
Digital Data Inputs to Common .............................................. –1V to +18V
Reference Output to Common ............................................................ ±VCC
Reference Input to Common ............................................................... ±VCC
Bipolar Offset to Common................................................................... ±VCC
10V Range R to Common ................................................................... ±VCC
20V Range R to Common ................................................................... ±VCC
External Voltage to DAC Output .............................................. –5V to +5V
Lead Temperature (soldering, 10s)................................................ +300°C
Max Junction Temperature .............................................................. 165°C
Thermal Resistance, θJA: Plastic DIP ........................................... 100°C/W
Ceramic DIP ......................................... 65°C/W
PACKAGE DRAWING
NUMBER(1)
MODEL
PACKAGE
DAC80P
DAC80
24-Pin Plastic DIP
24-Pin Ceramic DIP
167
125
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
BURN-IN SCREENING
Burn-in screening is an option available for the models
indicated in the Ordering Information table. Burn-in dura-
tion is 160 hours at the maximum specified grade operating
temperature (or equivalent combination of time and tem-
perature).
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maxi-
mum conditions for extended periods may affect device reliability.
All units are tested after burn-in to ensure that grade speci-
fications are met. To order burn-in, add “–BI” to the base
model number.
ORDERING INFORMATION
MODEL
PACKAGE
OUTPUT
DAC80-CBI-I
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Plastic DIP
Current
Current
Voltage
Voltage
Voltage
DAC80Z-CBI-I
DAC80-CBI-V
DAC80Z-CBI-V
DAC80P-CBI-V
BURN-IN SCREENING OPTION
BURN-IN TEMP.
(160h)(1)
MODEL
PACKAGE
DAC80-CBI-V-BI
DAC80P-CBI-V-BI
Ceramic DIP
Plastic DIP
+125°C
+125°C
NOTE: (1) Or equivalent combination. See text.
®
3
DAC80/80P
DICE INFORMATION
PAD
15
16
17
18
19
20
21
22
23
24
25
26
27
FUNCTION
–VCC
PAD
1
FUNCTION
Bit 1 (MSB)
Bit 2
VOUT
2
Ref In
3
Bit 3
Bipolar Offset
Scale 10V FSR
Scale 20V FSR
NC
4
Bit 4
5
Bit 5
6
Bit 6
7
Bit 7
Sum Junct
COM
8
Bit 8
9
Bit 9
COM
10
11
12
13
14
Bit 10
Bit 11
Bit 12 (LSB)
NC
+VCC
Gain Adjust
6.3V Ref Out
NC
Substrate Bias: Isolated. NC: No Connection
MECHANICAL INFORMATION
MILS (0.001")
MILLIMETERS
Die Size
Die Thickness
Min. Pad Size
118 x 121 ± 5
20 ± 3
3.0 x 3.07 ± 0.13
0.51 ± 0.08
0.10 x 0.10
4 x 4
DAC80KD-V DIE TOPOGRAPHY
Metalization
Aluminum
PAD
FUNCTION
PAD
FUNCTION
15
16
17
18
19
20
21
22
23
24
25
26
27
–VCC
IOUT
1
2
Bit 1 (MSB)
Bit 2
Ref In
3
Bit 3
Bipolar Offset
Scale 10V FSR
Scale 20V FSR
Scale
4
Bit 4
5
Bit 5
6
Bit 6
7
Bit 7
NC
8
Bit 8
COM
9
Bit 9
COM
10
11
12
13
14
Bit 10
Bit 11
Bit 12 (LSB)
NC
+VCC
Gain Adjust
6.3V Ref Out
NC
Substrate Bias: Isolated. NC: No Connection
MECHANICAL INFORMATION
MILS (0.001")
MILLIMETERS
Die Size
Die Thickness
Min. Pad Size
118 x 121 ± 5
20 ± 3
3.0 x 3.07 ± 0.13
0.51 ± 0.08
0.10 x 0.10
4 x 4
DAC80KD-I DIE TOPOGRAPHY
Metalization
Aluminum
®
4
DAC80/80P
SETTLING TIME
DISCUSSION OF
SPECIFICATIONS
DIGITAL INPUT CODES
Settling time for each DAC80 model is the total time
(including slew time) required for the output to settle within
an error band around its final value after a change in input
(see Figure 1).
The DAC80 accepts complementary binary digital input
codes. The CBI model may be connected by the user for any
one of three complementary codes: CSB, COB, or CTC (see
Table I).
1
V Models
10kΩ
Feedback
0.3
I Models
DIGITAL INPUT
ANALOG OUTPUT
5kΩ
Feedback
0.1
CSB
Complementary
Straight
COB
CTC(1)
Complementary Complementary
0.03
RL=
Offset
Binary
Two’s
Complement
MSB
LSB
Binary
10Ω
to 100Ω
↓
↓
0.01
000000000000
011111111111
100000000000 1/2 Full Scale –1LSB
111111111111 Zero
+Full Scale
+1/2 Full Scale
+Full Scale
Zero
–1LSB
–1LSB
–Full Scale
–Full Scale
Zero
RL=
0.003
1000Ω
to 1875Ω
–Full Scale
0.001
0.1
1
10
100
NOTE: (1) Invert the MSB of the COB code with an external inverter to obtain
CTC code.
Settling Time (µs)
TABLE I. Digital Input Codes.
FIGURE 1. Full Scale Range Settling Time vs Accuracy.
ACCURACY
Voltage Output Models
Three settling times are specified to ±0.01% of full scale
range (FSR); two for maximum full scale range changes of
20V, 10V and one for a 1LSB change. The 1LSB change is
measured at the major carry (0111...11 to 1000...00), the
point at which the worst case settling time occurs.
Linearity of a D/A converter is the true measure of its
performance. The linearity error of the DAC80 is specified
over its entire temperature range. This means that the analog
output will not vary by more than ±1/2LSB, maximum, from
an ideal straight line drawn between the end points (inputs
all “1”s and all “0”s) over the specified temperature range of
0°C to +70°C.
Current Output Models
Two settling times are specified to ±0.01% of FSR. Each is
given for current models connected with two different resis-
tive loads: 10Ω to 100Ω and 1000Ω to 1875Ω. Internal
resistors are provided for connecting nominal load resis-
tances of approximately 1000Ω to 1800Ω for output voltage
range of ±1V and 0 to –2V (see Figures 11 and 12).
Differential linearity error of a D/A converter is the devia-
tion from an ideal 1LSB voltage change from one adjacent
output state to the next. A differential linearity error speci-
fication of ±1/2LSB means that the output voltage step sizes
can range from 1/2LSB to 3/2LSB when the input changes
from one adjacent input state to the next.
Monotonicity over a 0°C to +70°C range is guaranteed in the
DAC80 to insure that the analog output will increase or
remain the same for increasing input digital codes.
COMPLIANCE
Compliance voltage is the maximum voltage swing allowed
on the current output node in order to maintain specified
accuracy. The maximum compliance voltage of all current
output models is ±2.5V. Maximum safe voltage range of
±1V and 0 to –2V (see Figures 11 and 12).
DRIFT
Gain Drift is a measure of the change in the full scale range
output over temperature expressed in parts per million per
°C (ppm/°C). Gain drift is established by: 1) testing the end
point differences for each DAC80 model at 0°C, +25°C, and
+70°C; 2) calculating the gain error with respect to the 25°C
value, and; 3) dividing by the temperature change. This
figure is expressed in ppm/°C and is given in the electrical
specifications both with and without internal reference.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
power supply change on the D/A converter output. It is
defined as a percent of FSR per percent of change in either
the positive or negative supplies about the nominal power
supply voltages (see Figure 2).
Offset Drift is a measure of the actual change in output with
all “1”s on the input over the specified temperature range.
The offset is measured at 0°C, +25°C, and 70°C. The
maximum change in Offset is referenced to the Offset at
25°C and is divided by the temperature range. This drift is
expressed in parts per million of full scale range per °C (ppm
of FSR/°C).
REFERENCE SUPPLY
All DAC80 models are supplied with an internal 6.3V
reference voltage supply. This voltage (pin 24) has a toler-
ance of ±1% and must be connected to the Reference Input
®
5
DAC80/80P
0.1
0.01
OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
Connect power supply voltages as shown in Figure 3. For
optimum performance and noise rejection, power supply
decoupling capacitors should be added as shown. These
capacitors (1µF tantalum) should be located close to the
DAC80.
–VCC
+VCC
0.001
0.0001
±12V OPERATION
All DAC80 models can operate over the entire power supply
range of ±11.4V to ±16.5V. Even with supply levels drop-
ping to ±11.4V, the DAC80 can swing a full ±10V range,
provided the load current is limited to ±2.5mA. With power
supplies greater than ±12V, the DAC80 output can be loaded
up to ±5mA. For output swing of ±5V or less, the output
current is ±5mA, minimum, over the entire VCC range.
1
10
100
1k
10k
100k
Power Supply Ripple Frequency (Hz)
FIGURE 2. Power Supply Rejection vs Power Supply Ripple.
(pin 16) for specified operation. This reference may be used
externally also, but external current drain is limited to
2.5mA.
No bleed resistor is needed from +VCC to pin 24, as was
needed with prior hybrid Z versions of DAC80. Existing
±12V applications that are being converted to the monolithic
DAC80 must omit the resistor to pin 24 to insure proper
operation.
If a varying load is to be driven, an external buffer amplifier
is recommended to drive the load in order to isolate bipolar
offset from load variations. Gain and bipolar offset adjust-
ments should be made under constant load conditions.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
LOGIC INPUT COMPATIBILITY
Offset and gain may be trimmed by installing external Offset
and Gain potentiometers. Connect these potentiometers as
shown in Figure 3 and adjust as described below. TCR of the
potentiometers should be 100ppm/°C or less. The 3.9MΩ
and 10MΩ resistors (20% carbon or better) should be lo-
cated close to the DAC80 to prevent noise pickup. If it is not
convenient to use these high value resistors, an equivalent
“T” network, as shown in Figure 4, may be substituted.
DAC80 digital inputs are TTL, LSTTL and 4000B,
54/74HC CMOS compatible. The input switching threshold
remains at the TTL threshold over the entire supply range.
Logic “0” input current over temperature is low enough to
permit driving DAC80 directly from outputs of 4000B and
54/74C CMOS devices.
Current Output Models
Voltage Output Models
+VCC
10kΩ
to
100kΩ
+VCC
1
2
24
1
2
24
23
22
21
20
19
18
17
16
15
14
13
Reference
Control
Circuit
10MΩ
10MΩ
Reference
Control
Circuit
10kΩ
to
100kΩ
23
22
21
20
19
18
17
16
15
14
13
3
0.01µF
0.01µF
3
–VCC
–VCC
4
4
3.9MΩ
10kΩ
to
100kΩ
10kΩ
to
100kΩ
12-Bit
Resistor
Ladder
Network
and
12-Bit
Resistor
Ladder
Network
and
5
5
5kΩ
2kΩ
6
3kΩ
5kΩ
6
5kΩ
6.3kΩ
7
7
+VCC
+VCC
Current
Switches
Current
Switches
1µF
1µF
1µF
8
8
6.3kΩ
9
9
3.9MΩ
10
11
12
10
11
12
–VCC
–VCC
1µF
FIGURE 3. Power Supply and External Adjustment Connection Diagrams.
®
6
DAC80/80P
Offset Adjustment
10MΩ
270kΩ
180kΩ
270kΩ
For unipolar (CSB) configurations, apply the digital input
code that should produce zero potential output and adjust the
Offset potentiometer for zero output.
7.8kΩ to 10kΩ
For bipolar (COB, CTC) configurations, apply the digital
input code that should produce the maximum negative
output. Example: If the Full Scale Range is connected for
20V, the maximum negative output voltage is –10V. See
Table II for corresponding codes.
3.9MΩ
180kΩ
10kΩ
FIGURE 4. Equivalent Resistances.
Gain Adjustment
For either unipolar or bipolar configurations, apply the
digital input that should give the maximum positive output.
Adjust the Gain potentiometer for this positive full scale
output. See Table II for positive full scale voltages and
currents.
Existing applications that are converting to the monolithic
DAC80 must change the gain trim resistor on pin 23 from
33MΩ to 10MΩ to insure sufficient adjustment range. Pin
23 is a high impedance point and a 0.001µ1F to 0.01µF
ceramic capacitor should be connected from this pin to
Common (pin 21) to prevent noise pickup. Refer to Figure
5 for relationship of Offset and Gain adjustments to unipolar
and bipolar D/A operation.
ANALOG OUTPUT
(1)
DIGITAL INPUT
VOLTAGE
0 to +10V
CURRENT
0 to –2mA ±1mA
MSB
LSB
±10V
↓
↓
000000000000
011111111111
100000000000
111111111111
One LSB
+9.9976V
+5.0000V
+4.9976V
0.0000V
2.44mV
+9.9951V
0.0000V
–0.0049V
–10.0000V
4.88mV
–1.9995mA –0.9995mA
–1.0000mA 0.0000mA
–0.9995mA +0.0005mA
Unipolar
0.0000mA
+1.000mA
Range of
0.488µA
0.488µA
+ Full Scale
Gain Adjust
NOTE: (1) To obtain values for other binary ranges:
0 to +5V range divide 0 to +10V range values by 2.
±5V range: divide ±10V range values by 2.
±2.5V range: divide ±10V range values by 4.
1LSB
TABLE II. Digital Input/Analog Output.
Gain Adjust
Rotates the Line
VOLTAGE OUTPUT MODELS
Output Range Connections
Internal scaling resistors provided in the DAC80 may be
connected to produce bipolar output voltage ranges of ±10V,
±5V, or ±2.5V; or unipolar output voltage ranges of 0 to
+5V or 0 to +10V. See Figure 6.
All Bits
Range
of Offset
Logic 1
All Bits
Logic 0
Adjust
Digital Input
Offset Adjust Translates the Line
To Reference Control Circuit
Reference Input
16
6.3kΩ(1)
Bipolar
Offset
Bipolar
17
+ Full Scale
Range of
Summing
Junction
21 Common
Gain Adjust
1LSB
20
5kΩ(1) 18
5kΩ(1)
From Weighted
Resistor
Network
19
Full Scale
All Bits
Logic 1
Range
Gain Adjust
Rotates the Line
15 Output
All Bits
Logic 0
NOTE: (1) Resistor Tolerances: ±2% max.
MSB On,
All Others
Off
Bipolar
Offset
Range of
Offset Adjust
FIGURE 6. Output Amplifier Voltage Range Scaling Circuit.
–Full Scale
Gain and offset drift are minimized because of the thermal
tracking of the scaling resistors with other internal device
components. Connections for various output voltage ranges
are shown in Table III. Settling time for a full-scale range
change is specified as 4µs for the 20V range and 3µs for the
10V range.
Digital Input
Offset Adjust Translates the Line
FIGURE 5. Relationship of Offset and Gain Adjustments for
a Unipolar and Bipolar D/A Converter.
®
7
DAC80/80P
Output
Range
Digital
Connect Connect Connect Connect
19
18
20V Range
10V Range
Input Codes Pin 15 to Pin 17 to Pin 19 to Pin 16 to
5kΩ
±10
±5
±2.5V
0 to +10V
0 to +5V
COB or CTC
COB or CTC
COB or CTC
CSB
19
18
18
18
18
20
20
20
21
21
15
NC
20
NC
20
24
24
24
24
24
5kΩ
15
A
CSB
(1)
OPA604
IOUT
0 to
TABLE III. Output Voltage Range Connections for Voltage
Models.
6.6kΩ
VOUT
2mA
21
CURRENT OUTPUT MODELS
NOTE: (1) For fast settling.
The resistive scaling network and equivalent output circuit
of the current model differ from the voltage model and are
shown in Figures 7 and 8.
FIGURE 9. External Op-Amp—Using Internal Feedback
Resistors.
the current output model DAC80 provides output voltage
ranges the same as the voltage model DAC80. To obtain the
desired output voltage range when connecting an external op
amp, refer to Table IV.
To Reference Control Circuit
6.3kΩ(1)
3kΩ(1)
Reference Input
16
17
19
2kΩ(1)
18
15
Output
Range
Digital
Input Codes
Connect Connect Connect Connect
5kΩ(1)
A to
Pin 17 to Pin 19 to Pin 16 to
±10V
±5V
±2.5V
0 to +10V
0 to +5V
COB or CTC
COB or CTC
COB or CTC
CSB
19
18
18
18
18
15
15
15
21
21
A
NC
15
NC
15
24
24
24
24
24
20
NOTE: (1) Resistor Tolerances: ±2% max.
CSB
FIGURE 7. Internal Scaling Resistors.
TABLE IV. Voltage Range of Current Output.
Output Larger Than 20V Range
24 Reference Out
17 Bipolar Offset
To
For output voltage ranges larger than ±10V, a high voltage
op amp may be employed with an external feedback resistor.
Use IOUT value of ±1mA for bipolar voltage ranges and
–2mA for unipolar voltage ranges. See Figure 10. Use
protection diodes when a high voltage op amp is used.
Reference
Control
Circuit
6.3kΩ
16 Reference Input
15 IOUT
+
–
6.3V
0 to
2mA
RO
6.6kΩ
I
The feedback resistor, RF, should have a temperature coef-
ficient as low as possible. Using an external feedback
resistor, overall drift of the circuit increases due to the lack
of temperature tracking between RF and the internal scaling
resistor network. This will typically add 50ppm/°C plus RF
drift to total drift.
21 Common
FIGURE 8. Current Output Model Equivalent Output Circuit.
Internal scaling resistors (Figure 7) are provided to scale an
external op amp or to configure load resistors for a voltage
output. These connections are described in the following
sections.
24
RF
17
+
If the internal resistors are not used for voltage scaling,
external RL (or RF) resistors should have a TCR of
±25ppm/°C or less to minimize drift. This will typically add
±50ppm/°C plus the TCR of RL (or RF) to the total drift.
6.3kΩ
6.3kΩ
–
16
15
BB3582J(1)
I
6.6kΩ
0 to
2mA
VOUT
Driving An External Op Amp
The current output model DAC80 will drive the summing
junction of an op amp used as a current-to-voltage converter
to produce an output voltage. See Figure 9.
21
NOTE: (1) For output voltage swings up to 290V p-p.
VOUT = IOUT x RF
FIGURE 10. External Op-Amp—Using External Feedback
Resistors.
where IOUT is the DAC80 output current and RF is the
feedback resistor. Using the internal feedback resistors of
®
8
DAC80/80P
Driving a Resistive Load Unipolar
A load resistance, RL = RLI + RLS, connected as shown in
Figure 11 will generate a voltage range, VOUT, determined
by:
Driving a Resistive Load Bipolar
The equivalent output circuit for a bipolar output voltage
range is shown in Figure 12, RL = RLI + RLS. VOUT is
determined by:
VOUT = –2mA [(RL x RO) ÷ (RL + RO)]
V
OUT = ±1mA [(RO x RL) ÷ (RO + RL)]
By connecting pin 17 to 15, the output current becomes
bipolar (±1mA) and the output impedance RO becomes
3.2kΩ (6.6kΩ in parallel with 6.3kΩ). RLI is 1200Ω (derived
by connecting pin 15 to 18 and pin 18 to 19). By choosing
Current Controlled
by Digital Input
RLS = 225Ω, RL = 1455Ω. RL in parallel with RO yields 1kΩ
15
total load. This gives an output range of ±1V. As indicated
above, trimming may be necessary.
+
RLI
18
0 to
–2mA
VOUT
RO
RLS
–
21
Common
FIGURE 11. Current Output Model Equivalent Circuit
Connected for Unipolar Voltage Output with
Resistive Load.
Current Controlled
by Digital Input
15
+
RLI
20
VOUT
RO
+1mA
The unipolar output impedance RO equals 6.6kΩ (typ) and
RLI is the internal load resistance of 968Ω (derived by
connecting pin 15 to 20 and pin 18 to 19). By choosing RLS
= 210Ω, RL = 1178Ω. RL in parallel with RO yields 1kΩ total
load. This gives an output range of 0 to –2V. Since RO is not
exact, initial trimming per Figure 3 may be necessary; also
RLS may be trimmed.
RLS
–
21
Common
FIGURE 12. Current Output Model Connected for Bipolar
Output Voltage with Resistive Load.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
9
DAC80/80P
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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