DAC8168A_技术文档

DAC7568

DAC8168

DAC8568

www.ti.com ..................................................................................................................................................... SBAS430A–JANUARY 2009–REVISED APRIL 2009

12-/14-/16-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output

DIGITAL-TO-ANALOG CONVERTERS with 2.5V, 2ppm/°C Internal Reference

1

FEATURES

APPLICATIONS

•

Portable Instrumentation

Closed-Loop Servo-Control/Process Control

Data Acquisition Systems

Programmable Attenuation, Digital Gain, and

Offset Adjustment

Programmable Voltage and Current Sources

234

• Relative Accuracy:

– DAC7568 (12-Bit): 0.3 LSB INL

– DAC8168 (14-Bit): 1 LSB INL

– DAC8568 (16-Bit): 4 LSB INL

•

Glitch Energy: 0.1nV-s

Internal Reference:

•

– 2.5V Reference Voltage (disabled by

default)

DESCRIPTION

The DAC7568, DAC8168, and DAC8568 are

low-power, voltage-output, eight-channel, 12-, 14-,

and 16-bit digital-to-analog converters (DACs),

respectively. These devices include a 2.5V, 2ppm/°C

internal reference (disabled by default), giving a

full-scale output voltage range of 2.5V or 5V. The

internal reference has an initial accuracy of 0.004%

and can source up to 20mA at the V_REFIN/V_REFOUT

pin. These devices are monotonic, providing excellent

linearity and minimizing undesired code-to-code

transient voltages (glitch). They use a versatile 3-wire

serial interface that operates at clock rates up to

50MHz. The interface is compatible with standard

SPI™, QSPI™, Microwire™, and digital signal

processor (DSP) interfaces.

– 0.004% Initial Accuracy (typ)

– 2ppm/°C Temperature Drift (typ)

– 5ppm/°C Temperature Drift (max)

– 20mA Sink/Source Capability

•

Power-On Reset to Zero Scale or Midscale

Ultra-Low Power Operation: 1.25mA at 5V

Including Internal Reference Current

•

Wide Power-Supply Range: +2.7V to +5.5V

Monotonic Over Entire Temperature Range

Low-Power Serial Interface with

Schmitt-Triggered Inputs: Up to 50MHz

•

On-Chip Output Buffer Amplifier with

Rail-to-Rail Operation

The DAC7568, DAC8168, and DAC8568 incorporate

a power-on-reset circuit that ensures the DAC output

powers up at either zero scale or midscale until a

valid code is written to the device. These devices

contain a power-down feature, accessed over the

serial interface, that reduces current consumption to

typically 0.18µA at 5V. Power consumption (including

internal reference) is typically 2.9mW at 3V, reducing

to less than 1µW in power-down mode. The low

power consumption, internal reference, and small

footprint make these devices ideal for portable,

battery-operated equipment.

Temperature Range: –40°C to +125°C

AV_DD

V_REFIN/V_REFOUT

DAC7568

DAC8168

DAC8568

2.5V

Reference

12-/14-/16-Bit

DAC

V_OUT

H

G

F

DAC Register H

DAC Register G

DAC Register F

DAC Register E

DAC Register D

DAC Register C

DAC Register B

DAC Register A

Data Buffer H

Data Buffer G

Data Buffer F

Data Buffer E

Data Buffer D

Data Buffer C

Data Buffer B

Data Buffer A

12-/14-/16-Bit

DAC

12-/14-/16-Bit

DAC

12-/14-/16-Bit

DAC

E

D

C

B

A

12-/14-/16-Bit

DAC

12-/14-/16-Bit

DAC

The DAC7568, DAC8168, and DAC8568 are drop-in

and function-compatible with each other, and are

available in TSSOP-16 and TSSOP-14 packages.

12-/14-/16-Bit

DAC

12-/14-/16-Bit

DAC

SYNC

SCLK

D_IN

32-Bit Shift Register

Buffer Control

Register Control

Power-Down

Control Logic

DEVICE COMPARISON

12-BIT

14-BIT

16-BIT

Control Logic

Pin- and

Function-Compatible

DAC7568

DAC8168

DAC8568

GND

LDAC

CLR

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

4

SPI, QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC7568

DAC8168

DAC8568

SBAS430A–JANUARY 2009–REVISED APRIL 2009..................................................................................................................................................... www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION⁽¹⁾

MAXIMUM

RELATIVE

ACCURACY

(LSB)

MAXIMUM

DIFFERENTIAL

NONLINEARITY

(LSB)

MAXIMUM

REFERENCE

DRIFT

OUTPUT

VOLTAGE

FULL-SCALE

RANGE

SPECIFIED

TEMPERATURE

RANGE

PACKAGE-

LEAD

PACKAGE

DESIGNATOR

PACKAGE

MARKING

PRODUCT

DAC8568A

DAC8568B

DAC8568C

DAC8568D

DAC8168A

DAC8168C

DAC7568A

DAC7568C

(ppm/°C)

RESET TO

Zero

±12

±4

±1

25

5

2.5V

5V

TSSOP-16

TSSOP-14

TSSOP-16

TSSOP-14

TSSOP-16

PW

–40°C to +125°C

DA8568A

DA8568B

DA8568C

DA8568D

DA8168A

DA8168C

DA7568A

DA7568C

Midscale

Zero

±1

5

5V

Midscale

Zero

±0.5

±0.25

25

5

2.5V

5V

±4

Zero

±1

25

5

2.5V

5V

Zero

±1

Zero

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

DAC7568/DAC8168/DAC8568

–0.3 to +6

UNIT

V

AV_DDto GND

Digital input voltage to GND

V_OUTto GND

–0.3 to +AV_DD+ 0.3

–40 to +125

V

V_REFto GND

V

Operating temperature range

Storage temperature range

°C

–65 to +150

°C

Junction temperature range (T_Jmax)

Power dissipation

+150

°C

(T_Jmax – T_A)/θ_JA

+118

W

Thermal impedance, θ_JA

Thermal impedance, θ_JC

°C/W

+29

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

2

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ELECTRICAL CHARACTERISTICS

At AV_DD= 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).

DAC7568/DAC8168/DAC8568

PARAMETER

STATIC PERFORMANCE⁽¹⁾

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

16

Bits

Measured by the line passing through codes 485 and

64714

DAC8568

DAC8168

DAC7568

Relative accuracy

±4

±12

±1

LSB

Differential nonlinearity

Resolution

16-bit monotonic

±0.2

LSB

Bits

14

12

Measured by the line passing through codes 120 and

16200

Relative accuracy

±1

±4

LSB

Differential nonlinearity

Resolution

14-bit monotonic

±0.1

±0.5

LSB

Bits

Measured by the line passing through codes 30 and

4050

Relative accuracy

±0.3

±1

LSB

Differential nonlinearity

12-bit monotonic

Extrapolated from two-point line⁽¹⁾, unloaded

±0.05

±1

±0.25

±4

LSB

mV

Offset error

Offset error drift

Full-scale error

Zero-code error

±0.5

±0.03

1

µV/°C

% of FSR

mV

DAC register loaded with all '1's

DAC register loaded with all '0's

±0.2

4

Zero-code error drift

Gain error

±2

µV/°C

% of FSR

Extrapolated from two-point line⁽¹⁾, unloaded

±0.01

±0.15

ppm of

FSR/°C

Gain temperature coefficient

±1

OUTPUT CHARACTERISTICS⁽²⁾

AV_DD≥ 2.7V; grades A and B: maximum output

voltage 2.5V when using internal reference

Output voltage range

0

AV_DD

10

V

AV_DD≥ 5V; grades C and D: maximum output voltage

5V when using internal reference

DACs unloaded; 1/4 scale to 3/4 scale to ±0.024%

5

10

Output voltage settling time

Slew rate

µs

V/µs

pF

R_L= 1MΩ

0.75

1000

3000

0.1

R_L= ∞

Capacitive load stability

R_L= 2kΩ

Code change glitch impulse

Digital feedthrough

1LSB change around major carry

SCLK toggling, SYNC high

R_L= 2kΩ, C_L= 470pF, AV_DD= 5.5V

R_L= 2kΩ, C_L= 470pF, AV_DD= 2.7V

Full-scale swing on adjacent channel

nV-s

mV

0.1

10

Power-on glitch impulse

6

mV

Channel-to-channel dc crosstalk

Channel-to-channel ac crosstalk

DC output impedance

0.1

LSB

R_L= 2kΩ, C_L= 420pF, 1kHz full-scale sine wave,

outputs unloaded

–109

4

dB

Ω

At mid-code input

DAC outputs at full-scale, DAC outputs shorted to

GND

Short-circuit current

11

mA

µs

Power-up time, including settling time

Coming out of power-down mode

50

(1) 16-bit: codes 485 and 64714; 14-bit: codes 120 and 16200; 12-bit: codes 30 and 4050

(2) Specified by design or characterization; not production tested.

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ELECTRICAL CHARACTERISTICS (continued)

At AV_DD= 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).

DAC7568/DAC8168/DAC8568

PARAMETER

AC PERFORMANCE⁽³⁾

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SNR

83

–63

63

dB

T_A= +25°C, BW = 20kHz, AV_DD= 5V, f_OUT= 1kHz,

first 19 harmonics removed for SNR calculation,

at 16-bit level

THD

SFDR

dB

SINAD

62

dB

DAC output noise density

DAC output noise

REFERENCE

T_A= +25°C, at zero-code input, f_OUT= 1kHz

T_A= +25°C, at mid-code input, 0.1Hz to 10Hz

90

nV/√Hz

µV_PP

2.6

AV_DD= 5.5V

AV_DD= 3.6V

360

348

µA

Internal reference current consumption

External reference current

External V_REF= 2.5V (when internal reference is

disabled), all eight channels active

80

µA

Grades A/B, AV_DD= 2.7V to 5.5V

Grades C/D, AV_DD= 5.0V to 5.5V

0

AV_DD

V

V_REFIN

Reference input range

AV_DD/2

Reference input impedance

REFERENCE OUTPUT

Output voltage

8

kΩ

T_A= +25°C; all grades

2.4995

–0.02

2.5

±0.004

5

2.5005

0.02

25

V

Initial accuracy

T_A= +25°C, all grades

%

DAC7568/DAC8168/DAC8568⁽⁴⁾,grades A/B

DAC7568/DAC8168/DAC8568⁽⁵⁾, grades C/D

f = 0.1Hz to 10Hz

Output voltage temperature drift

Output voltage noise

ppm/°C

2

5

12

µV_PP

T_A= +25°C, f = 1MHz, C_L= 0µF

T_A= +25°C, f = 1MHz, C_L= 1µF

T_A= +25°C, f = 1MHz, C_L= 4µF

T_A= +25°C

50

Output voltage noise density

(high-frequency noise)

20

nV/√Hz

16

Load regulation, sourcing⁽⁶⁾

Load regulation, sinking⁽⁶⁾

Output current load capability⁽³⁾

Line regulation

30

µV/mA

mA

T_A= +25°C

15

±20

10

T_A= +25°C

µV/V

ppm

Long-term stability/drift (aging)⁽⁶⁾

T_A= +25°C, time = 0 to 1900 hours

First cycle

50

100

25

Thermal hysteresis⁽⁶⁾

ppm

Additional cycles

LOGIC INPUTS⁽³⁾

Input current

±1

µA

V

V_INL

Logic input LOW voltage

Logic input HIGH voltage

2.7V ≤ AV_DD≤ 5.5V

0.8

3

V_INH

1.8

V

Pin capacitance

pF

(3) Specified by design or characterization; not production tested.

(4) Reference is trimmed and tested at room temperature, and is characterized from –40°C to +125°C.

(5) Reference is trimmed and tested at two temperatures (+25°C and +105°C), and is characterized from –40°C to +125°C.

(6) Explained in more detail in the Application Information section of this data sheet.

4

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ELECTRICAL CHARACTERISTICS (continued)

At AV_DD= 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).

DAC7568/DAC8168/DAC8568

PARAMETER

POWER REQUIREMENTS

AV_DD

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2.7

5.5

1.4

V

AV_DD= 3.6V to 5.5V

V_INH = AV_DDand V_INL = GND

0.95

0.81

1.25

1.1

Normal mode, internal

reference switched off

mA

µA

AV_DD= 2.7V to 3.6V

V_INH = AV_DDand V_INL = GND

1.3

2.0

1.9

3

AV_DD= 3.6V to 5.5V

V_INH = AV_DDand V_INL = GND

Normal mode, internal

reference switched on

(7)

I_DD

AV_DD= 2.7V to 3.6V

V_INH = AV_DDand V_INL = GND

AV_DD= 3.6V to 5.5V

V_INH = AV_DDand V_INL = GND

0.18

0.10

3.4

All power-down modes

AV_DD= 2.7V to 3.6V

V_INH = AV_DDand V_INL = GND

2.5

7.7

4.7

11

6.8

16

9

AV_DD= 3.6V to 5.5V

V_INH = AV_DDand V_INL = GND

Normal mode, internal

reference switched off

mW

AV_DD= 2.7V to 3.6V

V_INH = AV_DDand V_INL = GND

2.2

AV_DD= 3.6V to 5.5V

V_INH = AV_DDand V_INL = GND

4.5

Power

Normal mode, internal

reference switched on

dissipation⁽⁷⁾

AV_DD= 2.7V to 3.6V

V_INH = AV_DDand V_INL = GND

2.9

AV_DD= 3.6V to 5.5V

V_INH = AV_DDand V_INL = GND

0.6

All power-down modes

µW

AV_DD= 2.7V to 3.6V

V_INH = AV_DDand V_INL = GND

0.3

TEMPERATURE RANGE

Specified performance

–40

+125

°C

(7) Input code = midscale, no load.

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PIN CONFIGURATIONS

PW PACKAGE

TSSOP-16

TSSOP-14

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15 D_IN

14

SCLK

LDAC

SYNC

AV_DD

14

13

12

11

10

9

1

2

3

4

5

6

7

SCLK

D_IN

SYNC

AV_DD

GND

V_OUT

V_REFIN/V_REFOUT

A

GND

DAC7568

DAC8168

DAC7568

DAC8168

DAC8568

13 V_OUT

12 V_OUT

11 V_OUT

10 V_OUT

B

D

F

V_OUT

V_REFIN/V_REFOUT

A

C

V_OUT

B

C

E

D

F

E

G

H

G

8

H

9

CLR

PIN DESCRIPTIONS

16-PIN 14-PIN

NAME

DESCRIPTION

1

—

LDAC

Load DACs.

Level-triggered control input (active low). This input is the frame synchronization signal for the input

data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent

falling clock edges. The DAC output updates following the 32nd clock. If SYNC is taken high before

the 31st clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored

by the DAC7568/DAC8168/DAC8568. Schmitt-Trigger logic input.

2

1

SYNC

AV_DD

3

4

5

6

7

2

3

4

5

6

Power-supply input, 2.7V to 5.5V

Analog output voltage from DAC A

Analog output voltage from DAC C

Analog output voltage from DAC E

Analog output voltage from DAC G

V_OUT

A

C

E

V_OUT

G

V_REFIN/

V_REFOUT

8

7

Positive reference input / reference output 2.5V if internal reference used.⁽¹⁾

9

—

8

CLR

Asynchronous clear input.

10

11

12

13

14

V_OUT

H

Analog output voltage from DAC H

Analog output voltage from DAC F

Analog output voltage from DAC D

Analog output voltage from DAC B

Ground reference point for all circuitry on the device

9

V_OUT

F

10

11

12

V_OUT

D

B

V_OUT

GND

Serial data input. Data are clocked into the 32-bit input shift register on each falling edge of the serial

clock input. Schmitt-Trigger logic input.

15

16

13

14

D_IN

SCLK

Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.

(1) Grades A and B, external V_REFIN (max) ≤ AV_DD; grades C and D, external V_REFIN (max) ≤ AV_DD/2.

6

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TIMING DIAGRAM

t₁

t₂

t₃

SCLK

t₆

t₇

t₈

t₄

t₅

SYNC

DIN

t₁₀

t₉

DB31

DB0

t₁₁

t₁₂

LDAC⁽¹⁾

LDAC⁽²⁾

t₁₃

t₁₄

t₁₅

CLR

(1) Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section.

(2) Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section.

Figure 1. Serial Write Operation

TIMING REQUIREMENTS⁽¹⁾⁽²⁾

At AV_DD= 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).

DAC7568/DAC8168/DAC8568

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SCLK falling edge to SYNC falling edge (for

successful write operation)

t₁

t₂

t₃

AV_DD= 2.7V to 5.5V

10

ns

(3)

SCLK cycle time

AV_DD= 2.7V to 5.5V

20

13

SYNC rising edge to 31st SCLK falling edge

(for successful SYNC interrupt)

t₄

t₅

t₆

t₇

t₈

t₉

Minimum SYNC HIGH time

SYNC to SCLK falling edge setup time

SCLK LOW time

AV_DD= 2.7V to 5.5V

80

13

8

ns

SCLK HIGH time

8

SCLK falling edge to SYNC rising edge

Data setup time

10

6

t₁₀Data hold time

SCLK falling edge to LDAC falling edge for

asynchronous LDAC update mode

4

t₁₁

AV_DD= 2.7V to 5.5V

40

80

ns

t₁₂LDAC pulse width LOW time

LDAC falling edge to SCLK falling edge for

synchronous LDAC update mode

t₁₃

4 × t₁

t₁₄32nd SCLK falling edge to LDAC rising edge

t₁₅CLR pulse width LOW time

AV_DD= 2.7V to 5.5V

40

80

ns

(1) All input signals are specified with t_R= t_F= 3ns (10% to 90% of AV_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

(2) See the Serial Write Operation timing diagram.

(3) Maximum SCLK frequency is 50MHz at AV_DD= 2.7V to 5.5V.

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TYPICAL CHARACTERISTICS: Internal Reference

At T_A= +25°C, unless otherwise noted.

INTERNAL REFERENCE VOLTAGE

vs TEMPERATURE (Grades C and D)

INTERNAL REFERENCE VOLTAGE

vs TEMPERATURE (Grades A and B)

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.503

2.502

2.501

2.500

2.499

2.498

2.497

10 Units Shown

13 Units Shown

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 2.

Figure 3.

REFERENCE OUTPUT TEMPERATURE DRIFT

(–40°C to +125°C, Grades C and D)

REFERENCE OUTPUT TEMPERATURE DRIFT

(–40°C to +125°, Grades A and B)

40

30

20

10

0

30

20

10

0

Typ: 5ppm/°C

Typ: 2ppm/°C

Max: 5ppm/°C

Max: 25ppm/°C

0.5

1

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Temperature Drift (ppm/°C)

Figure 4.

3

5

7

9

11

13

15

17

19

Temperature Drift (ppm/°C)

Figure 5.

LONG-TERM

REFERENCE OUTPUT TEMPERATURE DRIFT

(0°C to +125°C, Grades C and D)

STABILITY/DRIFT⁽¹⁾

200

150

100

50

40

30

20

10

0

Typ: 1.2ppm/°C

Max: 3ppm/°C

0

-50

-100

-150

-200

Average

20 Units Shown

1200 1500 1800

0

300

600

900

0.5

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Temperature Drift (ppm/°C)

Figure 6.

Time (Hours)

Figure 7.

(1) See the Application Information section of this data sheet for more details.

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TYPICAL CHARACTERISTICS: Internal Reference (continued)

At T_A= +25°C, unless otherwise noted.

INTERNAL REFERENCE NOISE DENSITY

vs FREQUENCY

INTERNAL REFERENCE NOISE

0.1Hz TO 10Hz

300

250

200

150

100

50

12mV (peak-to-peak)

Reference Unbuffered

C_REF= 0mF

C_REF= 4.8mF

0

Time (2s/div)

10

100

1k

10k

100k

1M

20 25

5.5

Frequency (Hz)

Figure 8.

Figure 9.

INTERNAL REFERENCE VOLTAGE

vs LOAD CURRENT (Grades C and D)

INTERNAL REFERENCE VOLTAGE

vs LOAD CURRENT (Grades A and B)

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

+125°C

-40°C

+25°C

+125°C

-40°C

-25 -20 -15 -10 -5

0

5

10

15

-25 -20 -15 -10 -5

0

5

10

15

20 25

I_LOAD(mA)

Figure 10.

Figure 11.

INTERNAL REFERENCE VOLTAGE

vs SUPPLY VOLTAGE (Grades C and D)

INTERNAL REFERENCE VOLTAGE

vs SUPPLY VOLTAGE (Grades A and B)

2.503

2.502

2.501

2.500

2.499

2.498

2.503

2.502

2.501

2.500

2.499

2.498

+125°C

-40°C

+25°C

-40°C

2.5

3.0

3.5

4.0

4.5

5.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

AV_DD(V)

Figure 12.

Figure 13.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5V

Channel-specific information provided as examples. At T_A= +25°C, external reference used, DAC output not loaded, and all

DAC codes in straight binary data format, unless otherwise noted.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

6

4

6

4

Channel B

Channel C

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 5.5V, Ext. Ref. = 5.0V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 14.

Figure 15.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

6

4

6

4

Channel F

Channel G

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 5.5V, Ext. Ref. = 5.0V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 16.

Figure 17.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

6

4

6

4

Channel B

Channel C

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 5.5V, Ext. Ref. = 5.0V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 18.

Figure 19.

10

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5V (continued)

Channel-specific information provided as examples. At T_A= +25°C, external reference used, DAC output not loaded, and all

DAC codes in straight binary data format, unless otherwise noted.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

6

4

6

4

Channel F

Channel G

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 5.5V, Ext. Ref. = 5.0V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 20.

Figure 21.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+125°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+125°C)

6

4

6

4

Channel B

Channel C

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 5.5V, Ext. Ref. = 5.0V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 22.

Figure 23.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+125°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+125°C)

6

4

6

4

Channel F

Channel G

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 5.5V, Ext. Ref. = 5.0V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 24.

Figure 25.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5V (continued)

Channel-specific information provided as examples. At T_A= +25°C, external reference used, DAC output not loaded, and all

DAC codes in straight binary data format, unless otherwise noted.

OFFSET ERROR

vs TEMPERATURE

POWER-SUPPLY CURRENT

vs TEMPERATURE

1.6

1.2

1100

1000

900

AV_DD= 5.5V

Internal Reference Disabled

0.8

0.4

0

-0.4

-0.8

-1.2

-1.6

Ch A

Ch E

Ch F

Ch G

Ch H

800

Ch B

Ch C

Ch D

AV_DD= 5.5V

External Reference = 5V

Internal Reference Disabled

700

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 26.

Figure 27.

FULL-SCALE ERROR

vs TEMPERATURE

POWER-SUPPLY CURRENT

vs TEMPERATURE

0.020

0.015

0.010

0.005

0

1600

1400

1200

1000

AV_DD= 5.5V

Internal Reference Enabled

AV_DD= 5.5V

External V_REF= 5V

Internal Reference Disabled

Ch A

Ch B

Ch C

Ch D

Ch E

Ch F

Ch G

Ch H

-0.005

-0.010

-0.015

-0.020

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 28.

Figure 29.

GAIN ERROR

vs TEMPERATURE

POWER-DOWN CURRENT

vs TEMPERATURE

0.045

0.035

1..5

1.0

0.5

0

AV_DD= 5.5V

External V_REF= 5V

Internal Reference Disabled

AV_DD= 5.5V

Ch A

Ch B

Ch C

Ch D

Ch E

Ch F

Ch G

Ch H

0.025

0.015

0.005

-0.005

-0.015

-0.025

-0.035

-0.045

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 30.

Figure 31.

12

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5V (continued)

Channel-specific information provided as examples. At T_A= +25°C, external reference used, DAC output not loaded, and all

DAC codes in straight binary data format, unless otherwise noted.

SOURCE CURRENT AT POSITIVE RAIL

(Grades C and D)

SINK CURRENT AT NEGATIVE RAIL

(All Grades)

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

0.6

0.4

0.2

0

Channel C

AV_DD= 5.5V

Internal Reference Enabled

DAC Loaded with FFFFh

AV_DD= 5.5V

Internal Reference Enabled

DAC Loaded with 0000h

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

I_SOURCE(mA)

I_SINK(mA)

Figure 32.

Figure 33.

SOURCE CURRENT AT POSITIVE RAIL

(Grades C and D)

SINK CURRENT AT NEGATIVE RAIL

(All Grades)

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

0.6

0.4

0.2

0

Channel D

AV_DD= 5.5V

Internal Reference Enabled

DAC Loaded with FFFFh

AV_DD= 5.5V

Internal Reference Enabled

DAC Loaded with 0000h

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

10

I_SOURCE(mA)

I_SINK(mA)

Figure 34.

Figure 35.

SOURCE CURRENT AT POSITIVE RAIL

(Grades C and D)

SINK CURRENT AT NEGATIVE RAIL

(All Grades)

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

0.6

0.4

0.2

0

Channel H

AV_DD= 5.5V

Internal Reference Enabled

DAC Loaded with FFFFh

AV_DD= 5.5V

Internal Reference Enabled

DAC Loaded with 0000h

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

10

I_SOURCE(mA)

I_SINK(mA)

Figure 36.

Figure 37.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5V (continued)

Channel-specific information provided as examples. At T_A= +25°C, external reference used, DAC output not loaded, and all

DAC codes in straight binary data format, unless otherwise noted.

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

AV_DD= 5.5V

External Reference = 5V

AV_DD= 5.5V

Internal Reference Enabled and Included,

Code Loaded to all Eight DAC Channels

Internal Reference Disabled,

Code Loaded to all Eight DAC Channels

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 38.

Figure 39.

POWER-SUPPLY CURRENT

vs POWER-SUPPLY VOLTAGE

POWER-SUPPLY CURRENT

vs POWER-SUPPLY VOLTAGE

1000

900

800

700

1300

1200

1100

1000

AV_DD= 2.7V to 5.5V

Internal Reference Disabled

AV_DD= 2.7V to 5.5V

Internal Reference Enabled

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

AV_DD(V)

Figure 40.

Figure 41.

POWER-DOWN CURRENT

vs POWER-SUPPLY VOLTAGE

0.20

AV_DD= 2.7V to 5.5V

0.15

0.10

0.05

0

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

AV_DD(V)

Figure 42.

14

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5V (continued)

Channel-specific information provided as examples. At T_A= +25°C, external reference used, DAC output not loaded, and all

DAC codes in straight binary data format, unless otherwise noted.

POWER-SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

POWER-SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

2800

2400

2000

1600

1200

800

3200

2800

2400

2000

1600

1200

800

AV_DD= 5.5V

Internal Reference Disabled

SYNC Input (All other digital inputs = GND)

AV_DD= 5.5V

Internal Reference Enabled

SYNC Input (All other digital inputs = GND)

Sweep from 0V to 5.5V

Sweep from

5.5V to 0V

Sweep from

5.5V to 0V

400

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Logic Input Voltage (V)

Figure 43.

Figure 44.

POWER-SUPPLY CURRENT

HISTOGRAM

POWER-SUPPLY CURRENT

HISTOGRAM

35

30

25

20

15

10

5

35

30

25

20

15

10

5

AV_DD= 5.5V

Internal Reference Disabled

AV_DD= 5.5V

Internal Reference Enabled

V_REF= 2.5V

0

I_DD(mA)

Figure 45.

Figure 46.

SIGNAL-TO-NOISE RATIO

vs OUTPUT FREQUENCY

95

93

91

89

87

85

83

81

79

77

75

Ch A

Ch B

Ch C

Ch D

Ch E

Ch F

Ch G

Ch H

AV_DD= 5.5V, External V_REF= 5V

f_S= 225kSPS, -1dB FSR Digital Input

Measurement Bandwidth = 20kHz

0

1

2

3

4

5

f_OUT(kHz)

Figure 47.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5V (continued)

Channel-specific information provided as examples. At T_A= +25°C, external reference used, DAC output not loaded, and all

DAC codes in straight binary data format, unless otherwise noted.

SECOND HARMONIC DISTORTION

POWER SPECTRAL DENSITY

vs OUTPUT FREQUENCY

0

-20

-40

-50

-60

-70

-80

-90

-100

AV_DD= 5.5V, External V_REF= 5V

_OUT= 1kHz, f_S= 225kSPS

Measurement Bandwidth = 20kHz

f

-40

Ch A

Ch B

Ch C

Ch D

Ch E

Ch F

Ch G

Ch H

-60

-80

-100

-120

-140

AV_DD= 5.5V, External V_REF= 5V

f_S= 225kSPS, -1dB FSR Digital Input

Measurement Bandwidth = 20kHz

0

5

10

15

20

0

1

2

3

4

5

Frequency (Hz)

f_OUT(kHz)

Figure 48.

Figure 49.

THIRD HARMONIC DISTORTION

vs OUTPUT FREQUENCY

TOTAL HARMONIC DISTORTION

vs OUTPUT FREQUENCY

-50

-60

-40

-50

-60

-70

-80

-90

AV_DD= 5.5V, External V_REF= 5V

f_S= 225kSPS, -1dB FSR Digital Input

Measurement Bandwidth = 20kHz

AV_DD= 5.5V, External V_REF= 5V

f_S= 225kSPS, -1dB FSR Digital Input

Measurement Bandwidth = 20kHz

-70

-80

Ch A

Ch B

Ch C

Ch D

Ch E

Ch F

Ch G

Ch H

Ch A

Ch B

Ch C

Ch D

Ch E

Ch F

Ch G

Ch H

-90

-100

0

1

2

3

4

5

0

1

2

3

4

5

f_OUT(kHz)

Figure 50.

Figure 51.

FULL-SCALE SETTLING TIME:

5V RISING EDGE

FULL-SCALE SETTLING TIME:

5V FALLING EDGE

AV_DD= 5.5V

From Code: FFFFh

To Code: 0000h

Zoomed Rising Edge

200mV/div

Zoomed Falling Edge

200mV/div

Falling

Edge

1V/div

Internal Reference Enabled

Rising

Edge

1V/div

AV_DD= 5.5V

From Code: 0000h

To Code: FFFFh

Internal Reference Enabled

Trigger Pulse 5V/div

Time (2ms/div)

Figure 52.

Figure 53.

16

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5V (continued)

Channel-specific information provided as examples. At T_A= +25°C, external reference used, DAC output not loaded, and all

DAC codes in straight binary data format, unless otherwise noted.

HALF-SCALE SETTLING TIME:

5V RISING EDGE

HALF-SCALE SETTLING TIME:

5V FALLING EDGE

AV_DD= 5.5V

Zoomed Rising Edge

200mV/div

Zoomed Falling Edge

200mV/div

From Code: 4000h

To Code: C000h

Internal Reference Enabled

From Code: C000h

To Code: 4000h

Internal Reference Enabled

Falling

Edge

1V/div

Rising

Edge

1V/div

Trigger Pulse 5V/div

Time (2ms/div)

Figure 54.

Figure 55.

CLOCK FEEDTHROUGH

2MHz, MIDSCALE

POWER-ON GLITCH

RESET TO ZERO SCALE

AV_DD= 5.5V

Clock Feedthrough Impulse ~0.5nV-s

Internal Reference Enabled

~18mV_PP

Channel C

Channel D

~4mV_PP

AV_DD= 5.5V

External Reference = 2.5V

DAC = Zero Scale

Load = 470pF || 2kW

Time (1ms/div)

Time (4ms/div)

Figure 56.

Figure 57.

POWER-ON GLITCH

RESET TO MIDSCALE

POWER-OFF GLITCH

~4mV_PP

Channels A/B

AV_DD

Channel C

Channel D

AV_DD= 5.5V

External Reference = 2.5V

DAC = Midscale

AV_DD= 5.5V

DAC = Zero Scale

Load = 470pF || 2kW

Time (20ms/div)

Time (4ms/div)

Figure 58.

Figure 59.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5V (continued)

Channel-specific information provided as examples. At T_A= +25°C, external reference used, DAC output not loaded, and all

DAC codes in straight binary data format, unless otherwise noted.

GLITCH ENERGY:

5V, 1LSB STEP, RISING EDGE

GLITCH ENERGY:

5V, 1LSB STEP, FALLING EDGE

AV_DD= 5.5V

LDAC/Clock Feedthrough

From Code:7FFFh

To Code: 8000h

Channel C as Example

From Code:8000h

To Code: 7FFFh

Channel C as Example

Glitch Impulse

~0.15nV-s

Glitch Impulse

~0.1nV-s

LDAC/Clock Feedthrough

LDAC Trigger Pulse 5V/div

Time (5ms/div)

Figure 60.

Figure 61.

GLITCH ENERGY:

5V, 4LSB STEP, RISING EDGE

GLITCH ENERGY:

5V, 4LSB STEP, FALLING EDGE

AV_DD= 5.5V

From Code:7FFCh

To Code: 8000h

Channel D as Example

LDAC/Clock Feedthrough

Glitch Impulse

~0.15nV-s

AV_DD= 5.5V

From Code:8000h

To Code: 7FFCh

Channel D as Example

Glitch Impulse

~0.1nV-s

LDAC/Clock Feedthrough

LDAC Trigger Pulse 5V/div

Time (5ms/div)

Figure 62.

Figure 63.

GLITCH ENERGY:

5V, 16LSB STEP, RISING EDGE

GLITCH ENERGY:

5V, 16LSB STEP, FALLING EDGE

AV_DD= 5.5V

From Code:7FF0h

To Code: 8000h

Channel H as Example

LDAC/Clock Feedthrough

Glitch Impulse

~0.06nV-s

AV_DD= 5.5V

LDAC/Clock Feedthrough

From Code:8000h

To Code: 7FF0h

Channel H as Example

Glitch Impulse

~0.01nV-s

LDAC Trigger Pulse 5V/div

Time (5ms/div)

Figure 64.

Figure 65.

18

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 5.5V (continued)

Channel-specific information provided as examples. At T_A= +25°C, external reference used, DAC output not loaded, and all

DAC codes in straight binary data format, unless otherwise noted.

DAC OUTPUT NOISE DENSITY

vs FREQUENCY⁽¹⁾

DAC OUTPUT NOISE

0.1Hz TO 10Hz

600

500

400

300

200

100

0

AV_DD= 5.5V

AV_DD= 5V

DAC V_OUTA Unloaded

Internal Reference Enabled

DAC = Midscale, No Load

Internal Reference = 2.5V

Channel D

Full Scale

Midscale

~3mV_PP

Zero Scale

Time (2s/div)

10

100

1k

10k

100k

Frequency (Hz)

Figure 66.

Figure 67.

(1) See the Application Information section of this data sheet for more details.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 3.6V

Channel-specific information provided as examples. At T_A= +25°C, internal reference used, and DAC output not loaded, all

DAC codes in straight binary data format, unless otherwise noted

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

POWER-SUPPLY CURRENT

vs TEMPERATURE

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

900

800

700

600

AV_DD= 3.6V

Internal Reference Disabled

AV_DD= 3.6V

Internal Reference Enabled and Included,

Code Loaded to all Eight DAC Channels

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 68.

Figure 69.

POWER-SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

POWER-SUPPLY CURRENT

vs TEMPERATURE

1600

1400

1200

1000

800

1400

1300

1200

1100

1000

900

AV_DD= 3.6V

Internal Reference Enabled

AV_DD= 3.6V

Internal Reference Disabled

SYNC Input (All other digital inputs = GND)

Sweep from 0V to 3.6V

600

Sweep from

3.6V to 0V

400

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-40 -25 -10

5

20 35 50 65 80 95 110 125

Logic Input Voltage (V)

Temperature (°C)

Figure 70.

Figure 71.

POWER-SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

POWER-DOWN CURRENT

vs TEMPERATURE

2000

1800

1600

1400

1200

1000

800

1.0

0.8

0.6

0.4

0.2

0

AV_DD= 3.6V

Internal Reference Enabled

SYNC Input (All other digital inputs = GND)

Sweep from 0V to 3.6V

Sweep from

3.6V to 0V

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-40 -25 -10

5

20 35 50 65 80 95 110 125

Logic Input Voltage (V)

Temperature (°C)

Figure 72.

Figure 73.

20

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 3.6V (continued)

Channel-specific information provided as examples. At T_A= +25°C, internal reference used, and DAC output not loaded, all

DAC codes in straight binary data format, unless otherwise noted

POWER-SUPPLY CURRENT

HISTOGRAM

POWER-SUPPLY CURRENT

HISTOGRAM

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

AV_DD= 3.6V

Internal Reference Disabled

AV_DD= 3.6V

Internal Reference Enabled

V_REF= 2.5V

0

I_DD(mA)

Figure 74.

Figure 75.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7V

Channel-specific information provided as examples. At T_A= +25°C, internal reference used, and DAC output not loaded, all

DAC codes in straight binary data format, unless otherwise noted

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

6

4

6

4

Channel A

Channel D

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 2.7V, Int. Ref. = 2.5V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 76.

Figure 77.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C)

6

4

6

4

Channel E

Channel H

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 2.7V, Int. Ref. = 2.5V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 78.

Figure 79.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

6

4

6

4

Channel A

Channel D

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 2.7V, Int. Ref. = 2.5V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 80.

Figure 81.

22

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7V (continued)

Channel-specific information provided as examples. At T_A= +25°C, internal reference used, and DAC output not loaded, all

DAC codes in straight binary data format, unless otherwise noted

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C)

6

4

6

4

Channel E

Channel H

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 2.7V, Int. Ref. = 2.5V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 82.

Figure 83.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+105°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+105°C)

6

4

6

4

Channel A

Channel D

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 2.7V, Int. Ref. = 2.5V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 84.

Figure 85.

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+105°C)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+105°C)

6

4

6

4

Channel E

Channel H

2

0

-2

-4

-6

-2

-4

-6

AV_DD= 2.7V, Int. Ref. = 2.5V

1.0

0.5

1.0

0.5

0

-0.5

-1.0

-0.5

-1.0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 86.

Figure 87.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7V (continued)

Channel-specific information provided as examples. At T_A= +25°C, internal reference used, and DAC output not loaded, all

DAC codes in straight binary data format, unless otherwise noted

OFFSET ERROR

vs TEMPERATURE

POWER-SUPPLY CURRENT

vs TEMPERATURE

1.6

1.2

900

800

700

600

500

AV_DD= 2.7V

Internal Reference Disabled

0.8

0.4

0

-0.4

-0.8

-1.2

-1.6

Ch A

Ch E

Ch F

Ch G

Ch H

Ch B

Ch C

Ch D

AV_DD= 2.7V

Internal V_REF= 2.5V

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 88.

Figure 89.

FULL-SCALE ERROR

vs TEMPERATURE

POWER-SUPPLY CURRENT

vs TEMPERATURE

0.040

1300

1200

1100

1000

900

AV_DD= 2.7V

Internal Reference Enabled

0.030

0.020

0.010

0

-0.010

Ch A

Ch E

Ch F

Ch G

Ch H

-0.020

Ch B

Ch C

Ch D

-0.030 AV_DD= 2.7V

Internal V_REF= 2.5V

-0.040

800

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 90.

Figure 91.

POWER-DOWN CURRENT

vs TEMPERATURE

vs

0.045

0.035

1.0

0.8

0.6

0.4

0.2

0

AV_DD= 2.7V

Ch A

Ch B

Ch C

Ch D

Ch E

Ch F

Ch G

Ch H

AV_DD= 2.7V

Internal V_REF= 2.5V

0.025

0.015

0.005

-0.005

-0.015

-0.025

-0.035

-0.045

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 92.

Figure 93.

24

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7V (continued)

Channel-specific information provided as examples. At T_A= +25°C, internal reference used, and DAC output not loaded, all

DAC codes in straight binary data format, unless otherwise noted

SOURCE CURRENT AT POSITIVE RAIL

(Grades A and B)

SINK CURRENT AT NEGATIVE RAIL

(All Grades)

2.7

2.5

2.3

2.1

1.9

0.6

0.4

0.2

0

Channel A

AV_DD= 2.7V

Internal Reference Enabled

DAC Loaded with FFFFh

AV_DD= 2.7V

Internal Reference Enabled

DAC Loaded with 0000h

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

I_SOURCE(mA)

I_SINK(mA)

Figure 94.

Figure 95.

SOURCE CURRENT AT POSITIVE RAIL

(Grades A and B)

SINK CURRENT AT NEGATIVE RAIL

(All Grades)

2.7

2.5

2.3

2.1

1.9

0.6

0.4

0.2

0

Channel B

AV_DD= 2.7V

Internal Reference Enabled

DAC Loaded with FFFFh

AV_DD= 2.7V

Internal Reference Enabled

DAC Loaded with 0000h

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

10

I_SOURCE(mA)

I_SINK(mA)

Figure 96.

Figure 97.

SOURCE CURRENT AT POSITIVE RAIL

(Grades A and B)

SINK CURRENT AT NEGATIVE RAIL

(All Grades)

2.7

2.5

2.3

2.1

1.9

0.6

0.4

0.2

0

Channel G

AV_DD= 2.7V

Internal Reference Enabled

DAC Loaded with FFFFh

AV_DD= 2.7V

Internal Reference Enabled

DAC Loaded with 0000h

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

10

I_SOURCE(mA)

I_SINK(mA)

Figure 98.

Figure 99.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7V (continued)

Channel-specific information provided as examples. At T_A= +25°C, internal reference used, and DAC output not loaded, all

DAC codes in straight binary data format, unless otherwise noted

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

1000

900

800

700

600

500

400

AV_DD= 2.7V

Internal Reference Enabled and Included,

Code Loaded to all Eight DAC Channels

External Reference = 2.5V

Internal Reference Disabled and Not Included

Code Loaded to all Eight DAC Channels

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 100.

Figure 101.

POWER-SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

POWER-SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

1100

1000

900

800

700

600

500

400

1400

1300

1200

1100

1000

900

AV_DD= 2.7V

Internal Reference Disabled

SYNC Input (All other digital inputs = GND)

AV_DD= 2.7V

Internal Reference Enabled

SYNC Input (All other digital inputs = GND)

Sweep from

0V to 2.7V

Sweep from

0V to 2.7V

Sweep from

2.7V to 0V

Sweep from

2.7V to 0V

800

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

Logic Input Voltage (V)

Figure 102.

Figure 103.

POWER-SUPPLY CURRENT

HISTOGRAM

POWER-SUPPLY CURRENT

HISTOGRAM

40

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

AV_DD= 2.7V

Internal Reference Disabled

AV_DD= 2.7V

Internal Reference Enabled

V_REF= 2.5V

0

I_DD(mA)

Figure 104.

Figure 105.

26

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7V (continued)

Channel-specific information provided as examples. At T_A= +25°C, internal reference used, and DAC output not loaded, all

DAC codes in straight binary data format, unless otherwise noted

FULL-SCALE SETTLING TIME:

2.7V RISING EDGE

FULL-SCALE SETTLING TIME:

2.7V FALLING EDGE

Zoomed Rising Edge

200mV/div

Falling

Edge

1V/div

AV_DD= 2.7V

From Code: FFFFh

To Code: 0000h

Rising

Edge

1V/div

Zoomed Falling Edge

200mV/div

AV_DD= 2.7V

From Code: 0000h

To Code: FFFFh

Trigger

Pulse

5V/div

Trigger Pulse

5V/div

Time (2ms/div)

Figure 106.

Figure 107.

HALF-SCALE SETTLING TIME:

2.7V RISING EDGE

HALF-SCALE SETTLING TIME:

2.7V FALLING EDGE

AV_DD= 2.7V

From Code: C000h

To Code: 4000h

Rising

Edge

1V/div

Falling

Edge

1V/div

Zoomed Rising Edge

200mV/div

Zoomed Falling Edge

200mV/div

AV_DD= 2.7V

From Code: 4000h

To Code: C000h

Trigger

Pulse

5V/div

Trigger

Pulse

5V/div

Time (2ms/div)

Figure 108.

Figure 109.

CLOCK FEEDTHROUGH

2.7V, 2MHz, MIDSCALE

POWER-ON GLITCH

RESET TO ZERO SCALE

AV_DD= 2.7V

Clock Feedthrough Impulse ~0.4nV-s

Internal Reference Enabled

~8mV_PP

~4mV_PP

Channel E

Channel F

AV_DD= 2.7V

External Reference = 2.5V

DAC = Zero Scale

Load = 470pF || 2kW

Time (1ms/div)

Time (4ms/div)

Figure 110.

Figure 111.

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7V (continued)

Channel-specific information provided as examples. At T_A= +25°C, internal reference used, and DAC output not loaded, all

DAC codes in straight binary data format, unless otherwise noted

POWER-ON GLITCH

RESET TO MIDSCALE

POWER-OFF GLITCH

Channels G/H

Channel C

Channel D

AV_DD

AV_DD= 2.7V

External Reference = 2.5V

DAC = Midscale

AV_DD= 2.7V

DAC = Zero Scale

Load = 470pF || 2kW

Time (20ms/div)

Time (4ms/div)

Figure 112.

Figure 113.

GLITCH ENERGY:

2.7V, 1LSB STEP, RISING EDGE

GLITCH ENERGY:

2.7V, 1LSB STEP, FALLING EDGE

AV_DD= 2.7V

LDAC/Clock Feedthrough

From Code:7FFFh

To Code: 8000h

Channel E as Example

From Code:8000h

To Code: 7FFFh

Channel E as Example

Glitch Impulse

~0.15nV-s

Glitch Impulse

~0.2nV-s

LDAC/Clock Feedthrough

LDAC Trigger Pulse 5V/div

Time (5ms/div)

Figure 114.

Figure 115.

GLITCH ENERGY:

2.7V, 4LSB STEP, RISING EDGE

GLITCH ENERGY:

2.7V, 4LSB STEP, FALLING EDGE

AV_DD= 2.7V

LDAC/Clock Feedthrough

From Code:8000h

To Code: 7FFCh

Channel A as Example

From Code:7FFCh

To Code: 8000h

Channel A as Example

Glitch Impulse

~0.1nV-s

LDAC/Clock Feedthrough

LDAC Trigger Pulse 5V/div

Glitch Impulse

~0.08nV-s

LDAC Trigger Pulse 5V/div

Time (5ms/div)

Figure 116.

Figure 117.

28

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TYPICAL CHARACTERISTICS: DAC at AV_DD= 2.7V (continued)

Channel-specific information provided as examples. At T_A= +25°C, internal reference used, and DAC output not loaded, all

DAC codes in straight binary data format, unless otherwise noted

GLITCH ENERGY:

2.7V, 16LSB STEP, RISING EDGE

GLITCH ENERGY:

2.7V, 16LSB STEP, FALLING EDGE

AV_DD= 2.7V

LDAC/Clock Feedthrough

From Code:7FF0h

To Code: 8000h

Channel B as Example

Glitch Impulse

~0.2nV-s

AV_DD= 2.7V

LDAC/Clock Feedthrough

LDAC Trigger Pulse 5V/div

From Code:8000h

To Code: 7FF0h

Channel B as Example

Glitch Impulse

~0.04nV-s

LDAC Trigger Pulse 5V/div

Time (5ms/div)

Figure 118.

Figure 119.

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THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER (DAC)

V_REF

The DAC7568, DAC8168, and DAC8568 architecture

consists of eight string DACs each followed by an

output buffer amplifier. The devices include an

internal 2.5V reference with 2ppm/°C temperature

drift performance, and offer either 5V or 2.5V full

scale output voltage. Figure 120 shows a principal

block diagram of the DAC architecture.

R_DIVIDER

V_REF

2

R

V_REFH

50kW

To Output Amplifier

(2x Gain)

R

62kW

V_OUTX

REF(+)

Resistor String

REF(-)

DAC

Register

V_REFL

Figure 120. Device Architecture

The input coding to the DAC7568, DAC8168, and

DAC8568 is straight binary, so the ideal output

voltage is given by Equation 1:

R

D_IN

V_OUT

=

´ V_REF´ Gain

2ⁿ

(1)

Where:

D_IN= decimal equivalent of the binary code that

is loaded to the DAC register. It can range from 0

to 4095 for DAC7568 (12 bit), 0 to 16,383 for

DAC8168 (14 bit), and 0 to 65535 for DAC8568

(16 bit).

n = resolution in bits; either 12 (DAC7568), 14

(DAC8168) or 16 (DAC8568)

Figure 121. Resistor String

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating

rail-to-rail voltages on its output, giving a maximum

output range of 0V to AV_DD. It is capable of driving a

load of 2kΩ in parallel with 3000pF to GND. The

source and sink capabilities of the output amplifier

can be seen in the Typical Characteristics. The

typical slew rate is 0.75V/µs, with a typical full-scale

settling time of 5µs with the output unloaded.

Gain = 1 for A/B grades or 2 for C/D grades.

RESISTOR STRING

The resistor string section is shown in Figure 121. It

is simply a string of resistors, each of value R. The

code loaded into the DAC register determines at

which node on the string the voltage is tapped off to

be fed into the output amplifier by closing one of the

switches connecting the string to the amplifier. It is

monotonic because it is a string of resistors.

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Enable/Disable Internal Reference

INTERNAL REFERENCE

The internal reference in the DAC7568, DAC8168,

and DAC8568 is disabled by default for debugging,

evaluation purposes, or when using an external

reference. The internal reference can be powered up

and powered down using a serial command that

requires a 32-bit write sequence (see the Serial

Interface section), as shown in Table 1 and Table 3.

During the time that the internal reference is disabled,

the DAC functions normally using an external

reference. At this point, the internal reference is

disconnected from the V_REFIN/V_REFOUT pin (3-state

output). Do not attempt to drive the V_REFIN/V_REFOUT

pin externally and internally at the same time

indefinitely.

The DAC7568, DAC8168, and DAC8568 include a

2.5V internal reference that is disabled by default.

The internal reference is externally available at the

V_REFIN/V_REFOUT pin. A minimum 100nF capacitor is

recommended between the reference output and

GND for noise filtering.

The internal reference of the DAC7568, DAC8168,

and DAC8568 is a bipolar, transistor-based, precision

bandgap voltage reference. Figure 122 shows the

basic bandgap topology. Transistors Q₁and Q₂are

biased such that the current density of Q₁is greater

than that of Q₂. The difference of the two

base-emitter voltages (V_BE1– V_BE2) has a positive

temperature coefficient and is forced across resistor

R₁. This voltage is gained up and added to the

base-emitter voltage of Q₂, which has a negative

temperature coefficient. The resulting output voltage

is virtually independent of temperature. The

short-circuit current is limited by design to

approximately 100mA.

There are two modes that allow communication with

the internal reference: Static and Flexible. In Flexible

mode, DB19 must be set to '1'.

Static Mode (see Table 1 and Table 2)

Enabling Internal Reference:

To enable the internal reference, write the 32-bit

serial command shown in Table 1. When performing

a power cycle to reset the device, the internal

reference is switched off (default mode). In the

default mode, the internal reference is powered down

until a valid write sequence is applied to power up the

internal reference. If the internal reference is powered

up, it automatically powers down when all DACs

power down in any of the power-down modes (see

the Power Down Modes section). The internal

reference automatically powers up when any DAC is

powered up.

V_REF

Reference

Disable

Q₁

1

N

Q₂

R₁

Disabling Internal Reference:

To disable the internal reference, write the 32-bit

serial command shown in Table 2. When performing

a power cycle to reset the device, the internal

reference is put back into its default mode and

switched off (default mode).

R₂

Figure 122. Bandgap Reference Simplified

Schematic

Table 1. Write Sequence for Enabling Internal Reference (Static Mode)

(Internal Reference Powered On—08000001h)

DB31

DB27

1

DB23

DB19

DB4

X

DB0

1

0

X

0

X

|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |

Table 2. Write Sequence for Disabling Internal Reference (Static Mode)

(Internal Reference Powered On—08000000h)

DB31

DB27

1

DB23

DB19

DB4

X

DB0

0

X

0

X

|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |

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Flexible Mode (see Table 3, Table 4, and Table 5)

performing a power cycle to reset the device, the

internal reference is switched off (default mode). In

the default mode, the internal reference is powered

down until a valid write sequence is applied to power

up the internal reference. When the internal reference

is powered up, it remains powered up, regardless of

the state of the DACs.

Enabling Internal Reference:

Method 1) To enable the internal reference, write the

32-bit serial command shown in Table 3. When

performing a power cycle to reset the device, the

internal reference is switched off (default mode). In

the default mode, the internal reference is powered

down until a valid write sequence is applied to power

up the internal reference. If the internal reference is

powered up, it automatically powers down when all

DACs power down in any of the power-down modes

(see the Power Down Modes section). The internal

reference powers up automatically when any DAC is

powered up.

Disabling Internal Reference:

To disable the internal reference, write the 32-bit

serial command shown in Table 5. When performing

a power cycle to reset the device, the internal

reference is switched off (default mode).

When the internal reference is operated in Flexible

mode, Static mode is disabled and does not work. To

switch from Flexible mode to Static mode, use the

command shown in Table 6.

Method 2) To always enable the internal reference,

write the 32-bit serial command shown in Table 4.

When the internal reference is always enabled, any

power-down command to the DAC channels does not

change the internal reference operating mode. When

Table 3. Write Sequence for Enabling Internal Reference (Flexible Mode)

(Internal Reference Powered On—09080000h)

DB31

DB27

DB23

DB19

DB4

X

DB0

X

0

X

1

0

1

X

1

0

X

|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |

Table 4. Write Sequence for Enabling Internal Reference (Flexible Mode)

(Internal Reference Always Powered On—090A0000h)

DB31

DB27

DB23

DB19

DB4

X

DB0

X

0

X

1

0

1

X

1

0

1

X

|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |

Table 5. Write Sequence for Disabling Internal Reference (Flexible Mode)

(Internal Reference Always Powered Down—090C0000h)

DB31

DB27

DB23

DB19

DB4

X

DB0

X

0

X

1

0

1

X

1

0

X

|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |

Table 6. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference

(Internal Reference Always Powered Down—09000000h)

DB31

DB27

DB23

DB19

DB4

DB0

X

0

X

1

0

1

X

0

X

|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |

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SERIAL INTERFACE

The data format is straight binary with all '0's

corresponding to 0V output and all '1's corresponding

to full-scale output. For all documentation purposes,

the data format and representation used here is a

true 16-bit pattern (that is, FFFFh for data word for

full-scale) that the DAC7568, DAC8168, and

DAC8568 require.

The DAC7568, DAC8168, and DAC8568 have a

3-wire serial interface (SYNC, SCLK, and D_IN; see the

Pin Configurations) compatible with SPI, QSPI, and

Microwire interface standards, as well as most DSPs.

See the Serial Write Operation timing diagram

(Figure 1) for an example of a typical write sequence.

The write sequence begins by bringing the SYNC line

low. Data from the D_INline are clocked into the 32-bit

shift register on each falling edge of SCLK. The serial

clock frequency can be as high as 50MHz, making

the DAC7568, DAC8168, and DAC8568 compatible

with high-speed DSPs. On the 32nd falling edge of

the serial clock, the last data bit is clocked into the

shift register and the shift register locks. Further

clocking does not change the shift register data. After

receiving the 32nd falling clock edge, the DAC7568,

DAC8168, and DAC8568 decode the four control bits

and four address bits and 16/14/12 data bits to

perform the required function, without waiting for a

SYNC rising edge. A new write sequence starts at the

next falling edge of SYNC. A rising edge of SYNC

before the 31st-bit sequence is complete resets the

SPI interface; no data transfer occurs. After the 32nd

falling edge of SCLK is received, the SYNC line may

be kept low or brought high. In either case, the

minimum delay time from the 32nd falling SCLK edge

to the next falling SYNC edge must be met in order to

properly begin the next cycle; see the Serial Write

Operation timing diagram (Figure 1). To assure the

lowest power consumption of the device, care should

be taken that the levels are as close to each rail as

possible. Refer to the 5.5V, 3.6V, and 2.7V Typical

Characteristics sections for the Power-Supply Current

vs Logic Input Voltage graphs (Figure 43, Figure 44,

Figure 70, Figure 72, Figure 102, and Figure 103).

The DAC7568, DAC8168, and DAC8568 input shift

register is 32-bits wide, consisting of four prefix bits

(DB31 to DB28), four control bits (DB27 to DB24), 16

data bits (DB23 to DB4), and four feature bits. The 16

data bits comprise the 16-, 14-, or 12-bit input code.

When writing to the DAC register (data transfer), bits

DB0 to DB3 (for 16-bit operation), DB0 to DB5 (for

14-bit operation), and DB0 to DB7 (for 12-bit

operation) are ignored by the DAC and should be

treated as don't care bits (see Table 7 to Table 9). All

32 bits of data are loaded into the DAC under the

control of the serial clock input, SCLK.

DB31 (MSB) is the first bit that is loaded into the DAC

shift register and must be always set to '0'. It is

followed by the rest of the 32-bit word pattern,

left-aligned. This configuration means that the first 32

bits of data are latched into the shift register and any

further clocking of data is ignored. When the DAC

registers are being written to, the DAC7568,

DAC8168, and DAC8568 receive all 32 bits of data,

ignore DB31 to DB28, and decode the second set of

four bits (DB27 to DB24) in order to determine the

DAC operating/control mode (see Table 10). Bits

DB23 to DB20 are used to address selected DAC

channels. The next 16/14/12 bits of data that follow

are decoded by the DAC to determine the equivalent

analog output. The last four data bits (DB0 to DB3 for

DAC8568), last data six bits (DB0 to DB5 for

DAC8168), or last eight data bits (DB0 to DB7 for

DAC7568) are ignored in this case. For more details

on these and other commands (such as write to

LDAC register, power down DACs, etc.), see

Table 10.

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INPUT SHIFT REGISTER

DB4), and four additional feature bits. The 16 data

bits comprise the 16-, 14-, or 12-bit input code.

The input shift register (SR) of the DAC7568,

DAC8168, and DAC8568 is 32 bits wide (as shown in

Table 7, Table 8, and Table 9, respectively), and

consists of four Prefix bits (DB31 to DB28), four

control bits (DB27 to DB24), 16 data bits (DB23 to

The DAC7568, DAC8168, and DAC8568 support a

number of different load commands. The load

commands are summarized in Table 10.

Table 7. DAC8568 Data Input Register Format

DB31

DB27

DB23

DB19

DB4

DB0

0

X

|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |

Table 8. DAC8168 Data Input Register Format

DB31

DB27

DB23

DB19

DB4

X

DB0

0

X

|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------- Data Bits --------------------------------|

| Feature Bits |

Table 9. DAC7568 Data Input Register Format

DB23

DB31

DB27

DB19

DB4

X

DB0

0

X

|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------- Data Bits --------------------------|

| Feature Bits |

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SYNC INTERRUPT

In synchronous mode, data are updated with the

In a normal write sequence, the SYNC line stays low

for at least 32 falling edges of SCLK and the

addressed DAC register updates on the 32nd falling

edge. However, if SYNC is brought high before the

31st falling edge, it acts as an interrupt to the write

sequence; the shift register resets and the write

sequence is discarded. Neither an update of the data

buffer contents, DAC register contents, nor a change

in the operating mode occurs (as shown in

Figure 123).

falling edge of the 32nd SCLK cycle, which follows a

falling edge of SYNC. For such synchronous updates,

the LDAC pin is not required and it must be

connected to GND permanently.

In asynchronous mode, the LDAC pin is used as a

negative

edge

triggered

timing

signal

for

simultaneous DAC updates. Multiple single-channel

updates can be done in order to set different channel

buffers to desired values and then make a falling

edge on LDAC pin to simultaneously update the DAC

output registers. Data buffers of all channels must be

loaded with desired data before an LDAC falling

edge. After a high-to-low LDAC transition, all DACs

are simultaneously updated with the last contents of

the corresponding data buffers. If the content of a

data buffer is not changed, the corresponding DAC

output remains unchanged after the LDAC pin is

triggered.

POWER-ON RESET TO ZERO SCALE OR

MIDSCALE

The DAC7568, DAC8168, and DAC8568 contain a

power-on reset circuit that controls the output voltage

during power-up. For device grades A and C on

power-up, all DAC registers are filled with zeros and

the output voltages of all DAC channels are set to

zero scale. For device grades B and D all DAC

registers are set to have all DAC channels power up

in midscale. All DAC channels remain that way until a

valid write sequence and load command are made to

the respective DAC channel. The power-on reset is

useful in applications where it is important to know

the state of the output of each DAC while the device

is in the process of powering up. No device pin

should be brought high before power is applied to the

device. The internal reference is powered off / down

by default and remains that way until a valid

reference-change command is executed.

Alternatively, all DAC outputs can be updated

simultaneously using the built-in software function of

LDAC. The LDAC register offers additional flexibility

and control by allowing the selection of which DAC

channel(s) should be updated simultaneously when

the LDAC pin is being brought low. The LDAC

register is loaded with an 8-bit word (DB0 to DB7)

using control bits C3, C2, C1, and C0 (see Table 10).

The default value for each bit, and therefore for each

DAC channel, is zero. The external LDAC pin

operates in normal mode. If the LDAC register bit is

set to '1', it overrides the LDAC pin (the LDAC pin is

internally tied low for that particular DAC channel)

and this DAC channel updates synchronously after

the falling edge of the 32nd SCLK cycle. However, if

the LDAC register bit is set to '0', the DAC channel is

controlled by the LDAC pin.

LDAC FUNCTIONALITY

The DAC7568, DAC8168, and DAC8568 offer both a

software and hardware simultaneous update and

control

function.

The

DAC

double-buffered

architecture has been designed so that new data can

be entered for each DAC without disturbing the

analog outputs.

The combination of software and hardware

simultaneous update functions is particularly useful in

applications when updating only selective DAC

channels simultaneously, while keeping the other

channels unaffected and updating those channels

synchronously; see Table 10 for more information.

DAC7568, DAC8168, and DAC8568 data updates

can be performed either in synchronous or in

asynchronous mode.

31st Falling Edge

32nd Falling Edge

CLK

SYNC

DB31

DB0

DB31

DB0

D_IN

Invalid/Interrupted Write Sequence:

Output/Mode Does Not Update on the 32nd Falling Edge

Valid Write Sequence:

Output/Mode Updates on the 32nd Falling Edge

Figure 123. SYNC Interrupt Facility

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POWER-DOWN MODES

DACs. However, for the three power-down modes,

the supply current falls to 0.18µA at 5.5V (0.10µA at

3.6V). Not only does the supply current fall, but the

output stage also switches internally from the output

of the amplifier to a resistor network of known values.

The DAC7568, DAC8168, and DAC8568 have two

separate sets of power-down commands. One set is

for the DAC channels and the other set is for the

internal reference. For more information on powering

down the reference, see the Enable/Disable Internal

Reference section.

The advantage of this switching is that the output

impedance of the device is known while it is in

power-down mode. As described in Table 11, there

are three different power-down options. V_OUTcan be

connected internally to GND through a 1kΩ resistor, a

100kΩ resistor, or open circuited (High-Z). The output

stage is shown in Figure 124. In other words, DB27,

DB26, DB25, and DB24 = '0100' and DB9 and DB8 =

'11' represent a power-down condition with High-Z

output impedance for a selected channel. DB9 and

DB8 = '01' represents a power-down condition with

1kΩ output impedance, and '10' represents a

power-down condition with 100kΩ output impedance.

DAC Power-Down Commands

The DAC7568, DAC8168, and DAC8568 use four

modes of operation. These modes are accessed by

setting control bits C3, C2, C1, and C0, and

power-down register bits DB8 and DB9. The control

bits must be set to '0100'. Once the control bits are

set correctly, the four different power down modes

are software programmable by setting bits DB8 and

DB9 in the control register. Table 10 and Table 11

shows how to control the operating mode with data

bits PD0 (DB8), and PD1 (DB9).

Table 11. DAC Operating Modes

Resistor

Amplifier

V_OUTX

String

DAC

PD1

(DB9)

PD0

(DB8)

DAC OPERATING MODES

Power up selected DACs

0

1

0

1

0

1

Power down selected DACs 1kΩ to GND

Power down selected DACs 100kΩ to GND

Power down selected DACs High-Z to GND

Power-Down

Circuitry

Resistor

Network

The DAC7568, DAC8168, and DAC8568 treat the

power-down condition as data; all the operational

modes are still valid for power-down. It is possible to

Figure 124. Output Stage During Power-Down

broadcast

a

power-down condition to all the

All analog channel circuits are shut down when the

power-down mode is exercised. However, the

contents of the DAC register are unaffected when in

power down. By setting both bits, DB8 and DB9, to

different values, any combination of DAC channels

can be powered down or powered up. If a DAC

channel is being powered up from a previously power

down situation, this DAC channel powers up to the

value in its DAC register. The time required to exit

power-down is typically 2.5µs for AV_DD= 5V, and 4µs

for AV_DD= 3V. See the Typical Characteristics for

more information.

DAC8568, DAC8168, DAC7568s in a system. It is

also possible to power-down a channel and update

data on other channels. Furthermore, it is possible to

write to the DAC register/buffer of the DAC channel

that is powered down. When the DAC channel is then

powered up, it will power up to this new value (see

the Operating Examples section).

When both the PD0 and PD1 bits are set to '0', the

device works normally with its typical current

consumption of 1.25mA at 5.5V. The reference

current is included with the operation of all eight

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CLEAR CODE REGISTER and CLR PIN

sequence, this write sequence is aborted and the

DAC registers and DAC buffers are cleared as

described previously.

The DAC7568, DAC8168, and DAC8568 contain a

clear code register. The clear code register can be

accessed via the serial peripheral interface (SPI) and

is user-configurable. Bringing the CLR pin low clears

the content of all DAC registers and all DAC buffers,

and replaces the code with the code determined by

the clear code register. The clear code register can

be written to by applying the commands showed in

Table 12. The control bits must be set as follows to

access the clear code register that is programmed via

the feature bits, F0 and F1: C3 = '0', C2 = '1', C1 =

'0', and C0 = '1'. The default setting of the clear code

register sets the output of all DAC channels to 0V

when CLR pin is brought low. The CLR pin is

falling-edge triggered; therefore, the device exits clear

code mode on the 32nd falling edge of the next write

sequence. If CLR pin is brought low during a write

When performing a software reset of the device, the

clear code register is set back to its default mode

(DB1 = DB0 = '0'). Setting the clear code register to

DB1 = DB0 = '1' ignores any activity on the external

CLR pin.

SOFTWARE RESET FUNCTION

The DAC7568, DAC8168, and DAC8568 contain a

software reset feature. If the software reset feature is

executed, all registers inside the device are reset to

default settings; that is, all DAC channels are reset to

the power-on reset code (power on reset to zero

scale for grades A and C; power on reset to midscale

for grades B and D).

Table 12. Clear Code Register

DB30-

DB28

DB19-

DB10

DESCRIPTION

Don't

D16-

D7

0

Care C3 C2 C1 C0 A3 A2 A1 A0

D6 D5 D4 D3 D2 D1 F3 F2 F1 F0

GENERAL DATA FORMAT

Clear all DAC outputs to zero scale (default

mode)

0

X

0

1

0

1

X

0

X

0

1

0

1

X

0

1

0

1

Clear all DAC outputs to midscale

Clear all DAC outputs to full-scale

Ignore external CLR pin

Table 13. Software Reset

DB30-

DB28

DB19-

DB10

DESCRIPTION

Don't

D16-

D7

0

Care C3 C2 C1 C0 A3 A2 A1 A0

D6 D5 D4 D3 D2 D1 F3 F2 F1 F0

GENERAL DATA FORMAT

0

X

0

1

X

Software reset

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OPERATING EXAMPLES: DAC7568/DAC8168/DAC8568

For the following examples X = don't care; value can be either '0' or '1'.

Example 1: Write to Data Buffer A, B, G, H; Load DAC A, B, G, H Simultaneously

1st: Write to data buffer A:

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

DATA

X

2nd: Write to data buffer B:

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

D16-

0

Care

C3

C2

C1

C0

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

DATA

X

3rd: Write to data buffer G:

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

D16-

0

Care

C3

C2

C1

C0

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

DATA

X

4th: Write to data buffer H and simultaneously update all DACs:

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

1

DATA

X

The DAC A, DAC B, DAC G, and DAC H analog outputs simultaneously settle to the specified values upon

completion of the 4th write sequence. (The DAC voltages update simultaneously after the 32nd SCLK falling

edge of the fourth write cycle).

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Example 2: Load New Data to DAC C, D, E, F Sequentially

1st: Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

1

0

DATA

X

2nd: Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

1

DATA

X

3rd: Write to data buffer E and load DAC E: DAC E output settles to specified value upon completion:

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

1

0

DATA

X

4th: Write to data buffer F and load DAC F: DAC F output settles to specified value upon completion:

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

1

0

1

DATA

X

After completion of each write cycle, the DAC analog output settles to the voltage specified.

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Example 3: Power-Down DAC A, DAC B and DAC H to 1kΩ and Power-Down DAC C, DAC D, and DAC F

to 100kΩ

1st: Write power-down command to DAC channel A and DAC channel B: DAC A and DAC B to 1kΩ.

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

1

0

1

2nd: Write power-down command to DAC channel H: DAC H to 1kΩ.

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

1

0

3rd: Write power-down command to DAC channel C and DAC channel D: DAC C and DAC D to 100kΩ.

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

1

0

1

0

4th: Write power-down command to DAC channel F: DAC F to 100kΩ.

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

1

0

1

0

The DAC A, DAC B, DAC C, DAC D, DAC F, and DAC H analog outputs power-down to each respective

specified mode.

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Example 4: Power-Down All Channels Simultaneously while Reference is Always Powered Up

1st: Write sequence for enabling the DAC7568, DAC8168, and DAC8568 internal reference all the time:

DB30-

DB28

DB16-

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D13-

D4

0

C3

C2

C1

C0

A3

A2

A1

A0 D16 D15 D14

D3

D2

D1

F3

F2

F1

F0

0

X

1

0

1

X

1

0

1

X

2nd: Write sequence to power-down all DACs to high-impedance:

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

0

X

1

The DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC G, and DAC H analog outputs simultaneously

power-down to high-impedance upon completion of the first and second write sequences, respectively.

Example 5: Write a Specific Value to All DACs while Reference is Always Powered Down

1st: Write sequence for disabling the DAC7568, DAC8168, and DAC8568 internal reference all the time

(after this sequence, these devices require an external reference source to function):

DB30-

DB28

DB16-

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D13-

D4

0

C3

C2

C1

C0

A3

A2

A1

A0 D16 D15 D14

D3

D2

D1

F3

F2

F1

F0

0

X

1

0

1

X

1

0

X

2nd: Write sequence to write specified data to all DACs:

DB30-

DB28

DB19-

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don't

Care

D16-

D7

0

C3

C2

C1

C0

A3

A2

A1

A0

D6

D5

D4

D3

D2

D1

F3

F2

F1

F0

0

X

0

1

DATA

X

The DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC G, and DAC H analog outputs simultaneously settle

to the specified values upon completion of the second write sequence. (The DAC voltages update simultaneously

after the 32nd SCLK falling edge of the second write cycle). Reference is always powered-down (External

reference must be used for proper operation).

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APPLICATION INFORMATION

INTERNAL REFERENCE

Temperature Drift

The internal reference of the DAC7568, DAC8168,

The internal reference is designed to exhibit minimal

and DAC8568 does not require an external load

drift error, defined as the change in reference output

capacitor for stability because it is stable with any

voltage over varying temperature. The drift is

capacitive load. However, for improved noise

calculated using the box method described by

Equation 2:

performance, an external load capacitor of 150nF or

larger connected to the V_REFH/V_REFOUT output is

recommended. Figure 125 shows the typical

V

_{REF_MAX}- V_{REF_MIN}

´ 10⁶(ppm/°C)

connections required for operation of the DAC7568,

DAC8168, and DAC8568 internal reference. A supply

bypass capacitor at the AV_DDinput is also

recommended.

Drift Error =

V_REF´ T_RANGE

(2)

Where:

V_{REF_MAX}= maximum reference voltage observed

within temperature range T_RANGE

V_{REF_MIN}= minimum reference voltage observed

within temperature range T_RANGE

V_REF= 2.5V, target value for reference output

voltage.

DAC7568

DAC8168

DAC8568

.

SCLK

D_IN

1

2

3

4

5

6

7

8

LDAC

SYNC

AV_DD

16

15

14

13

12

11

10

9

The internal reference (grade C only) features an

exceptional typical drift coefficient of 2ppm/°C from

–40°C to +125°C. Characterizing a large number of

units, a maximum drift coefficient of 5ppm/°C (grade

C only) is observed. Temperature drift results are

summarized in the Typical Characteristics.

GND

AV_DD

1mF

V_OUT

CLR

B

V_OUT

A

C

E

G

D

F

H

Noise Performance

V_REFIN/V_REFOUT

150nF

Typical 0.1Hz to 10Hz voltage noise can be seen in

Figure 9, Internal Reference Noise. Additional filtering

can be used to improve output noise levels, although

care should be taken to ensure the output impedance

does not degrade the ac performance. The output

noise spectrum at V_REFH/V_REFOUT without any

external components is depicted in Figure 8, Internal

Reference Noise Density vs Frequency. A second

noise density spectrum is also shown in Figure 8.

This spectrum was obtained using a 4.8µF load

capacitor at V_REFH/V_REFOUT for noise filtering.

Internal reference noise impacts the DAC output

noise; see the DAC Noise Performance section for

more details.

Figure 125. Typical Connections for Operating the

DAC7568/DAC8168/DAC8568 Internal Reference

(16-Pin Version Shown)

Supply Voltage

The internal reference features an extremely low

dropout voltage. It can be operated with a supply of

only 5mV above the reference output voltage in an

unloaded condition. For loaded conditions, refer to

the Load Regulation section. The stability of the

internal reference with variations in supply voltage

(line regulation, dc PSRR) is also exceptional. Within

the specified supply voltage range of 2.7V to 5.5V,

the variation at V_REFH/V_REFOUT is less than 10µV/V;

see the Typical Characteristics.

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Load Regulation

Thermal Hysteresis

Load regulation is defined as the change in reference

output voltage as a result of changes in load current.

The load regulation of the internal reference is

measured using force and sense contacts as shown

in Figure 126. The force and sense lines reduce the

impact of contact and trace resistance, resulting in

accurate measurement of the load regulation

contributed solely by the internal reference.

Measurement results are summarized in the Typical

Characteristics. Force and sense lines should be

used for applications that require improved load

regulation.

Thermal hysteresis for a reference is defined as the

change in output voltage after operating the device at

+25°C, cycling the device through the operating

temperature range, and returning to +25°C.

Hysteresis is expressed by Equation 3:

|V_{REF_PRE}- V_{REF_POST}

|

´ 10⁶(ppm/°C)

V_HYST

=

V_{REF_NOM}

(3)

Where:

V_HYST= thermal hysteresis.

V_{REF_PRE}= output voltage measured at +25°C

pre-temperature cycling.

Output Pin

Contact and

V_{REF_POST}= output voltage measured after the

device cycles through the temperature range of

–40°C to +125°C, and returns to +25°C.

Trace Resistance

V_OUT

Force Line

I_L

DAC NOISE PERFORMANCE

Sense Line

Typical noise performance for the DAC7568,

DAC8168, and DAC8568 with the internal reference

enabled is shown in Figure 66 to Figure 67. Output

noise spectral density at the V_OUTpin versus

frequency is depicted in Figure 66 for full-scale,

midscale, and zero-scale input codes. The typical

noise density for midscale code is 120nV/√Hz at

1kHz and 100nV/√Hz at 1MHz. High-frequency noise

can be improved by filtering the reference noise.

Integrated output noise between 0.1Hz and 10Hz is

close to 6µV_PP(midscale), as shown in Figure 67.

Load

Meter

Figure 126. Accurate Load Regulation of the

DAC7568/DAC8168/DAC8568 Internal Reference

Long-Term Stability

Long-term stability/aging refers to the change of the

output voltage of a reference over a period of months

or years. This effect lessens as time progresses (see

Figure 7, the typical long-term stability curve). The

typical drift value for the internal reference is 50ppm

from 0 hours to 1900 hours. This parameter is

characterized by powering-up 20 units and measuring

them at regular intervals for a period of 1900 hours.

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BIPOLAR OPERATION USING THE

DAC7568/DAC8168/DAC8568

D_IN= decimal equivalent of the binary code that

is loaded to the DAC register. It can range from 0

to 4095 for DAC7568 (12 bit), 0 to 16,383 for

DAC8168 (14 bit), and 0 to 65535 for DAC8568

(16 bit).

n = resolution in bits; either 12 (DAC7568), 14

(DAC8168) or 16 (DAC8568)

The DAC7568, DAC8168, and DAC8568 are

designed for single-supply operation, but a bipolar

output range is also possible using the circuit in either

Figure 127 or Figure 128. The circuit shown gives an

output voltage range of ±V_REF. Rail-to-rail operation at

the amplifier output is achievable using an OPA703

as the output amplifier.

Gain = 1 for A/B grades or 2 for C/D grades.

With V_REFIN/V_REFOUT = 5V, R₁= R₂= 10kΩ, for

grades A and B.

The output voltage for any input code can be

calculated with Equation 4:

10 ´ D_IN

V_OUT

=

- 5V

2ⁿ

R₂

R₁

R₁+ R₂

R₁

D_IN

2ⁿ

(5)

V_OUT

=

V_REF´ Gain ´

´

- V_REF

´

This result has an output voltage range of ±5V with

0000h corresponding to a –5V output and FFFFh

corresponding to a +5V output for the 16-bit

DAC8568, as shown in Figure 127. Similarly, using

the internal reference, a ±2.5V output voltage range

can be achieved, as Figure 128 shows.

(4)

Where:

R₂

10kW

AV

DD

V

EXT

REF

+6V

R₁

10kW

±5V

OPA703

AV_DD

V_OUT

DAC7568

DAC8168

DAC8568

V_REFIN/

-6V

V_REFOUT

10mF

0.1mF

GND

3-Wire

Serial Interface

Figure 127. Bipolar Output Range Using External Reference at 5V

R₂

10kW

AV

DD

+6V

R₁

10kW

±2.5V

OPA703

AV_DD

V_OUT

DAC7568

DAC8168

DAC8568

V_REFIN/

V_REFOUT

-6V

150nF

GND

3-Wire

Serial Interface

Figure 128. Bipolar Output Range Using Internal Reference

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MICROPROCESSOR INTERFACING

DAC8568⁽¹⁾

SYNC

Microwireä

CS

DAC7568/DAC8168/DAC8568 to an 8051 Interface

SK

SO

SCLK

D_IN

Figure 129 shows a serial interface between the

DAC7568, DAC8168, and DAC8568 and a typical

8051-type microcontroller. The setup for the interface

is as follows: TXD of the 8051 drives SCLK of the

DAC7568, DAC8168, or DAC8568, while RXD drives

the serial data line of the device. The SYNC signal is

derived from a bit-programmable pin on the port of

the 8051; in this case, port line P3.3 is used. When

data are to be transmitted to the DAC7568,

DAC8168, and DAC8568, P3.3 is taken low. The

8051 transmits data in 8-bit bytes; thus, only eight

falling clock edges occur in the transmit cycle. To

load data to the DAC, P3.3 is left low after the first

eight bits are transmitted; then, a second write cycle

is initiated to transmit the second byte of data. P3.3 is

taken high following the completion of the third write

cycle. The 8051 outputs the serial data in a format

that has the LSB first. The DAC7568, DAC8168, and

DAC8568 require the data with the MSB as the first

bit received. Therefore, the 8051 transmit routine

must take this requirement into account, and mirror

the data as needed.

NOTE: (1) Also applies to DAC7568 and DAC8168. Additional pins omitted for clarity.

Figure 130. DAC7568/DAC8168/DAC8568 to

Microwire Interface

DAC7568/DAC8168/DAC8568 to 68HC11 Interface

Figure 131 shows a serial interface between the

DAC7568/DAC8168/DAC8568 and the 68HC11

microcontroller. SCK of the 68HC11 drives the SCLK

of the DAC7568, DAC8168, and DAC8568, while the

MOSI output drives the serial data line of the DAC.

The SYNC signal derives from a port line (PC7),

similar to the 8051 diagram.

68HC11⁽¹⁾

PC7

DAC8568⁽¹⁾

SYNC

SCK

SCLK

D_IN

MOSI

NOTE: (1) Also applies to DAC7568 and DAC8168. Additional pins omitted for clarity.

80C51/80L51⁽¹⁾

P3.3

DAC8568⁽¹⁾

SYNC

Figure 131. DAC7568/DAC8168/DAC8568 to

68HC11 Interface

TXD

SCLK

RXD

D_IN

The 68HC11 should be configured so that its CPOL

bit is '0' and its CPHA bit is '1'. This configuration

causes data appearing on the MOSI output to be

valid on the falling edge of SCK. When data are

being transmitted to the DAC, the SYNC line is held

low (PC7). Serial data from the 68HC11 are

transmitted in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. (Data are

transmitted MSB first.) In order to load data to the

DAC7568, DAC8168, and DAC8568, PC7 is left low

after the first eight bits are transferred; then, a second

and third serial write operation are performed to the

DAC. PC7 is taken high at the end of this procedure.

NOTE: (1) Also applies to DAC7568 and DAC8168. Additional pins omitted for clarity.

Figure 129. DAC7568/DAC8168/DAC8568 to

80C51/80L51 Interface

DAC7568/DAC8168/DAC8568 to Microwire

Interface

Figure 130 shows an interface between the

DAC7568, DAC8168, and DAC8568 and any

Microwire-compatible device. Serial data are shifted

out on the falling edge of the serial clock and are

clocked into the DAC7568, DAC8168, and DAC8568

on the rising edge of the SK signal.

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LAYOUT

The power applied to AV_DDshould be well-regulated

and low noise. Switching power supplies and dc/dc

converters often have high-frequency glitches or

spikes riding on the output voltage. In addition, digital

components can create similar high-frequency spikes

as their internal logic switches states. This noise can

easily couple into the DAC output voltage through

various paths between the power connections and

analog output.

A precision analog component requires careful layout,

adequate bypassing, and clean, well-regulated power

supplies.

The DAC7568, DAC8168, and DAC8568 offer

single-supply operation, and are often used in close

proximity with digital logic, microcontrollers,

microprocessors, and digital signal processors. The

more digital logic present in the design and the higher

the switching speed, the more difficult it is to keep

digital noise from appearing at the output.

As with the GND connection, AV_DDshould be

connected to a power-supply plane or trace that is

separate from the connection for digital logic until

they are connected at the power-entry point. In

addition, a 1µF to 10µF capacitor and 0.1µF bypass

capacitor are strongly recommended. In some

situations, additional bypassing may be required,

such as a 100µF electrolytic capacitor or even a Pi

filter made up of inductors and capacitors—all

designed to essentially low-pass filter the supply and

remove the high-frequency noise.

As a result of the single ground pin of the DAC7568,

DAC8168, and DAC8568, all return currents

(including digital and analog return currents for the

DAC) must flow through a single point. Ideally, GND

would be connected directly to an analog ground

plane. This plane would be separate from the ground

connection for the digital components until they were

connected at the power-entry point of the system.

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PARAMETER DEFINITIONS

With the increased complexity of many different

specifications listed in product data sheets, this

Full-Scale Error

section summarizes selected specifications related to

digital-to-analog converters.

Full-scale error is defined as the deviation of the real

full-scale output voltage from the ideal output voltage

while the DAC register is loaded with the full-scale

STATIC PERFORMANCE

code (0xFFFF). Ideally, the output should be AV_DD

–

1 LSB. The full-scale error is expressed in percent of

full-scale range (%FSR).

Static performance parameters are specifications

such as differential nonlinearity (DNL) or integral

nonlinearity (INL). These are dc specifications and

provide information on the accuracy of the DAC. They

are most important in applications where the signal

changes slowly and accuracy is required.

Offset Error

The offset error is defined as the difference between

actual output voltage and the ideal output voltage in

the linear region of the transfer function. This

difference is calculated by using a straight line

defined by two codes (code 485 and 64714). Since

the offset error is defined by a straight line, it can

have a negative or positive value. Offset error is

measured in mV.

Resolution

Generally, the DAC resolution can be expressed in

different forms. Specifications such as IEC 60748-4

recognize the numerical, analog, and relative

resolution. The numerical resolution is defined as the

number of digits in the chosen numbering system

necessary to express the total number of steps of the

transfer characteristic, where a step represents both

a digital input code and the corresponding discrete

analogue output value. The most commonly-used

definition of resolution provided in data sheets is the

numerical resolution expressed in bits.

Zero-Code Error

The zero-code error is defined as the DAC output

voltage, when all '0's are loaded into the DAC

register. Zero-scale error is a measure of the

difference between actual output voltage and ideal

output voltage (0V). It is expressed in mV. It is

primarily caused by offsets in the output amplifier.

Least Significant Bit (LSB)

Gain Error

The least significant bit (LSB) is defined as the

smallest value in a binary coded system. The value of

the LSB can be calculated by dividing the full-scale

output voltage by 2ⁿ, where n is the resolution of the

converter.

Gain error is defined as the deviation in the slope of

the real DAC transfer characteristic from the ideal

transfer function. Gain error is expressed as a

percentage of full-scale range (%FSR).

Most Significant Bit (MSB)

Full-Scale Error Drift

The most significant bit (MSB) is defined as the

largest value in a binary coded system. The value of

the MSB can be calculated by dividing the full-scale

output voltage by 2. Its value is one-half of full-scale.

Full-scale error drift is defined as the change in

full-scale error with

a change in temperature.

Full-scale error drift is expressed in units of

%FSR/°C.

Relative Accuracy or Integral Nonlinearity (INL)

Offset Error Drift

Relative accuracy or integral nonlinearity (INL) is

defined as the maximum deviation between the real

transfer function and a straight line passing through

the endpoints of the ideal DAC transfer function. DNL

is measured in LSBs.

Offset error drift is defined as the change in offset

error with a change in temperature. Offset error drift

is expressed in µV/°C.

Zero-Code Error Drift

Zero-code error drift is defined as the change in

zero-code error with a change in temperature.

Zero-code error drift is expressed in µV/°C.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is defined as the

maximum deviation of the real LSB step from the

ideal 1LSB step. Ideally, any two adjacent digital

codes correspond to output analog voltages that are

exactly one LSB apart. If the DNL is less than 1LSB,

the DAC is said to be monotonic.

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Gain Temperature Coefficient

Digital Feedthrough

The gain temperature coefficient is defined as the

change in gain error with changes in temperature.

The gain temperature coefficient is expressed in ppm

of FSR/°C.

Digital feedthrough is defined as impulse seen at the

output of the DAC from the digital inputs of the DAC.

It is measured when the DAC output is not updated. It

is specified in nV-s, and measured with a full-scale

code change on the data bus; that is, from all '0's to

all '1's and vice versa.

Power-Supply Rejection Ratio (PSRR)

Power-supply rejection ratio (PSRR) is defined as the

ratio of change in output voltage to a change in

supply voltage for a full-scale output of the DAC. The

PSRR of a device indicates how the output of the

DAC is affected by changes in the supply voltage.

PSRR is measured in decibels (dB).

Channel-to-Channel DC Crosstalk

Channel-to-channel dc crosstalk is defined as the dc

change in the output level of one DAC channel in

response to a change in the output of another DAC

channel. It is measured with a full-scale output

change on one DAC channel while monitoring

another DAC channel remains at midscale. It is

expressed in LSB.

Monotonicity

Monotonicity is defined as a slope whose sign does

not change. If a DAC is monotonic, the output

changes in the same direction or remains at least

constant for each step increase (or decrease) in the

input code.

Channel-to-Channel AC Crosstalk

AC crosstalk in a multi-channel DAC is defined as the

amount of ac interference experienced on the output

of a channel at a frequency (f) (and its harmonics),

when the output of an adjacent channel changes its

value at the rate of frequency (f). It is measured with

one channel output oscillating with a sine wave of

1kHz frequency, while monitoring the amplitude of

1kHz harmonics on an adjacent DAC channel output

(kept at zero scale). It is expressed in dB.

DYNAMIC PERFORMANCE

Dynamic performance parameters are specifications

such as settling time or slew rate, which are important

in applications where the signal rapidly changes

and/or high frequency signals are present.

Slew Rate

Signal-to-Noise Ratio (SNR)

The output slew rate (SR) of an amplifier or other

electronic circuit is defined as the maximum rate of

change of the output voltage for all possible input

signals.

Signal-to-noise ratio (SNR) is defined as the ratio of

the root mean-squared (RMS) value of the output

signal divided by the RMS values of the sum of all

other spectral components below one-half the output

frequency, not including harmonics or dc. SNR is

measured in dB.

DV

(t)

OUT

SR = max

Dt

Total Harmonic Distortion (THD)

Where ΔV_OUT(t) is the output produced by the

amplifier as a function of time t.

Total harmonic distortion + noise is defined as the

ratio of the RMS values of the harmonics and noise

to the value of the fundamental frequency. It is

expressed in a percentage of the fundamental

frequency amplitude at sampling rate f_S.

Output Voltage Settling Time

Settling time is the total time (including slew time) for

the DAC output to settle within an error band around

its final value after a change in input. Settling times

are specified to within ±0.003% (or whatever value is

specified) of full-scale range (FSR).

Spurious-Free Dynamic Range (SFDR)

Spurious-free dynamic range (SFDR) is the usable

dynamic range of a DAC before spurious noise

interferes or distorts the fundamental signal. SFDR is

the measure of the difference in amplitude between

the fundamental and the largest harmonically or

non-harmonically related spur from dc to the full

Nyquist bandwidth (half the DAC sampling rate, or

f_S/2). A spur is any frequency bin on a spectrum

analyzer, or from a Fourier transform, of the analog

output of the DAC. SFDR is specified in decibels

relative to the carrier (dBc).

Code Change/Digital-to-Analog Glitch Energy

Digital-to-analog glitch impulse is the impulse injected

into the analog output when the input code in the

DAC register changes state. It is normally specified

as the area of the glitch in nanovolt-seconds (nV-s),

and is measured when the digital input code is

changed by 1LSB at the major carry transition.

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Signal-to-Noise plus Distortion (SINAD)

DAC Output Noise

SINAD includes all the harmonic and outstanding

spurious components in the definition of output noise

power in addition to quantizing any internal random

noise power. SINAD is expressed in dB at a specified

input frequency and sampling rate, f_S.

DAC output noise is defined as any voltage deviation

of DAC output from the desired value (within a

particular frequency band). It is measured with a DAC

channel kept at midscale while filtering the output

voltage within a band of 0.1Hz to 10Hz and

measuring its amplitude peaks. It is expressed in

terms of peak-to-peak voltage (V_pp).

DAC Output Noise Density

Output

noise

density

is

defined

as

Full-Scale Range (FSR)

internally-generated random noise. Random noise is

characterized as a spectral density (nV/√Hz). It is

measured by loading the DAC to midscale and

measuring noise at the output.

Full-scale range (FSR) is the difference between the

maximum and minimum analog output values that the

DAC is specified to provide; typically, the maximum

and minimum values are also specified. For an n-bit

DAC, these values are usually given as the values

matching with code 0 and 2ⁿ.

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PACKAGE OPTION ADDENDUM

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4-May-2009

PACKAGING INFORMATION

Orderable Device

DAC7568IAPW

DAC7568IAPWR

DAC7568ICPW

DAC7568ICPWR

DAC8168IAPW

DAC8168IAPWR

DAC8168ICPW

DAC8168ICPWR

DAC8568IAPW

DAC8568IAPWR

DAC8568IBPW

DAC8568IBPWR

DAC8568ICPW

DAC8568ICPWR

DAC8568IDPW

DAC8568IDPWR

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

PW

14

16

14

16

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TSSOP

PW

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

4-May-2009

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Jul-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

DAC8168ICPWR

TSSOP

PW

16

2000

330.0

12.4

6.8

5.4

1.6

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Jul-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 16

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 29.0

DAC8168ICPWR

2000

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DAC8168A
厂家：	TEXAS INSTRUMENTS
描述：	12-/14-/16-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTERS with 2.5V, 2ppm/°C Internal Reference 12位/ 14位/ 16位，八通道，超低短时脉冲波形干扰，电压输出数字 - 模拟转换器具有2.5V ， 2ppm的/ ° C内部参考转换器脉冲
文件：	总58页 (文件大小：2096K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC8168A [TI]

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