DAC8551IDGKR [TI]
16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER; 16位，超低干扰，电压输出数位类比转换器
| 型号： | DAC8551IDGKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总22页 (文件大小：1725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC8551
SLAS429A–APRIL 2005–REVISED JULY 2005
16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16-Bit Monotonic Over Temperature
Relative Accuracy: 8 LSB (Max)
Glitch Energy: 0.1 nV-s
The DAC8551 is a small, low-power, voltage output,
16-bit digital-to-analog converter (DAC). It is
monotonic, provides good linearity, and minimizes
undesired code-to-code transient voltages. The
DAC8551 uses a versatile 3-wire serial interface that
operates at clock rates to 30 MHz and is compatible
with standard SPI™, QSPI™, Microwire™, and digital
signal processor (DSP) interfaces.
Settling Time: 10 µs to ±0.003% FSR
Power Supply: +2.7 V to +5.5 V
MicroPower Operation: 200 µA at 5 V
Rail-to-Rail Output Amplifier
Power-On Reset to Zero
The DAC8551 requires an external reference voltage
to set its output range. The DAC8551 incorporates a
power-on-reset circuit that ensures the DAC output
powers up at 0 V and remains there until a valid write
takes place to the device. The DAC8551 contains a
power-down feature, accessed over the serial
interface, that reduces the current consumption of the
device to 200 nA at 5 V.
Power-Down Capability
Schmitt-Triggered Digital Inputs
SYNC Interrupt Facility
Drop-In Compatible With DAC8531/01
Operating Temperature Range: -40°C to 105°C
Available Package:
The low-power consumption of this device in normal
operation makes it ideally suited for portable battery-
operated equipment. The power consumption is
1.00 mW at 5 V, reducing to 1 µW in power-down
mode.
– 3 mm × 5 mm MSOP-8
APPLICATIONS
•
•
•
•
•
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Process Control
The DAC8551 is available in an MSOP-8 package.
Data Acquisition Systems
Closed-Loop Servo-Control
PC Peripherals
Portable Instrumentation
Programmable Attenuation
FUNCTIONAL BLOCK DIAGRAM
VDD
VFB
VREF
Ref (+)
16−Bit DAC
VOUT
16
DAC Register
16
SYNC
Resistor
Network
Shift Register
PWD Control
SCLK
DIN
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola.
Microwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
MINIMUM
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFICATION
TEMPERATURE
RANGE
TRANSPORT
MEDIA,
QUANTITY
RELATIVE
ACCURACY
(LSB)
PACKAGE
LEAD
PACKAGE
DESIGNATOR(1)
PACKAGE
MARKING
ORDERING
NUMBER
PRODUCT
DAC8551IDGK
DAC8551IDGKT
DAC8551IDGKR
Tube, 80
DAC8551I
±8
±1
MSOP-8
DGK
–40°C TO 105°C
D81
Tape and Reel, 250
Tape and Reel, 2500
(1) For the most current specifications and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
UNIT
VDD to GND
–0.3 V to 6 V
–0.3 V to +VDD + 0.3 V
–0.3 V to +VDD + 0.3 V
–40°C to 105°C
–65°C to 150°C
150°C
Digital input voltage to GND
VOUT to GND
Operating temperature range
Storage temperature range
Junction temperature range (TJ max)
Power dissipation (DGK)
θJA Thermal impedance
θJC Thermal impedance
(TJmax – TA)/θJA
206°C/W
44°C/W
Vapor phase (60 s)
Lead temperature, soldering
Infrared (15 s)
215°C
220°C
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V,– 40°C to 105°C range (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE(1)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
Bits
LSB
Relative accuracy
Differential nonlinearity
Zero-code error
Measured by line passing through codes 485 and 64741
16-bit Monotonic
±3
±0.25
±2
±8
±1
LSB
±12
±0.5
mV
Full-scale error
Measured by line passing through codes 485 and 64741.
±0.05
% of FSR
% of FSR
µV/°C
Gain error
±0.02 ±0.15
Zero-code error drift
Gain temperature coefficient
±5
±1
ppm of FSR/°C
mV
8
Power supply rejection ratio
(PSRR)
RL = 2 kΩ, CL = 200 pF
0.75
mV/V
(1) Linearity calculated using a reduced code range of 485 to 64741; output unloaded.
2
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V,– 40°C to 105°C range (unless otherwise noted)
PARAMETER
OUTPUT CHARACTERISTICS(2)
Output voltage range
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
VREF
10
V
To ±0.003% FSR, 0200H to FD00H, RL = 2 kΩ, 0 pF < CL
<
8
µs
200 pF
Output voltage settling time
RL = 2 kΩ, CL = 500 pF
12
1.8
470
1000
0.1
0.1
1
µs
V/µs
pF
Slew rate
RL = ∞
Capacitive load stability
RL = 2 kΩ
pF
Code change glitch impulse
Digital feedthrough
1 LSB change around major carry
SCLK toggling, FSYNC high
At mid-code input
nV-s
Ω
DC output impedance
VDD = 5 V
50
Short-circuit current
Power-up time
mA
VDD = 3 V
20
Coming out of power-down mode VDD = 5 V
Coming out of power-down mode VDD = 3 V
2.5
5
µs
AC PERFORMANCE
SNR (1st 19 harmonics removed)
THD
95
85
87
84
BW = 20 kHz, VDD = 5 V, FOUT = 1 kHz
dB
SFDR
SINAD
REFERENCE INPUT
VREF Voltage
0
VDD
75
V
VREF = VDD = 5 V
50
30
µA
µA
kΩ
Reference input range
VREF = VDD = 3.6 V
45
Reference input impedance
125
(3)
LOGIC INPUTS
Input current
±1
µA
V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
0.8
0.6
VINL
Logic input LOW voltage
Logic input HIGH voltage
2.4
2.1
VINH
V
Pin capacitance
3
pF
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (normal mode)
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (all power-down modes)
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
Input code = 32768, reference current included, no load
VIH = VDD and VIL = GND
200
180
250
240
µA
VIH = VDD and VIL = GND
ILOAD = 2 mA, VDD = 5 V
0.2
1
1
µA
0.05
89%
TEMPERATURE RANGE
Specified performance
–40
105
°C
(2) Ensured by design and characterization, not production tested.
(3) Ensured by design and characterization, not production tested.
3
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
PIN CONFIGURATION
MSOP-8
(Top View)
1
2
3
4
8
7
6
5
VDD
VREF
VFB
GND
DIN
DAC8551
SCLK
SYNC
VOUT
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
1
2
3
4
VDD
VREF
VFB
Power supply input, 2.7 V to 5.5 V.
Reference voltage input.
Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally.
VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is
updated following the 24th clock (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts
as an interrupt and the write sequence is ignored by the DAC8551).
5
SYNC
6
7
8
SCLK Serial clock input. Data can be transferred at rates up to 30 MHz.
DIN Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input.
GND Ground reference point for all circuitry on the part.
4
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
TIMING REQUIREMENTS(1)(2)
VDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
50
ns
33
(3)
t 1
t 2
t 3
t 4
t 5
t 6
t 7
t 8
SCLK cycle time
SCLK HIGH time
SCLK LOW time
13
ns
13
22.5
ns
13
0
SYNC to SCLK rising edge setup time
Data setup time
ns
0
5
ns
5
4.5
Data hold time
ns
4.5
0
SCLK falling edge to SYNC rising edge
Minimum SYNC HIGH time
ns
0
50
ns
33
(1) All input signals are specified with tR = tF = 3 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
SERIAL WRITE OPERATION
t1
SCLK
t2
t8
t3
t7
t4
SYNC
t6
t5
DB23
DB0
DIN
5
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 5 V
At TA = 25°C, unless otherwise noted
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(-40°C)
CODE
(25°C)
6
6
V
= 5 V, V = 4.99 V
REF
V
= 5 V, V = 4.99 V
REF
DD
DD
4
2
4
2
0
0
−2
−4
−6
−2
−4
−6
1
1
0.5
0
0.5
0
−0.5
−1
−0.5
−1
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
Figure 1.
Figure 2.
LINEARITY ERROR AND
ZERO-SCALE ERROR
vs
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(105°C)
TEMPERATURE
6
10
V
= 5 V, V = 4.99 V
REF
DD
V
= 5 V, V = 4.99 V
REF
DD
4
2
0
−2
5
−4
−6
1
0.5
0
0
−0.5
−1
−5
0
8192
16384 24576 32768 40960 49152 57344 65536
−40
0
40
80
120
Digital Input Code
Temperature − 5C
Figure 3.
Figure 4.
FULL-SCALE ERROR
vs
IDD HISTOGRAM
TEMPERATURE
0
1000
800
600
400
V
= 5 V, V = 4.99 V
REF
DD
V
= V
REF
= 5.5 V,
DD
Reference Current Included
−5
200
0
−10
120 140 160 180 200 220
240 260 280 300
−40
0
40
80
120
I
− Supply Current − mA
Temperature − 5C
DD
Figure 5.
Figure 6.
6
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted
SOURCE AND SINK CURRENT CAPABILITY
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
300
250
200
150
100
50
6
V
= 5.5 V
DD
V
= V
REF
= 5.5 V
DD
5
4
3
2
1
0
DAC Loaded With FFFF
H
Reference Current Included
V
= V −10 mV
DD
REF
DAC Loaded With 0000
3
H
0
0
8192
16384 24576 32768 40960 49152 57344 65536
0
5
8
10
I
− mA
(SOURCE/SINK)
Digital Input Code
Figure 7.
Figure 8.
POWER-SUPPLY CURRENT
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
vs
TEMPERATURE
250
300
V
= V
= 5.5 V
280
260
240
220
200
180
160
140
120
100
DD
REF
V
= V
DD
REF
Reference Current Include, No Load
200
150
100
50
Reference Current Included
0
−40
−10
20
50
80
110
2.7
3.1
3.4
3.8
4.1
4.5
4.8
5.2
5.5
Temperature − 5C
V
− Supply Voltage − V
DD
Figure 9.
Figure 10.
POWER-DOWN CURRENT
vs
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
SUPPLY VOLTAGE
1
T
= 25°C, SCL Input (All Other Inputs = GND)
A
1700
1300
900
V
= V
REF
DD
V
= V
= 5.5 V
REF
DD
0.8
0.5
0.3
0
500
100
0
1
2
3
4
5
2.7
3.1
3.4
3.8
4.1
4.5
4.8
5.2
5.5
V
− V
V
− Supply Voltage − V
(LOGIC)
DD
Figure 11.
Figure 12.
7
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted
FULL-SCALE SETTLING TIME: 5-V RISING EDGE
FULL-SCALE SETTLING TIME: 5-V FALLING EDGE
Trigger Pulse
5 V/div
Trigger Pulse
5 V/div
V
V
= 5 V,
REF
From Code: 0000
To Code: FFFF
DD
V
V
= 5 V,
DD
REF
From Code: FFFF
To Code: 0000
= 4.096 V,
= 4.096 V,
Falling
Edge
1 V/div
Rising Edge
1 V/div
Zoomed Falling Edge
1 mV/div
Zoomed Rising Edge
1 mV/div
Time (2 µs/div)
Time (2 µs/div)
Figure 13.
Figure 14.
HALF-SCALE SETTLING TIME: 5-V RISING EDGE
HALF-SCALE SETTLING TIME: 5-V FALLING EDGE
Trigger Pulse
5 V/div
Trigger Pulse
5 V/div
V
V
= 5 V,
REF
From Code: CFFF
To Code: 4000
DD
= 4.096 V,
V
V
= 5 V,
REF
From Code: 4000
To Code: CFFF
DD
= 4.096 V,
Rising
Edge
1 V/div
Falling
Edge
1 V/div
Zoomed Rising Edge
1 mV/div
Zoomed Falling Edge
1 mV/div
Time (2 µs/div)
Time (2 µs/div)
Figure 15.
Figure 16.
GLITCH ENERGY: 5-V, 1-LSB STEP, RISING EDGE
GLITCH ENERGY: 5-V, 1-LSB STEP, FALLING EDGE
V
V
= 5 V,
DD
= 4.096 V
REF
V
V
= 5 V,
REF
From Code: 8000
To Code: 7FFF
DD
From Code: 7FFF
To Code: 8000
Glitch: 0.08 nV-s
= 4.096 V
Glitch: 0.16 nV-s
Measured Worst Case
Time 400 ns/div
Time 400 ns/div
Figure 17.
Figure 18.
8
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted
GLITCH ENERGY: 5-V, 16-LSB STEP, RISING EDGE
GLITCH ENERGY: 5-V, 16-LSB STEP, FALLING EDGE
V
V
= 5 V,
REF
From Code: 8010
To Code: 8000
DD
= 4.096 V
Glitch: 0.08 nV-s
V
V
= 5 V,
REF
From Code: 8000
To Code: 8010
DD
= 4.096 V
Glitch: 0.04 nV-s
Time 400 ns/div
Time 400 ns/div
Figure 19.
Figure 20.
GLITCH ENERGY: 5-V, 256-LSB STEP, RISING EDGE
GLITCH ENERGY: 5-V, 256-LSB STEP, FALLING EDGE
V
V
= 5 V,
REF
From Code: 80FF
To Code: 8000
DD
= 4.096 V
V
V
= 5 V,
REF
From Code: 8000
To Code: 80FF
DD
= 4.096 V
Glitch: Not Detected
Theoretical Worst Case
Glitch: Not Detected
Theoretical Worst Case
Time 400 ns/div
Time 400 ns/div
Figure 21.
Figure 22.
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE RATIO
vs
OUTPUT FREQUENCY
vs
OUTPUT FREQUENCY
98
96
94
92
90
88
86
84
−40
−50
−60
−70
−80
−90
−100
V
= V
REF
= 5 V
V
= 5 V, V = 4.9 V
REF
DD
DD
−1 dB FSR Digital Input, Fs = 1 MSPS
Measurement Bandwidth = 20 kHz
−1dB FSR Digital Input, Fs = 1 MSPS
Measurement Bandwidth = 20 kHz
THD
2nd Harmonic
3rd Harmonic
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
f − Output Frequency − kHz
Output Tone − kHz
Figure 23.
Figure 24.
9
DAC8551
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SLAS429A–APRIL 2005–REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted
POWER SPECTRAL DENSITY
OUTPUT NOISE DENSITY
350
300
250
200
150
100
V
V
= 5 V
−10
DD
= 4.096
REF
V
= 5.0 V, V
= 1 kHz
=
= 4.096 V
REF
DD
Code = 7FFF
No Load
f
f
OUT
−30
−50
CLK 1 MSPS
−70
−90
−110
−130
5000
10000
15000
20000
0
100
1000
10000
100000
f − Frequency − Hz
f − Frequency − Hz
Figure 25.
Figure 26.
TYPICAL CHARACTERISTICS: VDD = 2.7 V
At TA = 25°C, unless otherwise noted
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL
DIFFERENTIAL LINEARITY ERROR vs DIGITAL
INPUT CODE
INPUT CODE
(-40°C)
(25°C)
6
4
6
4
V
= 2.7 V, V = 2.69 V
REF
DD
V
= 2.7 V, V = 2.69 V
REF
DD
2
0
2
0
−2
−2
−4
−6
−4
−6
1
1
0.5
0
0.5
0
−0.5
−1
−0.5
−1
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192
16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
Figure 27.
Figure 28.
10
DAC8551
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SLAS429A–APRIL 2005–REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = 25°C, unless otherwise noted
LINEARITY ERROR AND
ZERO-SCALE ERROR
vs
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(105°C)
TEMPERATURE
6
10
5
V
= 2.7 V, V
= 2.69 V
REF
4
2
DD
V
= 2.7 V, V = 2.69 V
REF
DD
0
−2
−4
−6
1
0.5
0
0
−0.5
−1
−5
0
8192 16384 24576 32768 40960 49152 57344 65536
−40
0
40
80
120
Digital Input Code
Temperature − 5C
Figure 29.
Figure 30.
FULL-SCALE ERROR
vs
IDD HISTOGRAM
TEMPERATURE
5
1500
1200
900
600
300
0
V
= V
REF
= 2.7 V
DD
Reference Current Included
V
= 2.7 V, V = 2.69 V
REF
DD
0
−5
−10
−40
120 140 160 180 200 220 240 260 280 300
0
40
80
120
I
− Supply Current − mA
DD
Temperature − 5C
Figure 31.
Figure 32.
SOURCE AND SINK CURRENT CAPABILITY
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
3
2.5
2
180
160
140
120
100
80
V
= 2.7 V
V
= V = 2.7 V
REF
DD
DD
DAC Loaded With FFFF
H
Reference Current Included
1.5
1
V
= V − 10 mV
DD
REF
60
40
0.5
0
20
DAC Loaded With 0000
3
H
0
0
0
5
8
10
8192
16384 24576 32768 40960 49152 57344 65536
I
− mA
Digital Input Code
(SOURCE/SINK)
Figure 33.
Figure 34.
11
DAC8551
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SLAS429A–APRIL 2005–REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = 25°C, unless otherwise noted
POWER-SUPPLY CURRENT
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
vs
TEMPERATURE
250
T
A
= 25°C, SCL Input (All Other Inputs = GND)
V
= V = 2.7 V
REF
DD
700
500
300
100
200
150
100
50
V
= V = 2.7 V
REF
DD
Reference Current Included
0
0
0.5
1
1.5
2
2.5
−40
−10
20
50
80
110
V
− V
Temperature − 5C
(LOGIC)
Figure 35.
Figure 36.
FULL-SCALE SETTLING TIME: 2.7-V RISING EDGE
FULL-SCALE SETTLING TIME: 2.7-V FALLING EDGE
Trigger Pulse
2.7 V/div
Trigger Pulse
2.7 V/div
V
V
= 2.7 V,
REF
From Code: FFFF
To Code: 0000
DD
= 2.5 V,
V
V
= 2.7 V,
REF
From Code: 0000
To Code: FFFF
DD
= 2.5 V,
Rising
Edge
0.5 V/div
Falling
Edge
0.5 V/div
Zoomed Falling Edge
1 mV/div
Zoomed Rising Edge
1 mV/div
Time (2 µs/div)
Time (2 µs/div)
Figure 37.
Figure 38.
HALF-SCALE SETTLING TIME: 2.7-V RISING EDGE
HALF-SCALE SETTLING TIME: 2.7-V FALLING EDGE
Trigger Pulse
2.7 V/div
Trigger Pulse
2.7 V/div
V
V
= 2.7 V,
REF
From Code: CFFF
To Code: 4000
DD
V
V
= 2.7 V
DD
= 2.5 V,
= 2.5 V
REF
From code; 4000
To code: CFFF
Rising
Edge
0.5 V/div
Falling
Edge
0.5 V/div
Zoomed Rising Edge
1 mV / div
Zoomed Falling Edge
1 mV/div
Time (2 µs/div)
Time − 2 ms/div
Figure 39.
Figure 40.
12
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = 25°C, unless otherwise noted
GLITCH ENERGY: 2.7-V, 1-LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7-V, 1-LSB STEP, FALLING EDGE
V
V
= 2.7 V,
= 2.5 V
DD
REF
V
V
= 2.7 V,
= 2.5 V
DD
REF
From Code: 7FFF
To Code: 8000
From Code: 8000
To Code: 7FFF
Glitch: 0.08 nV-s
Glitch: 0.16 nV-s
Measured Worst Case
Time 400 ns/div
Time 400 ns/div
Figure 41.
Figure 42.
GLITCH ENERGY: 2.7-V, 16-LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7-V, 16-LSB STEP, FALLING EDGE
V
V
= 2.7 V,
REF
DD
= 2.5 V
From Code: 8010
To Code: 8000
Glitch: 0.12 nV-s
V
V
= 2.7 V,
REF
From Code: 8000
To Code: 8010
DD
= 2.5 V
Glitch: 0.04 nV-s
Time 400 ns/div
Time 400 ns/div
Figure 43.
Figure 44.
GLITCH ENERGY: 2.7-V, 256-LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7-V, 256-LSB STEP, FALLING EDGE
V
V
= 2.7 V,
REF
DD
= 2.5 V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
AV
V
= 2.7 V,
DD
= 2.5 V
ref
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time 400 ns/div
Time 400 ns/div
Figure 45.
Figure 46.
13
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
THEORY OF OPERATION
V
REF
R
DAC SECTION
The architecture consists of a string DAC followed by
an output buffer amplifier. Figure 47 shows a block
diagram of the DAC architecture.
Divider
V
REF
2
Ω
Ω
V
FB
R
Ω
62
To Output
Amplifier
(2x Gain)
R
GND
Figure 47. DAC8551 Architecture
The input coding to the DAC8551 is straight binary,
so the ideal output voltage is given by:
D
IN
V
X +
V
OUT
REF
65536
R
R
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 65535.
RESISTOR STRING
The resistor string section is shown in Figure 48. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
Figure 48. Resistor String
SERIAL INTERFACE
The DAC8551 has a 3-wire serial interface ( SYNC,
SCLK, and DIN), which is compatible with SPI™,
QSPI™, and Microwire™ interface standards, as well
as most DSPs. See the Serial Write Operation timing
diagram for an example of a typical write sequence.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, which gives an
output range of 0 V to VDD. It is capable of driving a
load of 2 kΩ in parallel with 1000 pF to GND. The
source and sink capabilities of the output amplifier
can be seen in the typical curves. The slew rate is 1.8
V/µs with a full-scale setting time of 8 µs with the
output unloaded.
The write sequence begins by bringing the SYNC line
LOW. Data from the DIN line is clocked into the 24-bit
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 30 MHz, making
the DAC8551 compatible with high-speed DSPs. On
the 24th falling edge of the serial clock, the last data
bit is clocked in and the programmed function is
executed (i.e., a change in DAC register contents
and/or a change in the mode of operation).
The inverting input of the output amplifier is brought
out to the VFB pin. This allows for better accuracy in
critical applications by tying the VFB point and the
amplifier output together directly at the load. Other
signal conditioning circuitry may also be connected
between these points for specific applications.
At this point, the SYNC line may be kept LOW or
brought HIGH. In either case, it must be brought
HIGH for a minimum of 33 ns before the next write
sequence so that a falling edge of SYNC can initiate
the next write sequence. As previously mentioned, it
must be brought HIGH again just before the next
write sequence.
14
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
INPUT SHIFT REGISTER
SYNC INTERRUPT
The input shift register is 24 bits wide, as shown in
Figure 49. The first six bits are don't cares. The next
two bits (PD1 andPD0) are control bits that control
which mode of operation the part is in (normal mode
or any one of three power-down modes). A more
complete description of the various modes is located
in the Power-Down Modes section. The next 16 bits
are the data bits. These are transferred to the DAC
register on the 24th falling edge of SCLK.
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
DAC is updated on the 24th falling edge. However, if
SYNC is brought HIGH before the 24th falling edge, it
acts as an interrupt to the write sequence. The shift
register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register con-
tents, or a change in the operating mode occurs, as
shown in Figure 50.
POWER-ON RESET
The DAC8551 contains a power-on-reset circuit that
controls the output voltage during power up. On
power up, the DAC registers is filled with zeros and
the output voltages is 0 V; it remains there until a
valid write sequence is made to the DAC. This is
useful in applications where it is important to know
the state of the output of the DAC while it is in the
process of powering up.
DB23
DB0
X
X
X
X
X
X
PD1 PD0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 49. DAC8551 Data Input Register Format
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB80
DB23
DB80
Valid Write Sequence: Output Updates
on the 24th Falling Edge
Figure 50. SYNC Interrupt Facility
15
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
POWER-DOWN MODES
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8551, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051. In this case, port line P3.3 is used. When
data is to be transmitted to the DAC8551, P3.3 is
taken LOW. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken HIGH following the
completion of the third write cycle. The 8051 outputs
the serial data in a format which has the LSB first.
The DAC8551 requires its data with the MSB as the
first bit received. The 8051 transmit routine must
therefore take this into account, and mirror the data
as needed.
The DAC8551 supports four separate modes of
operation. These modes are programmable by setting
two bits (PD1 and PD0) in the control register.
Table 1 shows how the state of the bits corresponds
to the mode of operation of the device.
Table 1. Modes of Operation for the DAC8551
PD1
PD0
OPERATING MODE
(DB17)
(DB16)
0
–
0
1
1
0
–
1
0
1
Normal Operation
Power-down modes
Output typically 1 kΩ to GND
Output typically 100 kΩ to GND
High-Z
When both bits are set to 0, the device works
normally with its typical current consumption of 200
µA at 5 V. However, for the three power-down
modes, the supply current falls to 200 nA at 5 V (50
nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the
output of the amplifier to a resistor network of known
values. This has the advantage that the output
impedance of the device is known while it is in
power-down mode. There are three different options.
The output is connected internally to GND through a
80C51/80L51(1)
P3.3
DAC8551(1)
SYNC
TXD
RXD
SCLK
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 52. DAC8551 to 80C51/80L51 Interface
1-kΩ resistor,
open-circuited (High-Z). The output stage is illustrated
in Figure 51.
a 100-kΩ resistor, or it is left
DAC8551 to Microwire Interface
Figure 53 shows an interface between the DAC8551
and any Microwire compatible device. Serial data is
shifted out on the falling edge of the serial clock and
is clocked into the DAC8551 on the rising edge of the
SK signal.
All analog circuitry is shut down when the
power-down mode is activated. However, the con-
tents of the DAC register are unaffected when in
power down. The time to exit power-down is typically
2.5 µs for VDD = 5 V, and 5 µs for VDD = 3 V. See the
Typical Characteristics for more information.
MicrowireTM
CS
DAC8551(1)
SYNC
VFB
SCLK
DIN
SK
SO
Amplifier
VOUT
Resistor
NOTE: (1) Additional pins omitted for clarity.
String DAC
Figure 53. DAC8551 to Microwire Interface
Power−Down
Circuitry
Resistor
Network
DAC8551 to 68HC11 Interface
Figure 54 shows a serial interface between the
DAC8551 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8551, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
Figure 51. Output Stage During Power Down
MICROPROCESSOR INTERFACING
DAC8551 TO 8051 Interface
See Figure 52 for a serial interface between the
DAC8551 and a typical 8051-type microcontroller.
16
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
valid on the falling edge of SCK. When data is being
transmitted to the DAC, the SYNC line is held LOW
(PC7). Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted
MSB first.) In order to load data to the DAC8551,
PC7 is left LOW after the first eight bits are trans-
ferred, then a second and third serial write operation
is performed to the DAC. PC7 is taken HIGH at the
end of this procedure.
DAC8551 (1)
68HC11(1)
PC7
SYNC
SCK
SCLK
DIN
MOSI
NOTE: (1) Additional pins omitted for clarity.
Figure 54. DAC8551 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is 0 and its CPHA bit is 1. This configuration
causes data appearing on the MOSI output to be
APPLICATION INFORMATION
5 V
5 kW
200 mA )
+ 1.2 mA
(2)
USING THE REF02 AS A POWER SUPPLY
FOR THE DAC8551
The load regulation of the REF02 is typically
0.005%/mA, which results in an error of 299 µV for
the 1.2-mA current drawn from it. This corresponds to
a 3.9 LSB error.
Due to the extremely low supply current required by
the DAC8551, an alternative option is to use a REF02
+5 -V precision voltage reference to supply the re-
quired voltage to the device, as shown in Figure 55.
BIPOLAR OPERATION USING THE DAC8551
+15
The DAC8551 has been designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in Figure 56. The circuit shown gives
an output voltage range of ±VREF. Rail-to-rail oper-
ation at the amplifier output is achievable using an
OPA703 as the output amplifier.
+5V
REF02
285µA
The output voltage for any input code can be calcu-
lated as follows:
SYNC
Three-Wire
VOUT = 0V to 5V
D
R1 ) R2
R2
R1
ǒ Ǔ ǒ
Ǔ* V
ǒ Ǔ
+ ƪVREF
ƫ
Serial
SCLK
DIN
V
DAC8551
O
REF
65536
R1
Interface
where D represents the input code in decimal
(0–65535).
With VREF = 5 V, R1 = R2 = 10 kΩ.
10 D
Figure 55. REF02 as a Power Supply to the
DAC8551
+ ǒ Ǔ* 5 V
V
O
65536
(4)
This is especially useful if the power supply is quite
noisy or if the system supply voltages are at some
value other than 5 V. The REF02 outputs a steady
supply voltage for the DAC8551. If the REF02 is
used, the current it needs to supply to the DAC8551
is 200 µA. This is with no load on the output of the
DAC. When a DAC output is loaded, the REF02 also
needs to supply the current to the load. The total
typical current required (with a 5-kΩ load on the DAC
output) is:
This is an output voltage range of ±5 V with 0000H
corresponding to a –5 V output and FFFFH corre-
sponding to a 5 V output. Similarly, using VREF = 2.5
V, a ±2.5-V output voltage range can be achieved.
LAYOUT
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC8551 offers single-supply operation, and it
often is used in close proximity with digital logic,
17
DAC8551
www.ti.com
SLAS429A–APRIL 2005–REVISED JULY 2005
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at
the output.
The power applied to VDD should be well regulated
and low noise. Switching power supplies and DC/DC
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes
as their internal logic switches states. This noise can
easily couple into the DAC output voltage through
various paths between the power connections and
analog output.
Due to the single ground pin of the DAC8551, all
return currents, including digital and analog return
currents for the DAC, must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they were connected at the
power-entry point of the system.
As with the GND connection, VDD should be connec-
ted to a 5-V power-supply plane or trace that is
separate from the connection for digital logic until
they are connected at the power-entry point. In
addition, a 1-µF to 10-µF capacitor and 0.1-µF
bypass capacitor are strongly recommended. In some
situations, additional bypassing may be required,
such as a 100-µF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors – all
designed to essentially low-pass filter the 5-V supply,
removing the high-frequency noise.
R2
VREF
10kΩ
+5V
R1
10kΩ
OPA703
VFB
±5V
VOUT
VREF
DAC8551
10µF
0.1µ
F
–5V
Three-Wire
Serial Interface
Figure 56. Bipolar Output Range
18
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2005
PACKAGING INFORMATION
Orderable Device
DAC8551IDGK
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
MSOP
DGK
8
8
8
8
80 Green (RoHS &
no Sb/Br)
CU
CU
CU
CU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
DAC8551IDGKR
DAC8551IDGKRG4
DAC8551IDGKT
MSOP
MSOP
MSOP
DGK
DGK
DGK
2500 Green (RoHS &
no Sb/Br)
2500 Green (RoHS &
no Sb/Br)
250 Green (RoHS &
no Sb/Br)
DAC8551IDRBR
DAC8551IDRBT
PREVIEW
PREVIEW
SON
SON
DRB
DRB
8
8
3000
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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Addendum-Page 1
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