DAC8560IDDGKTG4 [TI]
具有 2.5V、2ppm/°C 基准的 16 位、单通道、低功耗、超低干扰、电压输出 DAC | DGK | 8 | -40 to 105;
| 型号： | DAC8560IDDGKTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 2.5V、2ppm/°C 基准的 16 位、单通道、低功耗、超低干扰、电压输出 DAC | DGK | 8 | -40 to 105 光电二极管 转换器 |
| 文件： | 总40页 (文件大小：2085K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC8560
ZHCSBK1C –DECEMBER 2006–REVISED JANUARY 2018
具有 2.5V、2ppm/°C 内部基准电压的 DAC8560为16 位、超低毛刺脉冲、
电压输出数模转换器
1 特性
3 说明
1
•
•
•
•
相对精度：4 LSB
DAC8560 是一款低功耗、电压输出、16 位数模转换
器 (DAC)。DAC8560 包括 2.5V，2ppm/°C 内部基准
电压（默认为启用），可提供范围在 0V 到 2.5V 之间
的满量程输出电压。内部基准电压的初始精度为
0.02%，可在 VREF 引脚实现高达 20mA 的拉电流。此
器件具有单调性，可提供极佳的线性度，并且大大降低
了有害的码字间瞬态电压（毛刺脉冲）。DAC8560 使
用一个可运行在高达 30MHz 时钟速率上的多用途 3 线
制串行接口。该器件可与标准 SPI、QSPI、Microwire
和数字信号处理器 (DSP) 接口兼容。
毛刺脉冲能量：0.15nV-s
微功耗运行：510μA/2.7V
内部基准电压：
–
–
–
–
–
2.5V 基准电压（默认为启用）
0.02% 初始精度
2ppm/°C 温漂（典型值）
5ppm/°C 温漂（最大值）
20mA 灌电流/拉电流能力
•
•
•
•
•
•
•
•
•
•
上电复位至零
电源电压：2.7V 至 5.5V
DAC8560 包含一个上电复位 (POR) 电路，此电路可
确保 DAC 输出为零时上电，并在一段有效代码被写入
器件前保持此状态。DAC8560 包含一个由串口访问的
断电特性，这将器件在电压为 5V 时的功耗减少至
1.2μA。
在整个温度范围具有 16 位单调性
建立时间：10μs 达到 ±0.003% FSR
具有施密特触发输入的低功耗串口
支持轨至轨运行的片上输出缓冲放大器
掉电能力
此低功耗、集成内部基准电压和小封装尺寸使得这些器
件非常适合于便携式、电池供电类设备。电压为 5V 时
的功耗为 2.6mW，断电模式下减少到 6μW。
与DAC8531/01和DAC8550 /51直接兼容
温度范围：-40°C 至 +105°C
采用超小型 8 引脚 VSSOP 封装
DAC8560 采用 8 引脚 VSSOP 封装。
2 应用
器件信息(1)
•
•
•
•
•
过程控制
器件型号
DAC8560
封装
VSSOP (8)
封装尺寸（标称值）
数据采集系统
闭环伺服器控制
PC 外设
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
便携式仪表
功能方框图
VDD
VFB
VREF
VOUT
Ref (+)
16-Bit DAC
2.5V
Reference
16
DAC Register
16
SYNC
SCLK
DIN
PWD
Control
Resistor
Network
Shift Register
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLAS464
DAC8560
ZHCSBK1C –DECEMBER 2006–REVISED JANUARY 2018
www.ti.com.cn
目录
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 24
7.5 Programming........................................................... 25
7.6 Register Maps......................................................... 26
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Applications ................................................ 27
Power Supply Recommendations...................... 32
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 7
6.7 Typical Characteristics: Internal Reference .............. 8
6.8 Typical Characteristics: DAC at VDD = 5 V ............. 10
6.9 Typical Characteristics: DAC at VDD = 3.6 V .......... 15
6.10 Typical Characteristics: DAC at VDD = 2.7 V ........ 15
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
8
9
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 32
11 器件和文档支持 ..................................................... 33
11.1 文档支持................................................................ 33
11.2 接收文档更新通知 ................................................. 33
11.3 社区资源................................................................ 33
11.4 商标....................................................................... 33
11.5 静电放电警告......................................................... 33
11.6 术语表 ................................................................... 33
12 机械、封装和可订购信息....................................... 33
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (November 2011) to Revision C
Page
•
已添加 在 TI Designs 的器件信息、ESD 额定值、建议运行条件和热性能信息表、特性 说明 部分、器件功能模式、应
用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分添加了顶部
导航链接 ................................................................................................................................................................................. 1
Changes from Revision A (November 2011) to Revision B
Page
•
•
已更改 将版本日期从 2011 年 5 月 A 版本更改成了 2011 年 11 月 B 版本 ........................................................................... 1
Changed "Zero-code error drift" in the ELEC CHARA table, TYP from ±20 to ±4................................................................. 5
Changes from Original (December 2006) to Revision A
Page
•
•
Changed Output Voltage parameter min/max values from 2.4995 and 2.5005 to 2.4975 and 2.5025, respectively............. 6
Changed Initial Accuracy parameter min/max values from –0.02 and 0.02 to –0.1 and 0.1, respectively ............................ 6
Changes from Revision A (May 2011) to Revision B
Page
•
•
已更改 将版本日期从 2011 年 5 月 A 版本更改成了 2011 年 11 月 B 版本 ........................................................................... 1
Changed "Zero-code error drift" in the ELEC CHARA table, TYP from ±20 to ±4................................................................. 5
2
Copyright © 2006–2018, Texas Instruments Incorporated
DAC8560
www.ti.com.cn
ZHCSBK1C –DECEMBER 2006–REVISED JANUARY 2018
5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
1
2
3
4
8
7
6
5
VDD
VREF
VFB
GND
DIN
DAC8560
SCLK
SYNC
VOUT
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
VDD
PWR
I/O
I
Power supply input, 2.7 V to 5.5 V
Reference voltage input/output
2
VREF
VFB
3
Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally.
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
4
VOUT
O
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data.
When SYNC goes LOW, it enables the input shift register, and data is sampled on subsequent falling
clock edges. The DAC output updates following the 24th clock. If SYNC is taken HIGH before the
24th clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by
the DAC8560. Schmitt-Trigger logic input.
5
SYNC
I
6
7
8
SCLK
DIN
I
I
Serial clock input, Schmitt-Trigger logic input.
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial
clock input. Schmitt-Trigger logic input.
GND
GND
Ground reference point for all circuitry on the device.
Copyright © 2006–2018, Texas Instruments Incorporated
3
DAC8560
ZHCSBK1C –DECEMBER 2006–REVISED JANUARY 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
VDD to GND
6
VDD + 0.3
VDD + 0.3
(TJ(MAX) – TA) / RθJA
105
V
V
V
Digital input voltage to GND
VOUT to GND
Power dissipation (DGK)
Operating temperature
Junction temperature, TJ(MAX)
Storage temperature, Tstg
–40
–65
°C
°C
°C
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
0
NOM
MAX
5.5
UNIT
V
VDD
Supply voltage (VDD to GND)
Digital input voltage (DIN, SCLK, and SYNC)
Output amplifier feedback input
Operating ambient temperature
VDD
V
VFB
TA
VOUT
V
–40
125
°C
6.4 Thermal Information
DAC8560
THERMAL METRIC(1)
DGK (VSSOP)
UNIT
8 PINS
206
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
44
94.2
10.2
92.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2006–2018, Texas Instruments Incorporated
DAC8560
www.ti.com.cn
ZHCSBK1C –DECEMBER 2006–REVISED JANUARY 2018
6.5 Electrical Characteristics
VDD = 2.7 V to 5.5 V, –40°C to +105°C range (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE(1)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
Bits
LSB
DAC8560A, DAC8560C
DAC8560B, DAC8560D
±4
±4
±12
±8
Measured by line passing through
Relative accuracy
codes 485 and 64714
LSB
Differential nonlinearity
Zero-code error
Full-scale error
16-bit Monotonic
±0.5
±5
±1
LSB
±12
±0.5
±0.2
mV
Measured by line passing through codes 485 and 64714.
±0.2
±0.05
±4
% of FSR
% of FSR
μV/°C
Gain error
Zero-code error drift
VDD = 5 V
±1
ppm of
FSR/°C
Gain temperature coefficient
VDD = 2.7 V
±3
PSRR
Power supply rejection ratio
Output unloaded
1
mV/V
OUTPUT CHARACTERISTICS(2)
Output voltage range
0
VREF
10
V
To ±0.003% FSR, 0200h to FD00h, RL = 2 kΩ,
0 pF < CL < 200 pF
8
Output voltage settling time
μs
RL = 2 kΩ, CL = 500 pF
12
1.8
470
1000
0.15
0.15
1
Slew rate
V/μs
RL = ∞
Capacitive load stability
pF
RL = 2 kΩ
Code change glitch impulse
Digital feedthrough
1 LSB change around major carry
SCLK toggling, SYNC high
At mid-code input
nV-s
nV-s
Ω
DC output impedance
VDD = 5 V
50
Short-circuit current
mA
VDD = 3 V
20
Coming out of power-down mode VDD = 5 V
Coming out of power-down mode VDD = 3 V
2.5
5
Power-up time
μs
AC PERFORMANCE(2)
SNR
88
–77
79
dB
dB
THD
TA = 25°C, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz,
1st 19 harmonics removed for SNR calculation
SFDR
dB
SINAD
77
dB
DAC output noise density
DAC output noise
TA = 25°C, at mid-code input, fOUT = 1 kHz
TA = 25°C, at mid-code input, 0.1 Hz to 10 Hz
170
50
nV/√Hz
μVPP
(1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded.
(2) Ensured by design and characterization, not production tested.
Copyright © 2006–2018, Texas Instruments Incorporated
5
DAC8560
ZHCSBK1C –DECEMBER 2006–REVISED JANUARY 2018
www.ti.com.cn
Electrical Characteristics (continued)
VDD = 2.7 V to 5.5 V, –40°C to +105°C range (unless otherwise noted)
PARAMETER
REFERENCE OUTPUT
Output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
2.4975
–0.1%
2.5
2.5025
0.1%
25
V
Initial accuracy
TA = 25°C
±0.004%
DAC8560A, DAC8560B(3)
DAC8560C, DAC8560D(4)
f = 0.1 Hz to 10 Hz
5
2
Output voltage temperature
drift
ppm/°C
5
Output voltage noise
16
125
20
2
μVPP
TA = 25°C, f = 1 MHz, CL = 0 μF
TA = 25°C, f = 1 MHz, CL = 1 μF
TA = 25°C, f = 1 MHz, CL = 4 μF
TA = 25°C
Output voltage noise density
(high-frequency noise)
nV/√Hz
Load regulation, sourcing(5)
Load regulation, sinking(5)
30
15
μV/mA
μV/mA
TA = 25°C
Output current load
capability(2)
±20
10
mA
μV/V
ppm
Line regulation
TA = 25°C
Long-term stability/drift
(aging)(5)
TA = 25°C, time = 0 to 1900 hours
50
First cycle
100
25
Thermal hysteresis(5)
ppm
Additional cycles
REFERENCE
VDD = 5.5 V
360
348
20
Internal reference current
consumption
μA
VDD = 3.6 V
External reference current
Reference input range
External VREF = 2.5 V, if internal reference is disabled
μA
V
0
VDD
Reference input impedance
125
±1
kΩ
(2)
LOGIC INPUTS
Input current
μA
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
0.8
0.6
Logic input LOW
voltage
VIN
VIN
L
V
2.4
2.1
Logic input HIGH
voltage
H
V
Pin capacitance
POWER REQUIREMENTS
VDD
3
pF
2.7
5.5
0.85
0.84
2.5
2.2
4.7
3
V
VDD = 3.6 V to 5.5 V, VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND
VDD = 3.6 V to 5.5 V, VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND
VDD = 3.6 V to 5.5 V
0.53
0.51
1.2
0.7
2.6
1.5
6
Normal mode
mA
(6)
IDD
All power-down
modes
μA
mW
μW
Normal mode
Power
VDD = 2.7 V to 3.6 V
dissipatio
n(6)
VDD = 3.6 V to 5.5 V
14
All power-down
modes
VDD = 2.7 V to 3.6 V
2
8
TEMPERATURE RANGE
Specified performance
–40
105
°C
(3) Reference is trimmed and tested at room temperature, and is characterized from –40°C to +120°C.
(4) Reference is trimmed and tested at two temperatures (25°C and 105°C), and is characterized from –40°C to +120°C.
(5) Explained in more detail in Application and Implementation.
(6) Input code = 32768, reference current included, no load.
6
Copyright © 2006–2018, Texas Instruments Incorporated
DAC8560
www.ti.com.cn
ZHCSBK1C –DECEMBER 2006–REVISED JANUARY 2018
6.6 Timing Requirements
VDD = 2.7 V to 5.5 V, all specifications –40°C to +105°C (unless otherwise noted)(1)
(2)
PARAMETER
MIN NOM
MAX UNIT
VDD = 2.7 V to 3.6 V
50
33
13
13
22.5
13
0
(3)
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
SCLK cycle time
ns
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
SCLK HIGH time
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK LOW time
SYNC to SCLK rising edge setup time
Data setup time
0
5
5
4.5
4.5
0
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC HIGH time
24th SCLK falling edge to SYNC falling edge
0
50
33
100
100
15
15
SYNC rising edge to 24th SCLK falling edge
(for successful SYNC interrupt)
(1) All input signals are specified with tR = tF = 3 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2.
(2) See Figure 1.
(3) Maximum SCLK frequency is 3 0MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
t9
t1
SCLK
SYNC
1
24
t8
t2
t3
t7
t4
t10
t6
t5
DB23
DIN
DB0
DB23
Figure 1. Serial Write Operation
Copyright © 2006–2018, Texas Instruments Incorporated
7
DAC8560
ZHCSBK1C –DECEMBER 2006–REVISED JANUARY 2018
www.ti.com.cn
6.7 Typical Characteristics: Internal Reference
At TA = 25°C, unless otherwise noted.
2.503
2.502
2.501
2.500
2.499
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.498
10 Units Shown
100
13 Units Shown
80 100 120
2.497
-40
-20
0
20
40
60
120
-40
-20
0
20
40
60
Temperature (°C)
Temperature (°C)
Figure 2. Internal Reference Voltage vs Temperature
(Grades C and D)
Figure 3. Internal Reference Voltage vs Temperature
(Grades A and B)
40
30
Typ: 5ppm/°C
Typ: 2ppm/°C
Max: 5ppm/°C
Max: 25ppm/°C
30
20
10
0
20
10
0
0.5
1
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
3
5
7
9
11
13
15
17
19
Temperature Drift (ppm/°C)
Temperature Drift (ppm/°C)
Figure 4. Reference Output Temperature Drift (–40°C to
120°C, Grades C and D)
Figure 5. Reference Output Temperature Drift (–40°C to
120°, Grades A and B)
200
40
See the Applications Information
section for more information
Typ: 1.2ppm/°C
Max: 3ppm/°C
150
100
50
30
20
10
0
0
-50
-100
-150
-200
Average
20 Units Shown
1200 1500 1800
0
300
600
900
Time (Hours)
0.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Temperature Drift (ppm/°C)
Explained in more detail in Application and Implementation .
(1)
Figure 7. Long-Term Stability/Drift
Figure 6. Reference Output Temperature Drift (0°C to 120°C,
Grades C and D)
(1)
8
Copyright © 2006–2018, Texas Instruments Incorporated
DAC8560
www.ti.com.cn
ZHCSBK1C –DECEMBER 2006–REVISED JANUARY 2018
Typical Characteristics: Internal Reference (continued)
At TA = 25°C, unless otherwise noted.
400
See the Applications Information
section for more information
See the Applications Information
section for more information
VDD = 5V
16mVPP
300
Reference Unbuffered
CREF = 0mF
200
100
CREF = 4mF
0
Time (2s/div)
10
100
1k
10k
100k
1M
Frequency (Hz)
Explained in more detail in Application and Implementation.
Explained in more detail in Application and Implementation.
Figure 9. Internal Reference Noise 0.1 Hz to 10 Hz
Figure 8. Internal Reference Noise Density vs Frequency
2.504
2.504
-40°C
2.503
2.503
2.502
2.502
15mV/mA (sinking)
15mV/mA (sinking) -40°C
2.501
2.501
+25°C
+25°C
2.500
2.499
2.500
2.499
30mV/mA (sourcing)
+120°C
2.498
2.498
30mV/mA (sourcing)
2.497
2.497
+120°C
2.496
2.496
-25 -20 -15 -10 -5
0
5
10
15 20 25
-25 -20 -15 -10 -5
0
5
10
15 20 25
ILOAD (mA)
ILOAD (mA)
Figure 10. Internal Reference Voltage vs Load Current
(Grades C and D)
Figure 11. Internal Reference Voltage vs Load Current
(Grades A and B)
2.504
2.504
-40°C
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.503
2.502
2.501
2.500
2.499
2.498
2.497
-40°C
+25°C
< 10mV/V
< 10mV/V
+25°C
+120°C
+120°C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
Figure 12. Internal Reference Voltage vs Supply Voltage
(Grades C and D)
Figure 13. Internal Reference Voltage vs Supply Voltage
(Grades A and B)
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6.8 Typical Characteristics: DAC at VDD = 5 V
At TA = 25°C, external reference used, and DAC output not loaded, unless otherwise noted.
6
4
6
4
VDD = 5V, External VREF = 4.99V
VDD = 5V, External VREF = 4.99V
2
2
0
0
-2
-4
-6
-2
-4
-6
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
–40°C
25°C
Figure 14. Linearity Error and Differential Linearity Error vs
Digital Input Code
Figure 15. Linearity Error and Differential Linearity Error vs
Digital Input Code
10
6
VDD = 5V, External VREF = 4.99V
VDD = 5.0V
4
2
Internal VREF = 2.5V
0
-2
-4
-6
5
1.0
0.5
0
0
-0.5
-1.0
-5
0
8192 16384 24576 32768 40960 49152 57344 65536
-40
0
40
80
120
Temperature (°C)
Digital Input Code
105°C
Figure 17. Zero-Scale Error vs Temperature
Figure 16. Linearity Error and Differential Linearity Error vs
Digital Input Code
10
3.0
VDD = 5.0V
Internal VREF = 2.5V
2.5
2.0
1.5
1.0
0.5
0
VDD = 5V
Internal Reference Enabled
DAC Loaded with FFFFh
5
0
DAC Loaded with 0000h
-5
-40
0
40
80
120
0
5
10
15
20
Temperature (°C)
ISOURCE/SINK (mA)
Figure 18. Full-Scale Error vs Temperature
Figure 19. Source and Sink Current Capability
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Typical Characteristics: DAC at VDD = 5 V (continued)
At TA = 25°C, external reference used, and DAC output not loaded, unless otherwise noted.
650
600
550
500
450
6
5
4
3
2
1
0
VDD = 5.5V
Internal VREF = 2.5V
VDD = 5V
Internal Reference Disabled
External VREF = 4.99V
DAC Loaded with FFFFh
DAC Loaded with 0000h
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
5
10
15
20
ISOURCE/SINK (mA)
Figure 20. Source and Sink Current Capability
Figure 21. Power-Supply Current vs Digital Input Code
700
650
600
550
500
450
400
510
VDD = 5.5V
VDD = 2.7V to 5.5V
Internal VREF = 2.5V
Internal VREF Included
505
500
495
490
485
-40
0
40
80
120
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Temperature (°C)
VDD (V)
Figure 22. Power-Supply Current vs Temperature
Figure 23. Power-Supply Current vs Power-Supply Voltage
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2500
VDD = 5.5V, Internal VREF Included,
VDD = 2.7V to 5.5V
Sweep from 0V to 5V
SCLK Input
(all other digital inputs = GND)
2000
1500
1000
500
0
Sweep from 5V to 0V
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0
1
2
3
4
5
VDD (V)
VLOGIC (V)
Figure 25. Power-Supply Current vs Logic Input Voltage
Figure 24. Power-Down Current vs Power-Supply Voltage
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Typical Characteristics: DAC at VDD = 5 V (continued)
At TA = 25°C, external reference used, and DAC output not loaded, unless otherwise noted.
80
70
60
50
40
30
20
10
0
-40
-50
-60
-70
-80
-90
-100
VDD = 5V, External VREF = 4.9V
VDD = 5.5V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
Internal VREF = 2.5V
THD
2nd Harmonic
3rd Harmonic
450
475
500
525
550
575
600
0
1
2
3
4
5
IDD (mA)
fOUT (kHz)
Figure 27. Total Harmonic Distortion vs Output Frequency
Figure 26. Power-Supply Current Histogram
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: FFFFh
To Code: 0000h
VDD = 5V
Ext VREF = 4.096V
From Code: 0000h
To Code: FFFFh
Falling
Edge
1V/div
Rising Edge
1V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
5-V Rising Edge
5-V Falling Edge
Figure 28. Full-Scale Settling Time
Figure 29. Full-Scale Settling Time
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: CFFFh
To Code: 4000h
VDD = 5V
Ext VREF = 4.096V
From Code: 4000h
To Code: CFFFh
Rising
Edge
1V/div
Falling
Edge
1V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
5-V Rising Edge
Figure 30. Half-Scale Settling Time
5-V Falling Edge
Figure 31. Half-Scale Settling Time
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Typical Characteristics: DAC at VDD = 5 V (continued)
At TA = 25°C, external reference used, and DAC output not loaded, unless otherwise noted.
VDD = 5V
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Measured Worst Case
Ext VREF = 4.096V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
Time (400ns/div)
Time (400ns/div)
Rising Edge
Rising Edge
Rising Edge
5 V
1-LSB Step
Falling Edge
Falling Edge
Falling Edge
5 V
1-LSB Step
Figure 32. Glitch Energy
Figure 33. Glitch Energy
VDD = 5V
Ext VREF = 4.096V
From Code: 8010h
To Code: 8000h
Glitch: 0.08nV-s
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
5 V
16-LSB Step
5 V
16-LSB Step
Figure 34. Glitch Energy
Figure 35. Glitch Energy
VDD = 5V
Ext VREF = 4.096V
From Code: 80FFh
To Code: 8000h
Glitch: Not Detected
Theoretical Worst Case
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 80FFh
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
5 V
2566-LSB Step
5 V
256-LSB Step
Figure 36. Glitch Energy
Figure 37. Glitch Energy
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Typical Characteristics: DAC at VDD = 5 V (continued)
At TA = 25°C, external reference used, and DAC output not loaded, unless otherwise noted.
0
98
96
94
92
90
88
86
84
VDD = 5V, External VREF = 4.9V
VDD = 5V, External VREF = 4.9V
-10
fOUT = 1kHz, fS = 225kSPS
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
-20
Measurement Bandwidth = 20kHz
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
5
10
15
20
0
1
2
3
4
5
Frequency (kHz)
fOUT (kHz)
Figure 38. Signal-to-Noise Ratio vs Output Frequency
Figure 39. Power Spectral Density
1800
1000
800
600
400
200
0
Internal Reference Enabled
No Load at VREF Pin
Internal Reference Enabled
4mF vs No Load at VREF Pin
1600
1400
1200
1000
800
600
400
200
0
See the Applications Information
section for more information
See the Applications Information
section for more information
Full-Scale
Midscale
Zero-Scale
CREF = 0mF
CREF = 4mF
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Explained in more detail in Application and Implementation.
Explained in more detail in the Application and Implementation
Figure 40. DAC Output Noise Density vs Frequency
Figure 41. DAC Output Noise Density vs Frequency
DAC = Midscale
Internal Reference Enabled
50mVPP
Time (2s/div)
0.1 Hz to 10 Hz
Figure 42. DAC Output Noise
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6.9 Typical Characteristics: DAC at VDD = 3.6 V
At TA = 25°C, internal reference used, and DAC output not loaded, unless otherwise noted
700
650
600
550
500
450
400
90
80
70
60
50
40
30
20
10
0
VDD = 3.6V
VDD = 3.6V
Internal VREF = 2.5V
Internal VREF = 2.5V
-40
0
40
80
120
450
475
500
525
550
575
600
Temperature (°C)
IDD (mA)
Figure 43. Power-Supply Current vs Temperature
Figure 44. Power-Supply Current Histogram
6.10 Typical Characteristics: DAC at VDD = 2.7 V
At TA = 25°C, internal reference used, and DAC output not loaded, unless otherwise noted
6
4
6
4
VDD = 2.7V, Internal VREF = 2.5V
VDD = 2.7V, Internal VREF = 2.5V
2
2
0
0
-2
-4
-6
-2
-4
-6
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
–40°C
25°C
Figure 45. Linearity Error and Differential Linearity Error vs
Digital Input Code
Figure 46. Linearity Error and Differential Linearity Error vs
Digital Input Code
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Typical Characteristics: DAC at VDD = 2.7 V (continued)
At TA = 25°C, internal reference used, and DAC output not loaded, unless otherwise noted
10
6
VDD = 2.7V, Internal VREF = 2.5V
VDD = 2.7V
4
Internal VREF = 2.5V
2
0
-2
-4
-6
5
1.0
0.5
0
0
-0.5
-1.0
-5
0
8192 16384 24576 32768 40960 49152 57344 65536
-40
0
40
80
120
Temperature (°C)
Digital Input Code
105°C
Figure 48. Zero-Scale Error vs Temperature
Figure 47. Linearity Error and Differential Linearity Error vs
Digital Input Code
10
3.0
2.5
2.0
1.5
1.0
0.5
0
VDD = 2.7V
Internal VREF = 2.5V
VDD = 2.7V
Internal Reference Enabled
DAC Loaded with FFFFh
5
0
DAC Loaded with 0000h
-5
-40
0
40
80
120
0
5
10
15
20
Temperature (°C)
ISOURCE/SINK (mA)
Figure 49. Full-Scale Error vs Temperature
Figure 50. Source and Sink Current Capability
650
600
550
500
450
1000
900
800
700
600
500
400
VDD = 2.7V, Internal VREF Included,
SCLK Input
VDD = 2.7V
Internal VREF = 2.5V
(all other digital inputs = GND)
Sweep from 0V to 2.7V
Sweep from 2.7V to 0V
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4 2.7
VLOGIC (V)
Figure 51. Supply Current vs Digital Input Code
Figure 52. Power-Supply Current vs Logic Input Voltage
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Typical Characteristics: DAC at VDD = 2.7 V (continued)
At TA = 25°C, internal reference used, and DAC output not loaded, unless otherwise noted
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: FFFFh
To Code: 0000h
Rising
Edge
0.5V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: 0000h
To Code: FFFFh
Zoomed Falling Edge
1mV/div
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
2.7-V Rising Edge
2.7-V Falling Edge
Figure 53. Full-Scale Settling Time
Figure 54. Full-Scale Settling Time: 2.7-V Falling Edge
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: CFFFh
To Code: 4000h
VDD = 2.7V
Int VREF = 2.5V
From Code: 4000h
To Code: CFFFh
Rising
Edge
0.5V/div
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
2.7-V Rising Edge
Figure 55. Half-Scale Settling Time
2.7-V Falling Edge
Figure 56. Half-Scale Settling Time
VDD = 2.7V
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Measured Worst Case
Int VREF = 2.5V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
Time (400ns/div)
Time (400ns/div)
Rising Edge
2.7 V
Figure 57. Glitch Energy
1-LSB Step
Falling Edge
2.7 V
1-LSB Step
Figure 58. Glitch Energy
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Typical Characteristics: DAC at VDD = 2.7 V (continued)
At TA = 25°C, internal reference used, and DAC output not loaded, unless otherwise noted
VDD = 2.7V
Int VREF = 2.5V
From Code: 8010h
To Code: 8000h
Glitch: 0.12nV-s
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Rising Edge
2.7 V
16-LSB Step
Falling Edge
2.7 V
16-LSB Step
Figure 59. Glitch Energy
Figure 60. Glitch Energy
VDD = 2.7V
Int VREF = 2.5V
From Code: 80FFh
To Code: 8000h
Glitch: Not Detected
Theoretical Worst Case
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 80FFh
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Rising Edge
2.7 V
256-LSB Step
Falling Edge
2.7 V
256-LSB Step
Figure 61. Glitch Energy
Figure 62. Glitch Energy
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7 Detailed Description
7.1 Overview
The DAC8560 is a low-power, voltage output, 16-bit digital-to-analog converter (DAC). The DAC8560 includes a
2.5-V, 2-ppm/°C internal reference (enabled by default), giving a full-scale output voltage range of 2.5 V. The
internal reference has an initial accuracy of 0.02% and can source up to 20 mA at the VREF pin. The device is
monotonic, provides very good linearity, and minimizes undesired code-to-code transient voltages (glitch). The
DAC8560 uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with
standard SPI, QSPI, Microwire, and digital-signal-processor (DSP) interfaces.
7.2 Functional Block Diagram
VDD
VFB
VREF
VOUT
Ref (+)
16-Bit DAC
2.5V
Reference
16
DAC Register
16
SYNC
SCLK
DIN
PWD
Control
Resistor
Network
Shift Register
GND
7.3 Feature Description
7.3.1 Digital-to-Analog Converter (DAC)
The DAC8560 architecture consists of a string DAC followed by an output buffer amplifier. Figure 63 shows a
block diagram of the DAC architecture.
VREF
50kW
50kW
VFB
62kW
REF (+)
VOUT
DAC
Register
Register String
REF (-)
GND
Figure 63. DAC8560 Architecture
The input coding to the DAC8560 is straight binary, so the ideal output voltage is given by:
DIN
65536
VOUT
+
VREF
where DIN = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to
65535.
(1)
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Feature Description (continued)
7.3.2 Resistor String
The resistor string section is shown in Figure 64. It is simply a string of resistors, each of value R. The code
loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the
output amplifier by closing one of the switches connecting the string to the amplifier. It is monotonic because it is
a string of resistors.
VREF
RDIVIDER
VREF
2
R
To Output Amplifier
R
(2x Gain)
R
R
Figure 64. Resistor String
7.3.3 Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0
V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities
of the output amplifier can be seen in the Typical Characteristics: DAC at VDD = 5 V. The slew rate is 1.8 V/μs
with a full-scale settling time of 8 μs with the output unloaded.
The inverting input of the output amplifier is available at the VFB pin. This feature allows better accuracy in critical
applications by tying the VFB point and the amplifier output together directly at the load. Other signal conditioning
circuitry may also be connected between these points for specific applications.
20
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Feature Description (continued)
7.3.4 DAC Noise Performance
Typical noise performance for the DAC8560 with the internal reference enabled is shown in Figure 40 to
Figure 42. Output noise spectral density at pin VOUT versus frequency is depicted in Figure 40 for full-scale,
midscale, and zero-scale input codes. The typical noise density for midscale code is 170 nV/√Hz at 1 kHz and
100nV/√Hz at 1MHz. High-frequency noise can be improved by filtering the reference noise as shown in
Figure 41, where a 4-μF load capacitor is connected to the VREF pin and compared to the no-load condition.
Integrated output noise between 0.1 Hz and 10 Hz is close to 50 μVPP (midscale), as shown in Figure 42.
7.3.5 Internal Reference
The DAC8560 includes a 2.5-V internal reference that is enabled by default. The internal reference is externally
available at the VREF pin. TI recommends a minimum 100-nF capacitor between the reference output and GND
for noise filtering.
The internal reference of the DAC8560 is a bipolar transistor-based, precision bandgap voltage reference. The
basic bandgap topology is shown in Figure 65. Transistors Q1 and Q2 are biased such that the current density of
Q1 is greater than that of Q2. The difference of the two base-emitter voltages (VBE1 – VBE2) has a positive
temperature coefficient and is forced across resistor R1. This voltage is gained up and added to the base-emitter
voltage of Q2, which has a negative temperature coefficient. The resulting output voltage is virtually independent
of temperature. The short-circuit current is limited by design to approximately 100 mA.
VREF
Reference
Disable
Q1
1
N
Q2
R1
R2
Figure 65. Simplified Schematic of the Bandgap Reference
7.3.5.1 Enable/Disable Internal Reference
The DAC8560 internal reference is enabled by default; however, the reference can be disabled for debugging or
evaluation purposes. A serial command requiring at least two additional SCLK cycles at the end of the 24-bit
write sequence (see Serial Interface) must be used to disable the internal reference. For proper operation, a total
of at least 26 SCLK cycles are required for each enable/disable internal reference update sequence, during
which SYNC must be held low. To disable the internal reference, execute the write sequence illustrated in
Table 2 followed by at least two additional SCLK falling edges while SYNC is low.
To then enable the reference, either perform a power-cycle to reset the device, or sequentially execute the two
write sequences in Table 3 and Table 4. Each of these write sequences must be followed by at least two
additional SCLK falling edges while SYNC remains low.
During the time that the internal reference is disabled, the DAC will function normally using an external reference.
At this point, the internal reference is disconnected from the VREF pin (tri-state). Do not attempt to drive the VREF
pin externally and internally at the same time indefinitely.
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Feature Description (continued)
7.3.5.2 Internal Reference Load
The DAC8560 internal reference does not require an external load capacitor for stability because it is stable with
any capacitive load. However, for improved noise performance, TI recommends an external load capacitor of 150
nF or larger connected to the VREF output. Figure 66 shows the typical connections required for operation of the
DAC8560 internal reference. A supply bypass capacitor at the VDD input is also recommended.
DAC8560
GND
DIN
VDD
1
2
3
4
VDD
8
7
6
5
1mF
VREF
VFB
SCLK
SYNC
VREF
150nF
VOUT
Figure 66. Typical Connections for Operating the DAC8560 Internal Reference
7.3.5.2.1 Supply Voltage
The DAC8560 internal reference features an extremely low dropout voltage. It can be operated with a supply of
only 5mV above the reference output voltage in an unloaded condition. For loaded conditions, refer to the Load
Regulation section. The stability of the DAC8560 internal reference with variations in supply voltage (line
regulation, DC PSRR) is also exceptional. Within the specified supply voltage range of 2.7 V to 5.5 V, the
variation at VREF is smaller than 10 μV/V; see the Typical Characteristics: Internal Reference.
7.3.5.2.2 Temperature Drift
The DAC8560 internal reference is designed to exhibit minimal drift error, defined as the change in reference
output voltage over varying temperature. The drift is calculated using the box method, which is described by
Equation 2:
VREF_MAX * VREF_MIN
6
Drift Error + ǒ
Ǔ
10 (ppmń°C)
VREF TRANGE
where
•
•
•
VREF_MAX = maximum reference voltage observed within temperature range TRANGE
VREF_MIN = minimum reference voltage observed within temperature range TRANGE
VREF = 2.5 V, target value for reference output voltage
(2)
The DAC8560 internal reference (grades C and D) features an exceptional typical drift coefficient of 2 ppm/°C
from –40°C to +120°C. Characterizing a large number of units, a maximum drift coefficient of 5 ppm/°C (grades
C and D) is observed. Temperature drift results are summarized in the Typical Characteristics: Internal
Reference.
7.3.5.2.3 Noise Performance
Typical 0.1-Hz to 10-Hz voltage noise can be seen in Figure 9. Additional filtering can be used to improve output
noise levels, although care should be taken to ensure the output impedance does not degrade the AC
performance. The output noise spectrum at VREF without any external components is depicted in Figure 8,
Internal Reference Noise Density vs Frequency. Another noise density spectrum is also shown in Figure 8, which
was obtained using a 4μF load capacitor at VREF for noise filtering. Internal reference noise impacts the DAC
output noise; see the DAC Noise Performance section for more details.
22
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Feature Description (continued)
7.3.5.2.4 Load Regulation
Load regulation is defined as the change in reference output voltage as a result of changes in load current. The
load regulation of the DAC8560 internal reference is measured using force and sense contacts as pictured in
Figure 67. The force and sense lines reduce the impact of contact and trace resistance, resulting in accurate
measurement of the load regulation contributed solely by the DAC8560 internal reference. Measurement results
are summarized in the Typical Characteristics: Internal Reference. Force and sense lines should be used for
applications requiring improved load regulation.
Output Pin
Contact and
Trace Resistance
VOUT
Force Line
IL
Sense Line
Load
Meter
Figure 67. Accurate Load Regulation of the DAC8560 Internal Reference
7.3.5.2.5 Long-Term Stability
Long-term stability/aging refers to the change of the output voltage of a reference over a period of months or
years. This effect lessens as time progresses, as shown in Figure 7, the typical long-term stability curve. The
typical drift value for the DAC8560 internal reference is 50 ppm from 0 hours to 1900 hours. This parameter is
characterized by powering up and measuring 20 units at regular intervals for a period of 1900 hours.
7.3.5.2.6 Thermal Hysteresis
Thermal hysteresis for a reference is defined as the change in output voltage after operating the device at 25°C,
cycling the device through the specified temperature range, and returning to 25°C. It is expressed in Equation 3:
Ť
Ť
VREF_PRE * VREF_POST
6
+ ǒ
Ǔ
VHYST
10 (ppm)
VREF_NOM
where
•
•
•
VHYST = thermal hysteresis
VREF_PRE = output voltage measured at 25°C pre-temperature cycling
VREF_POST = output voltage measured after the device has been cycled through the temperature range of –40°C
to +120°C, and returned to 25°C
(3)
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7.4 Device Functional Modes
7.4.1 Power-Down Modes
The DAC8560 supports four separate modes of operation. These modes are programmable by setting two bits
(PD1 and PD0) in the control register. Table 1 shows how to control the operating mode with data bits PD1
(DB17) and PD0 (DB16).
Table 1. Operating Modes
PD1 (DB17)
PD0 (DB16)
OPERATING MODE
0
0
1
1
0
1
0
1
Normal operation
Power-down 1 kΩ to GND
Power-down 100 kΩ to GND
Power-down High-Z
When both bits are set to 0, the device works normally with its typical current consumption of 530 μA at 5.5 V.
However, for the three power-down modes, the supply current falls to 1.2 μA at 5.5 V (0.7 μA at 3.6 V). Not only
does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a
resistor network of known values.
The advantage of this switching is that the output impedance of the device is known while it is in power-down
mode. As shown in Table 1, there are three different power-down options. VOUT can be connected internally to
GND through a 1-kΩ resistor, a 100-kΩ resistor, or open-circuited (High-Z). The output stage is shown in
Figure 68.
VFB
Amplifier
VOUT
Resistor
String
DAC
Power-Down
Circuitry
Resistor
Network
Figure 68. Output Stage During Power Down
All analog circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power down. The time to exit power down is typically 2.5 μs for VDD = 5 V, and 5
μs for VDD = 3 V. See the Typical Characteristics: DAC at VDD = 5 V for more information.
24
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7.5 Programming
7.5.1 Serial Interface
The DAC8560 has a 3-wire serial interface ( SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSPs. See Figure 1 for an example of a typical write sequence.
The write sequence begins by bringing the SYNC line LOW. Data from the DIN line is clocked into the 24-bit shift
register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the
DAC8560 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is
clocked in and the programmed function is executed.
At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a
minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write
sequence. As previously mentioned, it must be brought HIGH again before the next write sequence.
7.5.2 Input Shift Register
The input shift register is 24 bits wide, as shown in Table 5. The first six bits must be 000000. The next two bits
(PD1 and PD0) are control bits that set the desired mode of operation (normal mode or any one of three power-
down modes) as indicated in Table 1.
A more complete description of the various modes is located in Power-Down Modes. The next 16 bits are the
data bits, which are transferred to the DAC register on the 24th falling edge of SCLK under normal operation
(see Table 1).
7.5.3 SYNC Interrupt
In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the DAC is
updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an
interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an
update of the DAC register contents, nor a change in the operating mode occurs, as shown in Figure 69.
7.5.4 Power-On Reset
The DAC8560 contains a power-on-reset circuit that controls the output voltage during power up. On power up,
all registers are filled with zeros and the output voltage is zero-scale; it remains there until a valid write sequence
is made to the DAC. This feature is useful in applications where it is important to know the state of the output of
the DAC while it is in the process of powering up.
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7.6 Register Maps
7.6.1 Write Sequence for Disabling the DAC8560 Internal Reference
Table 2. Write Sequence for Disabling the DAC8560 Internal Reference
DB23
0
DB0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
7.6.2 Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)
Table 3. Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)
DB23
DB0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
7.6.3 Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)
Table 4. Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)
DB23
DB0
1
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
7.6.4 DAC8560 Data Input Register Format
Table 5. DAC8560 Data Input Register Format
DB23
DB0
D0
0
0
0
0
0
0
PD1 PD0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB0
DB23
DB0
Invalid/Interrupted Write Sequence:
Output/Mode Does Not Update on the 24th Falling Edge
Valid Write Sequence:
Output/Mode Updates on the 24th Falling Edge
Figure 69. SYNC Interrupt Facility
26
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The low-power consumption of the DAC8560, coupled with the ultra-low current power-down modes, makes the
device a great choice for battery-operated and portable applications such as oscilloscopes and similar test and
measurement equipment. In addition to the low-power requirement, these applications often require a bipolar
output range for offset and gain calibration as described in the following sections.
8.2 Typical Applications
The output voltage with Figure 70 and Figure 71 for any input code can be calculated using Equation 4:
R1 ) R2
R2
R1
D
65536
ǒ Ǔ
ǒ Ǔ ǒ Ǔ
VO +
ƪ
VREF
* VREF
ƫ
R1
where D represents the input code in decimal (0–65535).
(4)
(5)
With VREF = 5 V, R1 = R2 = 10 kΩ.
10 D
ǒ Ǔ* 5V
VO +
65536
This result has an output voltage range of ±5 V with 0000h corresponding to a –5-V output and FFFFh
corresponding to a 5-V output, as shown in Figure 70. Similarly, using the internal reference, a ±2.5-V output
voltage range can be achieved, as shown in Figure 71.
R2
10kW
V
V
DD
REF
+6V
R1
10kW
±5V
OPA703
VDD
VFB
VOUT
VREF
DAC8560
-6V
10mF
0.1mF
GND
Three-Wire
Serial Interface
Copyright © 2018, Texas Instruments Incorporated
Figure 70. Bipolar Output Range Using External Reference at 5 V
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Typical Applications (continued)
R2
10kW
V
DD
+6V
R1
10kW
±2.5V
OPA703
VDD
VFB
VREF
VOUT
DAC8560
-6V
150nF
GND
Three-Wire
Serial Interface
Copyright © 2018, Texas Instruments Incorporated
Figure 71. Bipolar Output Range Using Internal Reference
RG1
RFB
CCOMP
VREF
RG2
VOUT
+
DAC8560
RISO
CLOAD
OPA188
Copyright © 2018, Texas Instruments Incorporated
Figure 72. Bipolar Output Range > ±VREF
8.2.1 Design Requirements
The design requirements and performance goals are summarized as follows:
•
•
•
•
•
DAC Supply Voltage: +5-V DC
Amplifier Supply Voltage: ±15-V DC
Input: 3-wire, 24-bit SPI
Output: ±10-V DC
Capacitance Load: 20 nF
Table 6. Comparison of Design Goal, Simulation, and Measured Performance
GOAL
SIMULATED
MEASURED
0.0939
Total unadjusted error (%FSR)
0.25
0.23
28
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8.2.2 Detailed Design Procedure or Bipolar Operation > ±VREF
8.2.2.1 Bipolar Operation Greater Than ±VREF
The DAC8560 has been designed for single-supply operation; a bipolar output range is also possible using the
circuit in Figure 71. This unipolar-to-bipolar signal conditioning circuit uses an operational amplifier (op amp) with
negative feedback and three resistors in a modified summing amplifier configuration to generate high-voltage
bipolar outputs. The DC transfer function is based on the ratio of the feedback resistor RFB and gain setting
resistors RG1 and RG2. This design takes consideration for generating voltage outputs and for driving reactive
loads such as long cables common in industrial process control applications. The circuit shown in Figure 72 gives
an output voltage range greater than ±VREF
.
The DC transfer function for this design is defined as:
≈
’
÷
◊
RFB RFB
+
RFB
RG2
VOUT = 1+
V
-
VREF
∆
DAC
RG2 RG1
«
(6)
8.2.2.1.1 Passive Component Selection
The amplifier in this circuit uses negative feedback to ensure that the voltages at the inverting and non-inverting
terminals are equal. When the DAC output is at zero scale (0 V) the inverting terminal is a virtual ground so no
current flows across RG1; this causes the circuit to function as an inverting amplifier with gain equal to RFB / RG2
.
When the DAC output is full-scale (VREF) the inverting terminal potential is equal to VREF so no current flows
across RG2; this causes the circuit to function as a non-inverting amplifier with gain equal to (1 + RFB / RG1). A
simple three-step process can be used to select the resistor values used to realize any bipolar output range
using DAC8560. The internal VREF value is 2.5 V. The desired output range for this design is ±10 V. First, using
the transfer function shown in Equation 6, consider the negative full-scale output case when VDAC is equal to 0 V,
VREF is equal to 2.5 V, and VOUT is equal to –10 V. This case is used to calculate the ratio of RFB to RG2 and is
shown explicitly in Equation 7.
≈
’
÷
◊
RFB RFB
+
RFB
RG2
-10 V = 1+
0 -
( )
2.5 V
(
)
∆
RG2 RG1
«
RFB
RG2
-10 V = -
2.5 V
(
)
RFB = 4 ì RG2
(7)
Second, consider the positive full-scale output case when VDAC is equal to 2.5 V, VREF is equal to 2.5 V, and
VOUT is equal to 10 V. This case is used to calculate the ratio of RFB to RG1 and is shown explicitly in Equation 8.
≈
’
÷
◊
RFB RFB
+
RFB
RG2
10 V = 1+
2.5 -
2.5 V
(
)
(
)
∆
RG2 RG1
«
≈
’
RFB
RG1
10 V = 1+
2.5 V
(
)
∆
÷
«
◊
RFB
RG1
=
3
(8)
Finally, seed the ideal value of RG2 to calculate the ideal values of RFB and RG2. The key considerations for
seeding the value of RG2 should be the drive strength of the reference source as well as choosing small resistor
values to minimize noise contributed by the resistor network. For this design RG2 of 8.25 kΩ was chosen, which
limits the peak current drawn from the reference source to approximately 333 µA under nominal conditions, well
within the 20-mA limit of the DAC8560. In this case the nearest, 0.1% tolerance, 0603 package values for each
resistor are ideal.
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Standard values for 0.1% resistors can be an obstacle for this design and it may take multiple iterations of
seeding the values to find real components or they may not exist. Workarounds can include utilizing multiple
resistors in series and/or parallel, using potentiometers for analog trim calibration, or providing extra gain in the
output circuit and applying digital calibration. In systems where the output voltage must reach the design-goal
end-points (±10 V) it may be desirable to apply additional gain to the circuit. This approach may contribute
additional overall system error since the end-point errors vary from system to system. For this design, use the
exact values calculated in the design process to keep error analysis easy to follow.
To deliver a near-universal cable drive solution, choose CLOAD to be relatively large compared to typical cable
capacitance such that its capacitance dominates the reactive load seen by the output amplifier. To drive larger
capacitive loads RISO, CCOMP, and CLOAD may need to be adjusted. An RISO of 70 Ω and CCOMP of 150 pF are
used for this design.
Resistor matching for the op amp resistor network is critical for the success of this design; choose components
with tight tolerances. For this design 0.1% resistor values are implemented but this constraint may be adjusted
based on application specific design goals. Resistor matching contributes to both offset error and gain error in
this design. The tolerance of stability components RISO and CCOMP is not critical and 1% components are
acceptable.
Table 7. Values of Resistor Network
RESISTOR
VALUE
11 kΩ
RG1
RG2
8.25 kΩ
33 kΩ
RFB
8.2.2.1.2 Amplifier Selection
Amplifier input offset voltage (VOS) is a key consideration for this design. VOS of an op amp is a typical data-sheet
specification but in-circuit performance is also impacted by drift over temperature, the common-mode rejection
ratio (CMRR), and power supply rejection ratio (PSRR). Thus, consider these parameters as well. For AC
operation also consider slew rate and settling time. Input-bias current (IB) can also be a factor, but typically the
resistor network is implemented with sufficiently small resistor values that the effects of input-bias current are
negligible.
8.2.2.2 Microprocessor Interfacing
8.2.2.2.1 DAC8560 to 8051 Interface
See Figure 73 for a serial interface between the DAC8560 and a typical 8051-type microcontroller. The setup for
the interface is as follows: TXD of the 8051 drives SCLK of the DAC8560, while RXD drives the serial data line of
the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port
line P3.3 is used. When data is to be transmitted to the DAC8560, P3.3 is taken LOW. The 8051 transmits data
in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a second write cycle is initiated to transmit the second byte of
data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a
format which has the LSB first. The DAC8560 requires its data with the MSB as the first bit received. The 8051
transmit routine must therefore take this into account, and mirror the data as needed.
DAC8560 (1)
SYNC
80C51/80L51(1)
P3.3
TXD
RXD
SCLK
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 73. DAC8560 to 80C51/80L51 Interface
8.2.2.2.2 DAC8560 to Microwire Interface
Figure 74 shows an interface between the DAC8560 and any Microwire compatible device. Serial data is shifted
out on the falling edge of the serial clock and is clocked into the DAC8560 on the rising edge of the SK signal.
30
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MicrowireTM
CS
DAC8560(1)
SYNC
SCLK
DIN
SK
SO
NOTE: (1) Additional pins omitted for clarity.
Figure 74. DAC8560 to Microwire Interface
8.2.2.2.3 DAC8560 to 68HC11 Interface
Figure 75 shows a serial interface between the DAC8560 and the 68HC11 microcontroller. SCK of the 68HC11
drives the SCLK of the DAC8560, while the MOSI output drives the serial data line of the DAC. The SYNC signal
is derived from a port line (PC7), similar to the 8051 diagram.
DAC8560 (1)
SYNC
68HC11(1)
PC7
SCK
SCLK
DIN
MOSI
NOTE: (1) Additional pins omitted for clarity.
Figure 75. DAC8560 to 68HC11 Interface
Configure the 68HC11 so that its CPOL bit is 0, and its CPHA bit is 1. This configuration causes data appearing
on the MOSI output to be valid on the falling edge of SCK. When data is being transmitted to the DAC, the SYNC
line is held LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data is transmitted MSB first.) In order to load data to the DAC8560, PC7
is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to
the DAC. PC7 is taken HIGH at the end of this procedure.
8.2.3 Application Curves
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
0
10000 20000 30000 40000 50000 60000
Input Code (Decimal)
D001
Figure 77. Full-Scale Step Response
Figure 76. Output Voltage Error vs Input Code
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9 Power Supply Recommendations
The DAC8560 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to VDD
must be well-regulated and low-noise. Switching power supplies and DC-DC converters often have high-
frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-
frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the
power connections and analog output. In order to further minimize noise from the power supply, TI strongly
recommends a 1-μF to 10-μF capacitor and 0.1-μF bypass capacitor. The current consumption on the VDD pin,
the short-circuit current limit, and the load current for the device is listed in Electrical Characteristics. The power
supply must meet the aforementioned current requirements.
10 Layout
10.1 Layout Guidelines
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The DAC8560 offers single-supply operation, and it often is used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output.
As a result of the single ground pin of the DAC8560, all return currents, including digital and analog return
currents for the DAC, must flow through a single point. Ideally, connect GND directly to an analog ground plane.
This plane would be separate from the ground connection for the digital components until they were connected at
the power-entry point of the system.
The power applied to VDD must be well regulated and low noise. Switching power supplies and DC-DC
converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, connect VDD to a power-supply plane or trace that is separate from the connection
for digital logic until they are connected at the power-entry point. In addition, a 1-μF to 10-μF capacitor and 0.1-
μF bypass capacitor are strongly recommended. In some situations, additional bypassing may be required, such
as a 100-μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors – all designed to
essentially low-pass filter the supply, removing the high-frequency noise.
10.2 Layout Example
Figure 78. DAC8560 Layout Example
32
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
CMOS，轨至轨，I/O 运算放大器
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
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33
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC8560IADGKR
DAC8560IADGKRG4
DAC8560IADGKT
DAC8560IBDGKR
DAC8560IBDGKT
DAC8560ICDGKR
DAC8560ICDGKT
DAC8560ICDGKTG4
DAC8560IDDGKR
DAC8560IDDGKT
DAC8560IDDGKTG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
DGK
DGK
DGK
DGK
DGK
DGK
DGK
8
8
8
8
8
8
8
8
8
8
8
2500 RoHS & Green
2500 RoHS & Green
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
D860
D860
D860
D860
D860
D860
D860
D860
D860
D860
D860
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
250
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
RoHS & Green
250
250
RoHS & Green
RoHS & Green
2500 RoHS & Green
250
250
RoHS & Green
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC8560IADGKR
DAC8560IBDGKR
VSSOP
VSSOP
DGK
DGK
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC8560IADGKR
DAC8560IBDGKR
VSSOP
VSSOP
DGK
DGK
8
8
2500
2500
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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