DAC8801IDRBT [TI]
14 位单通道串行接口乘法数模转换器 | DRB | 8 | -40 to 85;
| 型号： | DAC8801IDRBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14 位单通道串行接口乘法数模转换器 | DRB | 8 | -40 to 85 光电二极管 转换器 数模转换器 |
| 文件： | 总23页 (文件大小：1309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLAS403B–NOVEMBER 2004–REVISED FEBRUARY 2007
14-Bit, Serial Input Multiplying Digital-to-Analog Converter
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
14-Bit Monotonic
The DAC8801 multiplying digital-to-analog converter
is designed to operate from a single 2.7-V to 5.5-V
supply.
±1 LSB INL
±0.5 LSB DNL
The applied external reference input voltage VREF
determines the full-scale output current. An internal
Low Noise: 12 nV/√Hz
Low Power: IDD = 2 µA
+2.7 V to +5.5 V Analog Power Supply
feedback resistor (RFB
)
provides temperature
tracking for the full-scale output when combined with
an external I-to-V precision amplifier.
2 mA Full-Scale Current ±20%
with VREF = 10 V
A serial-data interface offers high-speed, three-wire
microcontroller compatible inputs using data-in (SDI),
clock (CLK), and chip select (CS).
•
•
•
•
•
•
•
0.5 µs Settling Time
4-Quadrant Multiplying Reference-Input
Reference Bandwidth: 10 MHz
±10 V Reference Input
On power-up, the DAC register is filled with zeroes,
and the DAC output is at zero scale.
The DAC8801 is packaged in space-saving 8-lead
SON and MSOP packages.
Reference Dynamics: -105 THD
3-Wire 50-MHz Serial Interface
Tiny 8-Lead 3 x 3 mm SON and 3 x 5 mm
MSOP Packages
•
Industry-Standard Pin Configuration
APPLICATIONS
14
•
•
•
•
Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration
Industrial Control PLCs
14
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
DAC8801
www.ti.com
SLAS403B–NOVEMBER 2004–REVISED FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
(1)
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
DIFFERENTIAL
SPECIFIED
TEMPERATURE
RANGE
TRANSPORT
MEDIA,
QUANTITY
ACCURACY NONLINEARITY PACKAGE-
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
PRODUCT
(LSB)
(LSB)
LEAD
Tape and Reel,
250
DAC8801
±1
±0.5
MSOP-8
DGK
DGK
DRB
DRB
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
F01
F01
E01
E01
DAC8801IDGKT
DAC8801IDGKR
DAC8801IDRBT
DAC8801IDRBR
Tape and Reel,
2500
DAC8801
DAC8801
DAC8801
±1
±1
±1
±0.5
±0.5
±0.5
MSOP-8
SON-8
SON-8
Tape and Reel,
250
Tape and Reel,
2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
DAC8801
–0.3 to 7
UNITS
V
VDD to GND
Digital Input voltage to GND
VOUT to GND
–0.3 to +VDD + 0.3
–0.3 to +VDD + 0.3
–40 to 105
–25 to 25
–65 to 150
125
V
V
Operating temperature range
VREF, RFB to GND
°C
V
Storage temperature range
Junction temperature range (TJ max)
Power dissipation
°C
°C
W
(TJ max – TA) / RΘJA
55
Thermal impedance, RΘJA
°C/W
°C
°C
V
Lead temperature, soldering
Lead temperature, soldering
ESD rating, HBM
Vapor phase (60s)
Infrared (15s)
215
220
4000
ESD rating, CDM
1000
V
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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SLAS403B–NOVEMBER 2004–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V; IOUT = Virtual GND, GND = 0 V; VREF = 10 V; TA = Full Operating Temperature; all specifications -40°C
to 85°C unless otherwise noted.
DAC8801
PARAMETER
CONDITIONS
UNITS
MIN
TYP MAX
STATIC PERFORMANCE
Resolution
14
Bits
LSB
LSB
nA
Relative accuracy
±1
±0.5
10
Differential nonlinearity
Output leakage current
Output leakage current
Full-scale gain error
Data = 0000h, TA = 25°C
Data = 0000h, TA = TMAX
10
nA
All ones loaded to DAC register
±1
±3
±4
mV
ppm of
FSR/°C
Full-scale tempco
OUTPUT CHARACTERISTICS(1)
Output current
2
mA
pF
Output capacitance
REFERENCE INPUT(1)
VREF Range
Code dependent
50
–15
15
V
Input resistance
5
5
kΩ
pF
Input capacitance
LOGIC INPUTS AND OUTPUT(1)
VDD = 2.7V
VDD = 5V
0.6
0.8
V
V
VIL
VIH
Input low voltage
Input high voltage
VDD = 2.7V
VDD = 5V
2.1
2.4
V
V
IIL
Input leakage current
Input capacitance
10
10
µA
pF
CIL
INTERFACE TIMING
fCLK
Clock input frequency
50
MHz
ns
t(CH)
t(CL)
Clock pulse width high
Clock pulse width low
CS to Clock setup time
Clock to CS hold time
Data setup time
10
10
0
ns
t(CSS)
t(CSH)
t(DS)
t(DH)
ns
10
5
ns
ns
Data hold time
10
ns
POWER REQUIREMENTS
VDD
2.7
5.5
5
V
IDD (normal operation)
Logic inputs = 0 V
µA
µA
µA
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
3
1
5
2.5
AC CHARACTERISTICS(1)(2)
To ±0.1% of full-scale, Data = 0000h to 3FFFh to 0000h
To ±0.006% of full-scale, Data = 0000h to 3FFFh to 0000h
VREF = 5 VPP, Data = 3FFFh
0.3
0.5
10
2
ts
Output voltage settling time
µs
Reference multiplying BW
DAC glitch impulse
Feedthrough error
MHz
nV/s
dB
VREF = 0 V, Data = 3FFFh to 2000h
VREF = 100 mVRMS, 100kHz, Data = 0000h
CS = 1 and fCLK = 1MHz
–70
2
Digital feedthrough
nV/s
(1) Specified by design and characterization, not production tested.
(2) All ac characteristic tests are performed in a closed-loop system using the THS4011 I-to-V converter amplifier.
3
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SLAS403B–NOVEMBER 2004–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V; IOUT = Virtual GND, GND = 0 V; VREF = 10 V; TA = Full Operating Temperature; all specifications -40°C
to 85°C unless otherwise noted.
DAC8801
PARAMETER
CONDITIONS
UNITS
MIN
TYP MAX
Total harmonic distortion
Output spot noise voltage
VREF = 5 VPP, Data = 3FFFh, f = 1 kHz
f = 1 kHz, BW = 1 Hz
–105
12
dB
nV/√Hz
PIN ASSIGNMENTS
DGK PACKAGE
(TOP VIEW)
DRB PACKAGE
(TOP VIEW)
8
7
6
5
CS
CLK
SDI
1
8
7
CLK
SDI
1
2
CS
V
DD
2
V
DD
3
4
R
FB
GND
R
FB
3
4
6
5
GND
I
V
REF
OUT
V
REF
I
OUT
TERMINAL FUNCTIONS
PIN
1
NAME
CLK
SDI
DESCRIPTION
Clock input, positive edge triggered clocks data into shift register
2
Serial register input, data loads directly into the shift register MSB first. Extra leading bits are ignored.
Internal matching feedback resistor. Connect to external op amp output.
DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance versus code.
DAC current output. Connects to inverting terminal of external precision I to V op amp.
Analog and digital ground
3
RFB
4
VREF
IOUT
GND
VDD
5
6
7
Posiitve power supply input. Specified range of operation 2.7 V to 5.5 V.
Chip select, active low digital input. Transfers shift register data to DAC register on rising edge. See Table 1 for
operation.
8
CS
4
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SLAS403B–NOVEMBER 2004–REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS: VDD = 5 V
At TA = 25°C, +VDD = 5 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
−
−
−
−
−
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 1.
Figure 2.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 3.
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 5.
Figure 6.
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SLAS403B–NOVEMBER 2004–REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, +VDD = 5 V, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE BANDWIDTH
1.6
6
0
6
0x3FFF
−
0x2000
0x1000
0x0800
0x0400
1.4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
12
18
24
30
36
42
48
54
60
66
72
78
84
90
96
VDD = +5.0V
1.2
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
1.0
0.8
0.6
0.4
0x0002
0x0001
0.2
0x0000
−
−
−
102
108
114
1
VDD = +2.7V
0
0
100
1k
10k
100k
1M
10M
100M
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Logic Input Voltage (V)
Bandwidth (Hz)
Figure 7.
Figure 8.
DAC SETTLING TIME
DAC GLITCH
Voltage Output Settling
Code: 3FFFh to 2000h
Trigger Pulse
Trigger Pulse
µ
Time (0.1 s/div)
µ
Time (0.2 s/div)
Figure 9.
Figure 10.
6
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SLAS403B–NOVEMBER 2004–REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS: VDD = 2.7 V
At TA = 25°C, +VDD = 2.7 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 11.
Figure 12.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 13.
Figure 14.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
−
−
−
−
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
0
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 15.
Figure 16.
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THEORY OF OPERATION
The DAC8801 is a single channel current output, 16-bit digital-to-analog converter (DAC). The architecture,
illustrated in Figure 17, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to GND or the IOUT terminal. The IOUT terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input VREF that determines the DAC full-scale current. The R-2R ladder presents a code independent load
impedance to the external reference of 5 kΩ± 25%. The external reference voltage can vary in a range of -10 V
to 10 V, thus providing bipolar IOUT current operation. By using an external I/V converter and the DAC8801 RFB
resistor, output voltage ranges of -VREF to VREF can be generated.
When using an external I/V converter and the DAC8801 RFB resistor, the DAC output voltage is given by
Equation 1:
CODE
16384
VOUT + −VREF
(1)
R
R
R
V
REF
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
R
FB
I
OUT
GND
Figure 17. Equivalent R-2R DAC Circuit
Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output
impedance as seen looking into the IOUT terminal changes versus code, the external I/V converter noise gain will
also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such
that the amplifier offset is not modulated by the DAC IOUT terminal impedance change. External op amps with
large offset voltages can produce INL errors in the transfer function of the DAC8801 due to offset modulation
versus DAC code. For best linearity performance of the DAC8801, an op amp (OPA277) as shown in Figure 18
is recommended. This circuit allows VREF to swing from -10V to +10V.
V
DD
U1
V
DD
R
FB
15 V
U2
V+
_
DAC8801
I
V
REF
OUT
OPA277
V
O
+
GND
V−
−15 V
Figure 18. Voltage Output Configuration
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SDI
SLAS403B–NOVEMBER 2004–REVISED FEBRUARY 2007
D13 D12 D11 D10 D9
D8 D7
D6
D1 D0
CLK
t
(DS)
t
(CH)
t
t
(CL)
(DH)
t
t
(CSH)
(CSS)
CS
Figure 19. DAC8801 Timing Diagram
Table 1. Control Logic Truth Table(1)
CLK
X
CS
H
Serial Shift Register
DAC Register
No effect
Latched
↑+
X
L
Shift register data advanced one bit
No effect
Latched
H
Latched
X
↑+
Shift register data transferred to DAC register
New data loaded from serial register
(1) ↑+ Positive logic transition; X = Don't care
Table 1. Serial Input Register Data Format, Data Loaded MSB First
B13
B0
Bit
Data(1)
(MSB)
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
(LSB)
D13
D0
(1) A full 16-bit data word can be loaded into the serial register, but only the last 14 bits are transferred to the DAC register when CS goes
high.
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APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design as shown in Figure 20, the DAC8801 current output (IOUT) and the connection
with the inverting node of the op amp should be as short as possible and according to correct PCB layout
design. For each code change there is a step function. If the GBP of the op amp is limited and parasitic
capacitance is excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a
compensation capacitor C1 (4 pF to 20 pF typ) can be added to the design as shown in Figure 20.
V
DD
V
DD
R
FB
C1
_
+
I
U1
V
REF
V
REF
OUT
V
OUT
U2
GND
Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor
Positive Voltage Output Circuit
As shown in Figure 21, in order to generate a positive voltage output, a negative reference is input to the
DAC8801. This design is suggested instead of using an inverting amp to invert the output due to tolerance
errors of the resistor. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual
ground and a -2.5 V input to the DAC8801 with an op amp.
V
DD
+2.5V Reference
V
IN
V
OUT
GND
R
FB
V
DD
C1
OPA277
V
−
+
REF
DAC8801
GND
−
+
−2.5 V
I
OUT
V
OUT
OPA277
0 3 V
3 +2.5 V
OUT
Figure 21. Positive Voltage Output Circuit
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APPLICATION INFORMATION (continued)
Bipolar Output Circuit
The DAC8801, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 22,
external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A
4-quadrant multiplying circuit is implemented by using a 2.5-V offset of the reference voltage to bias U4.
According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full scale produces
output voltages of VOUT = -2.5 V to VOUT = 2.5 V.
D
+ ǒ
Ǔ
VOUT
* 1 VREF
16, 384
(2)
10 kW
10 kW
V
DD
5 kW
C2
−
RFB
V
V
OUT
DD
+
C1
U4
OPA277
V
REF
DAC8801
GND
+2.5 V
(+10 V)
−
I
−2.5 V 3 V
(−10 V 3 V
3 +2.5 V
3 +10 V)
OUT
OUT
+
U2
OPA277
OUT
Figure 22. Bipolar Output Circuit
Programmable Current Source Circuit
A DAC8801 can be integrated into the circuit in Figure 23 to implement an improved Howland current pump for
precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of
the circuit. A application of this circuit includes a 4-mA to 20-mA current transmitter with up to a 500-Ω load.
With a matched resistor network, the load current of the circuit is shown in Equation 3:
(
)
R2 ) R3 ń R1
IL +
VREF D
R3
(3)
R24
15 kW
C1
10 pF
R14
150 kW
R34
50 W
U2
OPA277
V
DD
−
+
V
R
V
OUT
DD
FB
U2
R2
15 kW
R1
150 kW
OPA277
R3
V
U1
DAC8801
REF
V
REF
50 W
−
I
OUT
+
I
L
GND
LOAD
Figure 23. Programmable Bidirectional Current Source Circuit
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APPLICATION INFORMATION (continued)
The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can
drive ±20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination
of the circuit compensation capacitor C1 in the circuit is not suggested because of the change in the output
impedance ZO, according to Equation 4:
R1ȀR3(R1 ) R2)
R1(R2Ȁ ) R3Ȁ) * R1Ȁ(R2 ) R3)
ZO +
(4)
As shown in Equation 4, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation
problems are eliminated. The value of C1 can be determined for critical applications; however, for most
applications a value of several pF is suggested.
Cross-Reference
The DAC8801 has an industry-standard pinout. Table 2 provides the cross-reference information.
Table 2. Cross Reference
SPECIFIED
INL
(LSB)
DNL
(LSB)
TEMPERATURE
RANGE
PACKAGE
DESCIPTION
PACKAGE
OPTION
CROSS
REFERENCE
PRODUCT
DAC8801IDGK
DAC8801IDRB
±1
±1
±1
±1
-40°C to +85°C
-40°C to +85°C
8-Lead MicroSOIC
MSOP-8
SON-8
ADS5553CRM
N/A
8-Lead Small Outline
Table 3. DAC8801 Revision History
Revision
Date
Description
A
12/04 Removed the "Product Preview" label.
Added information to the Features.
Added Output leakage current Data = 0000h, TA = TMAX in the Electrical Characteristics table.
Added Input high voltage for 2.7 V and 5 V in the Electrical Characteristics table.
Changed the values of the Power Requirements and the AC characteristics in the Electrical Characteristics table.
10/06 Changed the ESD rating, HBM from 1500 to 4000 in the Absolute Maximum Ratings.
Revised Figure 8.
B
12
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC8801IDGKR
DAC8801IDGKT
DAC8801IDGKTG4
DAC8801IDRBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
SON
DGK
DGK
DGK
DRB
8
8
8
8
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F01
F01
F01
E01
250
250
250
RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC8801IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSSOP DGK
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
DAC8801IDGKR
8
2500
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
1.5 0.1
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
0.37
0.25
8X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
(0.65)
0.05
0.5
0.3
8X
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31)
1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
(
0.2) VIA
(0.23)
TYP
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
4X
(0.725)
8
1
8X (0.31)
(2.674)
(1.55)
SYMM
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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Copyright © 2021, Texas Instruments Incorporated
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