DAC8803IDBTG4 [TI]
14-Bit, Quad Channel, Serial Interface, Multiplying Digital-to-Analog Converter 28-SSOP -40 to 85;
| 型号： | DAC8803IDBTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-Bit, Quad Channel, Serial Interface, Multiplying Digital-to-Analog Converter 28-SSOP -40 to 85 光电二极管 转换器 |
| 文件： | 总26页 (文件大小：3061K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC8803
www.ti.com
SBAS340C–JANUARY 2005–REVISED FEBRUARY 2006
Quad, Serial Input 14-Bit Multiplying Digital-to-Analog Converter
FEATURES
DESCRIPTION
•
•
•
Relative Accuracy: 1 LSB Max
The DAC8803 is a quad, 14-bit, current-output
digital-to-analog converter (DAC) designed to operate
from a single +2.7-V to 5-V supply.
Differential Nonlinearity: 1 LSB Max
2-mA Full-Scale Current
with VREF = ±10 V
0.5-µs Settling Time
Midscale or Zero-Scale Reset
The applied external reference input voltage VREF
determines the full-scale output current. An internal
feedback resistor (RFB) provides temperature tracking
for the full-scale output when combined with an
external I-to-V precision amplifier.
•
•
•
Four Separate 4Q Multiplying Reference
Inputs
A
doubled buffered serial data interface offers
•
•
•
Reference Bandwidth: 10 MHz
high-speed, 3-wire, SPI and microcontroller
compatible inputs using serial data in (SDI), clock
(CLK), and a chip select (CS). In addition, a serial
data out pin (SDO) allows for daisy chaining when
Reference Dynamics: -105 dB THD
SPI™-Compatible 3-Wire Interface:
50-MHz
•
•
•
•
•
Double Buffered Registers Enable
Simultaneous Multichannel Update
Internal Power-On Reset
multiple
packages
are
used.
A
common
level-sensitive load DAC strobe (LDAC) input allows
simultaneous update of all DAC outputs from
previously loaded input registers. Additionally, an
internal power-on reset forces the output voltage to
zero at system turn on. An MSB pin allows system
reset assertion (RS) to force all registers to zero code
when MSB = 0, or to half-scale code when MSB = 1.
Compact SSOP-28 Package
Industry-Standard Pin Configuration
APPLICATIONS
•
•
•
Automatic Test Equipment
Instrumentation
Digitally-Controlled Calibration
The DAC8803 is packaged in an SSOP package.
A
B C D
V
REF
D0
D1
R A
FB
SDO
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
A0
Input
Register
DAC A
Register
DAC A
DAC B
DAC C
DAC D
I
A
OUT
R
R
R
R
R
R
A
A
GND
R
B
FB
Input
Register
DAC B
Register
14
I
C
OUT
A
B
GND
R
C
FB
A1
Input
Register
DAC C
Register
I
C
OUT
SDI
A
C
GND
CLK
EN
CS
R
D
FB
Input
Register
DAC D
Register
I
D
OUT
R
R
A
DAC
B
C
D
A
D
GND
2:4
Power-On
Reset
A
F
GND
Decode
DGND
RS
MSB
LDAC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
DAC8803
www.ti.com
SBAS340C–JANUARY 2005–REVISED FEBRUARY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFIED
TEMPERATURE
RANGE
TRANSPORT
MEDIA
QUANTITY
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
PRODUCT
DAC8803IDBT
DAC8803IDBR
Tape and Reel, 250
Tape and Reel, 2500
DAC8803
±1
±1
-40°C to +85°C
SSOP-28
DB
(1) For the most current specifications and package information, see the Package Option Addendum at the end of this document, or see the
TI website at www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
DAC8803
-0.3 to +8
-18 to +18
-0.3 to +8
-0.3 to VDD + 0.3
-0.3 to +0.3
±50
UNIT
V
VDD to GND
VREF to GND
V
Logic inputs and output to GND
V(IOUT) to GND
V
V
AGNDX to DGND
V
Input current to any pin except supplies
Package power dissipation
mA
W
(TJmax - TA)/θJA
100
Thermal resistance, θJA
28-Lead shrink surface-mount (RS-28)
°C/W
°C
°C
°C
Maximum junction temperature (TJmax)
Operating temperature range, Model A
Storage temperature range
150
-40 to +85
-65 to +150
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
2
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SBAS340C–JANUARY 2005–REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS
VDD = +2.7 V to +5.5 V; IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range,
unless otherwise noted.
DAC8803
PARAMETER
STATIC PERFORMANCE(1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
14
±1
±1
10
20
±3
Bits
LSB
LSB
nA
Relative accuracy
Differential nonlinearity
Output leakage current
DNL
IOUT
IOUT
X
X
Data = 0000h, TA = 25°C
Data = 0000h, TA = TA max
Data = 3FFFh
nA
Full-scale gain error
Full-scale tempco(2)
Feedback resistor
REFERENCE INPUT
VREFX Range
GFSE
±0.75
1
mV
TCVFS
ppm/°C
kΩ
RFB
X
VDD = 5 V
VREF
RREF
RREF
CREF
X
X
X
X
-15
4
15
6
V
Input resistance
5
1
5
kΩ
%
Input resistance match
Input capacitance(2)
ANALOG OUTPUT
Output current
Output capacitance(2)
LOGIC INPUTS AND OUTPUT
Input low voltage
Channel-to-channel
pF
IOUT
X
X
Data = 3FFFh
1.6
2.5
mA
pF
COUT
Code-dependent
50
VIL
VIL
VDD = +2.7 V
VDD = +5 V
VDD = +2.7 V
VDD = +5 V
0.6
0.8
V
V
Input high voltage
VIH
VIH
IIL
2.1
2.4
V
V
Input leakage current
Input capacitance(2)
1
10
µA
pF
V
CIL
VOL
VOH
Logic output low voltage
Logic output high voltage
IOL = 1.6 mA
IOH = 100 µA
0.4
4
V
INTERFACE TIMING(2) (3)
,
Clock width high
Clock width low
CS to Clock setup
Clock to CS hold
Clock to SDO prop delay
Load DAC pulsewidth
Data setup
tCH
tCL
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCSS
tCSH
tPD
25
2
20
tLDAC
tDS
25
20
20
5
Data hold
tDH
Load setup
tLDS
tLDH
Load hold
25
(1) All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter
amplifier. The DAC8803 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C.
(2) These parameters are specified by design and not subject to production testing.
(3) All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
3
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SBAS340C–JANUARY 2005–REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS (continued)
VDD = +2.7 V to +5.5 V; IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range,
unless otherwise noted.
DAC8803
PARAMETER
SUPPLY CHARACTERISTICS
Power supply range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
VDD RANGE
IDD
2.7
5.5
5
V
Logic inputs = 0 V,
VDD = +4.5 V to +5.5 V
Positive supply current
2
1
µA
Logic inputs = 0 V,
VDD = +2.7 V to +3.6 V
IDD
2.5
µA
Power dissipation
PDISS
PSS
Logic inputs = 0 V
0.025
0.006
mW
%
Power supply sensitivity
AC CHARACTERISTICS(4)
∆VDD = ±5%
To ±0.1% of full-scale,
Data = 0000h to 3FFFh to 0000h
Output voltage settling time
ts
ts
0.3
0.5
µs
µs
To ±0.006% of full-scale,
Data = 0000h to 3FFFh to 0000h
Reference multiplying BW
DAC glitch impulse
BW -3 dB VREFX = 100 mVRMS, Data = 3FFFh, CFB = 3 pF
10
1
MHz
nV/s
dB
Q
VREFX = 10 V, Data = 1FFFh to 2000h to 1FFFh
Data = 0000h, VREFX = 100 mVRMS, f = 100 kHz
Feedthrough error
VOUTX/VREF
X
-70
Data = 0000h, VREFB = 100 mVRMS
Adjacent channel, f = 100 kHz
,
Crosstalk error
VOUTA/VREF
B
-100
dB
Digital feedthrough
Q
THD
en
CS = 1 and fCLK = 1 MHz
1
-105
12
nV/s
dB
Total harmonic distortion
Output spot noise voltage
VREF = 5 VPP, Data = 3FFFh, f = 1 kHz
f = 1 kHz, BW = 1 Hz
nV/√Hz
(4) All ac characteristic tests are performed in a closed-loop system using a THS4011 I-to-V converter amplifier.
4
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SBAS340C–JANUARY 2005–REVISED FEBRUARY 2006
PIN CONFIGURATIONS
DAC8803
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
A
A
D
GND
GND
2
I
A
OUT
I
D
OUT
3
V
A
REF
V
REF
D
4
R
A
FB
R
D
FB
5
MSB
DGND
(1)
6
RS
V
SS
7
V
A
GND
F
DD
8
CS
CLK
SDI
LDAC
9
SDO
(1)
10
11
12
13
14
NC
R
B
B
B
B
R
C
FB
FB
V
V
REF
C
REF
I
I
C
OUT
OUT
A
GND
A
GND
C
Note (1): No internal connection
PIN DESCRIPTION
PIN
NAME
AGNDA, AGNDB, AGNDC, AGND
IOUTA, IOUTB, IOUTC, IOUT
DESCRIPTION
1, 14, 15, 28
2, 13, 16, 27
D
DAC A, B, C, D Analog ground
DAC A, B, C, D Current output
D
DAC A, B, C, D Reference voltage input terminal. Establishes DAC A, B, C, D full-scale
output voltage. Can be tied to VDD
3, 12, 17, 26
VREFA, VREFB, VREFC, VREFD
.
4, 11, 18, 25
5
RFBA, RFBB, RFBC, RFBD,
MSB
Establish voltage output for DAC A, B, C, D by connecting to external amplifier output.
MSB Bit set during a reset pulse (RS) or at system power-on if tied to ground or VDD
.
Reset pin, active low. Input register and DAC registers are set to all zeros or half-scale
code (2000h) determined by the voltage on the MSB pin. Register data = 2000h when
MSB = 1.
6
7
8
RS
VDD
CS
Positive power-supply input. Specified range of operation +2.7 V to +5.5 V.
Chip select; active low input. Disables shift register loading when high. Transfers shift
register data to input register when CS/LDAC goes high. Does not affect LDAC
operation.
9
CLK
SDI
NC
Clock input; positive edge triggered clocks data into shift register
Serial data input; data loads directly into the shift register.
Not connected; leave floating
10
19
Serial data output; input data load directly into shift register. Data appears at SDO, 17
clock pulses after input at the SDI pin.
20
21
SDO
Load DAC register strobe; level sensitive active low. Transfers all input register data to
the DAC registers. Asynchronous active low input. See Table 1 for operation.
LDAC
22
23
24
AGND
F
High current analog force ground.
No internal connection.
Digital ground.
VSS
DGND
5
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SBAS340C–JANUARY 2005–REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
Channel A
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
TA = +25 C
_
TA = +25 C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 1.
Figure 2.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
_
40
TA
=
C
−
_
40
TA
=
C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 3.
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
_
TA = +85 C
TA = +85 C
−
0.2
−
0.4
−
0.6
−
0.8
−
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Digital Input Code
Figure 5.
Figure 6.
6
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SBAS340C–JANUARY 2005–REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
Channel B
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
_
TA = +25 C
_
TA = +25 C
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 7.
Figure 8.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
_
40
TA
=
C
−
_
40
TA
=
C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 9.
Figure 10.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
_
TA = +85 C
TA = +85 C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Digital Input Code
Figure 11.
Figure 12.
7
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SBAS340C–JANUARY 2005–REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
Channel C
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
_
TA = +25 C
_
TA = +25 C
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 13.
Figure 14.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
_
40
TA
=
C
−
_
TA
=
40
C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 15.
Figure 16.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
_
TA = +85 C
TA = +85 C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Digital Input Code
Figure 17.
Figure 18.
8
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SBAS340C–JANUARY 2005–REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
Channel D
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
_
_
TA = +25 C
TA = +25 C
0.8
0.6
0.4
0.2
0
−
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
−
−
−
−
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Digital Input Code
Figure 19.
Figure 20.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
_
40
TA
=
C
−
_
40
TA
=
C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 21.
Figure 22.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
TA = +85 C
_
TA = +85 C
−
−
−
−
−
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Digital Input Code
Figure 23.
Figure 24.
9
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TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE MULTIPLYING BANDWIDTH
6
0
6
180
160
0x3FFF
−
0x2000
0x1000
0x0800
0x0400
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
12
18
24
30
36
42
48
54
60
66
72
78
84
90
96
VDD = +5.0V
140
0x0200
120
100
80
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
60
0x0002
0x0001
40
VDD = +2.7V
20
0
0x0000
100k
−
−
−
102
108
114
1
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Logic Input Voltage (V)
0
100
1k
10k
1M
10M
100M
Bandwidth (Hz)
Figure 25.
Figure 26.
DAC GLITCH
DAC SETTLING TIME
Voltage Output Settling
Code: 1FFFh to 2000h
Trigger Pulse
LDAC Pulse
µ
Time (0.1 s/div)
µ
Time (0.2 s/div)
Figure 27.
Figure 28.
IDD vs TEMPERATURE
ENDPOINT ERROR vs TEMPERATURE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
2
1
0
DAC C
DAC B
DAC D
5.0V
2.7V
DAC A
−
1
2
3
−
−
−
−
20
−
−
20
40
0
20
40
60
80
100
40
0
20
40
60
80
100
_
Temperature ( C)
_
Temperature ( C)
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS: VDD = +2.7 V
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
Channel A
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
_
TA = +25 C
_
TA = +25 C
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 31.
Figure 32.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
_
TA
=
40
C
−
_
40
TA
=
C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 33.
Figure 34.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
TA = +85 C
_
TA = +85 C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Digital Input Code
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
Channel B
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
_
TA = +25 C
_
TA = +25 C
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 37.
Figure 38.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
_
TA
=
40
C
−
_
TA
=
40
C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 39.
Figure 40.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
TA = +85 C
_
TA = +85 C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Digital Input Code
Figure 41.
Figure 42.
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TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
Channel C
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
_
TA = +25 C
_
TA = +25 C
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 43.
Figure 44.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
_
40
TA
=
C
−
_
TA
=
40
C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 45.
Figure 46.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
TA = +85 C
_
TA = +85 C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Digital Input Code
Figure 47.
Figure 48.
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TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
Channel D
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
_
TA = +25 C
_
TA = +25 C
0.8
0.6
0.4
0.2
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 49.
Figure 50.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
−
_
40
−
_
40
TA
=
C
TA
=
C
−
−
−
−
−
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 51.
Figure 52.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
_
TA = +85 C
_
TA = +85 C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Digital Input Code
Digital Input Code
Figure 53.
Figure 54.
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TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
DAC GLITCH
ENDPOINT ERROR vs TEMPERATURE
3
2
1
0
DAC C
DAC B
DAC D
Code: 1FFFh to 2000h
DAC A
−
1
2
3
−
−
LDAC Pulse
µ
Time (0.2 s/div)
−
−
20
40
0
20
40
60
80
100
_
Temperature ( C)
Figure 55.
Figure 56.
TIMING INFORMATION
SDI
A1
A0 D13 D12 D11 D10 D9 D8
D7 D6
D1
D0
CLK
Input REG. LD
t
t
csh
CSS
t
t
dh
t
t
cl
ds
ch
CS
t
lds
t
t
LDAC
pd
LDH
t
SDO
LDAC
Figure 57. DAC8803 Timing Diagram
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THEORY OF OPERATION
CIRCUIT OPERATION
The DAC8803 contains four, 14-bit, current-output, digital-to-analog converters (DACs) respectively. Each DAC
has its own independent multiplying reference input. The DAC8803 uses a 3-wire SPI-compatible serial data
interface, with a configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In
addition, an LDAC strobe enables four channel simultaneous updates for hardware synchronized output voltage
changes.
D/A Converter
The DAC8803 contains four current-steering R-2R ladder DACs. Figure 58 shows a typical equivalent DAC.
Each DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The RFBX pin
is connected to the output of the external amplifier. The IOUTX terminal is connected to the inverting input of the
external amplifier. The AGNDX pin should be Kelvin-connected to the load point in the circuit requiring the full
14-bit accuracy.
The DAC is designed to operate with both negative or positive reference voltages. The VDD power pin is only
used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the
internal 5 kΩ feedback resistor. If users are attempting to measure the value of RFB, power must be applied to
VDD in order to achieve continuity. The DAC output voltage is determined by VREF and the digital data (D)
according to Equation 1:
D
16384
VOUT + *VREF
(1)
Note that the output polarity is opposite to the VREF polarity for dc reference voltages.
V
DD
R
R
R
R
X
V
X
FB
REF
2R
2R
2R
R
5 kW
S2
S1
I
X
OUT
A
F
GND
A
X
GND
From other DACs A
GND
DGND
Digital interface connections omitted for clarity.
Switches S1 and S2 are closed. V must be powered.
DD
Figure 58. Typical Equivalent DAC Channel
The DAC is also designed to accommodate ac reference input signals. The DAC8803 accommodates input
reference voltages in the range of -15 V to +15 V. The reference voltage inputs exhibit a constant nominal input
resistance of 5 kΩ, ±20%. On the other hand, the DAC outputs IOUTA, B, C, D are code-dependent and produce
various output resistances and capacitances.
The choice of external amplifier should take into account the variation in impedance generated by the DAC8803
on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor
(CFB) may be needed to provide a critically damped output response for step changes in reference input
voltages.
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Figure 26 shows the gain versus frequency performance at various attenuation settings using a 3 pF external
feedback capacitor connected across the IOUTX and RFBX terminals. In order to maintain good analog
performance, power supply bypassing of 0.01 µF, in parallel with 1 µF, is recommended. Under these conditions,
clean power supply with low ripple voltage capability should be used. Switching power supplies are usually not
suitable for this application because of the higher ripple voltage and PSS frequency-dependent characteristics. It
is best to derive the DAC8803 5-V supply from the system analog supply voltages. (Do not use the digital 5-V
supply.) See Figure 59.
Analog
15 V
Power
Supply
2R
5 V
R
V
DD
R
R
R
R
X
FB
V
REF
X
2R
2R
2R
R
5 kW
15 V
S2
S1
I
X
OUT
V
CC
A1
A
F
V
GND
OUT
A
X
GND
V
EE
From other DACs A
GND
Load
DGND
Digital interface connections omitted for clarity.
Switches S1 and S2 are closed. V must be powered.
DD
Figure 59. Recommended Kelvin-Sensed Hookup
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V
REF
A B C D
DAC A
DAC B
DAC C
DAC D
CS
EN
CLK
V
DD
R
I
A
A
SDI
D0
FB
14
DAC A
Input
D1
Register
R
R
R
OUT
Register
R
R
D2
D3
A
GND
A
D4
D5
D6
D7
D8
D9
R B
FB
D10
D11
DAC B
Register
Input
Register
I
C
OUT
D12
D13
A0
DAC
2:4
A
GND
B
A
B
C
D
SDO
A1
Decode
R
I
C
C
FB
DAC C
Register
Input
Register
OUT
R
R
A
GND
C
R
I
D
FB
DAC D
Register
Input
Register
D
OUT
R
A D
GND
Set
MSB
Set MSB
Power-
On
Reset
A
GND
F
DGND
MSB
LDAC
RS
Figure 60. System Level Digital Interfacing
SERIAL DATA INTERFACE
The DAC8803 uses a 3-wire (CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8803 is
clocked into the serial input register in a 16-bit data-word format. MSB bits are loaded first. Table 2 defines the
16 data-word bits for the DAC8803.
Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data
setup and data hold time requirements specified in the Interface Timing Specifications. Data can only be clocked
in while the CS chip select pin is active low. For the DAC8803, only the last 16 bits clocked into the serial register
are interrogated when the CS pin returns to the logic high state.
Since most microcontrollers output serial data in 8-bit bytes, two right-justified data bytes can be written to the
DAC8803. Keeping the CS line low between the first and second byte transfers results in a successful serial
register update.
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Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new
data to the target DAC register, determined by the decoding of address bits A1and A0. For the DAC8803,
Table 2 and Table 3 define the characteristics of the software serial interface. Figure 61 shows the equivalent
logic interface for the key digital control pins for the DAC8803.
To Input Register
A
Address
B
CS
Decoder
C
D
EN
Shift Register
CLK
SDI
17th
Clock
SDO
Figure 61. DAC8803 Equivalent Logic Interface
Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If
these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all
input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).
POWER ON RESET
When the VDD power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the
zero-code state or half-scale, depending on the MSB pin voltage. The VDD power supply should have a smooth
positive ramp without drooping in order to have consistent results, especially in the region of VDD = 1.5 V to
2.3 V. The DAC register data stays at zero or half-scale setting until a valid serial register data load takes place.
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and VDD as
shown in Figure 62.
V
DD
250 W
Digital
Inputs
DGND
Figure 62. Equivalent ESD Protection Circuits
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PCB LAYOUT
The DAC8803 is a high-accuracy DAC that can have its performance compromised by grounding and printed
circuit board (PCB) lead trace resistance. The 14-bit DAC8803 with a 10-V full-scale range has an LSB value of
610 µV. The ladder and associated reference and analog ground currents for a given channel can be as high as
2 mA. With this 2 mA current level, a series wiring and connector resistance of only 305 mΩ will cause 1 LSB of
voltage drop. The preferred PCB layout for the DAC8803 is to have all AGNDX pins connected directly to an
analog ground plane at the unit. The non-inverting input of each channel I/V converter should also either connect
directly to the analog ground plane or have an individual sense trace back to the AGNDX pin connection. The
feedback resistor trace to the I/V converter should also be kept short and low resistance to prevent IR drops from
contributing to gain error. This attention to wiring ensures the optimal performance of the DAC8803.
Table 1. Control Logic Truth Table(1)
CS
H
L
CLK
X
LDAC
RS
H
MSB
X
SERIAL SHIFT REGISTER
No effect
INPUT REGISTER
DAC REGISTER
Latched
H
H
H
H
Latched
Latched
Latched
Latched
L
H
X
No effect
Latched
Latched
Latched
L
↑+
H
H
X
Shift register data advanced one bit
No effect
L
H
X
Selected DAC updated
with current SR contents
↑+
L
H
H
X
No effect
Latched
H
H
H
H
H
X
X
X
X
X
L
H
H
H
H
L
X
X
X
0
No effect
No effect
No effect
No effect
No effect
Latched
Transparent
Latched
Latched
↑+
H
Latched
Latched
Latched data = 0000h
Latched data = 2000h
Latched data = 0000h
Latched data = 2000h
H
L
H
(1) ↑+ Positive logic transition; X = Do not care
Table 2. Serial Input Register Data Format, Data Loaded MSB First(1)
Bit
B15
(MSB)
B14
A0
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
D2
B1
D1
B0 (LSB)
D0
Data
A1
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
(1) Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line positive edge returns to
logic high. At this point an internally generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded
DAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8803 shift register are ignored; only the
last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 3. Address Decode
A1
0
A0
0
DAC DECODE
DAC A
0
1
DAC B
1
0
DAC C
1
1
DAC D
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APPLICATION INFORMATION
The DAC8803, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing, as shown in Figure 63.
An additional external op amp A2 is added as a summing amp. In this circuit the first and second amps (A1 and
A2) provide a gain of 2X that widens the output span to 20 V. A 4-quadrant multiplying circuit is implemented by
using a 10-V offset of the reference voltage to bias A2. According to the following circuit transfer equation
(Equation 2), input data (D) from code 0 to full scale produces output voltages of VOUT = -10 V to VOUT = 10 V.
D
8192
+ ǒ
Ǔ
VOUT
*1 VREF
(2)
10 k
10 k
10 V
5 k
A2
OPA277
V
OUT
V
REF
-10 V < V
< +10 V
OUT
V
DD
V
X
R X
FB
REF
I
X
One Channel
DAC8803
OUT
A1
OPA277
A
F
A
X
GND
GND
Digital interface connections omitted for clarity.
Figure 63. Four-Quadrant Multiplying Application Circuit
Cross-Reference
The DAC8803 has an industry-standard pinout. Table 4 provides the cross-reference information.
Table 4. Cross-Reference
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
PACKAGE
OPTION
CROSS-
REFERENCE PART
PRODUCT
INL (LSB) DNL (LSB)
±1 ±1
DAC8803IDB
-40°C to +85°C
28-Lead MicroSOIC
SSOP-28
AD5554BRS
21
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Jun-2008
PACKAGING INFORMATION
Orderable Device
DAC8803IDBR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
28
28
28
28
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DAC8803IDBRG4
DAC8803IDBT
SSOP
SSOP
SSOP
DB
DB
DB
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DAC8803IDBTG4
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
DAC8803IDBR
DAC8803IDBT
SSOP
SSOP
DB
DB
28
28
2000
250
330.0
330.0
16.4
16.4
8.1
8.1
10.4
10.4
2.5
2.5
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC8803IDBR
DAC8803IDBT
SSOP
SSOP
DB
DB
28
28
2000
250
346.0
346.0
346.0
346.0
33.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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