DAC8871SBPWR [TI]

16 位、单通道、串行接口、+/-18V（高电压双极性）输出 DAC | PW | 16 | -40 to 105;


型号：	DAC8871SBPWR
厂家：	TEXAS INSTRUMENTS
描述：	16 位、单通道、串行接口、+/-18V（高电压双极性）输出 DAC \| PW \| 16 \| -40 to 105
文件：	总25页 (文件大小：807K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC8871

www.ti.com ............................................................................................................................................................. SBAS396A–JUNE 2007–REVISED JUNE 2008

16-Bit, Single-Channel, ±18V Output (Unbuffered), Ultra-Low Power, Serial Interface

DIGITAL-TO-ANALOG CONVERTER

FEATURES

DESCRIPTION

2345

•

16-Bit Resolution

The DAC8871 is a 16-bit, single-channel, serial input,

voltage output digital-to-analog converter (DAC). The

output range is determined by the reference voltage,

V_REFHand V_REFL. By properly selecting the reference,

the output can be unipolar or bipolar, and up to ±18V.

The DAC8871 provides excellent linearity (1LSB INL),

low noise, and fast settling (1µs to 1LSB of full scale

output) over the specified temperature range of

–40°C to +105°C. The output is unbuffered, which

reduces the power consumption and the error

introduced by the buffer. This device features a

standard high-speed clock (up to 50MHz), and a 3V

or 5V SPI serial interface to communicate with the

DSP or microprocessors. For optimum performance,

a set of Kelvin connections to external reference are

provided.

•

Output: ±18V for ±18V Reference Input

±18V Supply Operation

•

Very Low Power

High Accuracy INL: 1LSB

Low Noise: 10nV/√Hz

Fast Settling: 1µs to 1LSB

Fast SPI™ Interface: Up To 50MHz

16-Pin TSSOP Package

Selectable Reset to Zero or Midscale

APPLICATIONS

•

Portable Equipment

Automatic Test Equipment

Industrial Process Control

Data Acquisition Systems

Optical Networking

The DAC8871 is available in a TSSOP-16 package.

V_SS

V_CC

V_DD

DGND

V_REFH-S V_REFH-F V_REFL-F V_REFL-S

RSTSEL

RST

Control

V_OUT

DAC

Logic

LDAC

AGND

SCLK

SDI

Input

Serial

DAC

Latch

Data

Interface

DAC8871

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI DSP is a trademark of Texas Instruments.

SPI, QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC8871

SBAS396A–JUNE 2007–REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

MINIMUM

RELATIVE

ACCURACY

(LSB)

DIFFERENTIAL

NONLINEARITY

(LSB)

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

MARKING

PACKAGE-

LEAD

PACKAGE

DESIGNATOR

PRODUCT

DAC8871B

DAC8871

±1

±3

±1

–40°C to +105°C

8871

TSSOP-16

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI

website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range (unless otherwise noted).

DAC8871

–0.3 to +7

UNIT

V_DDto GND

Digital input voltage to GND

AGND to DGND

–0.3 to (V_DD+ 0.3)

–0.3 to +0.3

–0.3 to +39.6

–0.3 to +19.8

+0.3 to –19.8

–0.3 to +39.6

–0.3 to +19.8

–19.8 to +17.5

–40 to +105

–65 to +150

+150

V_CCto V_SS

V_CCto AGND

V_SSto AGND

V_REFHto V_REFL

V_REFHto AGND

V_REFLto AGND

Operating temperature range

Storage temperature range

Maximum junction temperature (T_Jmax)

Power dissipation

°C

C/W

(T_Jmax - T_A)/θ_JA

161.4

Thermal impedance, θ_JA

TSSOP-16

(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

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ELECTRICAL CHARACTERISTICS

All specifications at T_A= T_MINto T_MAX, V_CC= +15V, V_SS= –15V, V_REFH= +10V, V_REFL= –10V, and V_DD= +5V, unless

otherwise noted; specifications subject to change without notice.

DAC8871

PARAMETER

STATIC PERFORMANCE

CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

Bits

LSB

V_REFH= 10V, V_REFL= –5V

V_REFH= 10V, V_REFL= –10V

±0.75

±1

±1.5

±3

DAC8871B

DAC8871

Linearity error

LSB

±1

LSB

Differential linearity error

Gain error

±0.25

±0.5

±0.1

±1

LSB

T_A= +25°C

LSB

Gain drift

ppm/°C

LSB

Bipolar zero error

±4

±2

Bipolar drift

±0.1

±0.5

±0.05

ppm/°C

LSB

Zero code error

Zero code drift

ppm/°C

OUTPUT CHARACTERISTICS

Voltage output

V_REFL

V_REFH

kΩ

Output impedance

6.25

Settling time

Slew rate⁽¹⁾

Digital feedthrough⁽²⁾

To 1LSB of FS, C_L= 15 pF

C_L= 15pF

µs

0.2

V/µs

nV-s

nV/√Hz

LSB

Output noise

T_A= +25°C

Power supply rejection

REFERENCE INPUT

V_REFHRef high input voltage range

V_REFLRef low input voltage range

Ref high input current

Ref low input current

Reference input impedance⁽³⁾

Supplies vary ±10%

+18

–18

V_REFH– 1.25

1.3

kΩ

–1.3

7.5

Code = 0000h

Code = FFFFh

Reference input capacitance

120

DIGITAL INPUTS

V_DD= +5V

V_DD= +3V

V_DD= +5V

V_DD= +3V

DGND

2.6

0.8

0.6

V_DD

±1

V_IL

V_IH

Input low voltage

Input high voltage

2.1

Input current

µA

Input capacitance

(1) Slew Rate is measured from 10% to 90% of transition when the output changes from 0 to full scale.

(2) Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output

does not change; CS is held high, while SCLK and DIN signals are toggled. It is specified with a full-scale code change on the SDI bus

(that is, from all 0s to all 1s and vice versa).

(3) Reference input resistance is code-dependent, with a minimum at 8555h

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ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= T_MINto T_MAX, V_CC= +15V, V_SS= –15V, V_REFH= +10V, V_REFL= –10V, and V_DD= +5V, unless

otherwise noted; specifications subject to change without notice.

DAC8871

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

V_CC

V_SS

V_DD

I_CC

+13.5

–19.8

+2.7

+15

–15

+19.8

–13.5

+5.5

0.01

–0.01

µA

µW

I_SS

–2

I_DD

Power

TEMPERATURE RANGE

Specified performance

–40

+105

°C

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PIN CONFIGURATION (NOT TO SCALE)

PW PACKAGE

TSSOP-16

(TOP VIEW)

V_OUT

V_CC

V_SS

DGND

LDAC

SDI

SCLK

AGND

V_REFH-F

V_REFH-S

V_REFL-S

V_REFL-F

DAC8871

12 CS

RST

RSTSEL

V_DD

TERMINAL FUNCTIONS

TERMINAL

NO. NAME

V_OUT

DESCRIPTION

Analog output of the DAC

V_CC

Positive analog power supply: +15V

Negative analog power supply: –15V

Analog ground

V_SS

AGND

V_REFH-

V_REFHreference input (Force). Connect to external V_REFH

V_REFHreference input (Sense). Connect to external V_REFH

V_REFLreference input (Sense). Connect to external V_REFL

V_REFLreference input (Force). Connect to external V_REFL

Digital power. +5V for 5V interface logic; +3V for 3V logic.

V_REFL-

V_DD

Power-On-Reset select. Determines V_OUTafter power-on reset. If tied to V_DD, the DAC latch is set to mid-scale

after power-on, and V_OUTis (V_REFH– V_REFL)/2. If tied to DGND, the DAC latch is cleared ('0'), and V_OUTis V_REFL

RSTSEL

RST

Reset (active low)

Chip select input (active low). Data are not clocked into SDI unless CS is low.

Serial clock input

SCLK

SDI

Serial data input. Data are latched into input register on the rising edge of SCLK.

Load DAC control input (active low). When LDAC is low, the DAC latch is simultaneously updated with the content

of the input register.

LDAC

DGND

Digital ground

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TIMING DIAGRAMS

t_TD

DAC

Updated

t_Delay

t_SCK

t_WSCK

t_Lag

t_DSCLK

t_Lead

t_WSCK

SCLK

t_SU

t_HO

Bit 15 (MSB)

Bit 14

Bit 13, ..., Bit 1

Bit 0

SDI

LOW

t_RST

LDAC

RST

-- Don’t Care

Figure 1. Case 1—LDAC Tied Low

t_TD

t_Delay

t_SCK

t_WSCK

t_Lag

t_DSCLK

t_WSCK

t_Lead

SCLK

SDI

t_HO

t_SU

Bit 15 (MSB)

Bit 14

Bit 13, ..., Bit 1

Bit 0

t_WLDAC

t_DLADC

HIGH

LDAC

RST

DAC

Updated

t_RST

-- Don’t Care

Figure 2. Case 2—LDAC Active

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TIMING CHARACTERISTICS: V_DD= +5V^{(1) (2)}

At –40°C to +105°C, unless otherwise noted.

PARAMETER

MIN

MAX

UNIT

µs

t_SCK

SCLK period

t_WSCK

t_Delay

t_Lead

t_Lag

SCLK high or low time

Delay from SCLK high to CS low

CS enable lead time

CS enable lag time

t_DSCLK

t_TD

Delay from CS high to SCLK high

CS high between active period

Data setup time (input)

t_SU

t_HO

Data hold time (input)

t_WLDAC

t_DLDAC

t_RST

LDAC width

Delay from CS high to LDAC low

Reset (RST) low

V_DDhigh to CS low (power-up delay)

(1) Assured by design. Not production tested.

(2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter.

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TYPICAL CHARACTERISTICS

At T_A= +25°C, V_DD= +5V, V_CC= +15V, V_SS= –15V, V_REFH= +10V, and V_REFL=–10V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

1.00

0.75

0.50

0.25

T_A= +25°C

V_REFH= 10V

V_REFL= -5V

V_REFH= 10V

V_REFL= -5V

-0.25

-0.50

-0.75

-1.00

-0.25

-0.50

-0.75

-1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 3.

Figure 4.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

1.00

0.75

0.50

0.25

T_A= -40°C

V_REFH= 10V

V_REFL= -5V

T_A= -40°C

V_REFH= 10V

V_REFL= -5V

-0.25

-0.50

-0.75

-1.00

-0.25

-0.50

-0.75

-1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 5.

Figure 6.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

1.00

0.75

0.50

0.25

T_A= +105°C

V_REFH= 10V

V_REFL= -5V

T_A= +105°C

V_REFH= 10V

V_REFL= -5V

-0.25

-0.50

-0.75

-1.00

-0.25

-0.50

-0.75

-1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 7.

Figure 8.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, V_DD= +5V, V_CC= +15V, V_SS= –15V, V_REFH= +10V, and V_REFL=–10V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

1.00

0.75

0.50

0.25

T_A= +25°C

0.50

0.25

-0.25

-0.50

-0.75

-1.00

-1.25

-1.50

-0.25

-0.50

-0.75

-1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 9.

Figure 10.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

1.00

0.75

0.50

0.25

T_A= -40°C

0.50

0.25

-0.25

-0.50

-0.75

-1.00

-1.25

-1.50

-0.25

-0.50

-0.75

-1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 11.

Figure 12.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

1.00

0.75

0.50

0.25

T_A= +105°C

0.50

0.25

-0.25

-0.50

-0.75

-1.00

-1.25

-1.50

-0.25

-0.50

-0.75

-1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 13.

Figure 14.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, V_DD= +5V, V_CC= +15V, V_SS= –15V, V_REFH= +10V, and V_REFL=–10V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

1.00

0.75

0.50

0.25

V_REFH= 10V

V_REFL= 0V

-0.25

-0.50

-0.75

-1.00

-0.25

-0.50

-0.75

-1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 15.

Figure 16.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

2.00

1.50

1.00

0.50

1.00

0.75

0.50

0.25

V_CC= +18V

V_SS= -18V

V_REFH= +18V

V_REFL= -18V

-0.50

-1.00

-1.50

-2.00

-0.25

-0.50

-0.75

-1.00

V_CC= +18V

V_SS= -18V

V_REFH= +18V

V_REFL= -18V

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 17.

Figure 18.

INTEGRAL NONLINEARITY ERROR

vs REFERENCE VOLTAGE

DIFFERENTIAL NONLINEARITY ERROR

vs REFERENCE VOLTAGE

2.0

1.5

1.0

0.8

V_CC= +18V

V_SS= -18V

0.6

1.0

0.4

0.5

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

-0.5

-1.0

-1.5

-2.0

10 11 12 13 14 15 16 17 18

±Reference (V)

Figure 19.

Figure 20.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, V_DD= +5V, V_CC= +15V, V_SS= –15V, V_REFH= +10V, and V_REFL=–10V, unless otherwise noted.

INTEGRAL NONLINEARITY ERROR

vs ANALOG SUPPLY VOLTAGE

DIFFERENTIAL NONLINEARITY ERROR

vs ANALOG SUPPLY VOLTAGE

2.0

1.5

1.0

0.8

0.6

1.0

0.4

0.5

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

-0.5

-1.0

-1.5

-2.0

±Supply (V)

Figure 21.

Figure 22.

GAIN ERROR

vs TEMPERATURE

ZERO-CODE ERROR

vs TEMPERATURE

1.00

0.75

0.50

0.25

0.5

0.4

Bipolar Mode

V_CC= 15V

Unipolar Mode

V_CC= 15V

V_SS= -15V

V_REFH= 10V

V_REFL= 0V

V_SS= -15V

V_REF= ±10V

0.3

V_SS= -15V

V_REFH= 10V

V_REFL= 0V

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.25

-0.50

-0.75

-1.00

V_CC= 15V

V_SS= -15V

V_REF= ±10V

-60 -40 -20

80 100 120 140

-60 -40 -20

80 100 120 140

Temperature (°C)

Figure 23.

Figure 24.

BIPOLAR ZERO ERROR

vs TEMPERATURE

SUPPLY CURRENT

vs DIGITAL INPUT VOLTAGE

-0.25

-0.50

-0.75

2.5

2.0

1.5

1.0

0.5

V_CC= 15V

V_SS= -15V

V_REF= ±10V

Digital Input Code = 8000h

V_DD= +5V

V_DD= +3V

-60 -40 -20

80 100 120 140

Temperature (°C)

Digital Input Voltage (V)

Figure 25.

Figure 26.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, V_DD= +5V, V_CC= +15V, V_SS= –15V, V_REFH= +10V, and V_REFL=–10V, unless otherwise noted.

DUAL REFERENCE CURRENT

vs CODE

V_REFH= +10V, V_REFL= -10V

SINGLE REFERENCE CURRENT

vs CODE

V_REFH= +10V, V_REFL= 0V

800

700

600

500

400

300

200

100

1500

1250

1000

750

500

250

-100

-200

-300

-400

-500

-600

-700

-800

-250

-500

-750

-1000

-1250

-1500

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 27.

Figure 28.

SUPPLY CURRENTS

vs TEMPERATURE

DIGITAL SUPPLY CURRENT

vs DIGITAL SUPPLY VOLTAGE

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

I_DD(V_DD= 5V, V_LOGIC= 5V)

I_DD(V_DD= 3V, V_LOGIC= 3V)

I_CC(V_CC= 15V)

I_SS(V_SS= -15V)

-5

-60 -40 -20

80 100 120 140

2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0

Digital Supply Voltage (V)

Temperature (°C)

Figure 29.

Figure 30.

ANALOG SUPPLY CURRENT

vs ANALOG SUPPLY VOLTAGE

SUPPLY CURRENTS

vs REFERENCE VOLTAGES

0.10

0.08

0.06

0.04

0.02

I_DD(V_DD= +5V)

I_CC

I_SS

I_DD(V_DD= +3V)

I_CC(V_CC= +18V)

-0.02

-0.04

-0.06

-0.08

-0.10

I_SS(V_SS= -18V)

-5

12 14

18 20

±Analog Supply Voltage (V)

±Reference Voltages (V)

Figure 31.

Figure 32.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, V_DD= +5V, V_CC= +15V, V_SS= –15V, V_REFH= +10V, and V_REFL=–10V, unless otherwise noted.

MAJOR CARRY GLITCH

(FALLING)

MAJOR CARRY GLITCH

(RISING)

5V/div

LDAC

V_OUT

200mV/div

Time (0.5ms/div)

Figure 33.

Figure 34.

DAC SETTLING TIME

(FALLING)

DAC SETTLING TIME

(RISING)

5V/div

LDAC

V_OUT

5V/div

Time (0.5ms/div)

Figure 35.

Figure 36.

BROADBAND

NOISE

BW = 10kHz

Code = 8000h

Time (10ms/div)

Figure 37.

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THEORY OF OPERATION

GENERAL DESCRIPTION

The DAC8871 is a 16-bit, single-channel, serial-input, voltage-output DAC. It operates from a dual power supply

ranging from ±13.5V to ±19.8V, and typically consumes 10µA. The output range is from V_REFLto V_REFH. Data are

written to this device in a 16-bit word format, via an SPI serial interface. To ensure a known power-up state, the

DAC8871 is designed with a power-on reset function. After power on, the state of the RSTSEL pin sets the value

of the input register and DAC latch, which sets the output state of the V_OUTpin. Refer to the Power-On Reset and

Hardware Reset section for more details.

Kelvin sense connections for the reference and analog ground are also included.

DIGITAL-TO-ANALOG SECTIONS

The DAC architecture consists of two matched DAC sections and is segmented. A simplified circuit diagram is

shown in Figure 38. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of

these switches connects one of 15 matched resistors to either V_REFHor V_REFL. The remaining 12 bits of the data

word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.

V_OUT

S11

E15

V_REFH-F

V_REFH-S

V_REFL-F

V_REFL-S

12-Bit R-2R Ladder

Four MSBs Decoded into

15 Equal Segments

Figure 38. DAC Architecture

OUTPUT RANGE

The output of the DAC is:

_REFH* V_REFL

65536

V_OUT

Code ) V_REFL

(1)

Where Code is the decimal data word loaded to the DAC latch.

For example, if V_REFHis +10V, and V_REFLis –10V, the range of V_OUTis from –10V (Code = 0000h) to +10V (Code

= FFFFh).

The range of V_REFLis from –18V to (V_REFH– 1.25V), and the range of V_REFHis 0V to +18V. The output from the

DAC8871 can be unipolar (from 0V to +18V) or bipolar by setting the proper V_REFLand V_REFHvalues.

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DAC8871

POWER-ON RESET AND HARDWARE RESET

The DAC8871 has a power-on reset function. When the RSTSEL pin is low (tied to DGND), and after power-on

or a hardware reset signal is applied to the RST pin, the DAC latch is cleared ('0') and the V_OUTpin is set to

negative full-scale. When RSTSEL is high, the DAC latch and V_OUTare set to mid-scale.

SERIAL INTERFACE

The DAC8871 digital interface is a standard 3-wire connection compatible with SPI, QSPI™, Microwire™ and TI

DSP™ interfaces, which can operate at speeds up to 50 Mbits/second. The data transfer is framed by the chip

select (CS) signal. The DAC works as a bus slave. The bus master generates the synchronize clock (SCLK) and

initiates the transmission. When CS is high, the DAC is not accessed, and SCLK and SDI are ignored. The bus

master accesses the DAC by driving CS low. Immediately following the high-to-low transition of CS, the serial

input data on the SDI pin are shifted out from the bus master synchronously on the falling edge of SCLK and

latched on the rising edge of SCLK into the input shift register, MSB first. The low-to-high transition of CS

transfers the content of the input shift register to the input register.

All data registers are 16 bits. It takes 16 SCLK cycles to transfer one data word to the device. To complete a

whole data word, CS must be taken high immediately after the 16th SCLK is clocked in. If more than 16 SCLK

cycles are applied while CS is low, the last 16 bits are transferred into the input register on the rising edge of CS.

However, if CS is not kept low during the entire 16 SCLK cycles, the data are corrupted. In this case, reload the

DAC latch with a new 16-bit word.

The DAC8871 has an LDAC pin that allows the DAC latch to be updated asynchronously by bringing LDAC low

after CS goes high. In this case, LDAC must be kept high while CS is low. If LDAC is permanently tied low, the

DAC latch will be updated immediately after the input register is loaded (caused by the low-to-high transition of

CS).

EXTERNAL AMPLIFIER SELECTION

The output of the DAC8871 is unbuffered. The output impedance is approximately 6.2kΩ. If the applications

require an external buffer amplifier, the selected amplifier must have a low-offset voltage (1LSB = 305µV for

±10V output range), eliminating the need for output offset trims. Input bias current should also be low because

the bias current multiplied by the DAC output impedance (approximately 6.25kΩ) adds to the zero-code error.

Rail-to-rail input and output performance is required. For fast settling, the slew rate of the operational amplifier

should not impede the settling time of the DAC. The output impedance of the DAC is constant and

code-independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as

high as possible. The amplifier should also have a 3dB bandwidth of 1MHz or greater. The amplifier adds

another time constant to the system, thus increasing the settling time of the output. A higher 3dB amplifier

bandwidth results in a shorter effective settling time of the DAC and amplifier combination.

V_SS

V_CC

V_DD

DGND

V_REFH-S V_REFH-F V_REFL-F V_REFL-S

OPA277

RSTSEL

RST

Control

V_OUT

DAC

OPA211

Logic

LDAC

AGND

-V

SCLK

SDI

LOAD

Input

Serial

6.2kW

DAC

Latch

Data

Interface

DAC8871

Figure 39. DAC8871 with External Amplifier

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DAC8871

APPLICATION INFORMATION

REFERENCE INPUT

The DAC full-scale output voltage is determined by the reference voltage, as shown in the Output Range section.

Reference input V_REFHcan be any voltage from 0V to +18V. Reference input V_REFLcan be any voltage from

–18V to (V_REFH– 1.25V). The current into the V_REFHinput and out of V_REFLdepends on the DAC output voltages.

Refer to Figure 27 and Figure 28 for details. The reference input appears as a varying load to the reference. If

the reference can sink or source the required current, a reference buffer is not required. The DAC8871 features a

reference drive (force) and sense connection that minimizes the internal errors caused by the changing reference

current and the circuit impedances. Figure 40 shows a typical reference configuration.

DAC8871

V_REFH

OPA2277

V_REFH-F

V_REFH-S

V_REFL

OPA2277

V_REFL-F

V_REFL-S

Figure 40. Buffered Reference Connection

POWER-SUPPLY BYPASSING

For accurate, high-resolution performance, bypassing the supply pins with a 10µF tantalum capacitor in parallel

with a 0.1µF ceramic capacitor is recommended.

POWER-SUPPLY SEQUENCING

The analog supplies (V_CCand V_SS) must power up before the digital supply (V_DD). All three supplies must power

up before the reference voltages (V_REFHand V_REFL) are applied. Additionally, because the DAC input shift

unintentionally asserted during power-up of the device. It is recommended that the CS pin be connected to V_DD

through a pull-up resistor to avoid improper power-up.

Likewise, the state of the LDAC pin must not be accidentally changed during power-up. It is recommended that

the LDAC pin be connected to V_DDthrough a pull-up resistor, unless it is permanently tied to ground.

To ensure that the ESD protection circuitry of this device is not activated, all other digital pins must be kept at

ground potential until V_DDis applied.

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PACKAGE OPTION ADDENDUM

www.ti.com

14-Oct-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DAC8871SBPW

DAC8871SBPWR

DAC8871SPW

ACTIVE

TSSOP

RoHS & Green

Call TI

Level-2-260C-1 YEAR

-40 to 105

DAC8871

Samples

2000 RoHS & Green

90 RoHS & Green

2000 RoHS & Green

Call TI

DAC8871

DAC8871SPWR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

14-Oct-2022

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC8871SBPWR

DAC8871SPWR

TSSOP

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DAC8871SBPWR

DAC8871SPWR

TSSOP

2000

350.0

43.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

DAC8871SBPW

DAC8871SPW

TSSOP

530

10.2

3600

3.5

Pack Materials-Page 3

PACKAGE OUTLINE

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX AREA

14X 0.65

5.1

4.9

4.55

NOTE 3

0.30

16X

4.5

4.3

NOTE 4

1.2 MAX

0.19

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 -8

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

16X (1.5)

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

16X (1.5)

SYMM

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DAC8871SBPWR [TI]

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