DAC8871SBPW [TI]
16 位、单通道、串行接口、+/-18V(高电压双极性)输出 DAC | PW | 16 | -40 to 105;型号: | DAC8871SBPW |
厂家: | TEXAS INSTRUMENTS |
描述: | 16 位、单通道、串行接口、+/-18V(高电压双极性)输出 DAC | PW | 16 | -40 to 105 光电二极管 转换器 |
文件: | 总25页 (文件大小:807K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DAC8871
www.ti.com ............................................................................................................................................................. SBAS396A–JUNE 2007–REVISED JUNE 2008
16-Bit, Single-Channel, ±18V Output (Unbuffered), Ultra-Low Power, Serial Interface
DIGITAL-TO-ANALOG CONVERTER
1
FEATURES
DESCRIPTION
2345
•
16-Bit Resolution
The DAC8871 is a 16-bit, single-channel, serial input,
voltage output digital-to-analog converter (DAC). The
output range is determined by the reference voltage,
VREFH and VREFL. By properly selecting the reference,
the output can be unipolar or bipolar, and up to ±18V.
The DAC8871 provides excellent linearity (1LSB INL),
low noise, and fast settling (1µs to 1LSB of full scale
output) over the specified temperature range of
–40°C to +105°C. The output is unbuffered, which
reduces the power consumption and the error
introduced by the buffer. This device features a
standard high-speed clock (up to 50MHz), and a 3V
or 5V SPI serial interface to communicate with the
DSP or microprocessors. For optimum performance,
a set of Kelvin connections to external reference are
provided.
•
Output: ±18V for ±18V Reference Input
±18V Supply Operation
•
•
•
•
•
•
•
•
Very Low Power
High Accuracy INL: 1LSB
Low Noise: 10nV/√Hz
Fast Settling: 1µs to 1LSB
Fast SPI™ Interface: Up To 50MHz
16-Pin TSSOP Package
Selectable Reset to Zero or Midscale
APPLICATIONS
•
•
•
•
•
Portable Equipment
Automatic Test Equipment
Industrial Process Control
Data Acquisition Systems
Optical Networking
The DAC8871 is available in a TSSOP-16 package.
VSS
VCC
VDD
DGND
VREFH-S VREFH-F VREFL-F VREFL-S
RSTSEL
RST
Control
VOUT
DAC
Logic
LDAC
AGND
CS
SCLK
SDI
Input
Serial
DAC
Latch
Data
Interface
Register
DAC8871
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
5
TI DSP is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
DAC8871
SBAS396A–JUNE 2007–REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PRODUCT
DAC8871B
DAC8871
±1
±3
±1
±1
–40°C to +105°C
–40°C to +105°C
8871
8871
TSSOP-16
TSSOP-16
PW
PW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
DAC8871
–0.3 to +7
UNIT
V
VDD to GND
Digital input voltage to GND
AGND to DGND
–0.3 to (VDD + 0.3)
–0.3 to +0.3
–0.3 to +39.6
–0.3 to +19.8
+0.3 to –19.8
–0.3 to +39.6
–0.3 to +19.8
–19.8 to +17.5
–40 to +105
–65 to +150
+150
V
V
VCC to VSS
V
VCC to AGND
V
VSS to AGND
V
VREFH to VREFL
V
VREFH to AGND
V
VREFL to AGND
V
Operating temperature range
Storage temperature range
Maximum junction temperature (TJ max)
Power dissipation
°C
°C
°C
W
C/W
(TJ max - TA)/θJA
161.4
Thermal impedance, θJA
TSSOP-16
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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Product Folder Link(s): DAC8871
DAC8871
www.ti.com ............................................................................................................................................................. SBAS396A–JUNE 2007–REVISED JUNE 2008
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, and VDD = +5V, unless
otherwise noted; specifications subject to change without notice.
DAC8871
PARAMETER
STATIC PERFORMANCE
CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
16
Bits
LSB
VREFH = 10V, VREFL = –5V
VREFH = 10V, VREFL = –10V
±0.75
±1
±1
±1.5
±3
DAC8871B
DAC8871
Linearity error
LSB
±1
LSB
Differential linearity error
Gain error
±0.25
±0.5
±0.1
±1
±1
LSB
TA = +25°C
TA = +25°C
TA = +25°C
2
LSB
Gain drift
ppm/°C
LSB
Bipolar zero error
±4
±2
Bipolar drift
±0.1
±0.5
±0.05
ppm/°C
LSB
Zero code error
Zero code drift
ppm/°C
OUTPUT CHARACTERISTICS
Voltage output
VREFL
VREFH
V
kΩ
Output impedance
6.25
1
Settling time
Slew rate(1)
Digital feedthrough(2)
To 1LSB of FS, CL = 15 pF
CL = 15pF
µs
40
0.2
10
V/µs
nV-s
nV/√Hz
LSB
Output noise
TA = +25°C
Power supply rejection
REFERENCE INPUT
VREFH Ref high input voltage range
VREFL Ref low input voltage range
Ref high input current
Ref low input current
Reference input impedance(3)
Supplies vary ±10%
1
0
+18
V
V
–18
VREFH – 1.25
1.3
mA
mA
kΩ
pF
pF
–1.3
7.5
Code = 0000h
Code = FFFFh
75
Reference input capacitance
120
DIGITAL INPUTS
VDD = +5V
VDD = +3V
VDD = +5V
VDD = +3V
DGND
DGND
2.6
0.8
0.6
VDD
VDD
±1
V
V
VIL
VIH
Input low voltage
Input high voltage
V
2.1
V
Input current
µA
pF
Input capacitance
10
(1) Slew Rate is measured from 10% to 90% of transition when the output changes from 0 to full scale.
(2) Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output
does not change; CS is held high, while SCLK and DIN signals are toggled. It is specified with a full-scale code change on the SDI bus
(that is, from all 0s to all 1s and vice versa).
(3) Reference input resistance is code-dependent, with a minimum at 8555h
Copyright © 2007–2008, Texas Instruments Incorporated
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DAC8871
SBAS396A–JUNE 2007–REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, and VDD = +5V, unless
otherwise noted; specifications subject to change without notice.
DAC8871
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VCC
VSS
VDD
ICC
+13.5
–19.8
+2.7
+15
–15
+19.8
–13.5
+5.5
2
V
V
V
0.01
–0.01
3
µA
µA
µA
µW
ISS
–2
IDD
10
Power
15
30
TEMPERATURE RANGE
Specified performance
–40
+105
°C
4
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Product Folder Link(s): DAC8871
DAC8871
www.ti.com ............................................................................................................................................................. SBAS396A–JUNE 2007–REVISED JUNE 2008
PIN CONFIGURATION (NOT TO SCALE)
PW PACKAGE
TSSOP-16
(TOP VIEW)
VOUT
VCC
VSS
DGND
1
2
3
4
5
6
7
8
16
15
14
13
LDAC
SDI
SCLK
AGND
VREFH-F
VREFH-S
VREFL-S
VREFL-F
DAC8871
12 CS
11
10
9
RST
RSTSEL
VDD
TERMINAL FUNCTIONS
TERMINAL
NO. NAME
VOUT
DESCRIPTION
1
2
3
4
5
6
7
8
9
Analog output of the DAC
VCC
Positive analog power supply: +15V
Negative analog power supply: –15V
Analog ground
VSS
AGND
VREFH-
VREFH-
F
S
VREFH reference input (Force). Connect to external VREFH
VREFH reference input (Sense). Connect to external VREFH
VREFL reference input (Sense). Connect to external VREFL
VREFL reference input (Force). Connect to external VREFL
Digital power. +5V for 5V interface logic; +3V for 3V logic.
.
.
VREFL-
VREFL-
VDD
S
.
F
.
Power-On-Reset select. Determines VOUT after power-on reset. If tied to VDD, the DAC latch is set to mid-scale
after power-on, and VOUT is (VREFH – VREFL)/2. If tied to DGND, the DAC latch is cleared ('0'), and VOUT is VREFL
10
RSTSEL
.
11
12
13
14
RST
CS
Reset (active low)
Chip select input (active low). Data are not clocked into SDI unless CS is low.
Serial clock input
SCLK
SDI
Serial data input. Data are latched into input register on the rising edge of SCLK.
Load DAC control input (active low). When LDAC is low, the DAC latch is simultaneously updated with the content
of the input register.
15
16
LDAC
DGND
Digital ground
Copyright © 2007–2008, Texas Instruments Incorporated
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DAC8871
SBAS396A–JUNE 2007–REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
TIMING DIAGRAMS
tTD
CS
DAC
Updated
tDelay
tSCK
tWSCK
tLag
tDSCLK
tLead
tWSCK
SCLK
tSU
tHO
Bit 15 (MSB)
Bit 14
Bit 13, ..., Bit 1
Bit 0
SDI
LOW
tRST
LDAC
RST
-- Don’t Care
Figure 1. Case 1—LDAC Tied Low
tTD
CS
tDelay
tSCK
tWSCK
tLag
tDSCLK
tWSCK
tLead
SCLK
SDI
tHO
tSU
Bit 15 (MSB)
Bit 14
Bit 13, ..., Bit 1
Bit 0
tWLDAC
tDLADC
HIGH
LDAC
RST
DAC
Updated
tRST
-- Don’t Care
Figure 2. Case 2—LDAC Active
6
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Product Folder Link(s): DAC8871
DAC8871
www.ti.com ............................................................................................................................................................. SBAS396A–JUNE 2007–REVISED JUNE 2008
TIMING CHARACTERISTICS: VDD = +5V(1) (2)
At –40°C to +105°C, unless otherwise noted.
PARAMETER
MIN
20
10
10
10
10
10
30
10
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tSCK
SCLK period
tWSCK
tDelay
tLead
tLag
SCLK high or low time
Delay from SCLK high to CS low
CS enable lead time
CS enable lag time
tDSCLK
tTD
Delay from CS high to SCLK high
CS high between active period
Data setup time (input)
tSU
tHO
Data hold time (input)
tWLDAC
tDLDAC
tRST
LDAC width
30
30
10
10
Delay from CS high to LDAC low
Reset (RST) low
VDD high to CS low (power-up delay)
(1) Assured by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
Copyright © 2007–2008, Texas Instruments Incorporated
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DAC8871
SBAS396A–JUNE 2007–REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
TA = +25°C
TA = +25°C
VREFH = 10V
VREFL = -5V
VREFH = 10V
VREFL = -5V
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 3.
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
TA = -40°C
VREFH = 10V
VREFL = -5V
TA = -40°C
VREFH = 10V
VREFL = -5V
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 5.
Figure 6.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
TA = +105°C
VREFH = 10V
VREFL = -5V
TA = +105°C
VREFH = 10V
VREFL = -5V
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 7.
Figure 8.
8
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Product Folder Link(s): DAC8871
DAC8871
www.ti.com ............................................................................................................................................................. SBAS396A–JUNE 2007–REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
1.00
0.75
0.50
0.25
0
TA = +25°C
TA = +25°C
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-1.25
-1.50
-0.25
-0.50
-0.75
-1.00
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 9.
Figure 10.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
1.00
0.75
0.50
0.25
0
TA = -40°C
TA = -40°C
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-1.25
-1.50
-0.25
-0.50
-0.75
-1.00
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 11.
Figure 12.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
1.00
0.75
0.50
0.25
0
TA = +105°C
TA = +105°C
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-1.25
-1.50
-0.25
-0.50
-0.75
-1.00
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
VREFH = 10V
VREFH = 10V
VREFL = 0V
VREFL = 0V
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
0
0
5
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
0
5
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 15.
Figure 16.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
2.00
1.50
1.00
0.50
0
1.00
0.75
0.50
0.25
0
VCC = +18V
VSS = -18V
VREFH = +18V
VREFL = -18V
-0.50
-1.00
-1.50
-2.00
-0.25
-0.50
-0.75
-1.00
VCC = +18V
VSS = -18V
VREFH = +18V
VREFL = -18V
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 17.
Figure 18.
INTEGRAL NONLINEARITY ERROR
vs REFERENCE VOLTAGE
DIFFERENTIAL NONLINEARITY ERROR
vs REFERENCE VOLTAGE
2.0
1.5
1.0
0.8
VCC = +18V
VCC = +18V
VSS = -18V
VSS = -18V
0.6
1.0
0.4
0.5
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.5
-1.0
-1.5
-2.0
6
7
8
9
10 11 12 13 14 15 16 17 18
6
7
8
9
10 11 12 13 14 15 16 17 18
±Reference (V)
±Reference (V)
Figure 19.
Figure 20.
10
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www.ti.com ............................................................................................................................................................. SBAS396A–JUNE 2007–REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
INTEGRAL NONLINEARITY ERROR
vs ANALOG SUPPLY VOLTAGE
DIFFERENTIAL NONLINEARITY ERROR
vs ANALOG SUPPLY VOLTAGE
2.0
1.5
1.0
0.8
0.6
1.0
0.4
0.5
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.5
-1.0
-1.5
-2.0
12
13
14
15
16
17
18
12
13
14
15
16
17
18
±Supply (V)
±Supply (V)
Figure 21.
Figure 22.
GAIN ERROR
vs TEMPERATURE
ZERO-CODE ERROR
vs TEMPERATURE
1.00
0.75
0.50
0.25
0
0.5
0.4
Bipolar Mode
VCC = 15V
Unipolar Mode
VCC = 15V
VCC = 15V
VSS = -15V
VREFH = 10V
VREFL = 0V
VSS = -15V
VREF = ±10V
0.3
VSS = -15V
VREFH = 10V
VREFL = 0V
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.25
-0.50
-0.75
-1.00
VCC = 15V
VSS = -15V
VREF = ±10V
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (°C)
Temperature (°C)
Figure 23.
Figure 24.
BIPOLAR ZERO ERROR
vs TEMPERATURE
SUPPLY CURRENT
vs DIGITAL INPUT VOLTAGE
0
-0.25
-0.50
-0.75
2.5
2.0
1.5
1.0
0.5
0
VCC = 15V
VSS = -15V
VREF = ±10V
Digital Input Code = 8000h
VDD = +5V
VDD = +3V
-60 -40 -20
0
20
40
60
80 100 120 140
0
1
2
3
4
5
Temperature (°C)
Digital Input Voltage (V)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
DUAL REFERENCE CURRENT
vs CODE
VREFH = +10V, VREFL = -10V
SINGLE REFERENCE CURRENT
vs CODE
VREFH = +10V, VREFL = 0V
800
700
600
500
400
300
200
100
0
1500
1250
1000
750
500
250
0
0
-100
-200
-300
-400
-500
-600
-700
-800
0
-250
-500
-750
-1000
-1250
-1500
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 27.
Figure 28.
SUPPLY CURRENTS
vs TEMPERATURE
DIGITAL SUPPLY CURRENT
vs DIGITAL SUPPLY VOLTAGE
5
4
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
IDD (VDD = 5V, VLOGIC = 5V)
3
2
IDD (VDD = 3V, VLOGIC = 3V)
1
ICC (VCC = 15V)
0
ISS (VSS = -15V)
-5
-60 -40 -20
0
20
40
60
80 100 120 140
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0
Digital Supply Voltage (V)
Temperature (°C)
Figure 29.
Figure 30.
ANALOG SUPPLY CURRENT
vs ANALOG SUPPLY VOLTAGE
SUPPLY CURRENTS
vs REFERENCE VOLTAGES
0.10
0.08
0.06
0.04
0.02
0
5
4
IDD (VDD = +5V)
3
ICC
ISS
2
IDD (VDD = +3V)
ICC (VCC = +18V)
-0.02
-0.04
-0.06
-0.08
-0.10
1
0
ISS (VSS = -18V)
-5
10
11
12
13
14
15
16
17
18
0
2
4
6
8
10
12 14
16
18 20
±Analog Supply Voltage (V)
±Reference Voltages (V)
Figure 31.
Figure 32.
12
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DAC8871
www.ti.com ............................................................................................................................................................. SBAS396A–JUNE 2007–REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
MAJOR CARRY GLITCH
(FALLING)
MAJOR CARRY GLITCH
(RISING)
5V/div
5V/div
LDAC
LDAC
VOUT
VOUT
200mV/div
200mV/div
Time (0.5ms/div)
Time (0.5ms/div)
Figure 33.
Figure 34.
DAC SETTLING TIME
(FALLING)
DAC SETTLING TIME
(RISING)
5V/div
5V/div
5V/div
LDAC
LDAC
VOUT
VOUT
5V/div
Time (0.5ms/div)
Time (0.5ms/div)
Figure 35.
Figure 36.
BROADBAND
NOISE
BW = 10kHz
Code = 8000h
Time (10ms/div)
Figure 37.
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DAC8871
SBAS396A–JUNE 2007–REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
THEORY OF OPERATION
GENERAL DESCRIPTION
The DAC8871 is a 16-bit, single-channel, serial-input, voltage-output DAC. It operates from a dual power supply
ranging from ±13.5V to ±19.8V, and typically consumes 10µA. The output range is from VREFL to VREFH. Data are
written to this device in a 16-bit word format, via an SPI serial interface. To ensure a known power-up state, the
DAC8871 is designed with a power-on reset function. After power on, the state of the RSTSEL pin sets the value
of the input register and DAC latch, which sets the output state of the VOUT pin. Refer to the Power-On Reset and
Hardware Reset section for more details.
Kelvin sense connections for the reference and analog ground are also included.
DIGITAL-TO-ANALOG SECTIONS
The DAC architecture consists of two matched DAC sections and is segmented. A simplified circuit diagram is
shown in Figure 38. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of
these switches connects one of 15 matched resistors to either VREFH or VREFL. The remaining 12 bits of the data
word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.
R
R
VOUT
2R
2R
2R
2R
2R
2R
2R
S0
S1
S11
E1
E2
E15
VREFH-F
VREFH-S
VREFL-F
VREFL-S
12-Bit R-2R Ladder
Four MSBs Decoded into
15 Equal Segments
Figure 38. DAC Architecture
OUTPUT RANGE
The output of the DAC is:
V
REFH * VREFL
65536
VOUT
+
Code ) VREFL
(1)
Where Code is the decimal data word loaded to the DAC latch.
For example, if VREFH is +10V, and VREFL is –10V, the range of VOUT is from –10V (Code = 0000h) to +10V (Code
= FFFFh).
The range of VREFL is from –18V to (VREFH – 1.25V), and the range of VREFH is 0V to +18V. The output from the
DAC8871 can be unipolar (from 0V to +18V) or bipolar by setting the proper VREFL and VREFH values.
14
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POWER-ON RESET AND HARDWARE RESET
The DAC8871 has a power-on reset function. When the RSTSEL pin is low (tied to DGND), and after power-on
or a hardware reset signal is applied to the RST pin, the DAC latch is cleared ('0') and the VOUT pin is set to
negative full-scale. When RSTSEL is high, the DAC latch and VOUT are set to mid-scale.
SERIAL INTERFACE
The DAC8871 digital interface is a standard 3-wire connection compatible with SPI, QSPI™, Microwire™ and TI
DSP™ interfaces, which can operate at speeds up to 50 Mbits/second. The data transfer is framed by the chip
select (CS) signal. The DAC works as a bus slave. The bus master generates the synchronize clock (SCLK) and
initiates the transmission. When CS is high, the DAC is not accessed, and SCLK and SDI are ignored. The bus
master accesses the DAC by driving CS low. Immediately following the high-to-low transition of CS, the serial
input data on the SDI pin are shifted out from the bus master synchronously on the falling edge of SCLK and
latched on the rising edge of SCLK into the input shift register, MSB first. The low-to-high transition of CS
transfers the content of the input shift register to the input register.
All data registers are 16 bits. It takes 16 SCLK cycles to transfer one data word to the device. To complete a
whole data word, CS must be taken high immediately after the 16th SCLK is clocked in. If more than 16 SCLK
cycles are applied while CS is low, the last 16 bits are transferred into the input register on the rising edge of CS.
However, if CS is not kept low during the entire 16 SCLK cycles, the data are corrupted. In this case, reload the
DAC latch with a new 16-bit word.
The DAC8871 has an LDAC pin that allows the DAC latch to be updated asynchronously by bringing LDAC low
after CS goes high. In this case, LDAC must be kept high while CS is low. If LDAC is permanently tied low, the
DAC latch will be updated immediately after the input register is loaded (caused by the low-to-high transition of
CS).
EXTERNAL AMPLIFIER SELECTION
The output of the DAC8871 is unbuffered. The output impedance is approximately 6.2kΩ. If the applications
require an external buffer amplifier, the selected amplifier must have a low-offset voltage (1LSB = 305µV for
±10V output range), eliminating the need for output offset trims. Input bias current should also be low because
the bias current multiplied by the DAC output impedance (approximately 6.25kΩ) adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast settling, the slew rate of the operational amplifier
should not impede the settling time of the DAC. The output impedance of the DAC is constant and
code-independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as
high as possible. The amplifier should also have a 3dB bandwidth of 1MHz or greater. The amplifier adds
another time constant to the system, thus increasing the settling time of the output. A higher 3dB amplifier
bandwidth results in a shorter effective settling time of the DAC and amplifier combination.
VSS
VCC
VDD
DGND
VREFH-S VREFH-F VREFL-F VREFL-S
+V
OPA277
or
RSTSEL
RST
Control
VOUT
DAC
OPA211
Logic
LDAC
AGND
-V
CS
SCLK
SDI
LOAD
Input
Serial
6.2kW
DAC
Latch
Data
Interface
Register
DAC8871
Figure 39. DAC8871 with External Amplifier
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APPLICATION INFORMATION
REFERENCE INPUT
The DAC full-scale output voltage is determined by the reference voltage, as shown in the Output Range section.
Reference input VREFH can be any voltage from 0V to +18V. Reference input VREFL can be any voltage from
–18V to (VREFH – 1.25V). The current into the VREFH input and out of VREFL depends on the DAC output voltages.
Refer to Figure 27 and Figure 28 for details. The reference input appears as a varying load to the reference. If
the reference can sink or source the required current, a reference buffer is not required. The DAC8871 features a
reference drive (force) and sense connection that minimizes the internal errors caused by the changing reference
current and the circuit impedances. Figure 40 shows a typical reference configuration.
DAC8871
VREFH
OPA2277
VREFH-F
VREFH-S
VREFL
OPA2277
VREFL-F
VREFL-S
Figure 40. Buffered Reference Connection
POWER-SUPPLY BYPASSING
For accurate, high-resolution performance, bypassing the supply pins with a 10µF tantalum capacitor in parallel
with a 0.1µF ceramic capacitor is recommended.
POWER-SUPPLY SEQUENCING
The analog supplies (VCC and VSS) must power up before the digital supply (VDD). All three supplies must power
up before the reference voltages (VREFH and VREFL) are applied. Additionally, because the DAC input shift
register is not reset during a power-on reset (or a hardware reset through the RST pin), the CS pin must not be
unintentionally asserted during power-up of the device. It is recommended that the CS pin be connected to VDD
through a pull-up resistor to avoid improper power-up.
Likewise, the state of the LDAC pin must not be accidentally changed during power-up. It is recommended that
the LDAC pin be connected to VDD through a pull-up resistor, unless it is permanently tied to ground.
To ensure that the ESD protection circuitry of this device is not activated, all other digital pins must be kept at
ground potential until VDD is applied.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC8871SBPW
DAC8871SBPWR
DAC8871SPW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
16
16
16
16
90
RoHS & Green
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
DAC8871
Samples
Samples
Samples
Samples
2000 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
Call TI
Call TI
Call TI
DAC8871
DAC8871
DAC8871
DAC8871SPWR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC8871SBPWR
DAC8871SPWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC8871SBPWR
DAC8871SPWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DAC8871SBPW
DAC8871SPW
PW
PW
TSSOP
TSSOP
16
16
90
90
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2022, Texas Instruments Incorporated
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