DCV010505DP-U [TI]
微型 1W 1500Vrms 隔离式未稳压直流/直流转换器 | DUA | 7 | -40 to 85;
| 型号： | DCV010505DP-U |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 微型 1W 1500Vrms 隔离式未稳压直流/直流转换器 | DUA | 7 | -40 to 85 PC CD 光电二极管 输出元件 转换器 |
| 文件： | 总30页 (文件大小：1695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DCV010505, DCV010505D, DCV010512, DCV010512D, DCV010515, DCV010515D, DCV011512D,
DCV011515D, DCV012405, DCV012415D
ZHCSOO6C –AUGUST 2000 –REVISED AUGUST 2021
DCV01 系列1W、1500VRMS 隔离式非稳压直流/直流转换器模块
1 特性
3 说明
• 1.5kV 隔离（运行）：1 秒测试
• 在隔离层中施加连续电压：60VDC/42.5VAC
• UL1950 认证元件
• EN55022 B 类EMC 性能
• 7 引脚PDIP 和7 引脚SOP 封装
• 输入电压：5V、15V 或24V
• 输出电压：±5V、±12V 或±15V
• 器件间同步
DCV01 系列是一个 1W、1500Vrm 隔离式非稳压直流/
直流转换器模块系列。DCV01 系列器件具有片上器件
保护，只需要很少的外部元件即可提供额外的功能，例
如输出禁用和开关频率同步。
DCV01 系列器件集这些特性和较小的尺寸于一体，非
常适合用于各种应用，并且对需要信号路径隔离的应用
来说，它是一个易于使用的解决方案。
警告：此产品具有运行隔离功能，仅可用于信号隔离。不可用于需
要增强型隔离的安全隔离电路。请参阅节8.3 中的定义。
• 过热保护
• 短路保护
• 高效率
器件信息
2 应用
封装(1)
PDIP (7)
SOP (7)
封装尺寸（标称值）
19.18mm × 10.60mm
19.18mm × 10.60mm
器件型号
DCV01xxxx
• 信号路径隔离
• 消除接地环路
• 数据采集
• 工业控制和仪表
• 测试设备
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
SYNCOUT
SYNCOUT
Oscillator
800 kHz
Divide-by-2
Reset
Oscillator
800 kHz
Divide-by-2
Reset
+VOUT
SYNCIN
SYNCIN
+VOUT
Power
Stage
Power
Stage
œVOUT
œVOUT
Watchdog
Startup
Watchdog
Startup
COM
Thermal
Shutdown
PSU Thermal
Shutdown
+VS
+VS
Power Controller
Power Controller
œVS
œVS
单路输出方框图
双路输出方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS014
DCV010505, DCV010505D, DCV010512, DCV010512D, DCV010515, DCV010515D, DCV011512D,
DCV011515D, DCV012405, DCV012415D
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ZHCSOO6C –AUGUST 2000 –REVISED AUGUST 2021
Table of Contents
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................17
9.1 Application Information............................................. 17
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................20
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................23
12.1 Device Support....................................................... 23
12.2 Documentation Support.......................................... 23
12.3 接收文档更新通知................................................... 23
12.4 支持资源..................................................................23
12.5 Trademarks.............................................................23
12.6 静电放电警告.......................................................... 23
12.7 术语表..................................................................... 23
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Switching Characteristics............................................6
7.7 Typical Characteristics................................................7
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagrams....................................... 11
8.3 Feature Description...................................................12
Information.................................................................... 23
4 Revision History
Changes from Revision B (September 2016) to Revision C (August 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 更新了节1 ......................................................................................................................................................... 1
• 向节2 添加了链接...............................................................................................................................................1
• Added sentence in 节8.3.1.3 .......................................................................................................................... 12
• Added 节8.3.6 .................................................................................................................................................13
• Added 节8.3.7 .................................................................................................................................................13
• Added 节8.3.10 ...............................................................................................................................................14
Changes from Revision A (December 2013) to Revision B (September 2016)
Page
• 更改了特性.........................................................................................................................................................1
• 更改了应用.........................................................................................................................................................1
• 添加了器件信息表、器件比较表、ESD 等级表、特性说明部分、器件功能模式、应用和实施部分、电源相
关建议部分、布局部分、器件和文档支持部分以及机械、封装和可订购信息部分..........................................1
• Deleted Electrical Characteristics Per Device table............................................................................................6
• Added additional graphs to Typical Characteristics section................................................................................7
• Added Isolation subsection to Feature Description section..............................................................................12
• Deleted DCH, DCP, DCR, and DCV Series DC-DC Converters subsection.....................................................12
• Deleted Continuous Voltage subsection...........................................................................................................12
• Deleted references to DCP, DCR, DCR, and DCH series................................................................................ 12
• Added typical application design to Application Information section................................................................ 17
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5 Device Comparison Table
at TA = 25°C, +VS = nominal, CIN = 2.2 µF, and COUT = 0.1 µF (unless otherwise noted)
OUTPUT
VOLTAGE
VNOM at VS (TYP) (V)
75% LOAD
DEVICE
OUTPUT
CURRENT
(mA)(3)
LOAD
NO LOAD
CURRENT
IQ (mA)
BARRIER
CAPACITANCE
CISO (pF)
INPUT
VOLTAGE
VS (V)
EFFICIENCY
(%)
100% LOAD
REGULATION
10% TO 100%
LOAD(1)
DEVICE NUMBER
0% LOAD
VISO = 750 Vrms
MIN TYP MAX
MIN
TYP
MAX
MAX
TYP
MAX
TYP
TYP
TYP
DCV010505P
DCV010505P-U
4.5
4.5
5
5
5.5
5.5
4.75
5
5.25
200
200(2)
83
19
31
20
22
29
40
34
42
19
20
14
17
80
3.6
3.8
5.1
4
DCV010505DP
DCV010505DP-U
±4.25
11.4
±5
12
±5.75
12.6
18
21
19
26
19
11
12
13
10
32
38
37
42
41
39
39
23
35
81
85
82
82
85
78
80
77
76
DCV010512P
DCV010512P-U
4.5
5
5.5
DCV010512DP
DCV010512DP-U
4.5
5
5.5
±11.4
14.25
±14.25
±11.4
±14.25
4.75
±12
15
±12.6
15.75
83(2)
66
DCV010515P
DCV010515P-U
4.5
5
5.5
3.8
4.7
2.5
2.5
2.5
3.8
DCV010515DP
DCV010515DP-U
4.5
5
5.5
±15 ±15.75
±12 ±12.6
±15 ±15.75
5.25
±15 ±15.75
66(2)
83 (2)
66(2)
200
DCV011512DP
DCV011512DP-U
13.5
13.5
21.6
21.6
15
15
24
24
16.5
16.5
26.4
26.4
DCV011515DP
DCV011515DP-U
DCV012405P
DCV012405P-U
5
DCV012415DP
DCV012415DP-U
±14.25
66(2)
(1) Load regulation = (VOUT at 10% load –VOUT at 100%)/VOUT at 75% load
(2) IOUT1 + IOUT2
(3) POUT(max) = 1 W
6 Pin Configuration and Functions
1
2
14
1
2
14
+VS
SYNCIN
+VS
SYNCIN
œVS
œVS
DCV01
DCV01
5
6
7
5
6
7
œVOUT
+VOUT
NC
COM
+VOUT
œVOUT
8
8
SYNCOUT
SYNCOUT
图6-1. NVA, DUA Package 7-Pin PDIP, SOP (Single- 图6-2. NVA, DUA Package 7-Pin PDIP, SOP (Dual-
Output) (Top View)
Output) (Top View)
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
COM
NC
SINGLE-OUTPUT
DUAL-OUTPUT
5
O
Output side common
No connection
—
7
—
—
Synchronization. Synchronize multiple devices by
connecting the SYNC pins of each. Pulling this pin low
disables the internal oscillator.
SYNCIN
14
8
14
8
I
SYNCOUT
O
Synchronization output. Unrectified transformer output
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ZHCSOO6C –AUGUST 2000 –REVISED AUGUST 2021
表6-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
+VOUT
+VS
SINGLE-OUTPUT
DUAL-OUTPUT
6
1
5
2
6
1
7
2
O
I
Positive output voltage
Input voltage
O
I
Negative output voltage
Input side common
–VOUT
–VS
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7
UNIT
5-V input devices
Input voltage
15-V input devices
24-V input devices
18
V
29
Surface temperature of device body or pins
(maximum 10 s)
Lead temperature
PDIP package
SOP package
270
°C
Reflow solder temperature
Storage temperature, Tstg
Surface temperature of device body or pins
260
125
°C
°C
–60
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
5
MAX
5.5
UNIT
V
5-V input devices
15-V input devices
24-V input devices
Input voltage
13.5
21.6
–40
15
16.5
26.4
85
24
Operating temperature
7.4 Thermal Information
°C
DCV01
DCV01
THERMAL METRIC(1)
NVA (PDIP)
DVB (SOP)
UNIT
7 PINS
61
12 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
61
26
24
7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
26
24
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7
ψJT
24
24
ψJB
RθJC(bot)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
at TA = 25°C, +VS = nominal, CIN = 2.2 µF, COUT = 1 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
POUT
Output power
ILOAD = 100% (full load)
0.97
20
W
mVPP
°C
VRIPPLE
Output voltage ripple
COUT = 1 µF, ILOAD = 50%
–40°C ≤TA ≤25°C
25°C ≤TA ≤85°C
0.046%
0.016%
Voltage vs temperature
°C
INPUT
VS
Input voltage
10%
–10%
ISOLATION
Voltage
1.5
kVrms
V/s
1-second flash test
dV/dt
500
30
Leakage current
nA
VISO
Isolation
Continuous working DC
voltage across
isolation barrier
60
VDC
AC
42.5
VAC
LINE REGULATION
I
OUT ≥10% load current and constant,
1%
1%
15%
15%
VS (min) to VS (typ)
Output voltage
I
OUT ≥10% load current and constant,
VS (typ) to VS (max)
RELIABILITY
Demonstrated
THERMAL SHUTDOWN
TA = 55°C
75
FITS
TSD
ISD
Die temperature at shutdown
Shutdown current
150
3
°C
mA
7.6 Switching Characteristics
at TA = 25°C, +VS = nominal, CIN = 2.2 µF, COUT = 1 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kHz
V
fOSC
Oscillator frequency
fSW = fOSC/2
800
VIL
Low-level input voltage, SYNC
Input current, SYNC
0
0.4
ISYNC
tDISABLE
CSYNC
VSYNC = 2 V
External
75
2
µA
Disable time
µs
Capacitance loading on SYNC pin(1)
3
pF
(1) External Synchronization of the DCP01/02 Series of DC/DC Converters describes this configuration.
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7.7 Typical Characteristics
at TA = 25°C (unless otherwise noted)
60
50
60
50
Standard Limits
Class A
Standard Limits
Class A
Class B
Class B
40
30
20
10
0
40
30
20
10
0
10
20
œ10
œ20
0.15
1
10
30
0.15
1
10
30
Frequency(MHz)
Frequency(MHz)
DCV010505
125% Load
DCV010505
8% Load
图7-1. Conducted Emissions
图7-2. Conducted Emissions
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
50
45
40
35
30
25
20
15
10
5
1-mF Ceramic
4.7-mF Ceramic
10-mF Ceramic
0
10
20
30
40
50
60
70
80
90 100
4.5
4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Input Voltage (V)
Load (%)
DCV010505
20-MHz BW
DCV010505
图7-3. Output Ripple versus Load
图7-4. Line Regulation
85
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
80
75
70
65
60
55
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
DCV010505
DCV010505
图7-5. Efficiency versus Load
图7-6. Load Regulation
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85
80
75
70
65
60
55
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
+V
OUT
OUT
œV
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
DCV010505D
DCV010505D
图7-8. Load Regulation
图7-7. Efficiency versus Load
90
85
80
75
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
70
65
60
55
50
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
DCV010512
DCV010512
图7-9. Efficiency versus Load
图7-10. Load Regulation
85
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.00
80
75
70
65
60
55
50
+VOUT
-VOUT
10
20
30
40
50
60
70
80
90 100
10
20
30
40
50
60
70
80
90 100
Load (%)
Load (%)
DCV010512D
DCV010512D
图7-11. Efficiency versus Load
图7-12. Load Regulation
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85
80
75
70
65
60
55
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
50
10
10
20
30
40
50
60
70
80
90
100
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
DCV010515
DCV010515
图7-14. Load Regulation
图7-13. Efficiency versus Load
90
85
80
75
70
65
60
55
18
17
16
15
14
+VOUT
-VOUT
50
10
20
30
40
50
60
70
80
90 100
10
20
30
40
50
60
70
80
90 100
Load (%)
Load (%)
DCV010515D
DCV010515D
图7-15. Efficiency versus Load
图7-16. Load Regulation
90
80
70
60
50
40
30
20
10
5.60
5.50
5.40
5.30
5.20
5.10
5.00
4.90
4.80
0
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
100
Load (%)
Load (%)
DCV012405
DCV012405
图7-17. Efficiency versus Load
图7-18. Load Regulation
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80
75
70
13.5
13.0
12.5
12.0
11.5
11.0
10.5
+V
OUT
OUT
œV
65
60
55
50
45
40
35
30
10
20
30
40
50
60
70
80
80
80
90
100
10
20
30
40
50
60
70
80
90
90
90
100
100
100
Load (%)
Load (%)
DCV011512D
DCV011512D
图7-20. Load Regulation
图7-19. Efficiency versus Load
90
17
16.5
16
+V
OUT
œV
OUT
80
70
15.5
15
60
50
40
30
14.5
14
13.5
13
10
20
30
40
50
60
70
90
100
10
20
30
40
50
60
70
80
Load (%)
Load (%)
DCV011515D
DCV011515D
图7-22. Load Regulation
图7-21. Efficiency versus Load
90
16.5
16
+V
OUT
OUT
œV
80
70
60
50
40
30
20
15.5
15
14.5
14
13.5
10
20
30
40
50
60
70
90
100
10
20
30
40
50
60
70
80
Load (%)
Load (%)
DCV012415D
DCV012415D
图7-24. Load Regulation
图7-23. Efficiency versus Load
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8 Detailed Description
8.1 Overview
The DCV01 offers up to 1 W of isolated, unregulated output power from a 5-V, 15-V, or 24-V input source with a
typical efficiency of up to 86%. This efficiency is achieved through highly integrated packaging technology and
the implementation of a custom power stage and control device. The DCV01 devices are specified for
operational isolation only. The circuit design uses an advanced BiCMOS and DMOS process.
8.2 Functional Block Diagrams
SYNCOUT
Oscillator
800 kHz
Divide-by-2
Reset
SYNCIN
+VOUT
Power
Stage
œVOUT
Watchdog
Startup
Thermal
Shutdown
+VS
Power Controller
œVS
图8-1. Single Output Device
SYNCOUT
Oscillator
800 kHz
Divide-by-2
Reset
+VOUT
SYNCIN
Power
Stage
œVOUT
Watchdog
Startup
COM
PSU Thermal
Shutdown
+VS
Power Controller
œVS
图8-2. Dual Output Device
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8.3 Feature Description
8.3.1 Isolation
Underwriters Laboratories, UL™ defines several classes of isolation that are used in modern power supplies.
Safety extra low voltage (SELV) is defined by UL (UL1950 E199929) as a secondary circuit which is so
designated and protected that under normal and single fault conditions the voltage between any two accessible
parts, or between an accessible part and the equipment earthing terminal for operational isolation does not
exceed steady state 42.5 VRMS or 60 VDC peak.
8.3.1.1 Operation or Functional Isolation
The type of isolation used in the DCV01 products is referred to as operational or functional isolation. Insulated
wire used in the construction of the transformer acts as the primary isolation barrier. A high-potential (hipot), one-
second duration test (dielectric voltage, withstand test) is a production test used to verify that the isolation barrier
is functioning. Products with operational isolation must never be used as an element in a safety-isolation system.
8.3.1.2 Basic or Enhanced Isolation
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and
secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the
insulated wire in the construction of the transformer. Input and output circuits must also be physically separated
by specified distances.
Note
The DCV01 products do not provide basic or enhanced isolation.
8.3.1.3 Working Voltage
For a device with operational isolation, the continuous working voltage that can be applied across the device in
normal operation must be less than 42.5 VRMS or 60 VDC. Ensure that both input and output voltages maintain
normal SELV limits.
WARNING
Do not use the device as an element of a safety isolation system that exceeds the SELV limit.
If the device is expected to function correctly with more than 42.5 VRMS or 60 VDC applied continuously across
the isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe
voltage, and further isolation or insulation systems must form a barrier between these circuits and any user-
accessible circuitry according to safety standard requirements.
8.3.1.4 Isolation Voltage Rating
The terms Hipot test, flash-tested, withstand voltage, proof voltage, dielectric withstand voltage, and isolation
test voltage all relate to the same thing. These terms describe a test voltage that is applied across a component
for a specified time, to verify the integrity of the isolation barrier of the component. TI’s DCV01 series of DC/DC
converters are all 100% production tested at 1.5 kVrms for one second.
8.3.1.5 Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending
on materials, construction, and environment. The DCV01 series of DC/DC converters have toroidal, enameled,
wire isolation transformers with no additional insulation between the primary and secondary windings. While a
device can be expected to withstand several times the stated test voltage, the isolation capability depends on
the wire insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual
chemical degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-
voltage tests and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage
by 20% from specified test voltage with a duration limit of one second per test.
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8.3.2 Power Stage
The DCV01 series of devices use a push-pull, center-tapped topology. The DCV01 devices switch at 400 kHz
(divide-by-2 from an 800-kHz oscillator).
8.3.3 Oscillator and Watchdog Circuit
The onboard, 800-kHz oscillator generates the switching frequency via a divide-by-2 circuit. The oscillator can be
synchronized to other DCV01 device circuits or an external source, and is used to minimize system noise.
A watchdog circuit monitors the operation of the oscillator circuit. The oscillator can be disabled by pulling the
SYNC pin low. When the SYNC pin goes low, the output pins transition into tri-state mode, which occurs within
2 µs.
8.3.4 Thermal Shutdown
The DCV01 series of devices are protected by a thermal-shutdown circuit.
If the on-chip temperature rises above 150°C, the device shuts down. Normal operation resumes as soon as the
temperature falls below 150°C. While the overtemperature condition continues, operation randomly cycles on
and off. This cycling continues until the temperature is reduced.
8.3.5 Synchronization
When more than one DC/DC converter is needed onboard, beat frequencies and other electrical interference
can be generated. This interference occurs because of the small variations in switching frequencies between the
DC/DC converters.
The DCV01 series of devices overcome this interference by allowing devices to be synchronized to one another.
Synchronize up to eight devices by connecting the SYNC pins of each device, taking care to minimize the
capacitance of tracking. Stray capacitance (greater than 3 pF) reduces the switching frequency, or can
sometimes stop the oscillator circuit. The maximum recommended voltage applied to the SYNC pin is 3 V.
For an application that uses more than eight synchronized devices use an external device to drive the SYNC
pins. External Synchronization of the DCP01/02 Series of DC/DC Converters (SBAA035) describes this
configuration.
Note
During the start-up period, all synchronized devices draw maximum current from the input
simultaneously. If the input voltage falls below approximately 4 V, the devices may not start up. A
ceramic capacitor must be connected close to the input pin of each device. Use a 2.2-µF capacitor for
5-V and 15-V input devices, and a 0.47-µF capacitor for the
24-V devices.
8.3.6 Light Load Operation (< 10%)
Operation below 10% load can cause the output voltage to increase up to double the typical output voltage. For
applications that operate less than 10% of rated output current, it is recommended to add a minimum load to
ensure the output voltage of the device is within the load regulation range. For example, connect a 250-Ω pre-
load resistor to meet the 10% minimum load condition for the DCV010505P.
8.3.7 Load Regulation (10% to 100%)
The load regulation of the DCV01 series of devices are specified at 10% to 100% load. Placing a minimum of
10% load will ensure the output voltage is within the range specified in the 节 7.5. For more information
regarding the operation below 10% load, see 节8.3.6.
8.3.8 Construction
The basic construction of the DCV01 series of devices is the same as standard integrated circuits. The molded
package contains no substrate. The DCV01 series of devices are constructed using an IC, rectifier diodes, and a
wound magnetic toroid on a leadframe. Because the package contains no solder, the devices do not require any
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special printed circuit board (PCB) assembly processing. This architecture results in an isolated DC/DC
converter with inherently high reliability.
8.3.9 Thermal Management
Due to the high power density of this device, it is advisable to provide ground planes on the input and output
rails.
8.3.10 Power-Up Characteristics
The DCV01 series of devices do not include a soft-start feature. Therefore, a high in-rush current during power-
up is expected. To ensure a more stable start-up, allow the input voltage to be in regulation before enabling the
device. Refer to the 节 8.4.1 section on how to disable/enable the device. 图 8-6 shows the typical start-up
waveform for a DCV010505P when enabled after the input voltage is in regulation. 图8-3 shows the typical start-
up waveform for a DCV010505P, operating from a 5-V input with no load on the output. 图8-4 shows the start-up
waveform for a DCV010505P starting up into a 10% load. 图 8-5 shows the start-up waveform starting up into a
full (100%) load.
图8-4. DCV010505P Start-Up at 10% Load
图8-3. DCV010505P Start-Up at No Load
图8-5. DCV010505P Start-Up at 100% Load
图8-6. DCV010505P Enable Start-Up at 100% Load
8.4 Device Functional Modes
8.4.1 Disable and Enable (SYNCIN Pin)
Each of the DCV01 series devices can be disabled or enabled by driving the SYNCIN pin using an open-drain
CMOS gate. If the SYNCIN pin is pulled low, the DCV01 becomes disabled. The disable time depends upon the
external loading. The internal disable function is implemented in 2 µs. Removal of the pulldown causes the
DCV01 to be enabled.
Capacitive loading on the SYNCIN pin must be minimized (≤ 3 pF) in order to prevent a reduction in the
oscillator frequency. The External Synchronization of the DCP01/02 Series of DC/DC Converters application
report (SBAA035) describes disable/enable control circuitry.
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8.4.2 Decoupling
8.4.2.1 Ripple Reduction
The high switching frequency of 400 kHz allows simple filtering. To reduce ripple, TI recommends that a
minimum of 1-µF capacitor be used on the +VOUT pin. For dual output devices, decouple both of the outputs to
the COM pin. The required 2.2-µF, low ESR ceramic input capacitor also helps to reduce ripple and noise, (24-V
input voltage versions require only 0.47 µF of input capacitance). See the DC-to-DC Converter Noise Reduction
application report (SBVA012).
8.4.2.2 Connecting the DCV01 in Series
Multiple DCV01 devices can be connected in series to provide non-standard voltage rails. This configuration is
possible by using the floating outputs provided by the galvanic isolation of the DCV01.
Connect the +VOUT from one DCV01 to the –VOUT of another (see 图 8-7). If the SYNCIN pins are tied together,
the self-synchronization feature of the DCV01 prevents beat frequencies on the voltage rails. The
synchronization feature of the DCV01 allows easy series connection without external filtering, thus minimizing
cost.
VIN
+VS
+VOUT1
COUT
1.0 µF
CIN
SYNCIN
œVS
DCV
01
œVOUT1
VOUT1
+
VOUT2
VS
+VOUT2
COUT
1.0 µF
CIN
SYNCIN
œVS
DCV
01
œVOUT2
图8-7. Multiple DCV01 Devices Connected in Series
The outputs of a dual-output DCV01 can also be connected in series to provide two times the magnitude of
+VOUT, as shown in 图 8-8. For example, connect a dual-output, 15-V, DCP012415D device to provide a 30-V
rail.
VIN
+VS
+VOUT
œVOUT
COM
+VOUT
COUT
1.0 µF
CIN
DCV
01
œVOUT
COUT
1.0 µF
œVS
图8-8. Dual Output Devices Connected in Series
8.4.2.3 Connecting the DCV01 in Parallel
If the output power from one DCV01 is not sufficient, it is possible to parallel the outputs of multiple DCV01s, as
shown in 图 8-9 (applies to single output devices only). The synchronization feature allows easy synchronization
to prevent power-rail beat frequencies at no additional filtering cost.
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VIN
+VS
+VOUT1
DCV
01
COUT
1.0 µF
SYNCIN
œVS
CIN
œVOUT1
2 × Power Out
+VS
+VOUT2
COUT
1.0 µF
DCV
01
SYNCIN
œVS
CIN
œVOUT2
GND
图8-9. Multiple DCV01 Devices Connected in Parallel
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9 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The DCV01 devices offer up to 1 W of isolated, unregulated output power from a 5-V, 15-V, or 24-V input supply.
Applications requiring up to 1.5-kVrms of operational isolation benefit from the small size and ease-of-use of the
DCV01 family of devices.
9.2 Typical Application
VIN
+VS
+VOUT
+VOUT
DCV01
CIN
2.2 µF
COUT
1.0 µF
SYNC
œVS
œVOUT
œVOUT
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图9-1. DCV010505 Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1 and follow the procedures in the 节9.2.2.
表9-1. Design Example Parameters
PARAMETER
VALUE
V(+VS)
V(+VOUT)
IOUT
Input voltage
5 V
Output voltage
5 V
Output current rating
Operating frequency
200 mA
400 kHz
fSW
9.2.2 Detailed Design Procedure
9.2.2.1 Input Capacitor
For all 5-V and 15-V input voltage designs, select a 2.2-µF low-ESR ceramic input capacitor to ensure a good
start-up performance. 24-V input applications require only 0.47 µF of input capacitance.
9.2.2.2 Output Capacitor
For any DCV01 design, select a 1-µF low-ESR ceramic output capacitor to reduce output ripple.
9.2.2.3 SYNCIN Pin
In a stand-alone application, leave the SYNCIN pin floating.
9.2.2.4 PCB Design
The copper losses (resistance and inductance) can be minimized by using wide ground and power traces or
planes. If several devices are being powered from a common power source, a star-connected layout must be
used. Device inputs must not be connected in series, as this will cascade the resistive losses. The position of the
decoupling capacitors is important to reduce losses. Place the decoupling capacitors as close to the devices as
possible. See the PCB Layout for more details.
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9.2.2.5 Decoupling Ceramic Capacitors
All capacitors have losses because of internal equivalent series resistance (ESR), and to a lesser degree,
equivalent series inductance (ESL). Values for ESL are not always easy to obtain. However, some
manufacturers provide graphs of frequency versus capacitor impedance. These graphs typically show the
capacitor impedance falling as frequency is increased (as shown in 图 9-2). In 图 9-2, XC is the reactance due to
the capacitance, XL is the reactance due to the ESL, and f0 is the resonant frequency. As the frequency
increases, the impedance stops decreasing and begins to rise. The point of minimum impedance indicates the
resonant frequency of the capacitor. This frequency is where the components of capacitance and inductance
reactance are of equal magnitude. Beyond this point, the capacitor is not effective as a capacitor.
Z
X
C
X
L
0
f
0
Frequency (Hz)
图9-2. Capacitor Impedance versus Frequency
At f0, XC = XL; however, there is a 180° phase difference resulting in cancellation of the imaginary component.
The resulting effect is that the impedance at the resonant point is the real part of the complex impedance;
namely, the value of the ESR. The resonant frequency must be well above the 800-kHz switching frequency of
the device.
The effect of the ESR is to cause a voltage drop within the capacitor. The value of this voltage drop is simply the
product of the ESR and the transient load current, as shown in 方程式1.
VIN = VPK –(ESR × ITR
)
(1)
where
• VIN is the voltage at the device input
• VPK is the maximum value of the voltage on the capacitor during charge
• ITR is the transient load current
The other factor that affects the performance is the value of the capacitance. However, for the input and the full
wave outputs (single-output voltage devices), ESR is the dominant factor.
9.2.2.6 Input Capacitor and the Effects of ESR
If the input decoupling capacitor is not ceramic (and has an ESR greater than 20 mΩ), then at the instant the
power transistors switch on, the voltage at the input pins falls momentarily. If the voltage falls below
approximately 4 V, the DCV01 detects an undervoltage condition and switches the DCV01 drive circuits to a
momentary off state. This detection is carried out as a precaution against a genuine low input voltage condition
that could slow down or even stop the internal circuits from operating correctly. A slow-down or stoppage results
in the drive transistors being turned on too long, causing saturation of the transformer and destruction of the
device.
Following detection of a low input voltage condition, the device switches off the internal drive circuits until the
input voltage returns to a safe value, at which time the device tries to restart. If the input capacitor is still unable
to maintain the input voltage, shutdown recurs. This process repeats until the input capacitor charges sufficiently
to start the device correctly.
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Normal start-up must occur in approximately 1 ms after power is applied to the device. If a considerably longer
start-up duration time is encountered, it is likely that either (or both) the input supply or the capacitors are not
performing adequately.
For 5-V to 15-V input devices, a 2.2-µF, low-ESR ceramic capacitor ensures a good start-up performance. For
24-V input voltage devices, TI recommends 0.47-µF ceramic capacitors. Tantalum capacitors are not
recommended, because most do not have low-ESR values and will degrade performance. If tantalum capacitors
must be used, designers must pay close attention to both the ESR and voltage as derated by the vendor.
Note
During the start-up period, these devices can draw maximum current from the input supply. If the input
voltage falls below approximately 4 V, the devices may not start up. Connect a 2.2-µF ceramic
capacitor close to the input pins.
9.2.2.7 Ripple and Noise
A good quality, low-ESR ceramic capacitor placed as close as possible across the input reduces reflected ripple
and ensures a smooth start-up.
A good quality, low-ESR ceramic capacitor placed as close as possible across the rectifier output terminal and
output ground gives the best ripple and noise performance. See the DC-to-DC Converter Noise Reduction
application report (SBVA012) for more information on noise rejection.
9.2.2.7.1 Output Ripple Calculation Example
The following example shows that increasing the capacitance has a much smaller effect on the output ripple
voltage than does reducing the value of the ESR for the filter capacitor.
To calculate the output ripple for a DCV010505 device:
• VOUT = 5 V
• IOUT = 0.2 A
• At full output power, the load resistor is 25 Ω
• Output capacitor of 1 µF, ESR of 0.1 Ω
• Capacitor discharge time 1% of 800 kHz (ripple frequency)
• tDIS = 0.0125 µs
• τ= C × RLOAD
• τ= 1 × 10-6 × 25 = 25 µs
• VDIS = VO(1 –EXP(–tDIS / τ))
• VDIS = 2.5 mV
By contrast, the voltage dropped because of ESR:
• VESR = ILOAD × ESR
• VESR = 0.2 × 0.1 = 20 mV
• Ripple voltage = 22.5 mV
9.2.2.8 Dual DCV01 Output Voltage
The voltage output for dual DCV01 devices is half-wave rectified; therefore, the discharge time is 1.25 µs.
Repeating the previous calculations using the 100% load resistance of 50 Ω(0.1 A per output), the results are:
• τ= 50 µs
• tDIS = 1.25 µs
• VDIS = 123 mV
• VESR = 0.1 × 0.1 = 10 mV
• Ripple Voltage = 133 mV
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In this example, it is the capacitor discharging that contributes to the largest component of ripple. Changing the
output filter to 10 µF, and repeating the calculations, the result is that the ripple voltage is 22.3 mV.
This value is composed of almost equal components.
The previous calculations are offered as a guideline only. Capacitor parameters usually have large tolerances
and can be susceptible to environmental conditions.
9.2.2.9 Optimizing Performance
Optimum performance can only be achieved if the device is correctly supported. The very nature of a switching
converter requires power to be instantly available when it switches on. If the converter has DMOS switching
transistors, the fast edges create a high current demand on the input supply. This transient load placed on the
input is supplied by the external input decoupling capacitor, thus maintaining the input voltage. Therefore, the
input supply does not experience this transient (this is analogous to high-speed digital circuits). The positioning
of the capacitor is critical and must be placed as close as possible to the input pins and connected through a
low-impedance path.
The optimum performance primarily depends on two factors:
• Connection of the input and output circuits for minimal loss.
• The ability of the decoupling capacitors to maintain the input and output voltages at a constant level.
9.2.3 Application Curves
85
80
75
70
65
60
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
55
50
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
DCV010515
Note: Operations under 10% Load
DCV010505
图9-4. Load Regulation
图9-3. Efficiency versus Load
10 Power Supply Recommendations
The DCV01 is a switching power supply, and as such can place high peak current demands on the input supply.
To avoid the supply falling momentarily during the fast switching pulses, ground and power planes must be used
to connect the power to the input of DCV01. If this connection is not possible, then the supplies must be
connected in a star formation with the traces made as wide as possible.
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DCV010505, DCV010505D, DCV010512, DCV010512D, DCV010515, DCV010515D, DCV011512D,
DCV011515D, DCV012405, DCV012415D
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ZHCSOO6C –AUGUST 2000 –REVISED AUGUST 2021
11 Layout
11.1 Layout Guidelines
Due to the high power density of these devices, provide ground planes on the input and output.
图 11-1 shows a schematic for two DCV01 devices. 图 11-2 and 图 11-3 show a typical layout for two through-
hole PDIP devices.
Input power and ground planes provide a low-impedance path for the input power. For the output, the COM
signal connects through a ground plane, while the connections for the positive and negative voltage outputs
conduct through wide traces to minimize losses.
The output must be taken from the device using ground and power planes, thereby ensuring minimum losses.
The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the
effects of stray inductance, thus improving the ripple performance. This location is of particular importance to the
input decoupling capacitor, because this capacitor supplies the transient current associated with the fast
switching waveforms of the power drive circuits.
Allow the unused SYNC pin, to remain configured as a floating pad. It is advisable to place a guard ring
(connected to input ground) or annulus connected around this pin to avoid any noise pickup. When connecting a
SYNC pin to one or more SYNC design the linking trace to be short and narrow to avoid stray capacitance.
Ensure that no other trace is in close proximity to this trace SYNC trace to decrease the stray capacitance on
this pin. The stray capacitance affects the performance of the oscillator.
11.2 Layout Example
CON1
VS1
0V1
1
2
SYNC 14
JP1
+VS
C1
œVS
DCV01
+VOUT
+V1
6
5
7
C3
C2-1
C2
R1
COM
COM1
C5
C4-1
C4
R2
œ V1
œVOUT
CON2
VS2
0V2
1
2
SYNC 14
JP2
+VS
C6
œVS
DCV01
+VOUT
+V2
6
5
7
C8
C7-1
C7
R3
COM
COM2
C10
C9-1
C9
R4
œ V2
œVOUT
图11-1. PCB Schematic, P and U Package
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DCV011512D DCV011515D DCV012405 DCV012415D
DCV010505, DCV010505D, DCV010512, DCV010512D, DCV010515, DCV010515D, DCV011512D,
DCV011515D, DCV012405, DCV012415D
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ZHCSOO6C –AUGUST 2000 –REVISED AUGUST 2021
图11-2. PCB Layout Example, Component-Side
图11-3. PCB Layout Example, Non-Component-
View
Side View
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DCV011512D DCV011515D DCV012405 DCV012415D
DCV010505, DCV010505D, DCV010512, DCV010512D, DCV010515, DCV010515D, DCV011512D,
DCV011515D, DCV012405, DCV012415D
www.ti.com.cn
ZHCSOO6C –AUGUST 2000 –REVISED AUGUST 2021
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
DCV01 05
05 (D) (P)
Basic model number: 1-W product
Voltage input:
5, 15, or 24
Voltage output:
5, 12 or 15
Output type:
blank (single) or D (dual)
Package code:
P = 7-pin PDIP (NVA package)
P-U = 7-pin SOP (DUA package)
图12-1. Supplemental Ordering Information
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, External Synchronization of the DCP01/02 Series of DC/DC Converters (SBAA035)
• Texas Instruments, DC-to-DC Converter Noise Reduction (SBVA012)
• Texas Instruments, Optimizing Performance of the DCP01/02 Series of DC/DC Converters (SBVA013)
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
Underwriters Laboratories, UL™ is a trademark of UL LLC.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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DCV011512D DCV011515D DCV012405 DCV012415D
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
NVA
DUA
NVA
DUA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
NVA
Qty
25
25
25
25
700
25
25
25
25
25
25
25
25
25
25
25
(1)
(2)
(3)
(4/5)
(6)
DCV010505DP
DCV010505DP-U
DCV010505P
ACTIVE
PDIP
SOP
PDIP
SOP
SOP
PDIP
SOP
PDIP
SOP
PDIP
SOP
PDIP
SOP
PDIP
SOP
PDIP
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
Level-3-260C-168 HR
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
DCV010505DP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RoHS &
Non-Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
DCV010505DP-U
DCV010505P
RoHS &
Non-Green
DCV010505P-U
DCV010505P-U/700
DCV010512DP
DCV010512DP-U
DCV010512P
RoHS &
Non-Green
Level-3-260C-168 HR
Level-3-260C-168 HR
N / A for Pkg Type
DCV010505P-U
DCV010505P-U
DCV010512DP
DCV10512DPU
DCV010512P
RoHS &
Non-Green
RoHS &
Non-Green
RoHS &
Non-Green
Level-3-260C-168 HR
N / A for Pkg Type
RoHS &
Non-Green
DCV010512P-U
DCV010515DP
DCV010515DP-U
DCV010515P
RoHS &
Non-Green
Level-3-260C-168 HR
N / A for Pkg Type
DCV010512P-U
DCV010515DP
DCV010515DP-U
DCV010515P
RoHS &
Non-Green
RoHS &
Non-Green
Level-3-260C-168 HR
N / A for Pkg Type
RoHS &
Non-Green
DCV010515P-U
DCV011512DP
DCV011512DP-U
DCV011515DP
RoHS &
Non-Green
Level-3-260C-168 HR
N / A for Pkg Type
DCV010515P-U
DCV011512DP
DCV011512DP-U
DCV011515DP
RoHS &
Non-Green
RoHS &
Non-Green
Level-3-260C-168 HR
N / A for Pkg Type
RoHS &
Non-Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DCV011515DP-U
DCV011515DP-U/700
DCV012405P
ACTIVE
SOP
SOP
PDIP
SOP
PDIP
SOP
SOP
DUA
7
7
7
7
7
7
7
25
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
DCV011515DP-U
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DUA
700
25
RoHS &
Non-Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
DCV011515DP-U
DCV012405P
NVA
RoHS &
Non-Green
DCV012405P-U
DUA
25
RoHS &
Non-Green
Level-3-260C-168 HR
N / A for Pkg Type
DCV012405P-U
DCV012415DP
DCV012415DP-U
DCV012415DP-U
DCV012415DP
NVA
25
RoHS &
Non-Green
DCV012415DP-U
DCV012415DP-U/700
DUA
25
RoHS &
Non-Green
Level-3-260C-168 HR
Level-3-260C-168 HR
DUA
700
RoHS &
Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DCV010505DP
DCV010505P
DCV010512DP
DCV010512P
DCV010512P-U
DCV010515DP
DCV010515P
DCV011512DP
DCV011515DP
DCV012405P
DCV012415DP
NVA
NVA
NVA
NVA
DUA
NVA
NVA
NVA
NVA
NVA
NVA
PDIP
PDIP
PDIP
PDIP
SOP
PDIP
PDIP
PDIP
PDIP
PDIP
PDIP
7
7
7
7
7
7
7
7
7
7
7
25
25
25
25
25
25
25
25
25
25
25
533.4
533.4
533.4
533.4
532.13
533.4
533.4
533.4
533.4
533.4
533.4
14.33
14.33
14.33
14.33
13.51
14.33
14.33
14.33
14.33
14.33
14.33
13.03
13.03
13.03
13.03
7.36
8.07
8.07
8.07
8.07
6.91
8.07
8.07
8.07
8.07
8.07
8.07
13.03
13.03
13.03
13.03
13.03
13.03
Pack Materials-Page 1
重要声明和免责声明
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不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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